國立中山大學電機工程學系...
TRANSCRIPT
⊕國立中山大學電機工程學系
碩士論文
低抖動高線性電壓控制震盪器
A Low Jitter High Linearity Voltage Controlled Oscillator
研究生：彭子軒 撰
指導教授：高家雄 博士
中華民國九十三年六月
Acknowledgement
在研究所兩年寶貴的時光，感謝我的指導教授 高家雄博士；謝謝老師您在積體
電路設計上給我的教導與研究學問的方法和態度，相信對於未來必定受用無窮。
感謝口試委員林吉聰博士、周世傑博士、蔡曜聰博士(依筆劃排序)，在口試期間
給予寶貴的意見，讓我的論文更加完善。另外，實驗室的學長姐與學弟們以及一
起渡過這兩年歲月的同學們，感謝你們平日在生活上幫助以及課業上的討論。
最後，我要感謝我的家人﹔謝謝爸媽的支持，讓我擁有無後顧之憂的求學生活完
成學業，還有兩位弟弟的打氣加油，你們讓我有勇氣與力量去面對克服未來的挑
戰，謝謝我的家人，我愛你們。祝福每一位關心我、愛我的人，希望你們健康、
平安。
低抖動高線性電壓控制震盪器
摘要
鎖相迴路電路應用在許多方面。例如時脈訊號的產生與資料回復以及頻率合
成器、調頻器、解頻器的應用上。鎖相迴路必須能夠提供緊密跟隨輸入時脈的一
個輸出時脈訊號﹔而在高頻環境時，時脈雜訊也隨之增加。雜訊主要的來源在於
供應電壓雜訊與基板雜訊。因此在鎖相迴路電路設計中擁有低雜訊抖動是很重要
的。在本論文中，我們討論在鎖相迴路系統之中，產生最大雜訊抖動的電壓控制
震盪器。
我們提出了一個低抖動的電壓控制震盪器，採用台積電 0.35μm 2P4M 混合
信號製程完成電路設計。我們在震盪電路中加入穩壓器用來降低供應電壓雜訊，
藉此提高整體電路的供應電壓抑制雜訊比。此電路架構提供了一個高度線性的增
益(Kvco)，可以降低震盪器雜訊並使得鎖相回路擁有更高的穩定度。
A Low Jitter High Linearity Voltage Controlled Oscillator
Abstract
Phase locked loops (PLL) are used in many applications. Application examplesinclude clock and data recovery, clock synthesis, frequency synthesis, modulator, andde-modulator. In many circuits, PLL must provide an output clock to follow the inputclock closely. For high speed environments, the noises also rise up. Noises mainlycome from the power supply and substrate. They produce jitter. A low jitter design isimportant in PLL circuit. In this thesis, we discuss the Voltage Controlled Oscillator(VCO) which has the largest jitter in PLL system.
We propose a low jitter voltage controlled oscillator designed in TSMC 0.35μm
2P4M Mixed-Signal process technology. We include a regulator to reduce jitter byincreasing the VCO PSRR. This structure also provides a high linearity gain (Kvco)which decreases the VCO jitter in the PLL circuit and improve the system stability.
Contents
Abstract
Chapte1. Introduction………………………….…………………….1
Chapter2.Conventional Oscillators
Section 2.1 L-C Tank Oscillator………………….………….……2Section 2.2 Relaxation Oscillator…………….….……….…….…4Section 2.3 Ring Oscillator.…………………..…..……………….5Section 2.4 Summary of VCOs …………….…….………….…….7
Chapter3.The proposed Voltage Controlled Oscillator….……. .8
Section 3.1 Current Controlled Oscillator……….……………….9
Section 3.1.1 High Speed Schmitt Trigger………...…..….………10Section 3.1.2 The CCO Circuit………………….……...………...12
Section 3.2 Voltage-to-Current Converter
Section 3.2.1 Type1 V-I Converter…...…..……..………...………15Section 3.2.2 Type2 V-I Converter……...……….……..………….17
Section 3.3 Regulator……………………………..……….………..19
Section 3.3.1 Self-Biasing Voltage Reference…………..…………20Section 3.3.2 Cascode Self-Biasing & voltage divider………..23Section 3.3.3 Voltage Follower & Output Driver………….……...25
Section 3.4 The Proposed Circuits…………………….………….28
Chapter4.Results & Discussions
Section 4.1 Design Issues…………………………………………..30
Section 4.1.1 Jitter Effect………………………………………….30Section 4.1.2 Jitter Definitions………………………………….…31
.(a) The Cycle-to-Cycle Jitter…………….………………………..31(b) The Period Jitter……………………...…..……….…………..32(c) The Long-Term Jitter………………………..……......………..33
Section 4.1.3 VCO Linearity………………...……………………..34
Section 4.2 The Frequency Versus Voltage Diagrams………...36
Section 4.3 Jitter Simulation and Results………………..……...38
Section 4.4 Layouts and Measured Results……………………..41
Section 4.5 Comparison Lists…………………………….………..45
Chapter5.Conclusion…………...…………………………………...46
Reference………………………..…………………………………….47
List of Figures
Fig. 1. Rule of thumb to design a low jitter Phase-Lock Loop………………………..1Fig. 2.1. Cross-Coupled LC-Tank Oscillator………………………………………….2Fig. 2.2. (a) Decaying impulse response of a tank.
(b) Addition of negative resistance to cancel loss in R(c) use of an active circuit to provide negative resistance…………….3
Fig. 2.3. (a) Schematic of CMOS relaxation oscillator.(b) Illustration of the operation principle…………………………………...4
Fig. 2.4. (a) N-stages Single-ended ring oscillator(b) N-stages differential ring oscillator………………………………………5
Fig. 2.5. Waveform of single-ended ring oscillator (Used N=3 as example)………….6Fig. 2.6. Implementation of the Delay Cell……………………………………………6Fig. 3.1. Structure of the Voltage Controlled Oscillator……...………...…………...…8Fig. 3.2. Basic Concept of the CCO…………………………………………………...9Fig. 3.3. High speed Schmitt trigger using basic latch……………………………….10Fig. 3.4. Schmitt trigger transfer curve and characteristics……………………….….10Fig. 3.5. Transfer between triangle wave and square wave…………………………..11Fig. 3.6. Complete circuit of proposed Current Controlled Oscillator……………….12Fig. 3.7. The output waveform of proposed CCO (Icontrol=80uA)…………………13Fig. 3.8. Type1 V-I Converter………………………………………………………...15Fig. 3.9. Output current of type1 V-I Converter……………………………………...16Fig. 3.10. The proposed V-I Converter……………………………………………….17Fig. 3.11. Output current of type2 V-I Converter…………………………………….18Fig. 3.12. The structure of Regulator………………………………………………...19Fig. 3.13. Basic Self-Biasing Reference Circuit……………………………………..20Fig. 3.14. Operating points of the Self-Biasing Reference………………………..…20Fig. 3.15. Cascode Self-Biasing Reference & Voltage Level Shift…………………..23Fig. 3.16. Results of Cascode Self-Biasing Voltage Reference………………………24Fig. 3.17. Basic Structure of the Regulator…………………………………………..25Fig. 3.18. Schematic of the voltage follower and output driver……………………...26Fig. 3.19. PSRR of the Proposed Regulator………………………………………….27Fig. 3.20. The circuit diagram of the Proposed Regulator…………………………...27Fig. 3.21. Structure of the proposed Voltage Controlled Oscillator………………….28Fig. 3.22. Circuit Diagram of VCO1 (Type1 V-I Converter with CCO)………...…..28Fig. 3.23. Circuit Diagram of VCO2 (Type2 V-I Converter with CCO)………...…..29Fig. 3.24. The Circuit of proposed Voltage Control Oscillator………………………29
Fig. 4.1. The effect of jitter in sampling error………………………………………..30Fig. 4.2. Cycle-to-Cycle Jitter………………………………………………………..31Fig. 4.3. Period Jitter………………………………………………………………....32Fig. 4.4. Long-Term Jitter……………………………………………………………33Fig. 4.5. The Definition of an ideal VCO…………………………………………….34Fig. 4.6. Non-linearity in actual VCO………………………………………………..35Fig. 4.7. The actual VCO curve and ideal curve……………………………...…...…35Fig. 4.8. The Curves of Output Frequency Versus Input Voltage………...…………..36
(VCO without Regulator)Fig. 4.9. The Curve of Output Frequency Versus Input Voltage………...………...…37
(VCO with Regulator)Fig. 4.10. Type1 V-I Converter and CCO with Power supply noise………...……….38Fig. 4.11. Proposed V-I Converter and CCO with Power supply Noise…...……...…38Fig. 4.12. Proposed VCO with Power supply Noise………………...……………….39Fig. 4.13. Ring Oscillator with Power supply Noise………………...…………….…39Fig. 4.14. Proposed VCO without Supply Noise……………………...……………..40Fig. 4.15. Layout of VCO1 and VCO2………………………...………………….…41Fig. 4.16. Layout of Proposed VCO……………………………………………….…41
Fig. 4.17. The test frame of Voltage Controlled Oscillator……...…………………...42Fig. 4.18. The Output waveform……………………………………...…………...…42Fig. 4.19. Measured Curve of Output Frequency Versus Input Voltage………...……43Fig. 4.20. Duty-Cycle Deviation of the Proposed VCO………………...…………....43Fig. 4.21. The Jitter Measurement of the Proposed VCO………...……………….…44
List of Tables
Table 1. Summary of the VCO characteristics…………………………...7
Table 2. Design of the High Speed Schmitt Trigger…………………….11
Table 3. Design of the proposed Current Controlled Oscillator………...14
Table 4. Design of the type1 V-I Converter……………………………..16
Table 5. Design of the type2 V-I Converter…………………………..…18
Table 6. Design of the Cascode Self-Biasing Voltage Reference……….24
Table 7. Design of the Voltage Follower & Output Driver……………...26
Table 8. The Simulation Results of Proposed VCO…………………….40
Table 9. Measured Results of the Proposed VCO………………………44
Table 10. The Comparison Lists………………………………………...45
1
Chapter 1. Introduction
Phase-Lock Loops (PLL) is widely used in communication system as clockgenerators or data recovery circuits (DRC). [1~2] The Voltage Controlled Oscillator(VCO) plays an important role in PLL. It requires a high linearity Frequency-Voltagerelation, wide tuning range, low jitter and low power consumption for differentapplications. In this thesis, we focus on high linearity and low jitter issues in order tobuild a low jitter PLL system. The basic design concept is shown in Fig. 1.
For intermediate frequency (IF) band, there are applications such as ADSL innerclock (40MHz ~ 120MHz), 10X DVD-ROMs & 64X CD-ROMs (90MHz ~280MHz) …etc. The tuning range of the proposed VCO is less than 300MHz. Chapter2 discusses previous VCOs, including LC-Tank oscillator, relaxation oscillator andring oscillator. We will summarize the characteristics of these different VCO types. Inchapter 3, we propose a new oscillator structure which has high linearity and low jitter.By using a high linearity voltage-to-current converter (V-I converter), a currentcontrolled oscillator, and a high-speed Schmith trigger, we obtain a high linearity &low jitter VCO.
Chapter 4 shows the simulation and chip measurement results. We also discuss thedefinitions of cycle-to-cycle jitter, period jitter and long-term jitter and the ways tomeasure them. All results show that our design fits the expectation. The VCOprovides only 5% maximum frequency variation and period jitter is 0.1-ppm in centralfrequency and the duty-cycle sustains about 50%. Finally, the conclusion is presentedin Chapter 5.
Fig. 1. Rule of thumb to design a low jitter Phase-Lock Loop
2
Chapter 2. Conventional Oscillators
Chapter 1 discussed the problems in VCO design. Especially the on-chiposcillator requires wide tuning range, low noise, low power, and low voltage. For aVCO to be used in a PLL, the following parameters are important: (1)Tuning range:the range between the minimum and maximum VCO frequency. In this range, theoutput amplitude variation and jitter must be minimum. (2)Jitter and phase noise:timing accuracy and spectral purity requirements increase the difficulty in circuitdesign. (3)Power supply and substrate noise rejection: The immunity against supplynoise can reduce the outside noise into PLL system. (4)Input/output linearity: Thevariation of Kvco across the tuning range is undesirable. This nonlinearity degradesthe loop stability and affects the phase error. [3]~[4]
In this chapter we will introduce the three most popular VCO types used in PLL.
Section 2.1 LC-Tank Oscillator
Because of the progress in bipolar and CMOS technologies. [5] Monolithicinductors become possible in a chip. The LC-Tank oscillator is becoming important.Here we introduce two LC-tank oscillator structures. Fig. 2.1, shows theCrossed-Coupled Oscillator.
Fig. 2.1. Cross-Coupled LC-Tank Oscillator
3
The circuit of Fig. 2.1 serves as the core of many LC oscillators. The cross-coupledpair provides a negative resistance (–R) between node X and Y to enable oscillation.This resistance is equal to –2/gm. This VCO type is also called a “negative-Gmoscillator”. Fig. 2.2 shows the basic concept of the oscillator.
Fig. 2.2 (a) Decaying impulse response of a tank. (b) Addition ofnegative resistance to cancel loss in R. (c) use of an active circuit toprovide negative resistance.
With careful selection of R, L, and C, the output frequency of the LC-tankoscillator is determined by following equation:
LCω
1 (rad/s) (2.1)
The limited tuning range in LC oscillators is a drawback but it has the advantage oflow phase noise. The LC-tank oscillator is suitable for high speed digital and RFapplications.
4
Section 2.2 Relaxation Oscillator
In this section, we introduce another oscillator type called relaxation oscillator.[6] The circuit combines a cross-coupled pair (M1&M2) with a floating storageelement C. It has a function like a multivibrator. Fig. 2.3 (a) shows the circuitschematic of a CMOS relaxation oscillator and the operation principle is shown in Fig.2.3 (b).
Fig. 2.3. (a) Schematic of CMOS relaxation oscillator.(b) Illustration of the operation principle.
As shown in Fig. 2.3, the M1 and M2 cross-coupled pair has a function likeswitches to determine the output state. Assume that the floating capacitor is initiallycharged by the current through M6, M2 and M3 (M2 on ; M3 off). When the capacitoris charged to a high voltage (Vs2=VDD-2I*R), M2 turns off and M1 turns on. Thencapacitor is charged by the current through M5, M1 and M4. Again, when Vs1 ischarged to VDD-2I*R , M1 turns off and M2 turns on. The circuit is oscillating. Theoscillation frequency of the relaxation oscillator is proportional to the chargingcurrent I and inversely proportional to the floating capacitor.
CI
fOSC (2.2)
By controlling the charge current I, we can determine the oscillator frequency.Although relaxation oscillators bring high tuning range, the noise induced by passiveelements and parasitic capacitors in cross-coupled transistors produce unbalance thatstrongly affects the jitter performance.
5
Section 2.3 Ring Oscillators
Ring oscillators are the most popular VCO type, because it is easy to design and nopassive elements in the circuit. [7]~[8] Fig. 2.4 (a) and (b) show the schematic of asingle-ended ring oscillator and a differential ring oscillator respectively.
Fig. 2.4. (a) N-stages Single-ended ring oscillator(b) N-stages differential ring oscillator
As shown in Fig. 2.4 (a), It consists of N inverter stages in a feedback connection.Assume N=3, and that Vz1=Vdd, Vz2=0, and Vz3=Vdd at t=0. Then Vz1 begins tofall to zero, forcing Vz2 to rise to Vdd after one inverter delay time (τ), and Vz3 to
fall to zero after another inverter delay. The circuit therefore oscillates, yielding aperiod of 6τ. The timing diagram is shown in Fig. 2.5. We can realize that the
frequency of a single-ended ring oscillator is proportional to the delay times.
21
N
fOSC (2.3)
In equation (2.3), N must be odd to keep the circuit oscillating.
6
Fig. 2.5. Waveform of single-ended ring oscillator(Used N=3 as example)
Once we control the bias currents, we can control the oscillator frequency anddelay time(τ). For a differential ring oscillator, the basic delay cell is a source
coupled differential pair shown in Fig. 2.6. (CL denotes the total capacitance seen atnode X1 or Y1)
Fig. 2.6. Implementation of the Delay Cell
Consider the differential pair of Fig. 2.6, M3 and M4 are in the triode region. IfVcont is increased, the resistances of M3 and M4 are also increased. Thus the delaytime(τ) increases, and the frequency is decreased.
L
thpcont
LonOSC CN
VVVdd
CRNNf
4.3
4,3
11
(2.4)
7
Section 2.4 Summary of VCOs
In this section, we summarize the characteristics of these oscillators. Differentapplications affect the oscillator’s choice. For example, the optical fiber transceivers(or receivers) need high speed up to several GHz for communication. As for computerinterface, they need low noise and high stability. Here, the summary table is listed asblow.
Summary of the VCO characteristics
PropertiesLC-Tank
OscillatorsRelaxationOscillators
RingOscillators
ProposedOscillator
Stabilization Good Good
TuningRange
Good Good Good
Chip sizeLarge(L&C)
Small Small Small
Low Jitter(Phase noise)
Good Good
Linearity Good
OperationalFrequency
RF Band RF~IF Band RF~IF Band IF Band
Circuitmatching
Hard Hard Easy Easy
Table 1. Summary of the VCO characteristics
We observe that the L-C tank oscillator is suitable for RF applications but thetuning range is poor and the chip size is large. The relaxation oscillator has thecircuit-matching problem which causes the unbalanced output waveform. We intendto develop a high linearity (constant kVCO) and low jitter VCO which is better than ringoscillator and doesn’thave the circuit-matching problem.
8
Chapter 3. The proposed Voltage Controlled Oscillator
In this chapter, we will describe our design. Our design is different from otherVCOs that are usually used in PLL circuits. The circuit has the following features: (1)the VCO frequency is several hundred MHz, (2) the VCO has a high linear full tuningrange. (3) The PSRR is improved using a regulator. Trade-off is necessary amongthem. Nevertheless, by using such structure, we obtain the required advantages.
In section 3.1, a current controlled oscillator is described. The circuit includes ahigh speed Schmitt trigger (HSST) and pass transistor switches. The duty-cycle is50%. In section 3.2, two voltage-to-current (V-I) converters are proposed. Thefunction of these V-I converters is to provide a high linearity V-I function. The circuitcombines the CCO with the V-I converter to produce a grounded capacitor relaxationoscillator. Fig. 3.1 depicts the frame. In the section 3.3, we add a regulator to improvethe PSRR of the VCO, and therefore to decrease the power supply noise. As a result,the VCO with a regulator reduces the jitter effectively. In section 3.4, we will describethe whole circuit.
Fig. 3.1 Structure of the Voltage Controlled Oscillator [9]
9
Section 3.1 Current Controlled Oscillator
Current-mode (CM) signal processing has become popular in the past decades [10].Using a current to control the output signal has many advantages such as circuitsimplicity, wide dynamic range, high accuracy, and low power consumption. Themost important is to bring high linearity to the output signal. Here we design a currentcontrolled oscillator (CCO). As shown in Fig. 3.2., the oscillator is composed of aSchmitt trigger, a grounded timing capacitor, a controllable current mirror, and passtransistor switches.
Fig. 3.2. Basic Concept of the CCO
This oscillator is a positive feedback multi-vibrator. The current mirror M1~M5is connected with a controllable current source. Assume that the grounded timingcapacitor initially has a zero voltage, and the output of the schmitt trigger is Vdd. Inthe same time, switch1 (PMOS) is on and switch2 (NMOS) is off. Thus the controlledcurrent from transistor M5 charges the grounded timing capacitor. When the capacitoris charging across the high switching point voltage, the output of the Schmitt triggerswitches to ground to turn on switch2 and turn off switch1. And the capacitor isdischarging toward ground by transistor M3 again. And vice versa. In this section, wewill show the components of our CCO and analyze them individually.
10
Section 3.1.1 High Speed Schmitt Trigger
Conventional Schmitt triggers have a limited speed around several MHz. [11]Here we describe a high speed Schmitt trigger (HSST) which combines a basiclatch with an inverter. The high speed Schmitt trigger circuit is shown in Fig. 3.3.
Fig. 3.3. High speed Schmitt trigger using basic latch
As shown in Fig. 3.3, the HSST circuit is composed of three inverters. Inverter 1changes the state of Schmitt trigger. Inverter2 and inverter3 construct the basic latch.If the input is grounded, then the output of inverter1 is equal to Vdd. As a result, inputof the latch is high and the output is grounded. And vice versa. The circuit is a highspeed Schmitt trigger and the propagation time is small. We show the results of thehigh switching point voltage (VSPH), the low switching point voltage (VSPL) and thehysteresis width (VHW) in Fig. 3.4. The value of the hysteresis voltage is about 0.8V.
Fig. 3.4. Schmitt trigger transfer curve and characteristics
11
The Schmitt trigger circuit design is shown in Table2. Fig. 3.5 exhibits thetransformation from triangle input wave to square wave.
Fig. 3.5. Transfer between triangle wave and square wave
The triangular input signal period is 3ns (≒333.33MHz). The HSST circuit has a
frequency higher than several hundreds of MHz without distortion.
Design of the High Speed Schmitt Trigger
INV1
Minv1(p) 18.5um/0.5umMinv1(n) 5um/0.5um
INV2 & INV3
Minv2,3(p) 7um/0.5umMinv2,3(n) 2.5um/0.5um
Table 2. Design of the High Speed Schmitt Trigger
12
Section 3.1.2 The CCO Circuit
The CCO circuit is shown in Fig. 3.6, where M1~M3 construct a current mirror andM4~M11 are switches and M12~M17 construct the Schmitt trigger as discussed inlast section.
Assume the capacitor is initially grounded and the output of Schmitt trigger is alsogrounded. M5 is off, and M4 is on. Therefore,
82,12,1 MGSMGSMDS VVV (3.1)
The current through M1, M2, and M8 are equal to the control current. In themeanwhile, the output sets M10 on and M11 off. Therefore, M6 is off and M7 is on.As a result, switch2 (M9) is off.
)9(970 MtnMGSMDS VVV (3.2)
Switch2 is immediately off when the output voltage is zero. The grounded timingcapacitor is charging by the control current. When the voltage across the capacitorreaches VSPH, the output state will be changed. And hence, the operation of theoscillator is reversed making the capacitor to discharge, and so on. The outputwaveform is shown in Fig. 3.6.
Fig. 3.6. Complete circuit of proposed Current Controlled Oscillator
13
Fig. 3.7. The output waveform of proposed CCO (Icontrol=80uA)
As shown in Fig. 3.7, the output waveform is a rectangular wave. When thecontrol current is about 80uA, the frequency of the rectangular wave is about 274MHz.The expression of the current control oscillator is
CVVI
Tf
SPLSPH
control
OSC
21
(3.3)
In equation (3.3), the oscillator frequency is proportional to the control current(Icontrol) and is inverse to the hysteresis width (VHW=VSPH-VSPL) and the groundedtiming capacitor (C).
14
Design of the Current Controlled Oscillator
Current Mirror
M1(p),M2(p),M3(n) 1um/1um
Pass transistors & Switches
M4(p),M6(p),M10(p) 5um/0.5umM5(n),M7(n),M11(n) 2um/0.5um
M8(p) 25um/0.5umM9(n) 10um/0.5um
High Speed Schmitt Trigger
M13(p) 18.5um/0.5umM12(n) 5um/0.5um
M15(p),M17(p) 7um/0.5umM14(n),M16(n) 2.5um/0.5um
Grounded timing capacitor
C = 0.1 pf
Table 3. Design of the proposed Current Controlled Oscillator
The details are shown in Table 3. The oscillator has good matching in chargingand discharging current such that the duty cycle is 50%. It is an important issue whenthe VCO is applied to microprocessors or computer interfaces where the 50%duty-cycle is required.
15
Section 3.2 Voltage-to-Current Converters
In this section, we introduce two converters. The V-I converter requires highlinearity and wide input range. Here we propose a new V-I converter and comparesthe new converter with the V-I converter in [12].
Section 3.2.1 Type1 V-I Converter
The previous V-I converter [12] is depicted in Fig. 3.8.
Fig. 3.8. Type1 V-I Converter [12]
The V-I converter provides a first-order linear relationship between the outputcurrent and the control voltage. Transistors M7 and M8 work in linear region toguarantee a linear output current. The output current is shown in Fig. 3.9.
16
Fig. 3.9. Output current of type1 V-I Converter
In Fig. 3.9, we clearly observe that the output current increases linearly. There isa cut-off voltage about 0.4V, and the input range is [0.4V~3.3V]. The output currentrange is from 0uA to 85.6uA. The maximum power consumption is less than 0.3mW.The design detail is shown in Table 4.
Design of the Type1 V-I Converter
M1(n), M2(n), M3(n) 4um/1umM4(n) 10um/1umM5(p) 4um/1umM6(p) 40um/1umM7(p) 20um/0.5umM8(p) 25um/1umM9(p) 40um/1um
R 50kΩ
Table 4. Design of the type1 V-I Converter
17
Section 3.2.2 Type2 V-I Converter
Fig. 3.10. The proposed V-I Converter
Here we propose a new V-I converter depicted in Fig. 3.10. The idea of thecircuit is that transistor M6, the current source M5 (which combine with thetransistors M4, and resistance R2) and resistance R1 construct the negative feedbackloop that provides a stable reference voltage (VSG6).
The negative feedback mechanism is described as follows. Assume Vin isconstant and there is a voltage variation(△V>0) on M6. When the voltage variation(△VSG6) is increased, VSG8(=VSD6) is also increased. Thus, the current of M8 (ID8)
increases. Meanwhile, the current (ID8) is mirrored by M2 and M1. As the voltage ofresistance R1 is increased by the increasing current I D1, the voltage variation(△VSG6)
on M6 is decreased. Therefore, the reference voltage (VSG6) is a constant.
outSGin I
RVV
I
6 (3.4)
18
The V-I converter provides a linear V-I relation and stable current. Thischaracteristic is suitable for a PLL system. Because the variation from power supplycan be reduced by such mechanism, the proposed converter is better than type1 V-Iconverter. The output current of type2 V-I converter is shown in Fig. 3.11.
Fig. 3.11. Output current of type2 V-I Converter
As we can see in Fig. 3.11, the output current range is from 3uA to 73uA. Themaximum power consumption is less than 0.25mW that is less than type1. The designdetail is shown in Table 5.
Design of the Type2 V-I Converter
M1(n), M2(n), M3(n) 10um/1umM4(n) 1um/1umM5(n) 2um/1umM6(p) 2um/1.2um
M7(p) , M8(p) 2um/1umR1 , R2 35kΩ
Table 5. Design of the type2 V-I Converter
19
Section 3.3 Regulator
Referring to [13], the jitter of the voltage controlled oscillators mainly comefrom power supply noises and substrate noises. For microprocessor applications,supply noises mainly come from instructions or instruction sets. The noises are slowerthan the system clock [14]~[15]. Thus, we set the maximum power supply noise as a10MHz square wave with the amplitude of 250mV. In the Fig. 3.12, we show thearchitecture of the proposed regulator which also called the Voltage Down Converter(VDC).
Fig. 3.12. The structure of Regulator
The core of the circuit is a voltage reference that must have high PSRR (PowerSupply Rejection Ratio). Here we define the PSRR as follow.
Internal
External
VV
PSRR log20 (3.5)
As we can see in Equation (3.5), the PSRR is the larger the better. Beside high PSRR,the output driver capability is another consideration and the temperature variation alsoneeds to be considered.
20
Section 3.3.1 Self-Biasing Voltage Reference
In this section, we present the basic self-biasing reference, which reduces theeffect of power supply variations and temperature variations. [16] The basic circuit isshown in Fig. 3.13.
Fig. 3.13. Basic Self-Biasing Reference Circuit
There are two possible operating points in the self-biasing reference circuit.Assume that M1 and M2 gates are grounded and M3 and M4 gates are VDD. Then thecurrent I is zero in the circuit. In Fig.3.14, the operating points are shown.
Fig. 3.14. Operating points of the Self-Biasing Reference
21
In Fig. 3.14, transistors M5-M8 construct a start-up circuit to avoid the referencecircuit from point2. If M1 and M2 gates are near ground, M5 will turn on and pull upthe M1 and M2 gate voltages. Therefore, this ensures that reference circuit will workat point 1. Since the circuit is stable at point 1, the M1 gate voltage increases until itreaches Vgs2+IR. This makes M5 OFF. Once the self-biasing circuit is working atpoint 1, the start-up circuit doesn’taffect the reference circuit.
Now we analyze the reference circuit. The width of M2 is made N times largerthan the width of M1. Then
RIVVGSGS
21
(Where 12 N ) (3.6)
The VGS of M1 and M2 can be expressed as follows.
1
1
1
2THNGS
VI
V
&2
2
2
2THNGS
VI
V
(3.7)
Thus, we can derive I by substituting Equation (3.7) into Equation (3.6).
2
12
2
212
11
2112
NRRI
(3.8)
From Equation (3.8) the size of M2 must be N times larger than the size ratio ofM1 and the size parameter N should be greater than 1 at the same time. From theequation, the output current is not influenced by the power supply variations.
Another merit of the circuit is that we can lower the temperature variation effectby carefully designing and adjusting the size. We will begin our discussion with thereference voltage.
1
1
1
2THNGSREF
VI
VV
(3.9)
22
Next, we substitute Equation (3.8) into Equation (3.9) as follows.
11
11
2THNREF V
NRV
(3.10)
Thus, we can derive the temperature variation in VREF
dT
VddT
RdNdT
Vd THNREF )()(112
)( 11
1
(3.11)
dTVd
dTRd
RdTd
NR
dTVd
dTRd
dTd
RRNR
THN
THN
)()(1)(111
)2(
)()()()
1(
11
)2(
11
11
11
1
11
dTVd
dTdR
RdTTdKP
TKPNRTHN )(1)(
)(11
1)2( 1
1
(3.12)
From the derivations above, we also know that the temperature coefficient of thethreshold voltage is
CmVdTVd THN /4.2
)( (3.13)
, the mobility variation with temperature is
TdTTdKP
TKPTT
TKPTKP5.1)(
)(1
)()(5.1
0
0
(3.14)
and the temperature coefficient of the poly1 resistor is
CppmdTdR
RRTC /2000
1)( (3.15)
Here we substitute Equation (3.13) ~ (3.15) into Equation (3.12) and this will result inthe final temperature coefficient of the reference voltage as follows.
)/4.2()/2000(5.11
1)2()(
1CmVCppm
TNRdTVd REF
(3.16)From Equation (3.16), we can make the TC of VREF equal to zero.
23
Section 3.3.2 Cascode Self-Biasing & voltage level shift
From the discussion of section 3.3.1, we had derived the expression of thereference voltage and TC. In this section, we design a cascode self-biasing circuit toimprove the PSRR and we also combine it with a simple level shift circuit to providean appropriate reference voltage. The schematic of the cascode self-biasing voltagedivider is shown below.
Fig. 3.15. Cascode Self-Biasing Reference & Voltage Level Shift
As shown in Fig. 3.15, the output voltage (Vout) is the desired one to supplyinternal circuit and the reference voltage (VREF) can be calculated using Equation(3.9). Assume that the temperature is at 25℃(T=298°K). According to Equation (3.16),we select the size of resistor equal to 15kΩ and β2 is four times larger than β1
(N=4). Then the voltage of VREF is 1.78V and Vout is 2.8V that becomes the referencevoltage of our regulator. The value is calculated as follow:
VVVV
VVVVA
VVVVA
DSDSout
DSDSDS
DSDSDS
832.2561.2271.0
561.2)2/()56.0613.1(10
271.0)2/()5.094.0(10
109
102
101010
92
999
The result of the design is shown in Fig. 3.16 and the detail design of cascodeself-biasing and voltage divider are listed in Table 6.
24
Fig. 3.16. Results of Cascode Self-Biasing Voltage Reference
Design of the Cascode Self-Biasing Reference&
Voltage Level Shift
Cascode Self-Biasing Reference
M1(n) 1um/1umM2(n),M3(n),M4(n) 4um/1um
M5(p)~M8(p) 10um/1umR 15kΩ
Voltage Level Shift
M9(n) 1um/1umM10(n) 1um/6um
M11(p),M12(p) 10um/1um
Cascode Self-Biasing Reference
M13(n) 3um/2umM14(n),M15(n) 3um/1umM16(p),M17(p) 1um/4um
Table 6. Design of the Cascode Self-Biasing Voltage Reference
25
Section 3.3.3 Voltage Follower & Output Driver
The voltage follower should have enough current capacity and low outputimpedance so that the output voltage (internal power supply) is not affected by theloading current fluctuations. We construct the regulator using a differential amplifierand a large size PMOS transistor. The basic structure is shown in Fig. 3.17.
Fig. 3.17. Basic Structure of the Regulator
In Fig. 3.17, the biasing voltage is provided by the self-biasing voltage referencediscussed in section 3.3.2 and the differential amplifier which requires: (1)high PSRRto increase the noise immunity from power supply, (2)high voltage gain (Av) to cancelthe power supply variation, (3)higher Gain Bandwidth that must be higher than10MHz because the power supply noise is about 10MHz as discussed in section 3.3.
The voltage follower and output driver diagram is shown in Fig. 3.18. And thedesign details of the voltage follower and output driver are listed in Table 7. In the endof section 3.3, we show the frequency response of the proposed regulator in Fig. 3.19and the whole circuit diagram of the proposed regulator is depicted in Fig. 3.20. Andthe PSRR of the regulator is 49.42dB when the power supply with a 10MHz, 250mVamplitude noise.
26
Fig. 3.18. Schematic of the voltage follower and output driver
Design of the Voltage Follower & Output Driver
Cascode Self-Biasing Reference
M1(n),M2(n),M5(n) 25um/1umM3(p),M4(p) 20um/1um
VBias 870 mV
Output Driver
M6(p) 400um/1um
Table 7. Design of the Voltage Follower & Output Driver
27
Fig. 3.19. PSRR of the Proposed Regulator
Fig. 3.20. The circuit diagram of the Proposed Regulator
28
Section 3.4 The Proposed Circuits
Our function block diagram is shown in Fig. 3.21.
Fig. 3.21. Structure of the proposed Voltage Controlled Oscillator
The proposed circuit diagrams are shown in the following figures.
Fig. 3.22. Circuit Diagram of VCO1 (Type1 V-I Converter with CCO)
29
Fig. 3.23. Circuit Diagram of VCO2 (Type2 V-I Converter with CCO)
Fig. 3.24. The Circuit of proposed Voltage Control Oscillator
30
Chapter 4. Results & Discussions
In the chapter, we will show the results and discussions. In section 4.1, thedefinitions of important characteristics are given. In section 4.2, we show thefrequency versus voltage diagrams and exhibit the output data. Section 4.3 shows thesimulation of the jitter. We also compare with the results with the ring oscillatorproposed by [7]. In section 4.4, our layouts are depicted and chip measurement resultsare shown. The last section shows the comparison list.
Section 4.1 Design Issues
In this section, we will discuss the important issues including the oscillator jitter andlinearity.
Section 4.1.1 Jitter Effect
The noise is called jitter in time domain and phase noise in frequency domain. InIF-band applications, jitter occurs often. We can observe in the Fig. 4.1, the clockjitter produces the sampling error of the sample and hold circuit. If there is auncertainty in sampling time, it translates directly to the uncertainty in the sampledoutput.
Fig. 4.1. The effect of jitter in sampling error
31
Section 4.1.2 Jitter Definitions
Jitter can be defined as the deviations in a clock’s transition from their idealpositions. The deviation can be either leading or lagging the ideal position. There arethree types such as cycle-to-cycle jitter, period jitter and long-term jitter. In thissection, we will discuss these jitters.
Section 4.1.2(a) The Cycle-to-Cycle Jitter
Cycle-to-cycle jitter is the change in a clock’s transition from its correspondingposition in the previous cycle. This jitter is the most difficult to measure and requiresa Timing Interval Analyzer (TIA). Fig. 4.2 depicts the graphical representation ofcycle-to-cycle jitter.
Fig. 4.2. Cycle-to-Cycle Jitter
According to [11], the magnitude of this jitter is
N
nn
NCycletoCycle J
NJ
1
21lim (4.1)
The magnitude of N is better to be enlarged to capture a accurate cycle-to-cycle jitter.The measurement requires TIA instrument to obtain cycle-to-cycle jitter. A predictionis provided in section 4.3.
32
Section 4.1.2(b) The Period Jitter
The Period jitter is the maximum change in a clock’s output transition. It is alsocalled cycle jitter. The graphical representation is shown in Fig. 4.3.
Fig. 4.3. Period Jitter
The period jitter is important in calculating the timing margin in a system. Forexample, a microprocessor system in which the processor requires 5ns of data set-uptime. Assume that the clock driving the system has a 7ns period jitter. In this example,the rising edge of the clock can occur before the data is valid on the bus. Theprocessor will have incorrect data and the system will not function correctly.
The measurement of period jitter requires a storage oscilloscope. Trigger on therising (or falling) edge of the clock and scroll the display until a rising (or falling)edge is displayed. The period jitter is simply the band of the rising edge displayed onthe scope. The mathematical expression is shown below.
2
MinMaxPeriod
TTJ (4.2)
The effect shown in Fig. 4.1 is another illustration about period jitter. If we canreduce the period jitter, then the output error is also reduced. Thus, the systemaccuracy will be improved.
33
Section 4.1.2(c) The Long-Term Jitter
The long-term jitter is also called the absolute jitter or peak-to-peak jitter. Thegraphical representation is shown in Fig. 4.4.
Fig. 4.4. Long-Term Jitter
The mathematical expression is shown below.
N
nntermLong TTJ
1(4.3)
The expression is not suitable for jitter expression because of the variance oflong-term jitter diverges with time. Thus, the analysis of, cycle-to-cycle jitter andperiod jitter are more meaningful and significant.
Note the difference between the cycle-to-cycle jitter and period jitter: the formercompares the oscillation period with the preceding period and the latter compares theperiod with the average period. And the cycle-to-cycle jitter and period jitter are moresignificant than long-term jitter.
34
Section 4.1.3 VCO Linearity
In this section, the definition of linearity is given. Let’s begin with the Taylorexpansion.
)(.......)()()( 33
2210 txtxtxtxty n
n (4.4)
In equation (4.4), an easy way to identify the linearity of the characteristic curve is tofind a range that all high order parameters such as α2, α3 ….. andαn are zero. An
ideal voltage controlled oscillator is a circuit that output frequency is a linear functionof its input control voltage, which can be seen in Fig. 4.5.
Fig. 4.5 The Definition of an ideal VCO
The expression of the voltage controlled oscillator is:
inVCOOSC Vkff 0 (4.5)
(12
12
VVff
kwhere VCO
)
where f0 represents the free-running frequency and kVCO represents the “gain”of thecircuit and is always constant. The tuning range is between f1 and f2 (the tuning rangerequired by applications). Unfortunately the gain of VCO is not constant in reality. Itmay be influenced by Vdd and fosc variations and becomes nonlinear. The nonlinearcharacteristics are shown in Fig. 4.6, when the un-wanted property is happened inpractical voltage controlled oscillator.
35
Fig. 4.6 Non-linearity in actual VCO
A practical oscillator often exhibits a high gain region in the middle of the rangeand low gain regions in the upper and lower of the output range. Non-linearity bringshigh sensitivity in some region that the magnitude of kVCO is no longer a constant. Andnon-linearity will degrade the settling behavior of PLL making the system unstable.Next, we provide a useful way to determine the linearity of the output frequency. Asshown in Fig. 4.7, the actual VCO curve, we draw a straight line through the extremepoints, obtaining the deviations, and normalize the results to the maximum tuningrange. Hence, we define the linearity of the VCO as:
%100rangetuningfrequency
deviationfrequencyLinearity (4.6)
Fig. 4.7 The actual VCO curve and ideal curve
36
Section 4.2 The Frequency Versus Voltage Diagrams
The simulation results of the proposed VCO are depicted in Fig. 4.8, which arethe curves of output frequency versus input controlled voltage.
Fig. 4.8 The Curves of Output Frequency Versus Input Voltage(VCO without Regulator)
By Equation (4.6), we can derive the linearity of the F-V curves. The tuning range ofthe pre-simulation is 222.5MHz. And the maximum deviation is 12MHz. Thus, thelinearity of the pre-simulation F-V curve is:
Pre-Simulation %4.5%1005.29252
12
MHzMHzMHz
Linearity
The linearity of the post-simulation F-V curve is as follows.
Post-Simulation %1.6%1005.31293
16
MHzMHzMHz
Linearity
37
From Fig. 4.8, the output frequency increases progressively by raising up inputvoltage. The pre-simulation and the post-simulation curves have high linearity in theoverall tuning range. The maximum deviation is less than 7%, calculated by Equation(4.6). Next, we draw the results of the proposed VCO with regulator in Fig. 4.9.
Fig. 4.9 The Curve of Output Frequency Versus Input Voltage(VCO with Regulator)
From Fig. 4.9, the linearity of the F-V curve is:
%7.6%10061258
2.13
MHzMHzMHz
Linearity
The linearity of all F-V curves is less than 7%. In other words, our design hashigh linearity in all tuning range. In the next section, we will simulate the jitter of ourcircuit and compare it with a single-ended ring oscillator that was proposed by [7].
38
Section 4.3 Jitter Simulation and Results
In the section, we consider the jitter induced from power supply noises.According to [15], the supply noises mainly come from instructions or instruction sets.The noise frequency is about 10MHz, which is lower than system clock. Thus, we adda 250mV, 10MHz square wave to the power supply. We obtain the followingdiagrams:
Fig. 4.10 Type1 V-I Converter [12] and CCO with Power supply noise
Fig. 4.11 Proposed V-I Converter and CCO with Power supply Noise
39
Fig. 4.12 Proposed VCO with Power supply Noise
Fig. 4.13 Ring Oscillator [7] with Power supply Noise
From Fig.4.10 to Fig.4.13, We can easily determine the period jitter as mentionedin section 4.1.2. We also compare the jitter result with ring oscillator proposed by [7].The period jitter of the proposal is ±115 pS (without supply noise) and the
cycle-to-cycle jitter is less than 10 pS. From above diagrams, our proposal has lowjitter and high PSRR. And we prove that by adding a regulator circuit with VCO caneffectively improve the PSRR of overall circuit. Table 8 lists the proposed VCOresults.
40
Fig. 4.14 Proposed VCO without Supply Noise
Simulation Results
Power Supply(VDD) 3.3V
Power Supply(VSS) 0V
Central frequency 160MHz
Regulator PSRR 49.42dB
Tuning Range 61MHz ~ 258MHz
VCO Gain (Kvco) 77MHz /V
Linearity (%) 6.7%
Duty Cycle 50%±5%
Cycle-to-Cycle Jitter 2.65 pS @160MHz
Period Jitter 115pS @160MHz
Average Power consumption 2.925mW
Table 8. The Simulation Results of Proposed VCO
41
Section 4.4 Layouts and Measured Results
In the section, we measure the chip fabricated by TSMC 2P4M 0.35μm mix-signal
process. The layouts of our design are shown in Fig. 4.15 and Fig.4.16 respectively.
Fig. 4.15 Layout of VCO1 and VCO2( Layout Size: 277μm×317μm ; Chip Size: 1326μm×1326μm )
Fig. 4.16 Layout of Proposed VCO( Layout Size: 433μm×683μm ; Chip Size: 890μm×1165μm )
42
The test frame is depicted as follows. By tuning the input voltage, the oscilloscopeoutput will be changed.
Fig. 4.17 The test frame of Voltage Controlled Oscillator
The oscilloscope outputs are displayed as below.
Output Waveform (Low frequency) Output Waveform (High frequency)
Fig. 4.18 The Output waveformFrom Fig. 4.18, the output waveform becomes a sine wave in high frequency
because of the loading effect in the measurement equipments. The outputpeak-to-peak voltage is about 384mV and the oscillating frequency is 113.6MHz. Thelow frequency (454.5KHz) peak-to-peak voltage is 800mV. The curve of outputfrequency versus input voltage is depicted in Fig. 4.19 and the duty-cycle deviation isin Fig.4.20. The jitter measurement result is shown in Fig. 4.21. And the results of themeasurement are listed in Table 9.
43
Fig. 4.19 Measured Curve of Output Frequency Versus Input Voltage
Fig. 4.20 Duty-Cycle Deviation of the Proposed VCO
44
Fig. 4.21 The Jitter Measurement of the Proposed VCO
Measured Results
Central frequency 73MHz
Tuning Range 0.45MHz ~ 135MHz
VCO Gain (Kvco) 45MHz /V
Linearity (%) 3.78%
Duty Cycle 50%±7%
Period Jitter 111pS @70.65MHz
Average Power consumption 3.7mW
Layout Size (without PAD) 433μm×683μm
Chip Size (with PAD) 890μm×1165μm
Table 9. Measured Results of the Proposed VCO
45
Section 4.5 Comparison Lists
[17] [18] [19] [20] Proposal
FabricatedProcess
TSMC1P4M
0.35μm
MOSIS0.8μm
1P5M0.25μm
UMC2P2M
0.5μm
TSMC2P4M
0.35μm
PowerSupply
3.3V 3.3V 2.5V 3V 3.3V
SupplyNoise
--20MHz
Vpp=200mV-- --
10MHzVpp=500mV
TuningRang
150~400MHz(80%)
20~400MHz120~750MHz
(76%)200~650MHz
(53.3%)62~258MHz
(100%)
Gain(Kvco)
160MHz /V172.73
MHz /V363MHz /V 300MHz /V 77MHz /V
VCOLinearity
23.5% -- 8% 18% 5.4%
Cycle-to-CycleJitter
2.45 pS@380MHz
16 pS -- --2.65 pS
@160MHz
PeriodJitter
-- 605 pS130 pS
@460MHz160 pS
@200MHz115 pS
@160MHz
Duty-Cycle(%)
-- -- -- -- 50%±5%
PowerConsumption
108.9mW ＜16mW ＜53mW ＜4.86mW2.925mW
@160MHz
LayoutSize
(without PAD)-- -- --
(0.84×0.84)2mm
(0.43×0.68)2mm
ChipSize
(with PAD)
(1.1×0.86)2mm
--(1.3×0.9)
2mm
(0.924×0.9)2mm
(1.1×0.89)2mm
Table 10. The Comparison Lists
(PS. “-- ”means the data was not listed in the paper.)
46
Chapter 5. Conclusion
A low jitter high linearity voltage controlled oscillator is proposed. The thesisshows the grounded capacitor relaxation oscillator capable of IF-Band by using a highspeed Schmitt trigger and a wide range V-I converter. The simulation shows that themaximum operational frequency reaches 293MHz and the linearity is 6.7% (less than7%) in all-tuning range. For jitter consideration, we add a regulator for the VCO toimprove the PSRR. The cycle-to-cycle jitter is 2.65 pS and the period jitter is 115 pS.From comparison lists in section 4.5, we observe that our design has low jitter andhigh linear tuning range at the same time. And the measurement results show that ourdesign having 50%±5% duty-cycle output.
Our design owns the merits as follows: 1.Low Jitter and high linearity. 2.HighPSRR by adding a regulator. 3.Operational frequency is higher than the severalhundreds of MHz. 4.Chip size is small and easy to design (433μm×683μm).
5.Power Consumption is less than 3.7mW. Thus, the required characteristics areaccomplished. The VCO is suitable for the systems that require low jitter.
47
Reference
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