OCTEON Fusion CNF95xxPress Briefing PresentationCNF95xx Product Introduction

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Announcing Next Generation Family of OCTEON Fusion§ Industry-leading merchant silicon 5G macro cell

baseband processor family§ Supports traditional all-in-one macro and

disaggregated Distributed Unit (DU) base station architectures

§ Delivers the performance of an ASIC with the flexibility of a processor

§ May be tailored via differentiated IP integration on a per customer basis

CNF95xx is involume productionwith a Tier 1 OEM

© 2020 Marvell. All rights reserved. 3

A Long History of Compute Innovation

2010

OCTEON Fusion CNF7130Small Cell

2015

OCTEON Fusion CNF75xx

Macro Cell

OCTEON Fusion CNF73xxMicro Cell

2019

OCTEON Fusion CNF95xx

Macro Cell

3G LTER9

LTER133G2G 5GLTE

R143G2G

OCTEON FusionSemi-customBeamformer

2020 2021

© 2020 Marvell. All rights reserved. 4

OCTEON Fusion CNF95xx Architecture

Sec Vault TrustZone PowerManagement

OCTEON TX26 Cores

Up to 1.25MB iMLC

SIMD

FPU

VGIC

AES

System MMU

66K I-cache

41K D-cache

OCTEON TX2

SIMD

FPU

VGIC

AES

SMMU

66K I-cache

41K D-cache

OCTEON TX2

Low Latency Crossbar at Core frequency

Up to 3.5MBCoherent LLC

3x Hyper Access Memory

Controller

2x 72b DDR4-2666

6x25GS

erDes

Ethernet1/10/25GE50/100GE NIX

Misc I/O*

*Boot/Flash, eMMC, SPI, GPIO, UART, 12C

I/O & Co-Proc Networks

Timers

NPA

App Acc Manager

PENC

PDEC

LDEC

RDEC

VDEC

TDEC

DENC

PHY SMEM24MB

LENC

RMAP

DMAP

FDEQ

ULFE

DLFE

PHY Scheduler

BPHY Ethernet (ROE/Chip2Chip)

XB

AR

4x25GSerD

es

BTSWireless Basebandoptimized DSPs

cnSBP2DSP Core64K IMEM

256K DMEM

cnMBP2DSP Core

64K IS + 64K IMEM128K DMEM x40 2x

PHY Subsystem

• Software defined PHY subsysatem

• Multi-core DSPs• 4G/5G Specific HW accelerator blocks

• Dedicated large internal SMEM

• High-speed non-blocking multi-ported Interconnect Fabric

• PHY Ethernet for radio and very low-latency chip-to-chip interface

SoC Interfaces• 25G SerDes support• 100G/50G/25G/10G/1GbE support

• Application acceleration manager for core workload distribution

• Packet IO acceleration support

OCTEON TX2CPU Cores

• Arm v8.2 Architecture, Up to 2.6 GHz

• Quad Issue, Out-of-order Pipeline

• 128b SIMD and floating-point support

• Full ARM virtualization spec supporteda

Cache, Interconnect

• Coherent MLC and LLC• Low-latency interconnect at core speed

• Up-to 2x DDR4-2666 MHz

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Multiple Business Model Options

ASIC designed around OCTEON Fusion IP

BUILD

End-to-end technology development

Leading process nodes and IP

OCTEON Fusion CNF95xx Merchant

Solution

BUY

Leading cellular baseband supplier to infrastructure market

Proven 10+ year track record

Software and ecosystem support

Semi-custom CNF95xx-based solutions

Customer IP

PARTNER

Leverage OCTEON Fusion for related processing functions

© 2020 Marvell. All rights reserved. 6

5G Macro Cell All-in-One Example

OCTEON FusionCNF95XX

Layer 1

OCTEON TX2CN92XX

Layer 2 / Layer 3(MAC Scheduler RLC,

PDCP, Transport, IPSec, Control)

25GbE 10/25/40GbE

Midhaul/Backhaul

RoE/eCPRI

RU(4x4 100Mhz)

RU(4x4 100Mhz)

RU(4x4 100Mhz)

RU(4x4 100Mhz)

Integrates to Radio Units using eCPRI

OCTEON Fusion

implements 5G Layer 1

OCTEON TX2 implements Layer 2 and 3 as well as Transport functions

© 2020 Marvell. All rights reserved. 7

5G O-RAN Architecture Design Example

OCTEON FusionCNF95XX

OCTEON FusionCNF95XX

OCTEON FusionCNF95XX

OCTEON TX2CN96XX

(MAC Scheduler RLC)

10/25GbE 25GbEPrestera98CX85xx

Ethernet switch

OCTEON TX2CN96XX

(PDCP, Transport, IPSec, Control)

Lower L1RF Upper L1 Lower L2 Upper L2 &

L3

ThunderX2(5G CORE)

Prestera98CX85xx

Ethernet switch

Core Network

Split 7.2 Split 6 Split 2

Marvell complete Portfolio enables 5G system architectures, such as the one proposedby the ORAN Alliance, to scale deployments and achieve the best OPEX and CAPEX in the industry

RoE/eCPRI4x RF4x RF4x RF

RF4x4

100MHz

4x RF4x RF4x RF

RF4x4

100MHz

4x RF4x RF4x RF

RF4x4

100MHz

25GbE 25GbE 25GbE

© 2020 Marvell. All rights reserved. 8

OCTEON Fusion – Key Takeaways

§ Industry-leading merchant silicon 5G macro cell baseband processor family

§ Supports traditional all-in-one macro and disaggregated Distributed Unit (DU) base station architectures

§ Delivers the performance of an ASIC with the flexibility of a processor

§ Currently in Volume production with a Tier1