oct 31 st 2007university of utah1 multi-cores: architecture/vlsi perspective the hardware-software...
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University of Utah How to use “multiple” cores? Oct 31 st Parallel programming Synchronization Deadlock Livelock Memory managementTRANSCRIPT
Oct 31st 2007 University of Utah 1
Multi-Cores: Architecture/VLSI Perspective
The Hardware-Software Relationship:
Date or Dump?
University of Utah
Embedded Applications --Spencer From discreet
cochlear implants to high-end biomedical imaging!
Multi-cores speed up performance by 50x!
Creating new application domains!
University of Utah
How to use “multiple” cores?
Oct 31st 2007
3
Parallel programmin
gSynchronization
DeadlockLivelockMemory management
University of Utah
Oct 31st 2007
4
How to use “multiple” cores?
Program = Communicat
ion + Computatio
n
Global restructuring and parallelization
University of Utah
Oct 31st 2007
5
Structured “Communication”
Lang: StreamIt, MPICompilers: RAW,
CoGenEArchitecture: TRIPS,
HWRT
Key: Help other levels and leverage communication
University of Utah
Another Constraint?
Oct 31st 2007
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Parallel programmin
gSynchronization
DeadlockLivelockMemory management
Hey..
Surprise!!!
Communication Scheduling
University of Utah
Another Constraint?
Oct 31st 2007
7
Oh God!!!
Communication Scheduling
University of Utah
Focus of Architecture Research Reduce the load of programmers
Hardware transactional memory Aggressive pre-fetching Dynamic reconfiguration at every possible level
Keep the architectural innovations transparent to compilers or programmers Learn from the mistakes of ITANIUM ! Remember the success of OOO execution
Oct 31st 2007
8
University of Utah9
Reliability Issues --Niti Shrinking transistor sizes & lower voltages
Increased transient faults, process variations – leakage power and frequency variations, hard errors, interconnect noise
Many-core – “Many cores” may not work reliably Some cores will end up providing redundancy
Heterogeneous cores may be able to help Simple in-order cores can provide redundancy at low cost
The compute power gain of many-core can get offset by reliability requirements of the system
University of Utah
Oct 31st 2007
10
On-Chip Sensor Networks --Nathaniel, Amlan
Analog sensors everywhere! Need to monitor power, voltage droop,
variation, critical paths, delays, slew rates, etc.
Control system to react to changes. In multi-core, sensor network will only
grow.
Xeon and Itanium processors JSSC Jan 06 & 07
On-chip sensors