obstacle detecting guiding vehicle using gps

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OBSTACLE DETECTING GUIDING VEHICLE USING GPS

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CHAPTER 1

Introduction

1.1 Objective of the project

1.2 Background of the Project

1.3 Organization of the Thesis

CHAPTER 2

Overview of the technologies used

2.1 Embedded Systems

2.2 GPS Technology

CHAPTER 3

Hardware Implementation of the Project

3.1 Project Design

3.2 Power Supply

3.3 Microcontrollers

3.4 GPS Technology

3.5 Serial Communication

3.6 Switches and Pushbuttons

3.7 IR Section

3.8 Liquid Crystal Display

3.9 L293D- Current Driver

3.10 Electric Motors

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CHAPTER 4

Firmware Implementation of the project design

4.1 Software Tools Required

CHAPTER 5

Results and Discussions

5.1 Results

5.2 Conclusion

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OBSTACLE DETECTING GUIDING VEHICLE USING GPS

Chapter 1

Introduction

The advent of new high-speed technologies and the growing IC technology provided realistic

opportunity for new cost effective technologies and realization of new methods of innovations.

This technical improvement together with the need for high performance techniques created

faster, more accurate and more intelligent products using new drives and advanced control

algorithms.

An automotive guiding system is a satellite navigation system designed for use in automobiles. It

typically uses a GPS navigation device to acquire position data to locate the user on a road in the

unit's map database. Using the road database, the unit can give directions to other locations along

roads also in its database.

The project intends to guide the users by giving the directions when they want to go to a new

place using GPS. The user has to enter the place he wishes to go. Then the system gives the

latitude and longitude parameters of the place and guides the user with the directions like East,

West, North and South. These directions will be displayed on the LCD.

The project uses the underlying concept GPS (Global Positioning System). The main application

of this system in this context is to give the directions to the user when he wants to go to a new

place. The GPS antenna present in the GPS module receives the information from the GPS

satellite in NMEA (National Marine Electronics Association) format and thus it reveals the

position information. This information got from the GPS antenna is sent to the controlling unit.

The controlling unit upon receiving the request displays the directions to reach the requested

place on the LCD.

The project also functions as an obstacle detecting device. Whenever the user vehicle finds any

obstacle in the opposite direction, the controlling unit changes the direction of the vehicle

immediately to avoid any kind of accident and moves forward on its way.

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This application is very much useful and important mainly during the night times since the user

driving the vehicle may be tired and not in a state of driving and most of the accidents occur

when the driving person is not in complete conscious state. Thus, this system avoids such kind of

accidents. IR sensor is used to detect the vehicle coming in the opposite direction and based on

the output of this sensor, the controlling unit takes the decision whether to stop the vehicle or

not.

1.4 Objective of the project

The project intends to interface the microcontroller with the GPS receiver and give the

latitude and longitude parameters of the place the user wishes to go and displays the directions to

reach the place. The project uses the GPS technology and Embedded Systems to design this

application. The main objective of this project is to design a system that gives the directions to

reach a place, the user wishes to and the system also functions as an obstacle detecting vehicle.

This project is a device that collects data from the GPS receiver, codes the data into a format

that can be understood by the controlling section. This system also collects information from the

master device and implements commands that are directed by the master.

The objective of the project is to develop a microcontroller based obstacle detection and

guiding vehicle. It consists of a GPS receiver, microcontroller, the interfacing unit to allow the

communication between the microcontroller and the GPS receiver, LCD and the motor and its

driver.

1.5 Background of the Project

The software application and the hardware implementation help the microcontroller

accept the input from the user, track the place using GPS receiver and give the directions to reach

the place, the user wishes to. The user is provided with switches to enter the place of interest to

the system. The microcontroller displays the directions on the LCD. Thus, the vehicle can reach

the place by following these directions. The system also detects the obstacle if any in its path and

immediately changes the direction of the vehicle so as to avoid the accident. The system is

totally designed using GPS and embedded systems technology.

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The Controlling unit has an application program to allow the microcontroller read the

incoming data from the user and provide the information using GPS receiver and make the

vehicle move in the given directions. The performance of the design is maintained by controlling

unit.

1.6 Organization of the Thesis

In view of the proposed thesis work explanation of theoretical aspects and algorithms

used in this work are presented as per the sequence described below.

Chapter 1 describes a brief review of the objectives and goals of the work.

Chapter 2 discusses the existing technologies and the study of various technologies in

detail.

Chapter 3 describes the Block diagram, Circuit diagram of the project and its description.

The construction and description of various modules used for the application are described in

detail.

Chapter 4 explains the Software tools required for the project, the Code developed for the

design.

Chapter 5 presents the results, overall conclusions of the study and proposes possible

improvements and directions of future research work.

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Chapter 2

Overview of the technologies used

Embedded Systems:

An embedded system can be defined as a computing device that does a specific focused job.

Appliances such as the air-conditioner, VCD player, DVD player, printer, fax machine, mobile

phone etc. are examples of embedded systems. Each of these appliances will have a processor

and special hardware to meet the specific requirement of the application along with the

embedded software that is executed by the processor for meeting that specific requirement.

The embedded software is also called firm ware. The desktop/laptop computer is a generalpurpose computer. You can use it for a variety of applications such as playing games, word

processing, accounting, software development and so on.

In contrast, the software in the embedded systems is always fixed listed below:

Embedded systems do a very specific task, they cannot be programmed to do different

things. . Embedded systems have very limited resources, particularly the memory. Generally,

they do not have secondary storage devices such as the CDROM or the floppy disk. Embedded

systems have to work against some deadlines. A specific job has to be completed within a

specific time. In some embedded systems, called real-time systems, the deadlines are stringent.

Missing a deadline may cause a catastrophe-loss of life or damage to property. Embedded

systems are constrained for power. As many embedded systems operate through a battery, the

power consumption has to be very low.

Some embedded systems have to operate in extreme environmental conditions such as very

high temperatures and humidity.

Following are the advantages of Embedded Systems:

1. They are designed to do a specific task and have real time performance constraints which

must be met.

2. They allow the system hardware to be simplified so costs are reduced.

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3. They are usually in the form of small computerized parts in larger devices which serve a

general purpose.

GPS Technology:

GPS is used in vehicles for both tracking and navigation. Tracking systems enable a base station

to keep track of the vehicles without the intervention of the driver where, as navigation system

helps the driver to reach the destination. Whether navigation system or tracking system, the

architecture is more or less similar. The navigation system will have convenient, usually a

graphic display for the driver which is not needed for a tracking system. Vehicle Tracking

Systems combine a number of well-developed technologies. Irrespective of the technology being

used, VTS consist of three subsystems: a) In-vehicle unit (IVU), b) Base station and c)

Communication link. The IVU includes a suitable position sensor and an intelligent controller

together with an appropriate interface to the communication link.

Network Overlay Systems use cell phone infrastructure for locating vehicles. The cell centers

with additional hardware and software assess the time of arrival (TOA) and angle of arrival

(AOA) of radio signals from vehicles to compute the position of the vehicles. This information is

sent to the tracking centre through the cell link or conventional link. Another technique used for

locating vehicles computes the time difference for signals from two cell centers to reach the

vehicle. This computation is made in the IVU and the position information is sent to the tracking

centre through the cell phone link.

A more common technique used is direct radio link (DRL). In this system, dedicated radio

infrastructure is used along with special IVU to compute vehicle location. However all these

techniques impose limitation on the operational area. Alternatively, embedded GPS receivers

provide absolute position co-ordinates at any point, without any area restrictions.

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Chapter 3

Hardware Implementation of the ProjectThis chapter briefly explains about the Hardware Implementation of the project. It discusses the

design and working of the design with the help of block diagram and circuit diagram and

explanation of circuit diagram in detail. It explains the features, timer programming, serial

communication, interrupts of AT89S52 microcontroller. It also explains the various modules

used in this project.

3.1 Project Design

The implementation of the project design can be divided in two parts.

Hardware implementation

Firmware implementation

Hardware implementation deals in drawing the schematic on the plane paper according to the

application, testing the schematic design over the breadboard using the various ICs to find if the

design meets the objective, carrying out the PCB layout of the schematic tested on breadboard,

finally preparing the board and testing the designed hardware.

The firmware part deals in programming the microcontroller so that it can control the operation

of the ICs used in the implementation. In the present work, we have used the Orcad design

software for PCB circuit design, the Keil v3 software development tool to write and compile

the source code, which has been written in the C language. The Proload programmer has been

used to write this compile code into the microcontroller. The firmware implementation is

explained in the next chapter.

The project design and principle are explained in this chapter using the block diagram and circuit

diagram. The block diagram discusses about the required components of the design and working

condition is explained using circuit diagram and system wiring diagram.

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3.1.1 Block Diagram of the Project and its Description

The block diagram of the design is as shown in Fig 3.1. It consists of power supply unit,

microcontroller, GSM modem, Serial communication unit and the Robot. The brief descriptionof each unit is explained as follows.

3.2 Power Supply:

The input to the circuit is applied from the regulated power supply. The a.c. input i.e., 230V from

the mains supply is step down by the transformer to 12V and is fed to a rectifier. The output

obtained from the rectifier is a pulsating d.c voltage. So in order to get a pure d.c voltage, the

output voltage from the rectifier is fed to a filter to remove any a.c components present even after

rectification. Now, this voltage is given to a voltage regulator to obtain a pure constant dc

voltage.

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Transformer:

Usually, DC voltages are required to operate various electronic equipment and these

voltages are 5V, 9V or 12V. But these voltages cannot be obtained directly. Thus the a.c input

available at the mains supply i.e., 230V is to be brought down to the required voltage level. This

is done by a transformer. Thus, a step down transformer is employed to decrease the voltage to a

required level.

Rectifier:

The output from the transformer is fed to the rectifier. It converts A.C. into pulsating

D.C. The rectifier may be a half wave or a full wave rectifier. In this project, a bridge rectifier is

used because of its merits like good stability and full wave rectification.

Filter:

Capacitive filter is used in this project. It removes the ripples from the output of rectifier

and smoothens the D.C. Output received from this filter is constant until the mains voltage and

load is maintained constant. However, if either of the two is varied, D.C. voltage received at this

point changes. Therefore a regulator is applied at the output stage.

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Voltage regulator:

As the name itself implies, it regulates the input applied to it. A voltage regulator is an

electrical regulator designed to automatically maintain a constant voltage level. In this project,

power supply of 5V and 12V are required. In order to obtain these voltage levels, 7805 and 7812

voltage regulators are to be used. The first number 78 represents positive supply and the numbers

05, 12 represent the required output voltage levels.

3.3 Microcontrollers:

Microprocessors and microcontrollers are widely used in embedded systems products.

Microcontroller is a programmable device. A microcontroller has a CPU in addition to a fixed

amount of RAM, ROM, I/O ports and a timer embedded all on a single chip. The fixed amountof on-chip ROM, RAM and number of I/O ports in microcontrollers makes them ideal for many

applications in which cost and space are critical.

The Intel 8051 is Harvard architecture, single chip microcontroller (C) which was developed by

Intel in 1980 for use in embedded systems. It was popular in the 1980s and early 1990s, but

today it has largely been superseded by a vast range of enhanced devices with 8051-compatible

processor cores that are manufactured by more than 20 independent manufacturers including

Atmel, Infineon Technologies and Maxim Integrated Products.

8051 is an 8-bit processor, meaning that the CPU can work on only 8 bits of data at a time. Data

larger than 8 bits has to be broken into 8-bit pieces to be processed by the CPU. 8051 is available

in different memory types such as UV-EPROM, Flash and NV-RAM.

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Features of AT89S52:

8K Bytes of Re-programmable Flash Memory.

RAM is 256 bytes.

4.0V to 5.5V Operating Range.

Fully Static Operation: 0 Hz to 33 MHzs

Three-level Program Memory Lock.

256 x 8-bit Internal RAM.

32 Programmable I/O Lines.

Three 16-bit Timer/Counters.

Eight Interrupt Sources.

Full Duplex UART Serial Channel.

Low-power Idle and Power-down Modes.Interrupt recovery from power down mode.

Watchdog timer.

Dual data pointer.

Power-off flag.

Fast programming time.

Flexible ISP programming (byte and page mode).

Description:

The AT89s52 is a low-voltage, high-performance CMOS 8-bit microcomputer with 8K bytes of

Flash programmable memory. The device is manufactured using Atmels high

density nonvolatile memory technology and is compatible with the industry-

standard MCS-51 instruction set. The on chip flash allows the program memory

to be reprogrammed in system or by a conventional non volatile memory

programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip,

the Atmel AT89s52 is a powerful microcomputer, which provides a highlyflexible and cost-effective solution to many embedded control applications.

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In addition, the AT89s52 is designed with static logic for operation down to zero frequency and

supports two software selectable power saving modes. The Idle Mode stops the

CPU while allowing the RAM, timer/counters, serial port and interrupt system to

continue functioning. The power-down mode saves the RAM contents but freezes

the oscillator disabling all other chip functions until the next hardware reset.

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Pin description:

Vcc Pin 40 provides supply voltage to the chip. The voltage source is +5V.

GND Pin 20 is the ground.

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Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight

TTL inputs. When 1s are written to port 0 pins, the pins can be used as high

impedance inputs. Port 0 can also be configured to be the multiplexed low-order

address/data bus during accesses to external program and data memory. In this

mode, P0 has internal pull-ups.

Port 0 also receives the code bytes during Flash programming and outputs the code bytes during

Program verification. External pull-ups are required during program verification.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can

sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulledhigh by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that

are externally being pulled low will source current (IIL) because of the internal

pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2

external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX),

respectively, as shown in the following table.

Port 1 also receives the low-order address bytes during Flash programming and verification.

Port 2Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can

sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled

high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that

are externally being pulled low will source current (IIL) because of the internal

pull-ups.

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Port 2 emits the high-order address byte during fetches from external program memory and

during accesses to external data memory that uses 16-bit addresses (MOVX @

DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s.

During accesses to external data memory that uses 8-bit addresses (MOVX @

RI), Port 2 emits the contents of the P2 Special Function Register. The port also

receives the high-order address bits and some control signals during Flash

programming and verification.

Port 3

Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can

sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled

high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that

are externally being pulled low will source current (IIL) because of the pull-ups.

Port 3 receives some control signals for Flash programming and verification.

Port 3 also serves the functions of various special features of the AT89S52, as shown in the

following table.

RST

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Reset input A high on this pin for two machine cycles while the oscillator is running resets the

device. This pin drives high for 98 oscillator periods after the Watchdog times

out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this

feature. In the default state of bit DISRTO, the RESET HIGH out feature is

enabled.

ALE/PROG

Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during

accesses to external memory. This pin is also the program pulse input (PROG)

during Flash programming.

In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be

used for external timing or clocking purposes. Note, however, that one ALE pulse

is skipped during each access to external data memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set,

ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is

weakly pulled high. Setting the ALE-disable bit has no effect if the

microcontroller is in external execution mode.

PSENProgram Store Enable (PSEN) is the read strobe to external program memory. When the

AT89S52 is executing code from external program memory, PSEN is activated

twice each machine cycle, except that two PSEN activations are skipped during

each access to external data memory.

EA/VPP

External Access Enable EA must be strapped to GND in order to enable the device to fetch

code from external program memory locations starting at 0000H up to FFFFH.

Note, however, that if lock bit 1 is programmed, EA will be internally latched on

reset.

EA should be strapped to VCC for internal program executions. This pin also receives the 12-

volt programming enable voltage (VPP) during Flash programming.

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XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be

configured for use as an on-chip oscillator. Either a quartz crystal or ceramic

resonator may be used. To drive the device from an external clock source,

XTAL2 should be left unconnected while XTAL1 is driven. There are no

requirements on the duty cycle of the external clock signal, since the input to the

internal clocking circuitry is through a divide-by-two flip-flop, but minimum and

maximum voltage high and low time specifications must be observed.

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Special Function Registers

A map of the on-chip memory area called the Special Function Register (SFR) space is shown in

the following table.

It should be noted that not all of the addresses are occupied and unoccupied addresses may not

be implemented on the chip. Read accesses to these addresses will in general

return random data, and write accesses will have an indeterminate effect.

User software should not write 1s to these unlisted locations, since they may be used in future

products to invoke new features. In that case, the reset or inactive values of the

new bits will always be 0.

Timer 2 Registers:Control and status bits are contained in registers T2CON and T2MOD for Timer 2. The register

pair (RCAP2H, RCAP2L) is the Capture/Reload register for Timer 2 in 16-bit

capture mode or 16-bit auto-reload mode.

Interrupt Registers:

The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the

six interrupt sources in the IP register.

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Dual Data Pointer Registers:

To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer

Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H

and 85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The

user should ALWAYS initialize the DPS bit to the appropriate value before

accessing the respective Data Pointer Register.

Power off Flag:

The Power off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to 1

during power up. It can be set and rest under software control and is not affected

by reset.

Memory Organization

MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes

each of external Program and Data Memory can be addressed.

Program Memory

If the EA pin is connected to GND, all program fetches are directed to external memory. On the

AT89S52, if EA is connected to VCC, program fetches to addresses 0000H

through 1FFFH are directed to internal memory and fetches to addresses 2000H

through FFFFH are to external memory.

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Data Memory

The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel

address space to the Special Function Registers. This means that the upper 128

bytes have the same addresses as the SFR space but are physically separate from

SFR space.

When an instruction accesses an internal location above address 7FH, the address mode used in

the instruction specifies whether the CPU accesses the upper 128 bytes of RAM

or the SFR space. Instructions which use direct addressing access the SFR space.

For example, the following direct addressing instruction accesses the SFR at location 0A0H

(which is P2).

MOV 0A0H, #data

The instructions that use indirect addressing access the upper 128 bytes of RAM. For example,

the following indirect addressing instruction, where R0 contains 0A0H, accesses

the data byte at address 0A0H, rather than P2 (whose address is 0A0H).

MOV @R0, #data

It should be noted that stack operations are examples of indirect addressing, so the upper 128

bytes of data RAM are available as stack space.

Watchdog Timer (One-time Enabled with Reset-out)

The WDT is intended as a recovery method in situations where the CPU may be subjected to

software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer

Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To

enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST

register (SFR location 0A6H).

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When the WDT is enabled, it will increment every machine cycle while the oscillator is running.

The WDT timeout period is dependent on the external clock frequency. There is

no way to disable the WDT except through reset (either hardware reset or WDT

overflow reset). When WDT overflows, it will drive an output RESET HIGH

pulse at the RST pin.

Using the WDT

To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register

(SFR location 0A6H). When the WDT is enabled, the user needs to service it

regularly by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The

14-bit counter overflows when it reaches 16383 (3FFFH) and this will reset the

device. When the WDT is enabled, it will increment every machine cycle while

the oscillator is running. This means the user must reset the WDT at least for

every 16383 machine cycles.

To reset the WDT, the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only

register. The WDT counter cannot be read or written. When WDT overflows, it

will generate an output RESET pulse at the RST pin. The RESET pulse duration

is 98xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it

should be serviced in those sections of code that will periodically be executed

within the time required to prevent a WDT reset.

WDT during Power-down and Idle

In Power down mode the oscillator stops, which means the WDT also stops. Thus the user does

not need to service the WDT in Power down mode.

There are two methods of exiting Power down mode:

By a hardware reset or

By a level-activated external interrupt which is enabled prior to entering Power down mode.

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When Power-down is exited with hardware reset, servicing the WDT should occur as it normally

does whenever the AT89S52 is reset. Exiting Power down with an interrupt is

significantly different.

The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought

high, the interrupt is serviced. To prevent the WDT from resetting the device

while the interrupt pin is held low, the WDT is not started until the interrupt is

pulled high. It is suggested that the WDT be reset during the interrupt service for

the interrupt used to exit Power down mode.

To ensure that the WDT does not overflow within a few states of exiting Power down, it is best

to reset the WDT just before entering Power down mode.

Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether

the WDT continues to count if enabled. The WDT keeps counting during IDLE

(WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the

AT89S52 while in IDLE mode, the user should always set up a timer that will

periodically exit IDLE, service the WDT and reenter IDLE mode. With WDIDLE

bit enabled, the WDT will stop to count in IDLE mode and resumes the count

upon exit from IDLE.

UART

The Atmel 8051 Microcontrollers implement three general purpose, 16-bit timers/ counters.

They are identified as Timer 0, Timer 1 and Timer 2 and can be independently configured to

operate in a variety of modes as a timer or as an event counter. When operating as a timer, the

timer/counter runs for a programmed length of time and then issues an interrupt request. When

operating as a counter, the timer/counter counts negative transitions on an external pin. After a

preset number of counts, the counter issues an interrupt request. The various operating modes of

each timer/counter are described in the following sections.

A basic operation consists of timer registers THx and TLx (x= 0, 1) connected in cascade to form

a 16-bit timer. Setting the run control bit (TRx) in TCON register turns the timer on by allowing

the selected input to increment TLx. When TLx overflows it increments THx; when THx

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overflows it sets the timer overflow flag (TFx) in TCON register. Setting the TRx does not clear

the THx and TLx timer registers. Timer registers can be accessed to obtain the current count or

to enter preset values. They can be read at any time but TRx bit must be cleared to preset their

values, otherwise the behavior of the timer/counter is unpredictable.

The C/T control bit (in TCON register) selects timer operation or counter operation, by selecting

the divided-down peripheral clock or external pin Tx as the source for the counted signal. TRx

bit must be cleared when changing the mode of operation, otherwise the behavior of the

timer/counter is unpredictable. For timer operation (C/Tx# = 0), the timer register counts the

divided-down peripheral clock. The timer register is incremented once every peripheral cycle (6

peripheral clock periods). The timer clock rate is FPER / 6, i.e. FOSC / 12 in standard mode or

FOSC / 6 in X2 mode. For counter operation (C/Tx# = 1), the timer register counts the negative

transitions on the Tx external input pin. The external input is sampled every peripheral cycle.

When the sample is high in one cycle and low in the next one, the counter is incremented.

Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition, the

maximum count rate is FPER / 12, i.e. FOSC / 24 in standard mode or FOSC / 12 in X2 mode.

There are no restrictions on the duty cycle of the external input signal, but to ensure that a given

level is sampled at least once before it changes, it should be held for at least one full peripheral

cycle. In addition to the timer or counter selection, Timer 0 and Timer 1 have four operating

modes from which to select which are selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1and

2 are the same for both timer/counters. Mode 3 is different.

The four operating modes are described below. Timer 2, has three modes of operation: capture,

auto-reload and baud rate generator.

Timer 0

Timer 0 functions as either a timer or event counter in four modes of operation. Timer 0 is

controlled by the four lower bits of the TMOD register and bits 0, 1, 4 and 5 of the TCON

register. TMOD register selects the method of timer gating (GATE0), timer or counter operation

(T/C0#) and mode of operation (M10 and M00). The TCON register provides timer 0 control

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functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and interrupt type

control bit (IT0).

For normal timer operation (GATE0= 0), setting TR0 allows TL0 to be incremented by the

selected input. Setting GATE0 and TR0 allows external pin INT0# to control timer operation.

Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag, generating an interrupt

request. It is important to stop timer/counter before changing mode.

Mode 0 (13-bit Timer)

Mode 0 configures timer 0 as a 13-bit timer which is set up as an 8-bit timer (TH0 register) with

a modulo-32 prescaler implemented with the lower five bits of the TL0 register. The upper three

bits of TL0 register are indeterminate and should be ignored. Prescaler overflow increments the

TH0 register.

As the count rolls over from all 1s to all 0s, it sets the timer interrupt flag TF0. The counted

input is enabled to the Timer when TR0 = 1 and either GATE = 0 or INT0 = 1. (Setting GATE =

1 allows the Timer to be controlled by external input INT0, to facilitate pulse width

measurements). TR0 is a control bit in the Special Function register TCON. GATE is in TMOD.

The 13-bit register consists of all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3 bits of

TL0 are indeterminate and should be ignored. Setting the run flag (TR0) does not clear the

registers.

Mode 0 operation is the same for Timer 0 as for Timer 1. There are two different GATE bits, one

for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).

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Mode 1 is the same as Mode 0, except that the Timer register is being run with all 16 bits. Mode

1 configures timer 0 as a 16-bit timer with the TH0 and TL0 registers connected in cascade. The

selected input increments the TL0 register.

Mode 2 (8-bit Timer with Auto-Reload)

Mode 2 configures timer 0 as an 8-bit timer (TL0 register) that automatically reloads from the

TH0 register. TL0 overflow sets TF0 flag in the TCON register and reloads TL0 with the

contents of TH0, which is preset by software.

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When the interrupt request is serviced, hardware clears TF0. The reload leaves TH0 unchanged.

The next reload value may be changed at any time by writing it to the TH0 register. Mode 2

operation is the same for Timer/Counter 1.

Mode 3 (Two 8-bit Timers)

Mode 3 configures timer 0 so that registers TL0 and TH0 operate as separate 8-bit timers. This

mode is provided for applications requiring an additional 8-bit timer or counter. TL0 uses the

timer 0 control bits C/T0# and GATE0 in the TMOD register, and TR0 and TF0 in the TCON

register in the normal manner. TH0 is locked into a timer function (counting FPER /6) and takes

over use of the timer 1 interrupt (TF1) and run control (TR1) bits. Thus, operation of timer 1 is

restricted when timer 0 is in mode 3.

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Timer 1

Timer 1 is identical to timer 0, except for mode 3, which is a hold-count mode. The following

comments help to understand the differences:

Timer 1 functions as either a timer or event counter in three modes of operation. Timer 1s

mode 3 is a hold-count mode.

Timer 1 is controlled by the four high-order bits of the TMOD register and bits 2, 3, 6 and 7 of

the TCON register. The TMOD register selects the method of timer gating (GATE1), timer or

counter operation (C/T1#) and mode of operation (M11 and M01). The TCON register provides

timer 1 control functions: overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and

interrupt type control bit (IT1).

Timer 1 can serve as the baud rate generator for the serial port. Mode 2 is best suited for this

purpose.

For normal timer operation (GATE1 = 0), setting TR1 allows TL1 to be incremented by the

selected input. Setting GATE1 and TR1 allows external pin INT1# to control timer operation.

Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating an

interrupt request.

When timer 0 is in mode 3, it uses timer 1s overflow flag (TF1) and run control bit (TR1). For

this situation, use timer 1 only for applications that do not require an interrupt (such as a baud

rate generator for the serial port) and switch timer 1 in and out of mode 3 to turn it off and on.

It is important to stop timer/counter before changing modes.


Mode 0 configures Timer 1 as a 13-bit timer, which is set up as an 8-bit timer (TH1 register)

with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register. The upper 3

bits of the TL1 register are ignored. Prescaler overflow increments the TH1 register.


Mode 1 configures Timer 1 as a 16-bit timer with the TH1 and TL1 registers connected in

cascade. The selected input increments the TL1 register.

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Mode 2 (8-bit Timer with Auto Reload)

Mode 2 configures Timer 1 as an 8-bit timer (TL1 register) with automatic reload from the TH1

register on overflow. TL1 overflow sets the TF1 flag in the TCON register and reloads TL1 with

the contents of TH1, which is preset by software. The reload leaves TH1 unchanged.

Mode 3 (Halt)

Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt Timer 1

when TR1 run control bit is not available i.e., when Timer 0 is in mode 3.

Timer 2

Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type

of operation is selected by bit C/T2 in the SFR T2CON. Timer 2 has three operating modes:

capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by

bits in T2CON. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the

TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator

periods, the count rate is 1/12 of the oscillator frequency.

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In the Counter function, the register is incremented in response to a 1-to-0 transition at its

corresponding external input pin, T2. In this function, the external input is

sampled during S5P2 of every machine cycle. When the samples show a high in

one cycle and a low in the next cycle, the count is incremented. The new count

value appears in the register during S3P1 of the cycle following the one in which

the transition was detected. Since two machine cycles (24 oscillator periods) are

required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the

oscillator frequency. To ensure that a given level is sampled at least once before it

changes, the level should be held for at least one full machine cycle.

Capture Mode

In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2

is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit

can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the

same operation, but a 1-to-0 transition at external input T2EX also causes the

current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L,

respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be

set. The EXF2 bit, like TF2, can generate an interrupt.

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Auto-reload (Up or Down Counter)

Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload

mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR

T2MOD. Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When

DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin.

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The above figure shows Timer 2 automatically counting up when DCEN = 0. In this mode, two

options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up

to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the

timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L.

The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by

software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or

by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2

bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled.

Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 10-2. In this

mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes

Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This

overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded

into the timer registers, TH2 and TL2, respectively.

A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal

the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and

causes 0FFFFH to be reloaded into the timer registers.

The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit

of resolution. In this operating mode, EXF2 does not flag an interrupt.

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Baud Rate Generator

Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON. Note

that the baud rates for transmit and receive can be different if Timer 2 is used for

the receiver or transmitter and Timer 1 is used for the other function. Setting

RCLK and/or TCLK puts Timer 2 into its baud rate generator mode.

The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes

the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2Hand RCAP2L, which are preset by software.

The baud rates in Modes 1 and 3 are determined by Timer 2s overflow rate according to the

following equation.

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Programmable Clock Out

A 50% duty cycle clock can be programmed to come out on P1.0, as shown in the below figure.

This pin, besides being a regular I/O pin, has two alternate functions. It can be

programmed to input the external clock for Timer/Counter 2 or to output a 50%

duty cycle clock ranging from 61 Hz to 4 MHz (for a 16-MHz operatingfrequency).

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To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and

bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer.

The clock-out frequency depends on the oscillator frequency and the reload value

of Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following

equation.

In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar

to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a

baud-rate generator and a clock generator simultaneously. Note, however, that the

baud rate and clock-out frequencies cannot be determined independently from one

another since they both use RCAP2H and RCAP2L.

Interrupts

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The AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three

timer interrupts (Timers 0, 1, and 2) and the serial port interrupt. These interrupts

are all shown in the below figure.

Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit

in Special Function Register IE. IE also contains a global disable bit, EA, which

disables all interrupts at once. The below table shows that bit position IE.6 is

unimplemented. User software should not write a 1 to this bit position, since it

may be used in future AT89 products.

Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON.

Neither of these flags is cleared by hardware when the service routine is vectored

to. In fact, the service routine may have to determine whether it was TF2 or EXF2

that generated the interrupt, and that bit will have to be cleared in software.

The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers

overflow. The values are then polled by the circuitry in the next cycle. However,

the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the

timer overflows.

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Power saving modes of operation :

8051 has two power saving modes. They are:

1. Idle Mode

2. Power Down mode.The two power saving modes are entered by setting two bits IDL and PD in the special

function register (PCON) respectively.

The structure of PCON register is as follows.

PCON: Address 87H

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The schematic diagram for 'Power down' mode and 'Idle' mode is given as follows:

Idle Mode:

Idle mode is entered by setting IDL bit to 1 (i.e., IDL=1). The clock signal is gated off to

CPU, but not to interrupt, timer and serial port functions. The CPU status is preserved

entirely. SP, PC, PSW, Accumulator and other registers maintain their data during IDLE

mode. The port pins hold their logical states they had at the time Idle was initialized.

ALE and PSEN(bar) are held at logic high levels.

Ways to exit Idle Mode:

1. 1. Activation of any enabled interrupt will clear PCON.0 bit and hence the Idle

Mode is exited. The program goes to the Interrupt Service Routine (ISR). After RETI is

executed at the end of ISR, the next instruction will start from the one following the

instruction that enabled the Idle Mode.

2.

3. 2. A hardware reset exits the idle mode. The CPU starts from the instruction

following the instruction that invoked the Idle mode.

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Power Down Mode:

The Power Down Mode is entered by setting the PD bit to 1. The internal clock to the

entire microcontroller is stopped. However, the program is not dead. The Power down

Mode is exited (PCON.1 is cleared to 0) by Hardware Reset only. The CPU starts from

the next instruction where the Power down Mode was invoked. Port values are not

changed/ overwritten in power down mode. Vcc can be reduced to 2V in Power down

Mode. However Vcc has to be restored to normal value before Power down Mode is

exited.

Program Memory Lock Bits

The AT89S52 has three lock bits that can be left unprogrammed (U) or can be programmed (P)

to obtain the additional features listed in the table.

When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset.

If the device is powered up without a reset, the latch initializes to a random value and holds that

value until reset is activated. The latched value of EA must agree with the current logic level at

that pin in order for the device to function properly.

Programming the Flash Parallel Mode

The AT89S52 is shipped with the on-chip Flash memory array ready to be programmed. The

programming interface needs a high-voltage (12-volt) program enable signal and is compatible

with conventional third-party Flash or EPROM programmers. The AT89S52 code memory array

is programmed byte-by-byte.

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Programming Algorithm:

Before programming the AT89S52, the address, data, and control signals should be set up

according to the Flash Programming Modes. To program the AT89S52, take the following

steps:

1. Input the desired memory location on the address lines.

2. Input the appropriate data byte on the data lines.

3. Activate the correct combination of control signals.

4. Raise EA/VPP to 12V.

5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte write

cycle is self-timed and typically takes no more than 50 s. Repeat steps 1 through

5, changing the address and data for the entire array or until the end of the object

file is reached.

Data Polling:

The AT89S52 features Data Polling to indicate the end of a byte write cycle. During a write

cycle, an attempted read of the last byte written will result in the complement of

the written data on P0.7. Once the write cycle has been completed, true data is

valid on all outputs, and the next cycle may begin. Data Polling may begin any

time after a write cycle has been initiated.

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Ready/Busy:

The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.0 is

pulled low after ALE goes high during programming to indicate BUSY. P3.0 is

pulled high again when programming is done to indicate READY.

Program Verify:

If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read

back via the address and data lines for verification. The status of the individual

lock bits can be verified directly by reading them back.

Reading the Signature Bytes:

The signature bytes are read by the same procedure as a normal verification of locations 000H,

100H, and 200H, except that P3.6 and P3.7 must be pulled to a logic low. The

values returned are as follows.

(000H) = 1EH indicates manufactured by Atmel

(100H) = 52H indicates AT89S52

(200H) = 06H

Chip Erase:

In the parallel programming mode, a chip erase operation is initiated by using the proper

combination of control signals and by pulsing ALE/PROG low for a duration of

200 ns - 500 ns.

In the serial programming mode, a chip erase operation is initiated by issuing the Chip Erase

instruction. In this mode, chip erase is self-timed and takes about 500 ms. During

chip erase, a serial read from any address location will return 00H at the data

output.

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Programming the Flash Serial Mode

The Code memory array can be programmed using the serial ISP interface while RST is pulled to

VCC. The serial interface consists of pins SCK, MOSI (input) and MISO

(output). After RST is set high, the Programming Enable instruction needs to be

executed first before other operations can be executed. Before a reprogramming

sequence can occur, a Chip Erase operation is required.

The Chip Erase operation turns the content of every memory location in the Code array into

FFH. Either an external system clock can be supplied at pin XTAL1 or a crystal

needs to be connected across pins XTAL1 and XTAL2. The maximum serial

clock (SCK) frequency should be less than 1/16 of the crystal frequency. With a

33 MHz oscillator clock, the maximum SCK frequency is 2 MHz.

Serial Programming Algorithm

To program and verify the AT89S52 in the serial programming mode, the following sequence is

recommended:

1. Power-up sequence:

a. Apply power between VCC and GND pins.

b. Set RST pin to H.

If a crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to 33 MHz clock to

XTAL1 pin and wait for at least 10 milliseconds.

2. Enable serial programming by sending the Programming Enable serial instruction to

pin MOSI/P1.5. The frequency of the shift clock supplied at pin SCK/P1.7

needs to be less than the CPU clock at XTAL1 divided by 16.

3. The Code array is programmed one byte at a time in either the Byte or Page mode. The write

cycle is self-timed and typically takes less than 0.5 ms at 5V.

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4. Any memory location can be verified by using the Read instruction which returns the content

at the selected address at serial output MISO/P1.6.

5. At the end of a programming session, RST can be set low to commence normal device

operation.

Power-off sequence (if needed):

1. Set XTAL1 to L (if a crystal is not used).

2. Set RST to L.

3. Turn VCC power off.

Data Polling:The Data Polling feature is also available in the serial mode. In this mode, during a write cycle

an attempted read of the last byte written will result in the complement of the

MSB of the serial output byte on MISO.

Serial Programming Instruction Set

The Instruction Set for Serial Programming follows a 4-byte protocol and is shown in the table

given below.

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Programming Interface Parallel Mode

Every code byte in the Flash array can be programmed by using the appropriate combination of

control signals. The write operation cycle is self-timed and once initiated, will automatically time

itself to completion.

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After Reset signal is high, SCK should be low for at least 64 system clocks before it goes high to

clock in the enable data bytes. No pulsing of Reset signal is necessary. SCK

should be no faster than 1/16 of the system clock at XTAL1.

For Page Read/Write, the data always starts from byte 0 to 255. After the command byte and

upper address byte are latched, each byte thereafter is treated as data until all 256 bytes are

shifted in/out. Then the next instruction will be ready to be decoded.

3.4 GPS Technology:

The Global Positioning System (GPS) is a satellite based navigation system that sends and

receives radio signals. A GPS receiver acquires these signals and provides the user with

information. Using GPS technology, one can determine location, velocity and time, 24 hours aday, in any weather conditions anywhere in the world for free.

GPS was formally known as the NAVSTAR (Navigation Satellite Timing and Ranging). Global

Positioning System was originally developed for military. Because of its popular navigation

capabilities and because GPS technology can be accessed using small, inexpensive equipment,

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the government made the system available for civilian use. The USA owns GPS technology and

the Department of Defense maintains it.

A Brief History of Navigation Systems

Navigation can be defined as going from one place to another while logging your position

periodically and as necessary. In older times, our ancestors looked at the sky and made many

calculations to determine their location on earth. For hundreds of years, seamen used celestial

objects and this continued until the 1940s. Then, various navigation systems emerged like

DECCA, LORAN and OMEGA. However, all these required special charts and the positions

calculated were not pinpoint positions in many cases.

The GPS concept originated during the race to space between Russia and the United States.

U.S. scientists realized that they could monitor Sputniks transmissions and determine

its position in the sky by measuring the Doppler distortion of the signals frequency

between the satellite and their known position on earth. They realized that the converse

would also be true that if the satellites position was known then they could determine a

particular location on earth.

GPS satellites were first launched over 20 years ago in 1978, paid for by the American taxpayer.

However, it was not until 1993, when a full constellation of 24 satellites were deployed, that it

was considered fully operational. Early commercial applications in 1984 were ascertaining

position fixes on offshore oil rigs, and surveying, when GPS equipment was very expensive

($150K) as well as large and unwieldy.

Handheld units arrived on the scene in 1989 and their purchase price was $3,000, still not in the

price range for casual hobbyist users. However, by 1995 this barrier was crossed when handhelds

came down to $200 a unit, making it feasible for hunters, fishermen and hikers. Now GPS isintegrated into the cell phones, even though in most cases it has not been activated by the service

provider. CDMA cell sites use GPS for network synchronization. As a result of the current price

point of GPS receivers and increasing accuracy, GPS is showing up in many new personal and

business applications.

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For national security reasons, the civilian signalled was originally deliberately injected with an

error factor, referred to as selective availability (SA). In May 2000, the government turned off

SA. It should be noted that the military can jam GPS signals over a particular geographic region

if necessary for national security purposes.

How GPS works

GPS is funded by and controlled by the U. S. Department of Defense (DOD). While there

are many thousands of civil users of GPS worldwide, the system was designed for and is

operated by the U. S. military.

GPS provides specially coded satellite signals that can be processed in a GPS receiver,

enabling the receiver to compute position, velocity and time.

Four GPS satellite signals are used to compute positions in three dimensions and the time

offset in the receiver clock.

The architectural components of GPS are typically referred to as the control segment (ground

stations), the space segment (satellites) and the user segment (receivers).

Space Segment

The Space Segment of the system consists of the GPS satellites. These space vehicles

(SVs) send radio signals from space.

A minimum of 24 active satellites is required to be fully functional. These satellites are

constantly streaming data over a downlink. Their signals can be read by GPS receivers anywhere

in the world. However, the receiver must have a minimum of four satellites in view.

Buildings, terrain and electronic interference can block signal reception. The satellites vary in

age and have a lifespan of seven to twelve years and have to be replaced as they expire. Future

satellites will offer additional civilian signals. The progression of satellite series currently

operational starts with 16 II/IIA (in Block II), followed by 12 IIR. Most recently two of IIR-M

series were launched.

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Control Segment-Ground Stations

The Control Segment consists of a system of tracking stations located around the world.

There are six operational control system (OCS) monitoring stations and four ground antenna

stations. These stations track all GPS signals. Three of them are capable of uplinking to the

satellites. In other words, they both speak and listen to the satellites, updating them with regard

to clock corrections and satellite positions. They listen to the satellites to determine their health

by looking at their signal integrity and orbital position stability.

These ground control stations are all under the jurisdiction of the U.S. Department of Defense

(DoD) and are positioned around the world. The master station is located in Colorado Springs at

the Air Force base. The master station can send commands to the satellites to make orbit

adjustments, upload new software and so on.

In 2005, additional feeds from an initial set of six National Geospatial Intelligence Agency

(NGA) stations were included in the OCS data processing and the OCS data modeling was

improved to be able to better use these additional data feeds.

User Segment-Receivers

These receivers read the available satellite signals to determine a users position, velocity and

time. Underlying how these components work together is the clock and the satellites orbit. To

get an accurate position fix, a receiver sees at least four satellites. The receiver uses the time

stamp from the satellite to determine the transmission delay. Getting this information

simultaneously from a minimum of four different satellites is what enables the calculation of a

users 3-D position. Position refers to the coordinates in 3-D space in other words, not just

where one is standing, but how high. 2-D (latitude and longitude) can be determined with only 3

satellite signals.

Determining Position:

Upon taking in all available satellite signals, the receiver compares the time that the satellite sent

the signal to the time it was received for each of the available signals. Trilateralization (similar to

triangulation) then calculates the position by comparing the difference among the signals.

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Goal of the Global Positioning System

The Global Positioning System (GPS) includes 24 satellites, in circular orbits around Earth

with orbital period of 12 hours, distributed in six orbital planes equally spaced in angle.

Each satellite carries an operating atomic clock (along with several backup clocks) and emits

timed signals that include a code telling its location. By analyzing signals from at least four of

these satellites, a receiver on the surface of Earth with a built-in microprocessor can display the

location of the receiver (latitude, longitude and altitude).

Military versions decode the signal to provide position readings that are more accurate, the exact

accuracy. Civilian receivers are the approximate size of a hand-held calculator, cost a few

hundred dollars and provide a position accurate to 100 meters or so. GPS satellites are gradually

revolutionizing driving, flying, hiking, exploring, rescuing and map making.

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The goal of the Global Positioning System (GPS) is to determine the position of a person or any

object on Earth in three dimensions: east-west, north-south and vertical (longitude, latitude and

altitude). Signals from three overhead satellites provide this information. Each satellite sends a

signal that codes where the satellite is and the time of emission of the signal. The receiver clock

times the reception of each signal, then subtracts the emission time to determine the time lapse

and hence how far the signal has traveled (at the speed of light).

This is the distance the satellite was from the object when it emitted the signal. In effect, three

spheres are constructed from these distances, one sphere centered on each satellite. Thus, the

object is located at the single point at which the three spheres intersect.

Operating Principles:

The basis of the GPS technology is a set of 24 satellites that are continuously orbiting the earth.

These satellites are equipped with atomic clocks and send out radio signals as to the exact time

and their location. These radio signals from the satellites are picked up by the GPS receiver.

Once the GPS receiver locks on to four or more of these satellites, it can triangulate its location

from the known positions of the satellites.

Regarding the issue of time, UTC time is the basis of all GPS time functions and calculations.

The receiver updates itself from the atomic clocks on the satellites. It is also very important to

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understand that the receiver must know the time difference between the user location and of

Greenwich England or UTC time. This is a function in the set-up of all GPS receivers. With

many GPS manufacturers, this is referred to as Offset which is referring to the offset or

difference in time zones from the present location to UTC time.

The functionality of a receiver is dependent on the ability to receive signals from the satellites.

Certain locations such as under very thick foliage or down in the bottom of a slot canyon will

preclude the receiver from getting a good signal from enough satellites to determine the user

location. With many of the newer receivers however, these problems are minimal. All receivers

have warning messages when they are not getting sufficient signal to properly navigate.

Accuracy of GPS:

The accuracy of GPS depends on a number of factors, number of channels on the receiver,

number of satellites in view, and signal interference caused by buildings, mountains and

ionospheric disturbances. Accuracy should be within 15 meters (without SA) provided the

receiver has a clear shot at a minimum of four satellites.

There are several methods that can improve GPS accuracy. Two commonly discussed are

Differential GPS (DGPS) and Wide Area Augmentations System (WAAS). These improve

accuracy to within 1 to 3 meters. DGPS uses fixed, mounted GPS receivers to calculate the

difference between their actual known position and the calculated GPS position. This difference

is then broadcast over a local FM signal. GPS units within range of the local FM signal can

improve their position accuracy to within 1cm over short distances (but more typically 3-5

meters).

WAAS, developed and deployed by the FAA, takes this approach a step further. Today there are

25 WAAS ground stations networked together. These communicate errors back to the wide area

master station. The master station applies correction algorithms to the original GPS data stream

and sends a correction message to a geosynchronous satellite. This satellite then transmits on the

same signal as GPS satellites. This correction results in better than a 3 meter degree of accuracy.

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Position Fix vs. Waypoints:

When a reading on GPS is taken, it gives a real-time position fix. The memory on the receiver

decides whether to store that information so that the user can return to that exact location and can

be saved in memory as a waypoint. Obviously, the number of waypoints to be stored depends on

how much available memory the receiver has.

GPS Receiver Set-Up:

To be able to properly use a GPS receiver, it needs to be set-up and initialized. Set-up establishes

the basic information about the units of distance, speed, Map Datum, Navigation Grid system,

time difference from Greenwich England or UTC time, and other basics.

The users manual that comes with each GPS receiver gives detailed instructions on the process

of selecting the options for initialization and set-up. This must be done to be able to use the unit

for navigation.

Factors that affect GPS

There are a number of potential error sources that affect either the GPS signal directly or the user

ability to produce optimal results:

Number of satellites-minimum number required:

Atleast four common satellites must be tracked, the same four satellites at both the reference

receiver and rover for either DGPS or RTK solutions. Also to achieve centimeter -level

accuracy, it is necessary to have a fifth satellite for on-the fly RTK initialization. This extra

satellite adds a check on the internal calculation. Any additional satellites beyond five

provide even more checks, which is always useful.

Multipath-reflection of GPS signals near the antenna:

Multipath is simply reflection of signals similar to the phenomenon of ghosting on our

television screen. GPS signals may be reflected by surfaces near the antennae, causing error

in the travel time and therefore error in the GPS positions.

Ionosphere - change in the travel time of the signal:

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Before GPS signals reach the antenna on the earth, they pass through a zone of charged

particles called the ionosphere, which changes the speed of the signal. If the reference fixed

by the user and rover receivers is relatively close together, the effect of ionosphere tends to

be minimal. And if a lower range of GPS precisions is used, the ionosphere is not a major

consideration. However if the rover is working too far from the reference station, problems

may arise, particularly with initializing the RTK fixed solution.

Troposphere - change in the travel time of the signal:

Troposphere is essentially the weather zone of our atmosphere, and droplets of water vapour

in it can affect the speed of the signals. The vertical component of the GPS answer

(elevation) is particularly sensitive to the troposphere.

Satellite Geometry - general distribution of the satellites:

Satellite Geometry or the distribution of satellites in the sky effects the computation of the

position of the user. This is often referred to as Position Dilution of Precision (PDOP).

PDOP is expressed as a number, where lower numbers are preferable to higher numbers. The

best results are obtained when PDOP is less than about 7. PDOP is determined by the

geographic location, the time of day of working and any site obstruction, which might block

satellites. When satellites are spread out, PDOP is Low (good). When satellites are closer

together, PDOP is High (weak).

Satellite Health - Availability of Signal:

While the satellite system is robust and dependable, it is possible for the satellites to

occasionally be unhealthy. A satellite broadcasts its health status based on information from

the U.S. Department of Defense. The receivers have safeguards to protect against using data

from unhealthy satellites.

Signal Strength - Quality of Signal :

The strength of the satellite signal depends on obstructions and the elevation of the satellites

above the horizon. To the extent it is possible, obstructions between the setup GPS antennae

and the sky should be avoided. It is also suggested to watch out for satellites which are close

to the horizon, because the signals are weaker.

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Distance from the Reference Receiver :

The effective range of a rover from a reference station depends primarily on the type of

accuracy trying to achieve. For the highest real time accuracy (RTK fixed), rovers should be

within about 10-15 Km (about 6-9 miles) of the reference station. As the range exceeds this

recommended limit, it is difficult to initialize and will be restricted to RTK float solutions

(decimeter accuracy).

Radio Frequency (RF) Interference:

RF interference may sometimes be a problem both for GPS reception and the radio system.

Some sources of RF interference include:

o Radio towers

o Transmitters

o Satellite dishes

o Generators

One should be particularly careful of sources which transmit either near the GPS frequencies

(1227 and 1575 MHz) or near harmonics (multiples) of these frequencies. One should also be

aware of the RF generated by his own machines.

Loss of Radio Transmission from Base:

If, for any reason, there is an interruption in the radio link between a reference receiver and a

rover, then the rover is left with an autonomous position. It is very important to set up a

network of radios and repeaters, which can provide the uninterrupted radio link needed for

the best GPS results.

GPS Receiver:When people talk about "a GPS," they usually mean a GPS receiver. The Global Positioning

System (GPS) is actually a constellation of 27 Earth-orbiting satellites (24 in operation and

three extras in case one fails).

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A GPS receiver's job is to locate four or more of these satellites, figure out the distance to each,

and use this information to deduce its own location. This operation is based on a simple

mathematical principle called trilateration. Trilateration in three-dimensional space can be a

little tricky.

Trilateration in GPS

Global Positioning System (GPS) navigators use the mathematical technique oftrilateration to

determine user position, speed, and elevation. GPS navigators constantly receive and analyze

radio signals from GPS satellites, calculating precise distance (range) to each satellite being

tracked.

The data from a single satellite narrows position down to a large area of the earth's surface.

Adding data from a second satellite narrows position down to the region where two spheres

overlap. Adding data from a third satellite (see illustration) provides relatively accurate position.

Data from a fourth satellite (or more) enhances precision and also the ability to determine

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synchronized clocks, atomic clocks are needed not only on all the satellites, but also in the

receiver. But atomic clocks cost somewhere between $50,000 and $100,000, which makes them

a just a bit too expensive for everyday consumer use.

The Global Positioning System has a clever, effective solution to this problem. Every satellite

contains an expensive atomic clock, but the receiver itself uses an ordinary quartz clock, which it

constantly resets. In a nutshell, the receiver looks at incoming signals from four or more satellites

and gauges its own inaccuracy. In other words, there is only one value for the current time that

the receiver can use. The correct time value will cause all of the signals that the receiver is

receiving to align at a single point in space. That time value is the time value held by the atomic

clocks in all of the satellites. So the receiver sets its clock to that time value and thus has the

same time value that all the atomic clocks in all of the satellites have. The GPS receiver getsatomic clock accuracy for free.

When the distance to four located satellites is measured, four spheres that all intersect at one

point can be drawn. Three spheres will intersect even if the given numbers are way off, but four

spheres will not intersect at one point if measured incorrectly. Since the receiver makes all its

distance measurements using its own built-in clock, the distances will all be proportionally

incorrect.

The receiver can easily calculate the necessary adjustment that will cause the four spheres to

intersect at one point. Based on this, it resets its clock to be in sync with the satellite's atomic

clock. The receiver does this constantly whenever it's on, which means it is nearly as accurate as

the expensive atomic clocks in the satellites.

In order for the distance information to be of any use, the receiver also has to know where the

satellites actually are. This isn't particularly difficult because the satellites travel in very high and

predictable orbits. The GPS receiver simply stores an almanac that tells it where every satellite

should be at any given time. Things like the pull of the moon and the sun change the satellites'

orbits very slightly, but the Department of Defense constantly monitors their exact positions and

transmits any adjustments to all GPS receivers as part of the satellites' signals.

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The most essential function of a GPS receiver is to pick up the transmissions of at least four

satellites and combine the information in those transmissions with information in an electronic

almanac, all in order to figure out the receiver's position on Earth.

Once the receiver makes this calculation, it can provide the latitude, longitude and altitude (or

some similar measurement) of its current position. To make the navigation more user-friendly,

most receivers plug this raw data into map files stored in memory.

A standard GPS receiver will not only place the user on a map at any particular location, but will

also trace the path across a map as the user moves. If a receiver is left on, it can stay in constant

communication with GPS satellites to see how the user location is changing. With this

information and its built-in clock, the receiver can give several pieces of valuable information:

How far the person have travelled (odometer)

How long he has been traveling

The current speed (speedometer)

The average speed

The estimated time of arrival at the destination if he maintains the current speed.

GPS ApplicationsOne of the most significant and unique features of the Global Positioning Systems is the fact that

the positioning signal is available to users in any position worldwide at any time. With a fully

operational GPS system, it can be generated to a large community of likely to grow as there are

multiple applications, ranging from surveying, mapping and navigation to GIS data capture. The

GPS will soon be a part of the overall utility of technology.

There are countless GPs applications, a few important ones are covered in the following section.

Surveying and Mapping

The high precision of GPS carrier phase measurements, together with appropriate adjustment

algorithms, provides an adequate tool for a variety of tasks for surveying and mapping. Using

DGPs methods, accurate and timely mapping of almost anything can be carried out. The GPS is

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used to map cut blocks, road alignments, and environmental hazards such as landslides, forest

fires, and oil spills. Applications, such as cadastral mapping, needing a high degree of accuracy

also can be carried out using high grade GPS receivers. Continuous kinematic techniques can be

used for topographic surveys and accurate linear mapping.

Navigation

Navigation using GPS can save countless hours in the field. Any feature, even if it is under

water, can be located up to one hundred meters simply by scaling coordinates from a map,

entering waypoints and going directly to the site. Examples include road intersections, corner

posts, plot canters, accident sites, geological formations etc. GPS navigation in helicopters, in

vehicles, or in a ship can provide an easy means of navigation with substantial savings.

Remote Sensing and GIS

It is also possible to integrate GPS positioning into remote-sensing methods such as

photogrammetry and aerial scanning, magnetometry and video technology. Using DGPS or

kinematic techniques, depending upon the accuracy required, real time or post-processing will

provide positions for the sensor which can be projected to the ground, instead of having ground

control projected to an image. GPS are becoming very effective tools for GIS data capture.

The GIS user community benefits from the use of GPS for locational data capture in various GIS

applications. The GPS can easily be linked to a laptop computer in the field, and, with

appropriate software, users can also have all their data on a common base with every little

distortion. Thus GPS can help in several aspects of construction of accurate and timely GIS

databases.

Geodesy

Geodetic mapping and other control surveys can be carried out effectively using high-grade GPs

equipment. Especially when helicopters were used or when the line of sight is not possible, GPS

can set new standards of accuracy and productivity.

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Mode Selection

M1 M0 Mode Operating Mode

0 0 0 13-bit timer mode

8-bit timer/counter THx with TLx as 5-bit prescaler

0 1 1 16-bit timer mode

16-bit timer/counters THx and TLx are cascaded

1 0 2 8-bit auto reload timer/counter

THx holds a value that is to be reloaded into TLx each time

it overflows

1 1 3 Split timer mode

The mode used here to generate a time delay is MODE 2. This mode 2 is an 8-bit timer and

therefore it allows only values of 00H to FFH to be loaded into the timers register TH. After TH

is loaded with the 8-bit value, the 8051 give a copy of it to TL. When the timer starts, it starts to

count up by incrementing the TL register. It counts up until it reaches its limit of FFH. When it

rolls over from FFH to 00H, it sets high the TF (timer flag). If Timer 0 is used, TF0 goes high

and if Timer 1 is used, TF1 goes high. When the TL register rolls from FFH to 0 and TF is set to

1, TL is reloaded automatically with the original value kept by the TH register.

Asynchronous and Synchronous Serial Communication

Computers transfer data in two ways: parallel and serial. In parallel data transfers, often 8 or

more lines are used to transfer data to a device that is only a few feet away. Although a lot of

data can be transferred in a short amount of time by using many wires in parallel, the distance

cannot be great. To transfer to a device located many meters away, the serial method is best

suitable.

In serial communication, the data is sent one bit at a time. The 8051 has serial communication

capability built into it, thereby making possible fast data transfer using only a few wires.

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The fact that serial communication uses a single data line instead of the 8-bit data line instead of

the 8-bit data line of parallel communication not only makes it cheaper but also enables two

computers located in two different cities to communicate over the telephone.

Serial data communication uses two methods, asynchronous and synchronous. The synchronous

method transfers a block of data at a time, while the asynchronous method transfers a single byte

at a time. With synchronous communications, the two devices initially synchronize themselves to

each other, and then continually send characters to stay in sync. Even when data is not really

being sent, a constant flow of bits allows each device to know where the other is at any given

time. That is, each character that

obstacle detecting guiding vehicle using gps

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