o ssvv72014
TRANSCRIPT
8. Storage Management
11/15/2014 SDM SVV OS 1
Mr. S. V. Viraktamath
Dept of E&CE,
SDMCT, Dharwad
Storage Management
Overview, Main memory management-
Background, Swapping, Contiguous allocation,
Paging, Segmentation, Segmentation with
paging.
11/15/2014 SDM SVV OS 2
CPU scheduling
• Recall what has been discussed in CPU
scheduling chapter
• We must keep several processes in memory;
that is, we must share memory
• We discuss various ways to manage memory.
• Algorithms/Approach – Each has its own
advantages and disadvantages.
11/15/2014 SDM SVV OS 3
Background
• How the program is executed? / Instructions
• The CPU fetches instructions from memory -
program counter.
• Instruction cycle?
• Example 8085 LDA addr instruction.
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Background
• Program must be brought (from disk) intomemory -for it to be run
• CPU can access directly- Main memory andregisters.
• Register access in one CPU clock (Mov a,b)
• Main memory can take many cycles. (STA Addr)
• Cache sits between main memory and CPUregisters.
• Protection of memory required to ensure correctoperation.
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Mov a,b OFSTA Addr OF, MR, MR, MW
8085 SVV EC SDMCET 6
Timing diagram for memory read operation
clk
T1 T2 T3
Memory addressA15-A8
ALE
AD0-AD7
IO/M, s1,s0
IO/M=0, S1=1, S0=0
A7-A0 Data from Memory
RD
8085 SVV EC SDMCET 7
clk
T1 T2 T3
Memory addressA15-A8
ALE
AD0-AD7
IO/M, s1,s0
IO/M=0, S1=1, S0=0
A7-A0Data from CPU
WR
Memory Write
8085 SVV EC SDMCET 8
Timing diagram for op-code fetch
clk
T1 T2 T3
Memory addressA15-A8
ALE
AD0-AD7
IO/M, s1,s0
IO/M=0, S1=1, S0=0
A7-A0 Op-code
RD
T4
Unspecified
Memory addr
8085 SVV EC SDMCET 9
Timing diagram for op-code fetch, Memory read, Mem write
clk
A15-A8
ALE
AD0-AD7
IO/M, s1,s0
RD
T1 T2 T3
Memory address
IO/M=0,S1=1,S0=0
A7-A0 Op-code
T4
Unspecified
Memory addr
T1 T2 T3
Memory address
IO/M=0,S1=1,S0=0
A7-A0 Data from Memory
T1 T2 T3
Memory address
IO/M=0,S1=1,S0=0
A7-A0 Data from CPU
• Main memory is too small-the computer
system must provide secondary storage.
• A file is a collection of related information
defined by its creator.
• Memory consists of a large array of words or
bytes, each with its own address.
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Address Binding
• Usually pgms in sec storage. Must be brought
to main mem- execution.
• Process may be moved between sec to main
mem depends on memory management use.
• The collection of processes on the disk that is
waiting to be brought into memory for
execution forms the input queue.
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Address Binding
• Address space of the computer starts at 00000.
• A user program will go through several steps-
being executed (Figure 9.1). (C programs)
• Addresses may be represented in different
ways during these steps.
• Addresses in the source program are generally
symbolic. Ex. Count. (Variables, labels)
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Address Binding
• Address space of the computer starts at 00000.
• A user program will go through several steps-
being executed (Figure 9.1). (C programs)
• Addresses may be represented in different
ways during these steps.
• Addresses in the source program are generally
symbolic. Ex. Count. (Variables, labels)
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Multistep Processing of a User Program
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• A compiler will typically bind these symbolicaddresses to re-locatable addresses.– such as 14 bytes from the beginning of this module
• The linkage editor or loader will in turn bindthese re-locatable addresses to absolute addresses.
– such as 74014
• The binding of instructions and data to memory addresses can be done at
– Compile time
– Load time
– Execution time
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Base and Limit Registers
• A pair of base and limit registers define the
logical address space
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Logical vs. Physical Address Space
• What is u r name?
• An address generated by the CPU is
commonly referred to as a logical address.
• An address seen by the memory unit - physical
address.
• The logical address referred to as a virtual
address.
• The set of all logical addresses generated by a
program is a logical-address space.
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• The set of all physical addresses corresponding
to these logical addresses is a physical-
address space.
• The virtual to physical addresses is done by a
hardware device called the memory-
management unit (MMU). (Many schemes)
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Memory-Management Unit (MMU)
• In MMU scheme, the value in the relocation
register is added to every address generated by
a user process at the time it is sent to memory
• The user program deals with logical addresses;
it never sees the real physical addresses.
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Dynamic relocation using a relocation register
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Short Name
Dynamic Loading
• So far-the size of a process is limited to the
size of physical memory.
• To obtain better memory-space utilization -
can use dynamic loading.
• A routine is not loaded until it is called.
• Main pgm loaded in main mem -routines are
kept on disk.
• Advantage of dynamic loading - unused
routine is never loaded.
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Dynamic Linking
• Linking postponed until execution time.
• Small piece of code, stub, used to locate the
appropriate memory-resident library routine.
• Stub replaces itself with the address of the
routine, and executes the routine.
• Dynamic linking is particularly useful for
libraries.
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Overlays
• Keep in memory only those instructions and
data that are needed at any given time.
• Needed when process is larger than amount of
memory allocated to it.
• Implemented by user, no special support
needed from operating system, programming
design of overlay structure is complex.
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Overlays
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Mem150KBPass 1130KBPass2140KB
Swapping
• A multiprogramming environment with a
round-robin CPU-scheduling algorithm.
• Quantum expires -memory manager -swap out
the process - swap in another (Figure).
• Memory manager can swap processes fast
enough that some processes will be in memory
• Priority-based scheduling algorithms -higher-
priority process arrives.
• The backing store is commonly a fast disk.
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Schematic View of Swapping
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Contiguous Memory Allocation
• Main memory usually - two partitions:– Resident operating system, usually held in low
memory with interrupt vector
– User processes then held in high memory
• Relocation registers used to protect user processesfrom each other, and from changing operating-system code and data– Base register contains value of smallest physical
address
– Limit register contains range of logical addresses –each logical address must be less than the limit register
– MMU maps logical address dynamically
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HW address protection with base and limit registers
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Memory Allocation
• Simplest method-divide memory into several
fixed-sized partitions.
• Each partition -exactly one process.
• Partition is free -select from-input queue and is
loaded into the free partition.
• Was originally used by the IBM 0S/360
operating system (called MFT) – Not in use
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• Initially - all memory is available for user
processes- considered as- one large a hole.
• When a process terminates - releases memory.
• At any given time, we have a list of available
block sizes and the input queue.
• If hole is not large enough to hold that process-
wait.
• A set of holes, of various sizes, is scattered
throughout memory at any given time.
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OS
process 5
2K
process 2
3K
process 10
5k
Process 1
7k
Contiguous Memory Allocation
• If the hole is too large-split into two- One part
is allocated to the process- other to the OS
• Process terminates - it releases its block of
memory.
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OS
process 5
process 8
process 2
OS
process 5
process 2
OS
process 5
process 2
OS
process 5
process 9
process 2
process 9
process 10
• If the new hole is adjacent to other holes, these
adjacent holes are merged to form one larger
hole.
• How to satisfy a request of size n from a list of
free holes
– First fit
– Best fit
– Worst fit
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Dynamic Storage-Allocation Problem
• First-fit: Allocate the first hole that is big
enough
• Best-fit: Allocate the smallest hole that is bigenough; must search entire list, unless orderedby size
– Produces the smallest leftover hole
• Worst-fit: Allocate the largest hole; must alsosearch entire list
– Produces the largest leftover hole
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Example
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OS
process 5
2K
process 2
3K
process 10
5k
Process 1
7k
1k is Needed•First fit•Best fit•Worst fit
2.5k is Needed•First fit•Best fit•Worst fit
• Neither first fit nor best fit is clearly better in
terms of storage utilization.
• First fit is generally faster.
• Algorithms -suffer from external fragmentation.
• External fragmentation = when enough total
memory space exists to satisfy a request, but it
is not contiguous.
• Ex. Program needs 10k, How much total free
space in memory?
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OS
process 5
2K
process 2
3K
process 10
5k
Process 1
7k
• A hole of 18,464 bytes - the next process
requests 18,462 bytes
• If allocate exactly - left with a hole of 2 bytes.
• Overhead to keep track of this hole –larger.
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Fragmentation • External Fragmentation – total memory space
exists to satisfy a request, but it is not contiguous.
• Internal Fragmentation – allocated memory may
be slightly larger than requested memory; this size
difference is memory internal to a partition, but not
being used.
• Reduce external fragmentation by compaction
– Shuffle memory contents to place all free memory
together in one large block.
– Compaction is possible only if relocation is dynamic,
and is done at execution time.
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Paging
• Paging is a memory-management scheme -
permits -noncontiguous.
• Divide physical memory into fixed-sized
blocks called frames (size is power of 2,
between 512 bytes and 8,192 bytes)
• Divide logical memory into blocks of same
size called pages
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Paging
• Os - Keep track of all free frames.
• To run a program of size n pages, need to find
n free frames and load program.
• Set up a page table to translate logical to
physical addresses.
• Internal fragmentation.
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Paging
• Every address generated by the CPU is dividedinto two parts: a page number (p) and a pageoffset (d).
• The page number is used as an index into apage table.
– Page number (p) – used as an index into a pagetable which contains base address of each page inphysical memory
– Page offset (d) – combined with base address todefine the physical memory address that is sent tothe memory unit
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Address Translation Scheme
• For given logical address space 2m and page size 2n
• where p is an index into the page table and d is the displacement within the page.
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page number page offset
p dm - n n
Paging Hardware
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No of bits will be same?
• Consider the memory using a
page size of 4 bytes and a
physical memory of 32 bytes (8
frames)
• How the user's view of memory
can be mapped into physical
memory?
• Logical address 0 is page 0,
offset 0.
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Frame 1
Frame 2
Frame 3
Frame 4
Frame 5
Frame 6
Frame 7
Frame 8
Paging Model of Logical and Physical Memory
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page size of 4 bytes physical memory of 32 bytes
Paging Example
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32-byte memory and 4-byte pages
Paging Example32-byte memory and 4-byte pages
Indexing into the page table, we find that page 0 is in frame 5. Thus, logical address 0 (a) maps to physical address 20 =( (5 x 4) + 0).
0000
0100
1000
1100
10100
Paging Example32-byte memory and 4-byte pages
Logical address 3 Physical address?Logical address 4 Physical address?
0000
0100
1000
1100
10100
Paging Example32-byte memory and 4-byte pages
Logical address 3 (page 0, offset 3) maps to physical address 23 (= (5 x 4) + 3)).
Page 00 d=11 ; Frame=101 d=11adr=23
0000
0100
1000
1100
10100
Paging Example32-byte memory and 4-byte pages
Logical address 4 is page 1, offset 0; Physical Address24 (= (6 x 4) + 0).
Page 01 d=00; Frame= 110, d=00Addr 24
0000
0100
1000
1100
10100
Paging Example32-byte memory and 4-byte pages
Logical address 13 maps to physical address ?
0000
0100
1000
1100
10100
Logical address 13 is page 3, offset 1; Physical Address24 (= (2 x 4) + 1).
Page 11 d=01; Frame= 010, d=01Addr 09
• Every logical address is bound by the paging
hardware to some physical address.
• Using paging is similar to using a table of base
registers.
• When a paging scheme used-no external
fragmentation
• Any free frame can be allocated to a process
that needs it.
• we may have some internal fragmentation!
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• If pages are 2,048 bytes, a process of 72,766
bytes would need 35 pages plus 1,086 bytes.
• It would be allocated 36 frames, resulting in an
internal fragmentation of 2048 - 1086 = 962 bytes.
• worst case- process need n pages plus one
byte.
• It-allocated n+1 frames, resulting in an internal
fragmentation of almost an entire frame.
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• Overhead is involved in each page-table entry,
and this overhead is reduced as the size of the
pages increases.
• If the process requires n pages, at least n
frames must be available in memory.
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Free Frames
Before allocation After allocation
• User program views that memory as one singlecontiguous space, containing only this oneprogram.
• In fact, the user program is scatteredthroughout physical memory.
• Logical to physical adr-mapping is hiddenfrom the user and is controlled by theoperating system. (God)
• It has no way of addressing memory outside of its page table.
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• OS allocate a page table for each process.
• Page table may be implemented as a set of
dedicated registers. (up to 256 entries)
• Instructions to load or modify the page-table
registers are – privileged.
• If the page table is very large? Using reg is not
feasible.
• The page table is kept in main memory. Adr?
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Implementation of Page Table
• Page-table base register (PTBR) points to the
page table
• Page-table length register (PTLR) indicates
size of the page table
• To access data/Instruction; the no of mem
access needed 1 or 2?
• In this scheme every data/instruction access
requires two memory accesses. One for the
page table and one for the data/instruction.
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• The two memory access problem can be
solved by the use of a special fast-lookup
hardware cache called associative memory or
translation look-aside buffers (TLBs)
• When the associative memory is presented
with an item, it is compared with all keys
simultaneously.
• The TLB contains only a few of the page-table
entries.
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• Logical address is generated by the CPU, its
page number is presented to the TLB.
• If the page number is found, its frame number
is immediately available- used.
• If the page number is not in the TLB?
• A memory reference to the page table must be
made.
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Paging Hardware With TLB
• Add the page number and frame number to theTLB (New/ Was not in TLB)
• If TLB is full of entries- Replace one.
• Replacement policies-LRU to Random
• The percentage of times that a particular pagenumber is found in the TLB is called the hitratio.
• An 80-percent hit ratio - we find the desiredpage number in the TLB 80 percent of thetime.
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Memory Protection
• Memory protection - protection bits that are
associated with each frame.
• Normally, these bits are kept in the page table.
• One bit can define a page to be read-write or
read-only.
• An attempt to write to a read-only page causes
a hardware trap to the OS.
• Separate protection bits for each kind of access
–Read only execute only….
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• One more bit is generally attached to each
entry in the page table: a valid-invalid bit.
• If this bit is set to "valid,“ -indicates that the
associated page is in the process' logical-
address space- Legal.
• Illegal addresses are trapped by using the
valid-invalid bit.
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Valid (v) or Invalid (i) Bit In A Page Table
Shared Page
• Adv of paging is possibility of sharing
common code-Ex Timesharing many are using
text editor
– (150kcodes+50Kdata*40 users=8000KB).
– With sharing (150K+50K*40=2150K)
• Réentrant code (or pure code/Read-only)-
never changes during execution.
• Thus, two or more processes can execute the
same code (Data differs).
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Shared Pages Example
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Structure of the Page Table
• IF a page table itself becomes excessively
large - A two-level page-table scheme.
• The page table itself is also paged -Fig
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Two-Level Page-Table Scheme
Segmentation
• Memory-management scheme that supports
user view of memory.
• The user's view of memory is not the same as
the actual physical memory.
• How you think of a program when you are
writing it
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Segmentation• A program is a collection of segments.
• A segment is a logical unit such as:
main program,
procedure,
function,
object,
local variables, global variables,
common block,
stack,
symbol table, arrays
Ex. 8086- 4 segments-DS,CS,SS,ES
User’s View of a Program
Logical View of Segmentation
1
3
2
4
1
4
2
3
user space physical memory space
• Segmentation is a memory-management
scheme that supports -user view of memory
• A logical-address space is a collection of
segments. Each segment has a name and a
length.
• The addresses specify both the segment name
and the offset within the segment.
• Logical address consists of a two tuple:
<segment-number, offset>,
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• Segment table –entry has:
– base – contains the starting physical address where
the segments reside in memory
– limit – specifies the length of the segment
• Segment-table base register (STBR) points
to the segment table’s location in memory
• Use of a segment table is illustrated in Figure
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Segmentation Hardware
• The segment base contains the starting -physical address where the segment resides inmemory
• The segment limit specifies the length of thesegment.
• The segment table is thus essentially an arrayof base-limit register pairs.
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• Ex. Five segments numbered from 0 through 4.
• Segments are stored in physical memory as
shownNext slide
• Segment table - beginning address of the
segment in physical memory (base) the length
of that segment (or limit).
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Example of Segmentation
Protection and Sharing
• Advantage of segmentation is the association
of protection with the segments.
– all entries in the segment will be used the same
way
– some segments are instructions, whereas other
segments are data.
• Another advantage of segmentation involves
the sharing of code or data.
• The sharing occurs at the segment level.
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• HW
• Segmentation with Paging (1 page)
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End of Topic storage management
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Memory
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Internet
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Memory
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• The human brain consists of about one billion neurons. Each neuron forms about 1,000 connections to other neurons, amounting to more than a trillion connections. If each neuron could only help store a single memory, running out of space would be a problem. You might have only a few gigabytes of storage space, similar to the space in an iPod or a USB flash drive. Yet neurons combine so that each one helps with many memories at a time, exponentially increasing the brain’s memory storage capacity to something closer to around 2.5 petabytes (or a million gigabytes)
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• For comparison, if your brain worked like a
digital video recorder in a television, 2.5
petabytes would be enough to hold three
million hours of TV shows. You would have to
leave the TV running continuously for more
than 300 years to use up all that storage.
• 11 terabytes, 8 or 7.2 Tera bytes.
• Another commonly cited estimate puts the
figure at closer to 100 terabytes of storage.
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End of Topic storage management
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