(nxp).1-day hands-on arm training

11/15/08

1

ARM7 Microcontrollers

1-day Hands-On ARM Training–Alexander Bashlykov

–Field Application Engineer

11/15/08

Subject/Department, Author, MMMM dd, yyyy

CONFIDENTIAL 2

15.11.08

Agenda

– General Introduction – Introduction to the ARM7 architecture– NXP LPC2000 ARM Implementation and Tools– Lunch break– Verification of Setup, Introduction to Tools– MAM, PLL, GP I/O– PWM, ADC– Serial Interfaces, SPI, I2C, UART– USB Interface

11/15/08


CONFIDENTIAL 3

15.11.08

Keil Softwarean ARM Company

Compiler– For Philips LPC900– For Philips LPC2000

Debugger– Simulator– JTAG Debugger

Evaluation Boards– For NXP LPC900– For NXP LPC2000

http://www.embeddedartists.com

11/15/08


CONFIDENTIAL 4

15.11.08

ETU NXP labTraining Class and Consulting Services

Turnkey software&hardware development

Modern equipment

Various cores & architectures

Customer support

Operating systems porting– Linux– eCOS– freeRTOS

Web site coming soon ://

11/15/08


CONFIDENTIAL 5

15.11.08

Insider’s Guide Book: How to start with LPC2000 family:

Published by Dodeca

Current Price: – 230 Rub.

With CD-ROM

Includes USB block description and programming manual.

http://www.book.dodeca.ru/books/.php

11/15/08


CONFIDENTIAL 6

15.11.08

Микроконтроллеры ARM7. Семейство LPC2000. Руководство пользователя.

Published by Dodeca

Current Price: – 420 Rub.

Contains CD-ROM

Full technical description of LPC2000 family

http://www.book.dodeca.ru/books/33044.php

11/15/08


CONFIDENTIAL 7

15.11.08

1. ARM - The Company

2. Architecture

3. Instruction Set

4. ARM7TDMI-S

5. NXP Implementation

6. Tools

7. ARM9 / LPC3000

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CONFIDENTIAL 8

15.11.08

ARM Holdings plc. (1)

*: part of NXP since 1999

Established as Advanced RISC Machines Ltd. in 1990 as a UK based joint venture between Apple Computer, Acorn Computer Group (computer manufacturer in the eighties) and VLSI Technology*

– Apple and VLSI provided funding

– Acorn supplied technology and first 12 engineers

Introduction of ARM6™ family in 1991, VLSI initial licensee

In April 1998 listed on the London Stock Exchange and Nasdaq

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CONFIDENTIAL 9

15.11.08

ARM Holdings plc. (2)

Develops the ARM range of RISC processor cores

Licenses its RISC microprocessor core and SoC IP to a network of partners; semiconductor and system companies

ARM does not manufacture silicon itself

Also licenses architectural extensions, development tools, peripheral IP and SoC solutions

ARM’s market share of the embedded RISC microprocessor market is approx. 75% and to date, ARM Partners have shipped more than one billion ARM core-based microprocessors

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CONFIDENTIAL 10

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NXP is a leader in ARM

NXP relationship with ARM Ltd. spans a decade– One of three founding partners of ARM

NXP offers the most ARM experience– Over 500 ARM designs - more than anyone else in the industry

– In Top 3 for ARM shipments worldwide

– More than a dozen ARM cores in over 7 CMOS processes

NXP is a long-term ARM licensee– Extensive license relationship provides continuous access to all architectures

– Announcing off-the-shelf ARM microcontrollers with embedded Flash

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CONFIDENTIAL 11

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2. Architecture

3. Instruction Set

4. ARM7TDMI-S


6. Tools

7. ARM9 / LPC3000

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CONFIDENTIAL 12

15.11.08

Bus Width

ARM7TDMI is a 32-bit architecture– Data pathes and ARM instructions

are 32 bits wide

– Von Neumann architecture• instructions and data use the

same 32-bit data bus

– There is a subset of 16-bit instructions (Thumb) optimized for code density

Registers

Address Register Incr.

Mult.

Shifter

ALU

Data Bus

Address Bus

InstructionDecode &GeneralControl

Data InData Out

Thumb Decom-pression

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CONFIDENTIAL 13

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Thumb Mode

Set of instructions re-coded from 32 into 16 bits– Improved code density by ~ 30%

– Saving program memory space

– Higher performance (up to 60%) when running from 16-bit wide external memory

In Thumb state only the program code is 16-bit wide– After fetching the 16-bit instructions from memory, they are de-

compressed to 32 bit instructions before they are decoded and executed

– All operations are still 32-bit operations

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CONFIDENTIAL 14

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Code size Benchmark

129.3

149.2125.1

207.4146.5150.2

123.9127.3

147.5184.7

212

183.5223227.8

145.8

121.1

100

0 50 100 150 200 250

SH

Thumb

H8S

X86

MSP430

MIPS32

68HC12

M-CORE

ST20

Mitsu16

Z80

AVR

ARM

C167

80C51

68K

V850V85068K

80C51C167

ARMAVR

Z80Mitsu16

ST20M-CORE

68HC12MIPS32

MSP430X86

H8SThumb

SH

40 kbyte “application like” code

Thumb Code Size Comparison

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CONFIDENTIAL 15

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CMX-CANopen Code Size Comparison (tested 7-Feb-05, with highest optimization level, all sizes in bytes)

Keil 8051 compilerPhilips P8xC591

Code: 10654

Const: 344

Data: 525– includes “overlay”

Stack: 128

Keil 166 compilerInfineon C167CR

Code: 11025

Const: 526

Data: 503

Stack: 512 (system)

Stack: 512 (user)

Note:These chips use very different CAN interfaces,

resulting in very different code on the driver level

Keil ARM compilerPhilips LPC2129

Code: 8512

Const: 776

Data: 503

Stack: 512

Other: 512 – CAN Rx buffer

CAN Rx ISR250 - 300 us

CAN Rx ISR5 - 6 us

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CONFIDENTIAL 16

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Data Types and Alignment

Definitions:– Word = 32 bits (four bytes) = UNSIGNED32

– Halfword = 16 bits (two bytes) = UNSIGNED16

– Byte = 8 bits = UNSIGNED8

1 2 3 4 1 2 3 4

Halfword Halfword

Word Word

Word Word

Halfword HalfwordHalfword Halfword

Byte Byte Byte Byte Byte Byte Byte Byte

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CONFIDENTIAL 17

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Processor Modes

ARM has seven operating modes– User unprivileged mode under which most applications run

– FIQ entered, when a high priority (fast) interrupt is raised

– IRQ general purpose interrupt handling

– Supervisor protected mode for the operating systementered on reset or software interrupt instruction

– System privileged mode using the same registers as user mode

– Abort used to handle memory access violations

– Undefined used to handle undefined instructions

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CONFIDENTIAL 18

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Registers (1)An ARM core has 37 registers (32-bit)

General purpose registers– 1 program counter

– 30 general purpose registers

Status registers– 1 current program status register

– 5 saved program status registers

These registers are not all accessible at the same time. The processor state and operating mode determine which registers are available to the programmer.

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CONFIDENTIAL 19

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Registers (2)

Depending on processor mode one of several banks is accessible. Each mode can access

– the program counter r15 (PC)

– a particular r13 (stack pointer SP)

– a particular r14 (subroutine link register, LR)

– a particular set of r0-r12 registers

– the current program status register (CPSR)

Privileged modes (except System mode) can also access– a particular SPSR (saved program status register)

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CONFIDENTIAL 20

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Register Bankingr0

r1

r2

r3

r4

r5

r6

r7

r8

r9

r10

r11

r12

r13 (SP)

r14 (LR)

r15 (PC)

CPSR

SPSR_undSPSR_abtSPSR_svcSPSR_irqSPSR_fiq

r13_fiq (SP)

r14_fiq (LR)

r13_irq (SP)

r14_irq (LR)

r13_svc (SP)

r14_svc (LR)

r13_abt (SP)

r14_abt (LR)

r13_und (SP)

r14_und (LR)

r9_fiq

r10_fiq

r11_fiq

r12_fiq

UndefinedAbortSupervisorIRQFIQ

User and System

Banked registers

r8_fiq

Used by SoftwareInterrupt

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CONFIDENTIAL 21

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Registers in Thumb Mode

The Thumb state register set is a subset of the ARM state set. The programmer has direct access to:

– eight general registers r0 - r7

– the program counter PC

– a Stack pointer SP

– a Link register LR

– the current program status register CPSR

In Thumb state, the high registers (r8 - r12) are not part of the standard register set. The assembly language programmer has limited access to them, but can use them for fast temporary storage

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CONFIDENTIAL 22

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Thumb vs. ARM

Thumb

Mode

r0

r1

r2

r3

r4

r5

r6

r7

r8

r9

r10

r11

r12

r13 (SP)

r14 (LR)

r15 (PC)

CPSR

SPSR

r0

r1

r2

r3

r4

r5

r6

r7

r13 (SP)

r14 (LR)

r15 (PC)

CPSR

SPSR

ARM

Mode

Thumb state

Low registers

Thumb state

High registers

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CONFIDENTIAL 23

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Program Status Register (1)

Condition Code Flags– N: Negative or less than

– Z: Zero

– C: Carry or borrow or extend

– V: Overflow

To not change reserved bits.A read-modify-write strategy should be applied to change PSR bits.

Condition code flags

N Z C V Q J I F T mode045678151623242728293031

Reserved Control bits

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CONFIDENTIAL 24

15.11.08

Program Status Register (2)

Control bits

N Z C V Q J I F T mode045678151623242728293031

ReservedCondition code flags

Interrupt Disable Bits– I: IRQ interrupts disable

– F: FIQ interrupts disable

T Bit– Thumb mode (when set)

– ARM mode (when cleared)

Mode Bits

System11111

Undefined11011

Abort10111

Supervisor10011

IRQ10010

FIQ10001

User10000

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CONFIDENTIAL 25

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Exception / Interrupt Handling

Entering an exception the ARM core– saves the address of the next instruction in the appropriate LR

– copies the CPSR into the appropriate SPSR

– sets appropriate CPSR bits• interrupt disable bits

• mode field bits

• if running in Thumb mode, enter ARM mode*

– forces PC to fetch next instruction from relevant exception vector*: all exceptions are handled in ARM mode!

r15 (PC) r14_<mode> (LR)PC + 4 or PC + 8

CPSR SPSR_<mode>

Control bits

I F T mode045678

CPSR:

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CONFIDENTIAL 26

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Exception Vectors

Vector Table

ResetUndefined Instruction

Software InterruptPrefetch Abort

Data Abort(Reserved)

IRQFIQ

0x00

0x04

0x08

0x0C

0x10

0x14

0x18

0x1C

...

Each entry is a branch instruction

with ‘always’ condition

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CONFIDENTIAL 27

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Leaving ExceptionTo leave an exception, the exception handler must

– copy SPSR back into CPSR

(automatically restoring also I, F and T)

– move contents of current LR minus offset* to PC

*: varies according to type of exception: 2, 4 or 8

r15 (PC)r14_<mode> (LR) PC - offset

CPSRSPSR_<mode>

Control bits

I F T mode045678

CPSR:

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CONFIDENTIAL 28

15.11.08

Multiple Exceptions

Exception priorities– When multiple exceptions arise at the same time, a fixed priority sytem

determines the order in which they are handled

SWI - Software Interrupt (to enter supervisor mode)

Undefined InstructionPrefetch Abort (instruction memory access cannot be completed)

IRQFIQData Abort (data memory access cannot be completed)

Reset

lowest priority

highest priority

7.6.5.4.3.2.1.

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CONFIDENTIAL 29

15.11.08


2. Architecture

3. Instruction Set

4. ARM7TDMI-S


6. Tools

7. ARM9 / LPC3000

11/15/08


CONFIDENTIAL 30

15.11.08

Instruction Set

All instructions are 32-bits long

Many instructions execute in a single cycle

Instructions are conditionally executed

ARM is a load / store architecture– Most operations are executed on registers

– Typical for RISC

Load or store multiple registers in a single instructionusing <register list>

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CONFIDENTIAL 31

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Conditional ExecutionDescriptionMnemonic

Always (normally omitted)AL

Signed less than or equalLE

Signed greater thanGT

Signed less thanLT

Signed greater than or equalGE

Unsigned lower or sameLS

Unsigned higherHI

No overflowVC

OverflowVS

Positive or zeroPL

NegativeMI

Carry Clear / Unsigned lowerCC / LO

Carry Set / Unsigned higher or sameCS / HS

Not equalNE

EqualEQ

4 bits in the operand of each instruction are used

for the condition code

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CONFIDENTIAL 32

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Implementation with conditional branch

– Compare– If condition is not true, branch to

else

• Execute “if true”

• Jump to End– Else:

• Execute “if not true”

– End:

Advantages of conditional executions

Implementation with conditional instructions

– Compare

• Conditional execute “if true”

• Conditional execute “if not true”

– End:

No jumps or branches required, better for pipelined execution

11/15/08


CONFIDENTIAL 33

15.11.08

ARM “C” and assembly code comparison:

“C” code:

if ((c==1) && (z==0)) R1=R2+(R3*8);

Assembly code:

HIADDS R1, R2, R3, LSL,#3

11/15/08


CONFIDENTIAL 34

15.11.08

Addressing Modes

In comparison to other chip architectures, only a limited number of addressing modes are provided

– Register Addressing– Indirect with Register (offset, increment)– Indirect with 2 Register (base, index)

• PC can be base register

Direct addressing is not supported

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CONFIDENTIAL 35

15.11.08

Thumb Instruction Subset

Subset of most commonly used 32-bit ARM instructions– 2 address format: destination register same as one source registers

Compressed into 16-bit wide code– Improved code density

Decompressed on execution to full 32-bit instructions– transparently

– in real-time

– no performance loss

ARM code can be combined with Thumb code for maximum flexibility

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CONFIDENTIAL 36

15.11.08

Thumb Instructions

ARM instruction set Thumb instruction set

ARM instructionARM instructionARM instructionARM instructionARM instructionARM instructionARM instruction

31 0Thumb instructionThumb instructionThumb instructionThumb instructionThumb instructionThumb instructionThumb instruction

15 0Recoding

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CONFIDENTIAL 37

15.11.08

Thumb Instruction Set (1)

Instruction Types– Branch

• Unconditional ± 2KBytes

• Conditional ± 256Bytes

• Branch with Link ± 4MBytes (2 Instructions!)

• Branch and exchange change to ARM state if Rm[0] = 0

• Branch and exchange with Link

– Data Processing• Subset of ARM data processing instructions

• Not conditionally executed (but some update flags)

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CONFIDENTIAL 38

15.11.08

Thumb Instruction Set (2)

Instruction Types– Load and Store

• Register plus 5-bit immediate addressing

• Register plus Register addressing

– Load and Store Multiple• Load / Store list of registers

• Push / Pop (ARM equivalent: STMDB SP!, <registers>)

– Exception Generating Instructions• SWI (switch to ARM mode and privileged mode)

• Breakpoint (prefetch abort, with debug monitor)

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CONFIDENTIAL 39

15.11.08

Translation of Thumb Instruction

Example: ADD Rd, # Constant

001 10 Rd 8-bit immediate15 0

Thumb code

31

000 1

Major op-code

denoting format 3

move/compare/add/sub/

with immediate value

0100 1

Minor op-code

denoting ADD

instruction

0000 8-bit immediate

Immediate

value

ARM code

1110

Always condition code

0 Rd 0 Rd

Destination and

source register

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CONFIDENTIAL 40

15.11.08

Program Counter (r15)

When the processor is executing in ARM mode– all instructions are 32 bits wide

– all instructions must be word aligned

– bits [31:2] contain the PC, bits [1:0] are zero(instructions cannot be halfword or byte aligned)

When the processor is executing in Thumb mode– all instructions are 16 bits wide

– all instructions must be halfword aligned

– bits [31:1] contain the PC, bit [0] is zero(instructions cannot be byte aligned)

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CONFIDENTIAL 41

15.11.08

ARM and Thumb Interworking

Switch between ARM mode and Thumb mode using BX instruction– In ARM state: BX<condition> Rn

– In Thumb state: BX Rn

Rnn: 0-15

0131

00131

Destinationaddress

ARM / Thumb selection0: ARM state1: Thumb state

BX

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CONFIDENTIAL 42

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So what is better:Thumb or ARM Mode?

Average code size reduction in Thumb mode: 30%– Thumb code size shrinks to 70%

After ‘decompression’, code size doubles– The ‘total’ code size for CPU to execute is 140%

Therefore ARM mode provides better performance as in total less code gets executed

– Unless bus system slows down performance…

11/15/08


CONFIDENTIAL 43

15.11.08


2. Architecture

3. Instruction Set

4. ARM7TDMI-S


6. Tools

7. ARM9 / LPC3000

11/15/08


CONFIDENTIAL 44

15.11.08

ARM7TDMI-S

The ARM7TDMI-S is based on ARM7 core– 3 stage pipeline

– Von Neumann architecture

– CPI ~1.9

– T: Thumb instruction set

– D: includes debug extensions

– M: enhanced multiplier (32x8) with instructions for 64-bit results

– I: core has EmbeddedICE logic extensions

– S: fully synthesisable (soft IP)

11/15/08


CONFIDENTIAL 45

15.11.08

The ARM7TDMI-S core uses a pipeline to increase the speed of the flow of instructions to the processor. This enables several operations to take place simultaneously

The Program Counter (PC) points tothe instruction being fetchedrather than to the instruction being executed

During normal operation- one instruction is being executed,

- its successor is being decoded,- and a third is being fetched from memory

Instruction Pipeline

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CONFIDENTIAL 46

15.11.08

Fetch

Decode

Execute

ARM

PC

PC - 4

PC - 8

Thumb

PC

PC - 2

PC - 4

3-Stage Instruction Pipeline

Instruction Fetched from Memory

Thumb only: Thumb instruction decompressed to ARM instruction

Instruction decoded

Registers read from Register Bank, Shift and ALU operations performed, Registers written back to Register Bank

11/15/08


CONFIDENTIAL 47

15.11.08

Optimal Pipelining– In this example it takes 6 clock cycles to execute 6 instructions

– All operations are on registers (single cycle instructions)

– Clock cycles per instruction (CPI) = 1

Cycle

Fetch DecodeFetch

ExecuteDecodeFetch

ExecuteDecodeFetch

ExecuteDecodeFetch

ExecuteDecodeFetch

ExecuteDecodeFetch

ExecuteDecodeFetch

ADDSUBMOVANDORREORCMPRSB

2 3 5 71 4 6 8

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CONFIDENTIAL 48

15.11.08

LDR Pipeline Example– In this example it takes 6 clock cycles to execute 4 instructions

– Clock cycles per instruction (CPI) = 1.5

2 3 5 7Cycle

1 4 6 8

Fetch Decode ExecuteFetch Decode

FetchExecuteDecodeFetch

Execute Data WriteDecodeFetch

Fetch

ExecuteDecode

ADDSUBLDRMOVANDORR

11/15/08


CONFIDENTIAL 49

15.11.08

Branch Pipeline Example

– Branches break the pipeline

– Example in ARM state

BLXX

ADDSUBMOVAND

0x80000x80040x80080x8FEC0x8FF00x8FF40x8FF8

1 2 4 6Cycle

3 5 7

Fetch Decode ExecuteFetch Decode

FetchFetch

Linkret

Decode

Adjust

FetchExecuteDecode ExecuteFetch

FetchDecode

11/15/08


CONFIDENTIAL 50

15.11.08

Example ARM Bus System

RAM16 bit wide

RAM32 bit wide

ARM core

Peripherals I / O

ROM8 bit wide

Interrupt Controller

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CONFIDENTIAL 51

15.11.08

AMBA

Advanced Microcontroller Bus Architecture– on-chip interconnect

– established, open specification

– framework for SoC designs

– enabler for IP reuse

– ‘digital glue’ that binds IP cores together

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CONFIDENTIAL 52

15.11.08

AHB and APB / VPB

Advanced High-Performance Bus– high-performance

– pipelined

– fully-synchronous backbone

– multiple bus masters

Advanced Peripheral Bus / VLSI Peripheral Bus– low-power

– non-pipelined

– simple interface

– wait support (VPB)

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CONFIDENTIAL 53

15.11.08

Example AMBA System

High-bandwidth on-chip RAM

ARM core

DMA Bus Master

High-bandwidth

Memory Interface

UART

Timer

Keypad

Display

APBAPB Bridge

RTC

I/O

AHB

11/15/08


CONFIDENTIAL 54

15.11.08

Default Usage of Bit Addressable Registers

In ARM7 implementations, bit addressable registers are typically divided into two registers

– One used for setting bits • Writing ‘1’ sets a bit, ‘0’ has no effect

– One used for clearing bits• Writing ‘1’ clears a bit, ‘0’ has no effect

Benefit– Unused bits are never written to

Drawback– No atomic bit clear and set at the same time

11/15/08


CONFIDENTIAL 55

15.11.08


2. Architecture

3. Instruction Set

4. ARM7TDMI-S


6. Tools

7. ARM9 / LPC3000

11/15/08


CONFIDENTIAL 56

15.11.08

The different cores

Low power hi-end applications, calculation

208MHz, VFP co-processor, Ultra low power options

ARM926EJ-S, LPC3000

Industrial, LCD display, hi-end266MHz, 16-bit color LCD controller, MMU, touch screen

ARM922T, BlueStreak

Industrial, motor controlLin interfaces, 80MHz - 90MIPSARM968E-S, LPC2900

Industrial, consumer, communications general purpose

LPC2000 family approach, portfolioARM7TDMI-S, LPC2000

LCD controllers, external memory

LCD controller, 80MHzARM7TDMI-S, BlueStreak

Larger applications with OS and LCD

LCD controller, MMUARM720T, BlueStreak

ApplicationsMain differentiatorCore

11/15/08


CONFIDENTIAL 57

15.11.08

NXP LPC Continuum

LPC1000 LPC2000 LPC2900

ARM Cortex-M3 ARM7TDMI-S

ARM968E-S

ARM926EJ-S

LPC3000

60-72 MHz 0-256 KB Flash 58 KB RAM Low power Ethernet USB Device CAN I2S

60-72 MHz 0 to 1MB Flash 100 KB RAM LCD controller LCD interface Ethernet USB Dev/Host/OTGCAN I2S ADC / DAC PWM

80-100 MHz 768 KB Flash 80KB RAM TCM CAN LIN PMU ADCs PWM

>200 MHz 32KB D-cache, 32KB I-Cache Up to 256KB RAM Vector Floating Point Java co-processor MMU 3V/1.8V Low Power 0.9V mode LCD controller Ethernet 10/100 USB Host/OTG I2S

Per

form

ance

, spe

ed, p

roce

ssin

g po

wer

NXP’s Cortex M3 based LPC1000 range will be introduced 2H 2008

11/15/08


CONFIDENTIAL 58

15.11.08

0.5μ 0.4μ 0.35μ 0.18μ 0.16μ 0.14μ 90n 65n 45n

Mature product linelow-cost, 3-5V OTP

LPC900 Family 3V Flash

ICN8 / ICF / ASMC

5V Flash family Foundry

LPC2000 FamilyARM7S-TDMI-STM

1.8V FlashICN8 / SSMC

NXP Embedded Flash Process Roadmap

Embedded Flash

(in development)NXP C90NV / TSMC eFlash

TSMC10/12

Process Feature Size

LPC3000 FamilyARM926EJTM

CMOS90LPTSMC10/12

CMOS65LPTSMC10/12

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CONFIDENTIAL 59

15.11.08

ARM7-based 32-bit Microcontrollers (1)

Shared system architecture– 32-bit ARM cores

– E-ICE RTM™ to support real-time debugging

– ETM™ to perform real-time tracing of the code being executed

– Vectored Interrupt Controller (ARM Prime Cell®)

All derivatives share

– high-bandwidth 128-bit Flash and on-chip programming interface

– memory map and interrupt structure

– ARM PrimeCell and NXP peripheral IP

– low-cost, high-volume production packages

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CONFIDENTIAL 60

15.11.08

0.18 µm process technology– Dual supply voltages for lowest power and easy interfacing

• Core (incl. Flash Memory): 1.8V I/Os: 3.3V

– Single supply voltage on LPC213x and LPC214x

– Advanced power management on LPC23xx/LPC24xx and LPC288x (on 0,14 µm)

– Embedded Flash• In-application programmable

• 2 transistor cell (0.78µm²), also easy implementation of on-chip E²PROM– improved reliability; further enhanced by error correction

• on-chip charge pumps for programming/erasing– down to 1.5V (reading down to 1.2V) Spec: 1.8V ± 0.15V !

• Memory Accelerator Module– enables fast ARM core to operate from slower Flash without speed penalty


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CONFIDENTIAL 61

15.11.08

Big pool of peripherals to select from for derivatives– NXP, ARM PrimeCell™ and 3rd-party IP

– Serial / Communication Interfaces• UARTs, I2C, SPI, CAN, Ethernet, USB, USB Host, HS USB, SD/MMC

– Timers• General purpose, watchdog, Capture / Compare, PWM, RTC ...

– ADC, DAC ...

Comprehensive 3rd-party development tools– ARM, Ashling, Green Hills, Hitex, Nohau, Keil, IAR, Embedded Artists

… plus many others


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CONFIDENTIAL 62

15.11.08

Portfolio

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CONFIDENTIAL 63

15.11.08

First Generation LPC2000 Family (1)

Some common features– ARM7TDMI-S core with E-ICE RTM™ / ETM™

– Operation up to 60MHz

– 32-bit timers• 2 (4 capture and 4 compare channels each)

• PWM (6 outputs)

• RTC

• Watchdog

– 2 UARTs (16C550)

– I²C (400kb/s)

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CONFIDENTIAL 64

15.11.08

First Generation LPC2000 Family (2)

-1-32-64K128K48LPC2106

14 channels 10-bit46-8K64K64LPC2109

x

x

x

x

x

x

-

-

-

-

-

-

-

Ext.

4

2

2

-

-

-

4

2

-

2

-

-

-

CAN

28 channels 10-bit11216K256K144LPC2292


28 channels 10-bit7616K-144LPC2290



28 channels 10-bit7616K-144LPC2210






1-3232K128K48LPC2105

1-3216K128K48LPC2104

SPIA/DI/ORAMFlashPinsPart

11/15/08


CONFIDENTIAL 65

15.11.08

Second Generation LPC2000 Family (1)LPC210x, LPC213x, LPC214x

3.3V Single-Voltage Supply32KHz RTC with Vbat inputBrown Out Detect, Power On ResetEnhanced user-code securityTiny Packages:

– LQFP64 (10 x 10 x 1.4 mm)

– HVQFN64 (9 x 9 x 0.85 mm)

– LQFP48 (7 x 7 x 1.4 mm)

60/70 MHz Operation from both on-chip Flash and SRAM2 I2C, 2 UARTs, 1 SPI, 1 SPI/ SSPUSB (LPC214x only)6/8/14/16-channels10-bit ADCs10-bit DAC4 Timers (Capture/Match/PWM/WDT)

32/45 I/O pins (5V tolerant)– 3.5 times faster than older I/O!

11/15/08


CONFIDENTIAL 66

15.11.08

Second Generation LPC2000 Family (2)

1114 channels 10-bit4532k+8K512K64LPC2148

1114 channels 10-bit4532k+8K256K64LPC2146


--8 channels 10-bit478K32K64LPC2131

-18 channels 10-bit4716K64K64LPC2132




1

1

-

-

-

USB






DACA/DI/ORAMFlashPinsPart

11/15/08


CONFIDENTIAL 67

15.11.08

Third generation LPC2000 family

11/15/08


CONFIDENTIAL 68

15.11.08


11No ext, DMA7058K512K100LPC2368

HS-16 bit ADC8564K1024K180LPC2888

HS-16 bit ADC8564K0K180LPC2880

Host, OTG1Ext. Bus 16bit, DAM16098K512K180LPC2458

Host, OTG1Ext. Bus 32bit, DMA16098K512K208LPC2468

Host, OTG

1

1

1

USB

1LCD Controller, 32bit ext, CAN4596K512K208LPC2478

1Minibus 8bit, DMA10458K512K144LPC2378



EthernetA/DI/ORAMFlashPinsPart

11/15/08


CONFIDENTIAL 69

15.11.08


11/15/08


CONFIDENTIAL 70

15.11.08

LPC247x Color LCD Controller

Based on the ARM PrimeCell® PL111 Single and dual panel Super Twisted Nematic (STN)

monochrome displays with 4 or 8 bit interfaces.Single and dual panel STN color displays.Thin Film Transistor (TFT) color displays.Resolution up to 1024x76815 level grey-scale, 3375 color STN and 32K color TFT display modes.1, 2 or 4 bits-per-pixel (bpp) monochrome palettes for STN displays.1, 2, 4 or 8bpp color palettes for STN and TFT displays.16 bpp direct true-color for STN and TFT displays.24 bpp direct true-color for TFT displays.Hardware Cursor support for single panel displays.Resistive Touchscreen capability by using internal ADC with port pins or external switches

http://www.standardics.nxp.com/products/lpc2000/lpc24xx/

11/15/08


CONFIDENTIAL 71

15.11.08

LCD controller performanceThe LCD controller is connected to the AHB1 bus, so it processes Frame data independently of the Ethernet (AHB2 bus) and Flash (Local bus)

Example bandwidth calculations– For 320 x 240 display: 76,800 pixels per frame ((x-bits x 76,800)/8 = # bytes/frame)– 4-bits per pixel: 38.4 Kbytes per frame – 8-bits per pixel: 76.8 Kbytes per frame– 12-bits per pixel: 115.2 Kbytes per frame– 16-bits per pixel: 153.6 Kbytes per frame

LCD refresh rate is 70 Hz = 14.3 ms per frame.For 16-bits/pixel - 153.6 Kbytes/ 14.28 ms = 10.76 Mbytes/sec

– An AHB1 transfer requires 2 clocks to transfer 4 bytes (one 32-bit word)– For a 60 MHz clock => 120 MBytes per second.

So 16-bits/pixel requires: – 10.76 MBytes/sec divided by 120 MBytes/sec = – ONLY 9% of the AHB1 bandwidth

11/15/08


CONFIDENTIAL 72

15.11.08

LPC2104/5/6 Blocks

VLSI Peripheral Bus (VPBVLSI Peripheral Bus (VPB))

Internal FlashController

FLASH

Vectored Interrupt

Controller

AHB to VPB BridgeWatchdog

TimerReal Time

Clock

AHB BusAHB BusARM Local BusARM Local Bus

External Static MemoryController (ESMC)

TCK

TMS

TDI

TDO

TRST

E-ICE ETM

ARM 7TDMI-S

AH

B B

us

Loca

l Bus

SRAMController

SRAM16/32/64k 128k

SystemFunctions

PLL

RST

X1X2

SPI

SCK

MIS

O

MO

SISS

ELUART0

2 pi

ns

UART1

8 pi

ns

Timer0

CAP

0.0-

2

MAT

0.0-

2

Timer1

CAP

1.0-

3

MAT

1.0-

3

PWM

PWM

1 - 6

GPIO

GPI

O

I2C

SCL

SDA

ADC10-bits

Inpu

ts

AVSS

AVD

D

32x

TX 0

,1..

RX

0,1.

.

CANDAC10-bits

AOU

T

V3A

Vref

VssA

48 pins

11/15/08


CONFIDENTIAL 73

15.11.08

LPC2114/24 Blocks



FLASH

Vectored Interrupt

Controller


TimerReal Time

Clock


TCK

TMS

TDI

TDO

TRST

E-ICE ETM

ARM 7TDMI-S

AH

B B

us

Loca

l Bus


SRAMController

SRAM16k 128/256k

SystemFunctions

PLL

RST

X1X2

SPI

SCK

MIS

O

MO

SISS

ELUART0

2 pi

ns

UART1

8 pi

ns

Timer0

CAP

0.0-

3

MAT

0.0-

3

Timer1

CAP

1.0-

3

MAT

1.0-

3

PWM

PWM

1 - 6

GPIO

GPI

O

I2C

SCL

SDA

ADC10-bits

4 In

puts

AVSS

AVD

D

46x

TX 0

,1..

RX

0,1.

.

CAN2x

DAC10-bits

AOU

T

V3A

Vref

VssA

64 pins

11/15/08


CONFIDENTIAL 74

15.11.08

LPC2119/29 Blocks



FLASH

Vectored Interrupt

Controller


TimerReal Time

Clock


TCK

TMS

TDI

TDO

TRST

E-ICE ETM

ARM 7TDMI-S

AH

B B

us

Loca

l Bus


SRAMController

SRAM16k 128/256k

SystemFunctions

PLL

RST

X1X2

SPI

SCK

MIS

O

MO

SISS

ELUART0

2 pi

ns

UART1

8 pi

ns

Timer0

CAP

0.0-

3

MAT

0.0-

3

Timer1

CAP

1.0-

3

MAT

1.0-

3

PWM

PWM

1 - 6

GPIO

GPI

O

I2C

SCL

SDA

ADC10-bits

4 In

puts

AVSS

AVD

D

32xCAN

TX 0

,1..

RX

0,1.

.

2x

DAC10-bits

AOU

T

V3A

Vref

VssA

2x

64 pins

11/15/08


CONFIDENTIAL 75

15.11.08

LPC2210 Blocks



FLASH

Vectored Interrupt

Controller


TimerReal Time

Clock


TCK

TMS

TDI

TDO

TRST

E-ICE ETM

ARM 7TDMI-S

AH

B B

us

Loca

l Bus


SRAMController

SRAM16k

TX 0

,1..

RX

0,1.

.

CAN

SystemFunctions

PLL

RST

X1X2

SPI

SCK

MIS

O

MO

SISS

ELUART0

2 pi

ns

UART1

8 pi

ns

Timer0

CAP

0.0-

3

MAT

0.0-

3

Timer1

CAP

1.0-

3

MAT

1.0-

3

PWM

PWM

1 - 6

GPIO

GPI

O

I2C

SCL

SDA

ADC10-bits

8 In

puts

AVSS

AVD

D

2x76x

144 pins

DAC10-bits

AOU

T

V3A

Vref

VssA

11/15/08


CONFIDENTIAL 76

15.11.08

LPC2212/14 Blocks


Vectored Interrupt

Controller


TimerReal Time

Clock


TCK

TMS

TDI

TDO

TRST

E-ICE ETM

ARM 7TDMI-S

AH

B B

us

Loca

l Bus



FLASH

SRAMController

SRAM16k 128/256k

SystemFunctions

PLL

RST

X1X2

SPI

SCK

MIS

O

MO

SISS

ELUART0

2 pi

ns

UART1

8 pi

ns

Timer0

CAP

0.0-

3

MAT

0.0-

3

Timer1

CAP

1.0-

3

MAT

1.0-

3

PWM

PWM

1 - 6

GPIO

GPI

O

I2C

SCL

SDA

ADC10-bits

8 In

puts

AVSS

AVD

D

112x

TX 0

,1..

RX

0,1.

.

CAN2x

144 pins

DAC10-bits

AOU

T

V3A

Vref

VssA

11/15/08


CONFIDENTIAL 77

15.11.08

LPC2290 Blocks


Vectored Interrupt

Controller


TimerReal Time

Clock


TCK

TMS

TDI

TDO

TRST

E-ICE ETM

ARM 7TDMI-S

AH

B B

us

Loca

l Bus


SRAMController

SRAM16k


FLASH

SystemFunctions

PLL

RST

X1X2

SPI

SCK

MIS

O

MO

SISS

ELUART0

2 pi

ns

UART1

8 pi

ns

Timer0

CAP

0.0-

3

MAT

0.0-

3

Timer1

CAP

1.0-

3

MAT

1.0-

3

PWM

PWM

1 - 6

CAN

TX 0

,1..

RX

0,1.

.

GPIO

GPI

O

I2C

SCL

SDA

ADC10-bits

8 In

puts

AVSS

AVD

D

76x 2x2x

144 pins

DAC10-bits

AOU

T

V3A

Vref

VssA

11/15/08


CONFIDENTIAL 78

15.11.08

LPC2292/94 Blocks


Vectored Interrupt

Controller


TimerReal Time

Clock


TCK

TMS

TDI

TDO

TRST

E-ICE ETM

ARM 7TDMI-S

AH

B B

us

Loca

l Bus



FLASH

SRAMController

SRAM16k 256k

SystemFunctions

PLL

RST

X1X2

SPI

SCK

MIS

O

MO

SISS

ELUART0

2 pi

ns

UART1

8 pi

ns

Timer0

CAP

0.0-

3

MAT

0.0-

3

Timer1

CAP

1.0-

3

MAT

1.0-

3

PWM

PWM

1 - 6

CAN

TX 0

,1..

RX

0,1.

.

GPIO

GPI

O

I2C

SCL

SDA

ADC10-bits

8 In

puts

AVSS

AVD

D

112x 2x2/4x

144 pins

-40 to +125°C

DAC10-bits

AOU

T

V3A

Vref

VssA

11/15/08


CONFIDENTIAL 79

15.11.08

VLSI Peripheral Bus (VPB)

MemoryAccelerator

512 KBFLASH

SRAMController

32KBSRAM

Test/Debug

TCK

TMS

TDI

TDO

Trace

TRST

Vectored Interrupt Controller


TimerReal Time

Clock

Local Bus and AHB

System Functions

X1 X2 RST

Vdd

Vss

PLL

System Clock

2x I2C

SCL

SDA

GPIO

GPI

O

SPI Port

MO

SI

MIS

OSC

K

SSEL

UART0

2 pi

ns

UART1

8 pi

ns

Timer0

CAP

0.0-

2

MAT

0.0-

2

Timer1

CAP

1.0-

3

MAT

1.0-

3

PWM

PWM

1 - 6

ARM 7TDMI-S

ADC0/1

2x8

pins

LPC2138 Block Diagram

BrownOutDetect

PowerOnReset

SSP Port

MO

SI

MIS

O

SSEL

SCK

DAC1-

10-b

it

32 kHz

Vbat

Package: LQFP64/HVQFN64

11/15/08


CONFIDENTIAL 80

15.11.08

VLSI Peripheral Bus (VPB)

MemoryAccelerator

64-512 KBFLASH

SRAMController

16-32KBSRAM

Test/Debug

TCK

TMS

TDI

TDO

ETM

TRST

VIC

AHB to VPB

BridgeWatchdog

TimerReal Time

Clock

AMBA AHB Bus

System Functions

X1 X2 RST

Vdd

Vss

PLL1System Clock

I2C 0/1

SCL

SDA

Fast I/O

GPI

O46

max

SPI Port

MO

SI

MIS

OSC

K

SSEL

UART0/1

Tx/R

X 0,

1

Timer0/1

CAP

x 8

MAT

x 8

PWM

PWM

1 - 6

ARM 7TDMI-S

ADC 0/1

6+8

pins

LPC2142/44/46/48 Block Diagram

BrownOutDetect

PowerOnReset

SSP Port

MO

SI

MIS

O

SSEL

SCK

DAC1-

10-b

it

32 kHz

Vbat

64-pin LQFP

USB 2.0 Full Speed Device

w/ DMA

PLL2USB Clock

8 KB SRAM shared w/ DMA

(LPC2148 only)

D+D-

Up_LED OR ConnectVbus

Mod

em

pins

(6)

Local Bus

11/15/08


CONFIDENTIAL 81

15.11.08

LPC2220 Blocks



FLASH

Vectored Interrupt

Controller


TimerReal Time

Clock


TCK

TMS

TDI

TDO

TRST

E-ICE ETM

ARM 7TDMI-S

AH

B B

us

Loca

l Bus


SRAMController

SRAM64k

SystemFunctions

PLL

RST

X1X2

SPI

SCK

MIS

O

MO

SISS

EL

UART02

pins

UART1

8 pi

ns

Timer0

CAP

0.0-

3

MAT

0.0-

3

Timer1

CAP

1.0-

3

MAT

1.0-

3

PWM

PWM

1 - 6

GPIO

GPI

O

I2C

SCL

SDA

ADC10-bits

8 In

puts

AVSS

AVD

D

2x76x

75MHz

TX 0

,1..

RX

0,1.

.

CAN

144 pins

DAC10-bits

AOU

T

V3A

Vref

VssA

11/15/08


CONFIDENTIAL 82

15.11.08

ETM

LPC2101/2/3 Blocks

Vectored Interrupt

Controller


VLSI Peripheral Bus (VPB)VLSI Peripheral Bus (VPB)

AHB to VPB Bridge

FastGPIO

Fast

GPI

O

WatchdogTimer

RTC Osc

Vbatt

RTCX1RTCX2

Real TimeClock

UART02

pins

UART1

8 pi

ns

2 x I2C

SCL

SDA

ADC10-bits

8 In

puts

AVS

S

AVD

DSRAM

Controller

SRAM


FLASHBootloader,RealMonitor

SPI

SCK

MIS

OM

OSI

SSEL

SPI/SSP

SCK

MIS

OM

OSI

SSEL

Timer032-bit

3 x

CA

P0

3 x

MA

T0

Timer132-bit

4 x

CA

P1

4 x

MA

T1

8/16/32Kb2/4/8Kb

TCK

TMS

TDI

TDO

TRST

E-ICE

ARM 7TDMI-S

AH

B B

us

Loca

l Bus

GPIO

GPI

O

SystemFunctions

PLL

RST

X1X2

Timer216-bit

3 x

CA

P2

3 x

MA

T2

Timer316-bit

4 x

MA

T3

70MHz

48 pins

11/15/08


CONFIDENTIAL 83

15.11.08


2. Architecture

3. Instruction Set

4. ARM7TDMI-S


6. Tools

7. ARM9 / LPC3000

11/15/08


CONFIDENTIAL 84

15.11.08

LPC2000 Development Tools Available from traditional 8-bit tool providers as well as established 32-bit providers

Low cost evaluation kits – IAR Kickstart kits with free 32K compiler– Keil evaluation kits with free 16K compiler

LPC2000Compilers,

IDEs

EvaluationBoards

RTOS

Emulators

http://arm.iniche.com/html/index.shtml

http://www.hitex.com/index.html

http://www.isystem.com/index.html

http://www.ghs.com/index.html

http://www.hitex.com/index.html

11/15/08


CONFIDENTIAL 85

15.11.08

IAR KS214x Плата разработки

ЖК интерфейс

RS232 порт для UART

Кнопки для внешних прерываний

SD card интерфейс для USB и SPI

Цена € 125.00

11/15/08


CONFIDENTIAL 86

15.11.08

Keil MCB2103 для LPC2103 и

LPC2103

Цена: $149 ($299 с ULINK)

http://www.keil.com/mcb2103/

11/15/08


CONFIDENTIAL 87

15.11.08

Keil MCB2130 для LPC213x серии

•LPC2131, LPC2132, LPC2134, LPC2136 и LPC2138•Цена: $149 ($299 с ULINK)

http://www.keil.com/mcb2130/

11/15/08


CONFIDENTIAL 88

15.11.08

Keil MCB2140 плата разработки

LPC2148 микроконтроллер

2x 9-pin D-type RS-232

8 LED статуса

Динамик на выходе ЦАП

Потенциометр на входе АЦП

SD Card интерфейс

Драйвера USB для Windows

Цена € 125.00

11/15/08


CONFIDENTIAL 89

15.11.08

Ashling ASK-2000 для LPC210x, LPC211x, LPC212x, LPC22xx

•LPC2104, LPC2105, LPC2106, LPC2114, LPC2119, LPC2124, LPC2129, LPC2210, LPC2212, LPC2214, LPC229х•Встроенный JTAG•Цена: $295 с LPC2106•Добавьте $90 для LPC2129 или LPC2294•Доступен адаптер для версий 21xx and 22xx

http://www.ashling.com/support/lpc2000/eval_kits.html

11/15/08


CONFIDENTIAL 90

15.11.08

Средства разработки EAEmbedded Artists’ QuickStart серия

– Все порты ввода-вывода доступны

– RS232 последовательный порт с ISP

– Специально для разработки прототипов

– Поставляется с большим набором программных средств. GCC based среда разработки

LPC213x/4x QuickStart Board 10M Ethernet LPC2138 QuickStart Board

Огромный выбор периферии– 100/10M Ethernet LPC2138– 10M Ethernet LPC2138– Bluetooth LPC2106– LPC2148 USB– LPC2138– LPC2132– LPC2129 CAN– LPC2106 RS232– LPC2106– LPC2103 USB– QuickStart Prototype Board

http://www.embeddedartists.com/

11/15/08


CONFIDENTIAL 91

15.11.08

JTAG интерфейс

11/15/08


CONFIDENTIAL 92

15.11.08

Интегрированные среды разработки

RealView AsIDE EWARM

Multi 2000 µVision3 CrossWorks

11/15/08


CONFIDENTIAL 93

15.11.08

ARM Compiler http://www.arm.com/devtools/soft_dev_tools?OpenDocument.

GHS Compiler http://www.ghs.com/products/arm_development.html

IAR Compiler http://www.iar.com/Products/?name=EWARM

GNU GCC

Компиляторы

http://www.arm.com/devtools/soft_dev_tools?OpenDocument

http://www.ghs.com/products/arm_development.html

http://www.iar.com/Products/?name=EWARM

11/15/08


CONFIDENTIAL 94

15.11.08

Поддержка ОСРВ

ChronOS™from InterNiche

Embedded LinuxNucleus from

Accelerated Technologya Mentor company

http://arm.iniche.com/html/products.shtml

11/15/08


CONFIDENTIAL 95

15.11.08

Application notes available on the web

http://standardics.nxp.com/support

11/15/08


CONFIDENTIAL 96

15.11.08

Sample software availables on the web

http://www.standardics.nxp.com/support/documents/?type=software

11/15/08


CONFIDENTIAL 97

15.11.08

40 NewMembers last

week

MEMBERS3645

11/15/08


CONFIDENTIAL 98

15.11.08

[email protected]

Russian language tech.support (from February 2008)

11/15/08


CONFIDENTIAL 99

15.11.08

www.standardics.nxp.com

http://ru.nxp.comwww.electronix.ru

www.keil.com

www.embeddedartists.com

http://www.standardics.nxp.com/

http://www.keil.com/

http://www.embeddedartists.com/

11/15/08


CONFIDENTIAL 100

15.11.08


2. Architecture

3. Instruction Set

4. ARM7TDMI-S


6. Tools

7. ARM9 / LPC3000

11/15/08


CONFIDENTIAL 101

15.11.08

ARM Core Applications

The ARM range of processor cores addresses various system categories

– ARM7: Embedded real-time systems• Storage, automotive, industrial and networking applications

– ARM9: Open platforms• Devices running platform operating systems including Linux, Palm OS,

Symbian OS and Windows CE

11/15/08


CONFIDENTIAL 102

15.11.08

Pipeline-Changes for ARM9TDMI

Decode

ARM decode

Reg. select

Thumb→ARM decompress

Fetch

Instruction Fetch

Execute

Reg. read Shift ALU Reg.

write

ARM7TDMI

ARM or Thumb instruction decode

Decode

ARM9TDMI

Reg. decode

Reg. read

Execute

Shift + ALUInstruction Fetch

Fetch

Instruction Fetch

Memory

Memory access

Writeback

Reg. write

CPI: ∼1.9

CPI: ∼1.5

11/15/08


CONFIDENTIAL 103

15.11.08

ARM Technology Roadmap

H

L

H

L

H

L

ApplicationsProcessor

Market

Real-TimeEmbedded

Market

MicrocontrollerMarket

ARM926EJ-S

Cortex-A8

ARM11 MPCore

ARM1176JZ(F)-S

ARM1136J(F)-S

600+ MIPS Uni-Proc

2000+ MIPS Uni-Proc

2000+ MIPS Multi-proc

600+ MIPS Uni-Proc

250+ MIPS Uni-Proc

ARM7TDMI

Cortex-M3

ARM968E-S

ARM946E-S

ARM1156T2(F)-S

ARM7TDMI

600+ MIPS Uni-Proc

150+ MIPS Uni-Proc

100+ MIPS Uni-Proc

LPC2900

Bluestreak

LPC2000

LPC1000

100+ MIPS Uni-Proc

100+ MIPS Uni-Proc

Bluestreak LPC3000

11/15/08


CONFIDENTIAL 104

15.11.08

LPC3000 Overview90nm Process

200 MHz Core

1.2V core operation

0.9V ultra low-power mode

3.3V I/O

32KB I- & D- caches

64KB SRAM

Standard E-ICE JTAG Interface

6KB Emb. Trace

320-pin TFBGA package

LPC3000 Overview

11/15/08


CONFIDENTIAL 105

15.11.08

Data and Instruction Caches

The LPC3100 has 32K I and 32K D Caches

Cache Access is single-cycle if hit

Cache is organized as 4 Ways of 8K each

11/15/08


CONFIDENTIAL 106

15.11.08

Computational Power

Simultaneous accesses allowed, for example:

– Data Cache to SRAM– Instruction Cache to DRAM– DMA to peripheral

Arbitration required only if accessing the same peripheral

Higher performance than a classic Bus master type scheme

High Performance Bus Matrix

11/15/08


CONFIDENTIAL 107

15.11.08

32 bit,104 MHz

AHB

GX175SDRAM

Ctrl

Port 2Port 3Port 4Port 0

32 bit, 104 MHzAHB Matrix

AHB slaves

NANDCtrl

AHB slaves

DMAregs

USBconfig

APB slavesAHB-2-APB

APB slavesAHB-2-APB

GPIO

SystemControlRTC

I2Cx 2

WatchdogTimer

Debug

UARTx 4

ROM16 kB

10-bitADC

KeyScan

32 bit wideexternalmemory

SRAM64 kB

SDRAMconfg

USB-OTGAHB

Master

ETBregs

InterruptController x3

AHB-2-FAB

FAB slaves

1 2 3

SPIx2

PWM

MLCNAND Ctrl

SDCard

I-TCM0 kB

I-cache32 kB

D-TCM0 kB

D-cache32 kB

MMUD-sidecontroller

I-sidecontroller

Data

ETM9ETBVFP9

ARM9EJS

USBtransceiverinterface

Instr

DMA CtrlPL080

M0

M1

Master Layer 0

High SpeedUART x3

Master/Slave connection supported by matrix

MillisecondTimer

High SpeedTimer

Slave port 0Slave port 1

Slave port 7

Slave port 3

Slave port 6

Slave port 2

Slave port 5

Bus MatrixHigh Performance Bus Matrix

11/15/08


CONFIDENTIAL 108

15.11.08

MMU and Cache Interaction

MMU RAM LCD Touch screen

USB Ethernet DMA VFP 0.9V Ultra Low Power

LPC3180 X 64KB Host/OTG X X X

LPC3180/01 X 64KB Host/OTG X X X



LPC3230 X 256KB X Host/OTG X X X

LPC3240 X 256KB Host/OTG X X X X

LPC3250 X 256KB X Host/OTG X X X X

LH7A400 X 96KB X Device X

LH7A404 X 96KB X X Host / Device X

releasedroadmap for 2008

Portfolio 32-bit microcontrollers, >100MHz

11/15/08


CONFIDENTIAL 109

15.11.08

Phytec LPC3000 Development board

• LPC3180 on board • VFP coprocessor• NAND Flash 32Mb• SDRAM 32Mb• 32 Kb EEPROM• USB OTG• 208MHz

•Price: $250

http://www.phytec.com/

11/15/08


CONFIDENTIAL 110

15.11.08

Hands-On

NXP LPC2000 Family

–Advanced ARM7TDMI Implementations

11/15/08


CONFIDENTIAL 112

15.11.08

Memory Addressing

System Control Block

Memory Accelerator Module (MAM)

General Purpose I/OPin Connect Block / External Memory Controller

• Integrated PeripheralsTimer 0 / Timer 1, PWM, RTC, Watchdog, ADC

• Vectored Interrupt Controller• Serial Communication Interfaces

UART 0 / UART 1, I²C, SPI, USB, CAN

11/15/08


CONFIDENTIAL 113

15.11.08

Memory Map

3FFF

7FFF

FFFF

*: nnnn

16KB

32KB

64KB

RAM

Memory blocks not drawn to scale!

0x0000 0000

0xFFFF FFFF

0x000m FFF**128 ... 512 KB On-Chip Non-Volatile Memory

0x4000 nnnn*

Reserved for On-Chip Memory

0.0 GB

1.0 GB

2.0 GB

3.0 GB

3.5 GB

0x3FFF FFFF0x4000 000016 / 32 / 64 KB On-Chip Static RAM


4.0 GBAHB Peripherals 0xF000 0000VPB Peripherals

Boot Block (re-mapped from On-Chip Flash)0x8000 0000

3.75 GB 0xEFFF FFFF0xE000 0000

0xC000 0000Reserved for External Memory

0x7FFF E000

7

3

1

**: m

512KB

256KB

128KB

Flash

11/15/08


CONFIDENTIAL 114

15.11.080x0

0x03 FFFF

Sector 9 64K

Sector 7 8K…

Sector 2 8k

Sector 1 8KSector 0 8K

Sector 16 8K…

Sector 10 8k

8K Boot Block

Sector 8 64K

LPC2100, 256k

0x0

0x01 FFFF


Sector 12 8K…

Sector 2 8k

Sector 1 8K

8K Boot Block

Sector 0 8K

LPC2100, 128k

Flash Memory Organization

0x0

0x07 FFFF

Sector 9 32K

Sector 7 4K...


12K Boot Block

Sector 8 32K

512k

Sector 10 32K

Sector 14 32K…

Sector 11 32k

Sector 21 32K…

Sector 15 32k

Sector 26 4K…

Sector 22 4k

0x03 FFFF

0x01 FFFF

0x00 FFFF

0x00 7FFF

0x07 CFFF

256k

128k

64k

32k

LPC213X

Graphic not to scale

11/15/08


CONFIDENTIAL 115

15.11.08

Flash Memory IAP Programming

IAP: In Application Programming

Bootloader contains flash programming routines – Erase Sectors– Write blocks (of 512 bytes)

• Re-write to blocks possible, if bits are cleared in 32 byte groups (see hands-on example)– Common entry point for IAP calls: 0x7ffffff1

During calls, all interrupts must be disabled– Note: hands-on example only disabled IRQ, not FIQ

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CONFIDENTIAL 116

15.11.08

SRAM: 8, 16, 32 or 64 KB

0x40000000

0x40003FFF

0x4000FFFF

0x4000003F

64KB SRAM

32KB SRAM

16KB SRAMRAM Int Vect

0x40007FFF

RAM Int Vect RAM Int Vect RAM Int Vect0x40001FFF

8KB SRAM

11/15/08


CONFIDENTIAL 117

15.11.08

Memory Addressing







Hands-On

Hands-On

Hands-On

Hands-On

11/15/08


CONFIDENTIAL 118

15.11.08

System Control

Includes a number of important system features– Power Control

– Memory mapping configuration

– Oscillator

– PLL

– VPB divider

– Reset (active low)

– Wakeup Timer

– External Interrupts

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CONFIDENTIAL 119

15.11.08

Power Control (1)

Power Down mode - oscillator and on-chip clocks stopped, wakeup by external interrupt

PDPCON 1

Idle mode - processor clock stopped, on-chip peripherals remain active, interrupts cause wakeup

IDLPCON 0

• Power Control Register [PCON – 0xE01FC0C0] R/W

20 uA at room temperature,

50 uA with single voltage supply

For example 5 mA with most peripherals powered down

Biggest factors: temperature, clock rates

Peripheral Clock Divider: 20%

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CONFIDENTIAL 120

15.11.08

Power Control (2)

Enable UART0PCURT0PCONP 3

Enable Timer1PCTIM1PCONP 2

Enable Timer0PCTIM0PCONP 1

Enable PWM0PCPWM0PCONP 5

Enable UART1PCURT1PCONP 4

...

Enable I2CPCI2CPCONP 7

• When disabled, peripherals are switched off to conserve power

• Power Control for Peripherals Register [PCONP – 0xE01FC0C4] R/W

Each peripheral typically below 1mA

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CONFIDENTIAL 121

15.11.08

Power Control (3)

Enable SPI0PCSP0PCONP 8

Enable RTCPCRTCPCONP 9

Enable External Memory ControllerPCEMCPCONP 11

Enable SPI1PCSPI1PCONP 10

Enable CAN Controller 1PCCAN1PCONP 13

Enable A/D-ConverterPCADPCONP 12

...




• Power Control for Peripherals Register cont'd

Acceptance Filter enabled with any CAN Controller

CAN peripheral typically below 2mA

11/15/08


CONFIDENTIAL 122

15.11.08

Boot Block

The uppermost Flash sector contains the Boot Loader– controls physical interface for programming and erasing the Flash

– supports ISP mode for initial programming of customer code

– supports In-Application Programming in a running system under the control of customer software

– buffers an entire Flash line (512 bytes) at once to keep programming time to a minimum

The Boot Loader is automatically run following reset– checks for a “Valid User Program” key to prevent running code on incorrectly programmed

devices

11/15/08


CONFIDENTIAL 123

15.11.08

Exception Vectors

Vector Table

ResetUndefined Instruction

Software InterruptPrefetch Abort

Data Abort(Reserved)

IRQFIQ

0x00

0x04

0x08

0x0C

0x10

0x14

0x18

0x1C

...

Valid user program key:Must contain a value that

ensures that the checksum of all vectors is zero

11/15/08


CONFIDENTIAL 124

15.11.08

Memory Mapping Control (1)

Re-mapping of Exception Vectors– always appear to begin at 0x0000 0000

– but can be mapped from different sources:• User Flash

– Exception Vectors are not re-mapped and reside in Flash

0x0000 0000Active Exception Vectors 0x0000 003F

On-chip Flash Memory

11/15/08


CONFIDENTIAL 125

15.11.08

0x8000 0000

• User RAM– Exception Vectors are re-mapped from RAM

Memory Mapping Control (2)• Boot Loader

– Always executed after reset. Exception Vectors re-mapped from Boot Block


On-chip User Flash Memory

Boot Loader

On-chip User RAM

0x4000 0000

Off-chip Memory

11/15/08


CONFIDENTIAL 126

15.11.08

Memory Mapping Control (3)

Re-mapping of Boot Block – mapped from top of Flash to top of on-chip memory space


On-chip User Flash Memory

On-chip User RAM

Boot Loader

2.0 GB

11/15/08


CONFIDENTIAL 127

15.11.08

Memory Mapping Overview

0x0000 0000

0xFFFF FFFF


2.0 GB

16/32/64 KB On-Chip Static RAM


AHB Peripherals

VPB Peripherals

Boot Block (re-mapped from On-Chip Flash)

Reserved for External Memory

0x00

0x3F

Active Exception Vectors

Boot Block

Exception Vector re-mapping

Boot Block re-mapping

128 KB On-Chip Non-Volatile Memory

4.0 GB

0x7FFF FFFF

0x4000 0000

11/15/08


CONFIDENTIAL 128

15.11.08

Memory Mapping Control Register

• Memory Mapping Control [MEMMAP – 0xE01FC040] R/W00: Boot Loader Mode

01: User Flash Mode (no re-mapping)

10: User RAM Mode

11: External Memory (where available)

MAP 1:0MEMMAP 1:0

Selects the memory being mapped to address zero

11/15/08


CONFIDENTIAL 129

15.11.08

Phase Locked Loop (LPC21xx/22xx)

Phase Detector

XTAL1

XTAL2 DividerValue

FOSC

Multiplier Value

FCCOcclk

pclk÷ M

VPBDivider÷ 1/2/4

÷ PCurrent

Controlled Oscillator

Oscillator

156 to 320 MHzFosc * 2 * M * P

10 to 60 MHzFosc * M

1 to 30 MHzwithout PLL

10 to 25 MHz

Default: 4

11/15/08


CONFIDENTIAL 130

15.11.08

Memory Addressing






UART 0 / UART 1, I²C, SPI, CAN

11/15/08


CONFIDENTIAL 131

15.11.08

32 bits needed with every clock

Memory access time < 17ns @ 60MHz

On-chip Memory with 0-wait States

ARM7TDMI-S is a 1-clock core– CPI of ~1.9, but many instructions execute in 1 cycle

– CPU requires one instruction per clock cycle

For highest performance

11/15/08


CONFIDENTIAL 132

15.11.08

On-chip RAM and FLASH

RAM is fast enough to supply 1 word in 1 cycle

Flash typically has access times <50 ns– Flash limits the maximum speed of the ARM core to about 20 MHz

or

– Additional wait-states required for Flash accesses

NXP Flash Architecture

– No cache (size, overhead)

– Deterministic (important for real-time control applications)

– No wait-states (performance)

11/15/08


CONFIDENTIAL 133

15.11.08

Memory Accelerator Module

Flash Memory Bank 1

Data Buffer

Branch Trail Buffer 1

Prefetch Buffer 1

128 bit

Flash Memory Bank 2

Branch Trail Buffer 2

Prefetch Buffer 2

128 bit

128 bit (2x) 128 bit (2x)

ARM7

Core

Bus

Inte

rfac

e

Local Bus

Data Bus (32 / 16 bit)

Address Bus

Selection

11/15/08


CONFIDENTIAL 134

15.11.08

Power Consumption and MAM

Enabling the MAM for low-clock applications does not bring a performance gain

However, enabling the MAM reduces the overall power consumption– Less fetches from Flash memory will be made

11/15/08


CONFIDENTIAL 135

15.11.08

Memory Addressing







Hands-On

11/15/08


CONFIDENTIAL 136

15.11.08

General Purpose I/O (1)

Pins available for GPIO:

– 48-pin devices: 32

– 64-pin devices: 46

– 144 pin devices: 76 (max.) (with external memory)

– 144 pin devices 112 (w/o external memory)

– 208 pin devices 160

Shared with

– Alternate functions of all peripherals

– Data/address bus and strobe signals for external memories

11/15/08


CONFIDENTIAL 137

15.11.08


Direction control of individual bits

Separate set and clear registers

Pin value and output register can be read separately

Slew rate controlled outputs (10 ns)

5 registers used to control I/Os

11/15/08


CONFIDENTIAL 138

15.11.08


The current state of the port pins is read from this register

Writing "1" sets pins high, writing "0" has no effect

Writing "1" sets pins low and clears corresponding bits in IOSET

Port pin direction: 0 = INPUT 1 = OUTPUT

Selects function of pins (Pin Connect Block)

IOPIN

Register

IOSET

IOCLR

IODIR

PINSEL

11/15/08


CONFIDENTIAL 139

15.11.08

Conventional GPIO Implementation Drawbacks

Conventional ARM GPIO is implemented on the APB peripheral bus

Toggling speed of the GPIO is limited due to the 3-stage pipeline, AHB bridge and the APB bus

11/15/08


CONFIDENTIAL 140

15.11.08

Understanding the slow port behavior

It takes 5 clocks to execute a port write

Total time from instruction fetch to port change is 7 clocks

Maximum achievable period is 14 clocks (cclk/14) = (60/14) = 4.28MHz

When cpu_clken_I is low indicates core is stalled

11/15/08


CONFIDENTIAL 141

15.11.08

10

Block diagram of new port configuration

11/15/08


CONFIDENTIAL 142

15.11.08

9

Improving Speed

GPIO registers are now interfaced directly to the ARM7 Local bus

Ports can now toggle every 2 clocks giving a clock period of cclk/4= 15Mhz

This is a 3.5x speed increaseEnables faster ‘soft’ peripherals

11/15/08


CONFIDENTIAL 143

15.11.08

6

Results of change (speed of writes)

FetchingWriting

DecodingE5803000ExecutingE5802000

FetchingE580500DecodingNothing

ExecutingE5803000

FetchingWriting



ExecutingE5804000

FetchingWriting



ExecutingE5805000

Port output

11/15/08


CONFIDENTIAL 144

15.11.08

Fast GPIO

Special features– GPIO registers accessed via ARM local bus in addition to conventional peripheral bus access

– Mask registers allow treating sets of port pins as a group, leaving other bits unchanged

– Local bus GPIO registers are now byte addressable

– Entire port value can be written in one instruction using the IOPIN register

11/15/08


CONFIDENTIAL 145

15.11.08

Mask Register- Advantages

Provides the capability to the user to separate the GPIO pins into groups

Any modifications to the FIOSET,FIOCLR and FIOPIN is only effected if the corresponding bits in the FIOMASK are set

Using Mask registers…

Individual I/O pins can be addressed separately

11/15/08


CONFIDENTIAL 146

15.11.08

Pin Connect Block (1)

Many on-chip functions can use I/O pins

Number of I/O-pins is limited

⇒ I/Os can be configured to adapt various functions

Pin function selection is done by Pin Connect Block

PIN

GPIOUARTTimer/Counterreserved

PINSEL0/1/2

11/15/08


CONFIDENTIAL 147

15.11.08


Pin Function Select Registers

– PINSEL0 and PINSEL1

• Configuration of P0

• Assign P0.0 ... P0.31 to GPIO or an alternate function (1 of max. 3)

– PINSEL2 (not available in 48-pin devices)

• Configuration of P1 (64/144-pin devices) and P2, P3 (144-pin devices)

• Select availability of debug and trace ports on Port1 pins

• Controls use of address/data bus and strobe pins (144-pin devices)

• Selection of additional ADC-inputs (144-pin devices)

Note: Peripherals should be connected to appropriate I/Os before activation

11/15/08


CONFIDENTIAL 148

15.11.08


• Pin Function Select Register 0 [PINSEL0 - 0xE002C000)] R/W

.........

.........

00: GPIO Port 0.10

01: RTS (UART1)

10: Capture 1.0 (Timer 1)

11: reserved

P0.10PINSEL0 21:20

Example:

11/15/08


CONFIDENTIAL 149

15.11.08

Pulse Width Modulator

Dedicated 32-bit PWM timer– similar functionality to Timer0 / Timer1

Three additional match registers for a total of 7– All PWM outputs have the same rate, which is programmable

– Allows up to 6 single edge controlled or 3 double edge controlled PWM outputs in any combination

– Single edge controlled PWM outputs all go high at the beginning of each cycle and low at a programmed time

– Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses, with edges at any location in the cycle

11/15/08


CONFIDENTIAL 150

15.11.08

Single-Edge Controlled PWM

PWM outputs all go high at the beginning of each cycle and go low on a Match

PWMx

PWMy

PWMz

Compare (Match) Value x

Compare (Match) Value yCompare (Match) Value z

Timer

Value

Match Register 0 Value

0000 0000h

11/15/08


CONFIDENTIAL 151

15.11.08

Double-Edge Controlled PWM

Double edge controlled PWM outputs can have either edge occur at any position within a cycle

PWM2

PWM4

PWM5

MR1=41, MR2=78 (PWM2)MR3=53, MR4=27 (PWM4)

MR5=65 (PWM5)

Timer

Value0000 0000h

Match Register 0 Value (100)(PWM Period)

(single-edge)

11/15/08


CONFIDENTIAL 152

15.11.08

Shadow Register 0

Match Register 0

Latch Enable 0Match

=

Control

R

S Q

EN

PWM1

R

S Q

EN

PWM2

=

=

Enable

Enable

R

S Q

EN

PWM6

= Enable

Interrupt

32-bit Timer Counter

32-bit Pre-Scaler

PCLK

PWM Diagram and Registers

11/15/08


CONFIDENTIAL 153

15.11.08

Real Time Clock (1)

Full Clock/Calendar function with alarms– Generates its own 32.768 kHz reference clock from any crystal frequency

– Counts seconds, minutes, hours, day of month, month, year, day of week and day of year

– Can generate an interrupt or set an alarm flag for any combination of the counters

11/15/08


CONFIDENTIAL 154

15.11.08

Clock Divider(prescaler)

Clock

AlarmRegisters

TimeCounters Comparators

Interrupt Generator

PCLK

The Counter Increment can

cause an interrupt

Real Time Clock (2)

11/15/08


CONFIDENTIAL 155

15.11.08

(Mis-)Using the RTC clock for a regular timer

If the RTC is not used it could be used as a simple timer

Fastest interrupt that can be provided in regular operation– 1 second

Changing the value for the prescaler and clock divider could produce faster interrupts

– NOTE: Renders other RTC values inusable

11/15/08


CONFIDENTIAL 156

15.11.08

Watchdog Timer (1)

Once activated, the Watchdog will reset the entire chip if it is not fed regularly

Feed is accomplished by a specific sequence of data writes

Watchdog flag allows software to tell that a watchdog reset has occurred

Selectable overflow time (µs ... minutes)

Debug Mode generates an interrupt instead of a reset

Secure: watchdog cannot be turned off once it is enabled

Watchdog Timer value can be read in one cycle

11/15/08


CONFIDENTIAL 157

15.11.08

Watchdog Timer (2)

32-bit Down Counter

WDFEED

Current Timer Count(WDTC)

WDEN WDTOF WDINT WDRESET

Sticky bits!(cleared by WDT underflow or

ext. reset)

WDMOD Register

/4PCLK

UN

DER

FLO

WRESET

INTERRUPT

Watchdog TimerConstant

11/15/08


CONFIDENTIAL 158

15.11.08

Hands-On Index Hands-On

0. Tools Setup / New project

1. MAM / PLL

2. GPIO

3. PWM

4. SPI

5. ADC / UART

6. USB

11/15/08


CONFIDENTIAL 159

15.11.08

Hands-OnStart Keil uVision3

Menu Selection:Project /New Project

Select HANDS_ON_2

Select readme.txt

11/15/08


CONFIDENTIAL 160

15.11.08

Hands-OnMAM and PLL setup

Open project 01_MAM_PLL.

Run it and notify LEDs blinking speed:

Explanation of MAM Register values–“Partially Enable”:Code fetches only–“Fully enable”:Code and data fetches–MAM TimingNumber of clock cycles used for one flash memory access

Try to increase core frequency up to 60 MHz:

11/15/08


CONFIDENTIAL 161

15.11.08


S tep 1.

S tep 2.

S tep 3.

Rebuild the project and load it to flash.

Try to enable MAM. Rebuild and load to flash. Make a conclusion.

11/15/08


CONFIDENTIAL 162

15.11.08

MSEL = 5, PSEL = 2, MAM Control = Fully Enabled.


Solution

11/15/08


CONFIDENTIAL 163

15.11.08

Open project 02_GPIO.

Run it and remember the result. Try to use Fast I/O instead of normal GPIO. Rewrite

the code. Rebuild and run your solution. Compare the results.

Hands-OnGPIO Exercise

11/15/08


CONFIDENTIAL 164

15.11.08

Just do the following replacement:SCS = 0x00 → SCS = 0x01

IODIR0 → FIO0DIRIOSET0 → FIO0SETIOCLR0 → FIO0CLR

Hands-OnGPIO Exercise

Solution

11/15/08


CONFIDENTIAL 165

15.11.08

Hands-OnOpen project 03_PWM.

Run it.

Note the color LEDs are blinking not very frequently.

- Modify PWM initialization code to get a ‘soft’ violet light.

- When done, the motor will start rotating automatically.

- Try to increase motor speed.

PWM Exercise

11/15/08


CONFIDENTIAL 166

15.11.08

Hands-OnInitPWM ():PWMMR0 = 0x000FFFFF;→PWMMR0 = 0x00000FFF;.

A and B values should be reduced to make a ‘soft’

light.

PWM Exercise - solution

11/15/08


CONFIDENTIAL 167

15.11.08

Hands-OnEnableMotor (): maxSpeed = PWMMR0 / 2; →maxSpeed = PWMMR0;

Value B should be increased closer to A.

PWM Exercise - solution

11/15/08


CONFIDENTIAL 168

15.11.08

A/D Converter

Features

– 10 bit successive approximation analog to digital converter

– Multiplexed inputs

• 4 pins (64-pin devices)

• 8 pins (144-pin devices)

– Power down mode

– Measurement range 0V ... 3V

– Minimum 10 bit conversion time: 2.44 µS

– Burst conversion mode for single or multiple inputs

– Optional conversion on transition on input pin or Timer Match signal

– Programmable divider to generate required 4.5MHz from VPB clock

11/15/08


CONFIDENTIAL 169

15.11.08

A/D Converter – Burst mode

CLKS: bit 17, 18, 19 of ADCR select the number of clocks used per conversion and the accuracy

– 000b: 11 clocks, 10 bits




– …


11/15/08


CONFIDENTIAL 170

15.11.08

ADC LPC213X, LPC214X

Separate result register for each channel– Reduces the interrupt overhead by a factor of 8

Measurement range of 0 V to 3 V– Separate voltage pins for analogue 3V supply (V3A) and analogue ground (VSSA)

11/15/08


CONFIDENTIAL 171

15.11.08

ADC – Software Controlled Mode

All conversions are 10-bit and take 11 clocks

4.5Mhz Maximum Clock

Allows conversion to start on an external edge

Select Single Channel ADCR (7:0)

7 56 4 3 012

10-bit ADC(11 Clocks/Conv)

ADDR0

ADC Inputs

VSSAV3A

ADDR1

ADDR7

11/15/08


CONFIDENTIAL 172

15.11.08

ADC – Burst Mode

Result accuracy and speed are programmable

Input selected by the SEL bits are scanned

Select Multiple Channels ADCR (7:0)

n-bit ADC(n Clocks/Conv)

ADC Inputs

1 - 8Input Scan

(SEL Bits)

ADC Clock(CLKS Bits)

ADDR0 ADDR1 ADDR7

11/15/08


CONFIDENTIAL 173

15.11.08

LPC213x DAC

Digital-to-Analog Converter (DAC)– 10-bit resolution DAC with a buffered output

• Last output value is held as long as DAC is on– Output from Zero Volt to Reference Voltage

• In 1024 steps– Selectable Conversion speed vs. power

• Settling time 2,5us, up to 350uA• Settling time 1us, up to 700uA

– Selective power down

http://images.google.com/imgres?imgurl=http://www.energyusernews.com/EUN/FILES/IMAGES/82710.jpg&imgrefurl=http://www.energyusernews.com/CDA/ArticleInformation/features/BNP__Features__Item/0,2584,97885,00.html&h=226&w=400&sz=34&tbnid=AGL6G8aYiGgJ:&tbnh=67&tbnw=118&start=16&prev=/images?q=sine+wave&hl=en&lr=&sa=G

11/15/08


CONFIDENTIAL 174

15.11.08

• Memory Addressing• System Control Block• Memory Accelerator Module (MAM)• General Purpose I/O

Pin Connect Block / External Memory Controller


Vectored Interrupt Controller

Serial Communication InterfacesUART 0 / UART 1, I²C, SPI, USB CAN

Hands-On

Hands-On

Hands-On

11/15/08


CONFIDENTIAL 175

15.11.08

Vectored Interrupt Controller (1)

ARM PrimeCell™

32 interrupt request inputs

16 IRQ interrupts can be auto-vectored– Single instruction vectoring to ISR

– Dynamic software priority assignment

16 non-vectored interrupts

Software interrupts

11/15/08


CONFIDENTIAL 176

15.11.08

IntE

nabl

eCle

arIn

tEna

ble

Vectored Interrupt Controller (2)So

ftInt

Cle

arS

oftIn

t

Interrupt Source

32

OR

Raw

Inte

rrup

t FIQ

Sta

tus

FIQ

High Prio

IRQ

Stat

us

VectorCntl

En

5

En

5

VICVectorAddr 15

VICVectorAddr 0

. . .

VICDefVectAddr

16

Channel

0:4

Channel

0:4

Low Prio

IntSelect

FIQ

IRQ

32Prioritized

11/15/08


CONFIDENTIAL 177

15.11.08

VICVectAddr4

Interrupt source linked to vector 4

VICVectAddr ISR

Load PC with Vector Address

VIC - Vectored Interrupts

PC

11/15/08


CONFIDENTIAL 178

15.11.08

VICDefVectAddrISR

Interrupt

VICVectAddr

CODE

ISR

ISRISRISR

ISRLoad PC with Common

Vector Address

VIC - Non-Vectored Interrupts

PC

11/15/08


CONFIDENTIAL 179

15.11.08

FIQs have higher priority than IRQs– Serviced first– FIQs disable IRQs

• FIQ Vector is last in vector table (allows handler to be run sequentially from that address)

• FIQ mode has 5 extra banked registers, r8-12 (interrupt handlers must always preserve non-banked registers)

VIC - FIQ Interrupt

11/15/08


CONFIDENTIAL 180

15.11.0816External Interrupt 2 (EINT2)System Control

15External Interrupt 1 (EINT1)System Control


13RTCCIF (Counter Increment), RTCALF (Alarm)RTC

12PLL Lock (PLOCK)PLL

11reserved-

10SPIF, MODFSPI

9SI (state change)I2C

8Match 0 - 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6)PWM 0

7Rx Line Status (RLS)

Transmit Holding Register empty (THRE)

Rx Data Available (RDA)Character Time-out Indicator (CTI)Modem Status Interrupt (MSI)

UART 1

6Rx Line Status (RLS)

Transmit Holding Register empty (THRE)

Rx Data Available (RDA)Character Time-out Indicator (CTI)

UART 0

5Match 0 -3 (MR0, MR1, MR2, MR3)Capture 0 - 3 (CR0, CR1, CR2, CR3)

Timer 1

4Match 0 -2 (MR0, MR1, MR2, MR3)Capture 0 - 2 (CR0, CR1, CR2)

Timer 0

3Embedded ICE, DbgCommTxARM Core

2Embedded ICE, DbgCommRxARM Core

1Reserved for software interrupts only-

0Watchdog Interrupt (WDINT)WDT

VIC IR Source #Flag(s)Block

VICIR Sources

LPC2104LPC2105LPC2106

11/15/08


CONFIDENTIAL 181

15.11.08

26CAN 1 ReceiveCAN

23CAN 4 TransmitCAN

18A/D ConverterA/D

29CAN 4 ReceiveCAN

28CAN 3 ReceiveCAN

27CAN 2 ReceiveCAN

22CAN 3 TransmitCAN

21CAN 2 TransmitCAN

20CAN 1 TransmitCAN

19CAN ErrorCAN


.........

VIC IR Source #Flag(s)Block

add'l

VICIR Sources

LPC2114/24LPC2119/29LPC2194LPC2210/12/14LPC2290/92LPC2294

plus more flags for UART0, Timer1, Capture 0 - 3 (CR0, CR1, CR2, CR3)

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Some instructions take multiple cycles to execute and cannot be interrupted– The longest STM and LDM instructions take 20 cycles– Subsets can be reduced to 7 cycles

FIQ: 12 (25) cycles, 200ns (416ns) @ 60MHz

First Vectored IRQ (assuming no FIQ pending): 26 (39) cycles, 433ns (650ns) @ 60MHz

Default IRQ Vector (assuming no other IRQ pending):

42 (55) cycles, 700ns (916ns) @ 60MHz

VIC Interrupt Latency

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Interrupt Prioritizing with Nesting

IRQ Service Routine of “lower” priority:

1. Clear IRQ source2. Push SPSR to LR and on stack3. Switch to System Mode (write CPSR, enable IRQ)4. Push system mode link register on stack5. Execute “real” service routine, can be interrupted6. Pop system mode link register from stack7. Switch back to IRQ mode 8. Pop SPSR to LR and restore SPSR9. Reset VIC

Macros provided by ESAcademy’s ESLIB

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Interrupt Prioritizing with RTOS

IRQ Service Routine starts RTOS task:1. Start appropriate RTOS task with desired priority2. Clear IRQ source3. Reset VIC

Prioritizing is handled by Real-Time Operating System

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Caution: Spurious Interrupts

Core and VIC operate asynchronous

“Unwanted” interrupts can occur, as disabling IRQ/FIQ and their sources is not instantaneous

– Instructions in pipeline continue to execute

One of multiple work-a-rounds:– Upon entry of IRQ/FIQ check if since occurrence the interrupt was disabled

• If yes, exit interrupt– Execute “protected code” as an IRQ interrupt

• which cannot be interrupted by another IRQ

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Serial Communication Interfaces

UARTs

I2C

SPI

CAN

USB*

10110101

10100101 10110110 01111000

00100000

1010010110110110 0

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UART

UART 0, UART 1

– 16 byte Receive and Transmit FIFOs

– PC UART 16C550 “look-alike”

– Built-in baud rate generator

– Supports 6 modem control signals

• CTS, RTS, DCD, DSR, DTR and RI functions are selectable

• Note:

UART 0 has Tx and Rx pins only

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I2C Bus

Fast-I2C compliant bus interface

– Configurable as Master, Slave, or both

– Multi-master bus

– Bi-directional data transfer between masters and slaves

– Up to 400kb/s

– Arbitration between simultaneously transmitting masters without corruption of serial data on the bus

– Serial clock synchronization allows devices with different bit rates to communicate via one serial bus

– Programmable clock rate

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SPI Bus

Compliant with Serial Peripheral Interface (SPI) specification

Combined SPI master and slave function

Maximum data bit rate of 1/8 of the peripheral clock rate

Programmable clock polarity and phase for data transmit/receive operations

No. of SPI channels:

– 1 (48-pin devices)

– 2 (64/144-pin devices)

– Up to 3

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USB 2.0

Since USB is a standard doesn’t that make all microcontrollers with USB the same?

NO!!

Architectural choices and implementation details make a big difference in performance and ease of use.

The LPC2148 is a high performance USB device.

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LPC2148 key high performance USB features

Flexible endpoint architecture– Supports all 32 USB endpoints

Large data FIFO– Can double buffer full isochronous packets

Flexible DMA capability– USB Buffer is present on the AHB bus

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USB 2.0 in LPC2148

Fully Compliant with USB 2.0 Spec

Supports 32 physical endpoints

Scalable realization of Endpoints during run time

Double buffering supported for Bulk and Isochronous Endpoints

Supports DMA transfer on all non-control endpoints

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USB 2.0 in LPC2148

Supports Control, Bulk, Interrupt and Isochronous endpoints

Supports SoftConnect™ feature

Supports GoodLink™ LED indicator

Flexible clock architecture (own PLL)

Remote wakeup

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LPC2148 USB Block Diagram

RegisterInterface

Serial Interface Engine(SIE)

Endpoint ramaccess control

Receivers

D+

D-TX DForce SE0

OE

RX D

ATXPADSUSB Logic

2K FIFO

8K AHBMemory

DMAEngine

AHB Bus

VPB Bus

Using the DMA, the USB Logic has direct

access to memory

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Transfer Modes

Slave Transfer Mode

DMA Transfer Mode

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Slave Mode Transfer

USB Block acts like a slave

It can only issue interrupts to the CPU

Control Endpoint uses this mode of transfer exclusively

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DMA Mode Transfer

USB Block acts like a Master

Will transfer data directly from the 8K SRAM to the EP_RAM and vice versa.

For Isochronous transfers, the DMA transfer is synchronized to the frame interrupt

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SoftConnect™ and GoodLink™ LED

SoftConnect™– Can connect/re-connect to the host through software– No need to unplug and plug the cable back again

GoodLink™ LED– Needs a shared GPIO pin– Shows indication on a LED if connection is established

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LPC2148 connections

LPC2148

ATXPad

D-

D+

Vusb supply

Good Link

Vusb bus sense

Soft connect_n

D-

D+

33

33

1.5k

Logic level pchannel FET

Philips BSH203

3.3 volt system power

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LPC2148 Clock Architecture

MainPLLXTAL

VPBdivider

cclk

pclk

USBPLL

VPB clock must be 16 MHzminimum for the USB vpb interface

LPC2148 clocks

USB clk

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Flexible Clocking Scheme

Two separate PLL’s provide lot of flexibility to the user to run the core and the USB independently at different speeds

Considering the three possible option– Crystal Frequency –12MHz

• Core Freq= 12,24,36,48,60MHz• USB Freq =48MHz

– Crystal Frequency –16MHz• Core Freq= 16,32,48MHz• USB Freq =48MHz

– Crystal Frequency –24MHz• Core Freq= 24,48MHz• USB Freq =48MHz

Fastest USB operation available at any CPU frequency

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Load project

Build

Run on hardware

Use joystick to move a point on the LED display

Browse through the program

Make a “worm” game on the LED display

Hands-OnExercise: 04 - SPI

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- Open project 05_ADC_and_UART

- Change UART speed to 57600.- Rebuild and run the code.- Check HyperTerminal for correct output.

Hands-OnExercise: 05 – ADC and UART

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- Rotate analog input AIN1 and notify the results.

- Try to increase ADC accuracy.


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Solution:

InitUART():U0DLL = ( 12000000 * 5 ) / ( 19200 * 16 * 4 ); →U0DLL = ( 12000000 * 5 ) / ( 57600 * 16 * 4 );

InitADC ():ADCR = … (7 << 17) …; →ADCR = … (0 << 17) …;


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Load project

Build

Run on hardware

Watch the new disk in Windows My Computer

Try to put something on it

Hands-OnExercise: 06 - USB

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Lowest power consumption (less than 1 mW / MHz)

Very small package options (as small as 7mm x 7mm)

The highest performance and most flexible external memory interface available

Product highlights:– ARM7 microcontrollers with Flash that operates up to the maximum clock

speed (60 - 72 MHz) thanks to our patented Memory Accelerator Module with 128-bit wide memory interface – competitive ARM7 products are limited to 30 – 45 MHz Flash speeds

– The only ARM7 MCU that allows multiple connectivity protocols to run at full performance at the same time (LPC2300 and LPC2400 family with dual AHB bus)

– The only ARM7 microcontrollers with full USB specification and implementation (LPC214x, LPC2300 and LPC2400)

IT’S A TEST TIME!

(nxp).1-day hands-on arm training

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