nuc745 eval. board user's manual - open ip cam documents/doc... · 2009. 12. 25. · close u3 push...

NUC745

32-BIT ARM7TDMI-BASED MCU

Revision B

A

NUC745 Evaluation Board User’s manual

The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.

Nuvoton is providing this document only for reference purposes of ARM926-based system design. Nuvoton assumes no

responsibility for errors or omissions. All data and specifications are subject to change without notice.

. For additional information or questions, please contact: Nuvoton Technology Corporation.

NUC745


Revision B

B

Table of Contents- 1. REVISION HISTORY .......................................................................... 1

2. OVERVIEW......................................................................................... 2

2.1 FEATURES...............................................................................................3 2.2 SYSTEM ARCHITECTURE.............................................................................4

3. SYSTEM CONFIGURATION ................................................................. 5

3.1 SYSTEM CLOCK SOURCE SELECTION..................................................................5 3.2 ENDIAN MODE SELECT...................................................................................5 3.3 RESET BUTTON ............................................................................................6

4. CIRCUIT DESCRIPTION ..................................................................... 7

4.1 SDRAM .....................................................................................................7 4.2 FLASH ......................................................................................................8 4.3 USB ..........................................................................................................9 4.4 UART...................................................................................................... 10 4.5 JTAG 14-PIN INTERFACE ........................................................................... 11 4.6 ETHERNET................................................................................................. 12 4.7 EBI TEST INTERFACE .................................................................................. 13

5 SCHEMATIC ...................................................................................... 14

NUC745


Revision B

1

1. Revision History

version date page description

A Feb 5, 2007 - Initial Issued

B Mar 30,2009 - Circuit and PHY update

Part number update

NUC745


Revision B

2

2. Overview

Picture 2-1

NUC745


Revision B

3

2.1 Features The NUC745 evaluation board consists of one application core module, which consists of NUVOTON ARM7-TDMI core MCU NUC745, 8MB SDRAM, 4MB FLASH, two UART for console port and other use, one USB host and one USB device port directly supported by NUC745. For detail information about this development system, please see the following list: NUC745 application Core Module: MCU: Nuvoton ARM7TDMI based NUC745 operating up to 80MHz Freq. Boot FLASH: Board supports up to 4MB (2Mbx16) FLASH, one 2Mbx16 FLASH on board. SDRAM: Board supports up to 32MB (4Mbx16x4 banks) SDRAM, totally 8MB on board. USB: One USB1.1 Host + one Slave UART: A TX/RX signal only UART port (UART0) for debug console. Another UART port supported with Male type connectors by NUC745’s UART interface. Network: A 10/100Mbps Ethernet port supported with IP101A (PHY) by NUC745’s RMII interface. JTAG: 14-pin JTAG debug interface.

NUC745


Revision B

4

2.2 System Architecture

Figure 2-1

NUC745


Revision B

5

3. System Configuration There are some system function settings will to be set to configure evaluation board H/W settings, please confirmed to the correct settings before using the functions.

3.1 System Clock Source selection The evaluation board supports system clock source selection, short 1-2 of JP1 (pull-high SDD15) will set 80MHz frequency as system operating clock(enable internal PLL), or short 2-3 of JP1(pull-low SDD15) will set 15MHz(external crystal source) frequency as system clock(disable internal PLL).

Jumper Setting Jumper Short 1-2 Short 2-3 Internal System Clock Select JP1 Enable PLL(80MHz) Disable PLL(15MHz)

R52 4.7K

CVDD33

SDD15

15MHZ

80MHZJP1

15M/80M

123

If the pin SDD15 is pull-up, the PLL output clock is used as internal system clock; otherwise, the external clock from EXTAL pin is served as internal system clock.

3.2 Endian Mode select The evaluation board supports system endian mode selection, short 1-2 of JP2 (pull-high SDD14) will set system operating mode at little endian, or short 2-3 of JP2 (pull-low SDD14) will set system operating mode at big endian mode.

Jumper Setting Jumper Short 1-2 Short 2-3 Endian mode Select JP2 Little Endian Big Endian

CVDD33JP2

15M/80M

123

LITTLE

BIG

SDD14R54 4.7K

If the pin SDD14 is pull-high, the system will be set at little endian mode, otherwise, it will be set at big endian mode.

NUC745


Revision B

6

3.3 Reset Button The SP1 is the System Reset button that connects to a reset IC (MIC811SU) and it will generate about 140ms (min.) long reset pulse for whole system reset.

SP1

SW PUSHBUTTON

VDD33

CB29

0.1uF

RESET circuit

CB28

TBD

VDD33

nSRST

VDD33

CB30

0.1uF

VDD33

R32

10K

VDD33

nRESET&U4

74VHC1G085

3

21 4

R33

10K

VDD33

nRESET

U3

MIC811SU

2

3

1

4

RESET

MR

GND

VCC

Close U3

Push Button Button System Reset SP１

NUC745


Revision B

7

4. Circuit Description

4.1 SDRAM This board support 16-bit bus width SDARM of 8Mbyte、16Mbyte or 32Mbyte size. Details please see below form.

Total Size Memory Configurations Bank Bus Width Part number

8Mbyte 1Mx16x4 Banks 1 16-bit W9864G6 16Mbyte 2Mx16x4 Banks 1 16-bit W9812G6 32Mbyte 4Mx16x4 Banks 1 16-bit W9825G6

SDMCLK

SDMCLK

SDRAM

nSCS0

SDD7

MCKE

AD11

SDD5

nWBE[0..1]

VDD33

U5

W986416EH

1

24

28

57

9

810

49

1113

3

15

1617181920

22

23242526

14

12

293031323334

46

3738

3941

43

4244

54

4547

27

4850

52

5153

6

35

21

36

40

VDD

DQ0DQ1

VSS

DQ2DQ3

VDDQ

DQ4DQ5

VDDQ

DQ6DQ7

VDDQ

DQML

/WE/CAS/RAS/CSBA0

A10/AP

A0A1A2A3

VDD

VSSQ

A4A5A6A7A8A9

VSSQ

CKECLK

DQMHVSS

VDDQ

DQ8DQ9

VSS

DQ10DQ11

VDD

DQ12DQ13

VSSQ

DQ14DQ15

VSSQ

A11

BA1

A12

NC

nSRAS

nWBE[0..1]

SDD8

SDD14

AD9nRESET

SDD10

SDD12

nSRAS

AD10

AD13

SDD2

AD7

SDD[0..15]

AD14

nSWE

nSCAS

nBTCSnBTCSnOE

nSRAS

nWBE1

nSCAS

SDD11

AD2

AD4

AD12

SDD9

nSWE

SDD4

SDD6

AD3

SDD15

SDD0SDD1

AD5

nWBE0

nSWE

nSCAS

nRESET

SDMCLK

nSCS0

VDD33

AD8

nSCS0

nOE AD0

SDD[0..15]

MCKEMCKE AD6

SDD13

SDD3

AD1

AD[0..20]AD[0..20]

NUC745


Revision B

8

4.2 FLASH This board support 8/16-bit bus width FLASH of 2Mbyte、4Mbyte size. Details please see below form.

Total Size Memory Configurations Bus Width Part number

2Mbyte 1Mx16 8/16-bit W28J160 4Mbyte 2Mx16 8/16-bit W19L320ABT

SDD13

AD17

AD10

AD7

AD9

SDD10

SDD15

nOE

AD11

SDD5

SDD0

SDD1

GND

AD12

AD16

AD13

AD2

VDD33

SDD12

SDD6

U6

W19B320ABT

123456789

10111213141516171819202122

48474645444342414039383736353433323130292827

2324

2625

A15A14A13A12A11A10A9A8A19A20WERESET#VPPWP#RY/BY#A18A17A7A6A5A4A3

A16BYTE#

VSSDQ15/A-1

DQ7DQ14

DQ6DQ13

DQ5DQ12

DQ4VCC

DQ11DQ3

DQ10DQ2DQ9DQ1DQ8DQ0OE#VSS

A2A1

CE#A0

BOOT FLASH

nBTCS

AD5

SDD4

SDD3

VDD33

VDD33

AD4

AD6

SDD2

AD8

SDD9

SDD14

AD3

SDD8

AD1

AD15

GNDAD14

AD18

AD19

nRESET

AD0

nWBE1AD20

SDD7

SDD11

NUC745


Revision B

9

4.3 USB The 1.5k resistor on D+ indicates to USB that a full speed device is connected when the device is hot

plugged into a USB hub or host port.

USB port Description Host CON9 (A-Type Connector)

Device CON10 (mini B-Type Connector)

CB54

0.01uF

R41 10K

LL7 FB

USB HOST

CON9

USB A-TYPE

1

23

4

VBUS

D-D+

GND

R42

15K

USB_FLAG

C15

33uF/16V

USB_ON/OFF

R40

10K

CB53

0.1uF

VDD5VVDD33

C16

33uF/16VCB55

0.1uF

D1+

USB_FLAG

LL6 FBU11

AIC1525-1

1234 5

678CTL

FLAGGNDNC IN

OUTIN

OUTUSB_ON/OFF

D1-

R43

15K

VDD33

D2-D2+

R44

1.5K CON10

mimi USB B-TYPE

12345

VBUSD-D+NCGND

LL8FB

USB Device

NUC745


Revision B

10

4.4 UART This board provides two UARY ports: URT0 is merely a general purpose UART used for console. And UART1 is designed for general purpose UART or Bluetooth transceiver. Both of them use Fe-Male type connector.

UART port Description Port 0 CON7 (Fe-Male Type) Port 1 CON8 (Male Type)

LED7GREEN_LED12

URXD0

RXD0

CB44

0.1uF

GND

RXD0

TXD0

UTXD0

VDD5V

TXD0

CB46 0.1uF

R37 1K

R36 1K

Female and Male are usedifference pindefine!!!

TXD0

TXD0

LED6GREEN_LED12

CB45

0.1uFU9

SP232ECA

12345678

161514131211109

C1+V+C1-C2+C2-V-T2_OUTR2_IN

VCCGND

T1_OUTR1_IN

R1_OUTT1_INT2_IN

R2_OUT

UART0(TX/RX only)

VDD33

UTXD0CON7

DSUB-9(FeMale)

162738495

CB43

0.1uF

URXD0

RXD0

RXD0

CB47 0.1uF

CB51 0.1uFCON8

DSUB-9(Male)

594837261

LED9GREEN_LED12TXD1CB48

0.1uF

CB52 0.1uF

RXD1

CB49

0.1uF

R38 1K

UTXD1

URXD1TXD1

GPIO8TXD1

RXD1

LED8GREEN_LED12

GND

Female and Male are usedifference pindefine!!!

UART1(TX/RX only)

GPIO[10..7]

VDD5V

U10

SP232ECA

12345678

161514131211109

C1+V+C1-C2+C2-V-T2_OUTR2_IN

VCCGND

T1_OUTR1_IN

R1_OUTT1_INT2_IN

R2_OUT

CB50

0.1uF

RXD1

UTXD1

VDD33

RP3

8P4R-22

1 82 73 64 5

R39 1K

GPIO[10..7]

GPIO7

URXD1

NUC745


Revision B

11

4.5 JTAG 14-PIN Interface NUC745 provide cost-effective JTAG-based debug solution using 14pin connecter interface.

Supports Type Output pin Description

JTAG Interface TDO,TDI,TMS,TCK,nTRST,nSRST CON5

R29

10K

TCK

nTRST

TCK

VDD33

R30

10K

R31

10K

CON5

10PX2

135791113151719

2468

101214161820

VTrefnTRST

TDITMSTCK

RTCKTDO

nSRSTDBGRQ

DBGACK

VSGNDGNDGNDGNDGNDGNDGNDGNDGND

VDD33

nSRST

VDD33JTAG CON

TDO

TDI

VDD33

nTRST

TMS

TDO

TMS

VDD33

CB27

0.1uF

R27

10K

VDD33

R28

10K

TDI

VDD33

NUC745


Revision B

12

4.6 Ethernet NUC745 provide an Ethernet MAC Controller (EMC) for LAN application. The EMC only support

RMII (Reduced MII) interface to connect with PHY operating on 50MHz REF-CLK.

Interface Type Pin out Description

RMII RMII interface Physical layer supported by IP101A

R24

5.1K

GPIO24PHY_MDIO

PHY_TXEN

MAC_REFCLK

CB13

0.1uF

ETHERNET

REGOUT

nRESET

LED4/PHYAD4

R15

5.1K

C2

20pF

Band Gap resistorLED1/PHYAD1

PHY_TXD1

RP2 8P4R-221 82 73 64 5

R2

5.1K

RX-

GPIO[29..20]

PHY_MDIO

GPIO25

LED0/PHYAD0

MDI_TN

R26

5.1K

CB7

5pF

MDI_TP

CL2

0.01uF/2KV

R4 22

VDD33

R3 22

CB17

0.1uF

CB8

5pF

Power-on Settings & LED diplay

CB21

TBD

GPIO23

FULL DUPLEX/COL

CB23

0.1uF

R22

510

MAC_REFCLKCRS

CB18

0.1uF

LED2/PHYAD2

R9

75,1%

VDD33

C50M_O

U1

IP101A

1

23456

7

8

910

11

12

2526

27

28

29

3031

32

3334

35

36

2423

2221201918

17

16

15

14

13

37383940

41

42

43

44

45

4647

48

COL/RMII

TX_ENTXD3TXD2TXD1TXD0

TX_CLK/REF_CLK

REGIN

LED0/PHYAD0LED1/PHYAD1

DGND

LED2/PHYAD2

MDCMDIO

TEST_ON

RTSET

AGND

MDI_RNMDI_RP

REGOUT

MDI_TNMDI_TP

AGND

AVDD33

RX_ERCRS/LEDMOD

RX_DV/CRS_DVRXD0RXD1RXD2RXD3

DGND

RX_CLK/C50M_O

LED4/PHYAD4

DVDD33

LED3/PHYAD3

AN_ENADPLXSPD

RPTR

APS

RESET_N

ISOL

MII_SNIB

DGND

X1X2

INTR

100Base T

LED1/PHYAD1

LED4/PHYAD4

PHY_RXERR

LED0/PHYAD0

CB19

0.1uF

TX+

LED1

LED_G

12

GPIO[29..20]

PHY_MDIO

REGOUT

CB22

0.1uF

GPIO26

PHY_TXEN

R6

50,1%

CB11

TBD

R7

50,1%

R12

75,1%

VDD33

CL1

0.1uF/2KV(DNE)

R1

1.5KPHY_RXERR

nRESET

X2

PHY_MDC

R13

50,1%

PHY address-->00001H

VDD33

MDI_TN

10/100 Mbps Fast Ethernet PHY

LED3/PHYAD3

PHY_RXD0

CON3

RJ-45L CON

12345678

910

TX+TX-

RX+NCNCRX-NCNC

Sold

erS

olde

r

REGIN

X2

CB24

0.01uF

L1 FB

CB12

0.1uF

Chasis Ground

GPIO27

PHY_RXD1

CB9

5pF

R17 0

X1

25MHz

CB10

TBD

R8

6.2K,1%

REGOUT

GPIO22

LINK/ACT

R18

0

PHY_CRSDV

PHY_TXD1

CB20

TBD

RX+

GPIO21

R23

5.1K

LED3

LED_G

1 2

R20

5.1K

MDI_RN

LED2/PHYAD2

PHY_CRSDV

U2

TS6121C

16

14

13

3

1

6

8

5

9

11

2

4

710

12

15TX+

TX-

NC

TD-

TD+

RD+

RD-

NC

RX-

RX+

CT

NC

CTCT

NC

CT

MDI_RPX1

LAN_AVDD3.3

PHY_REFCLK

C3

20pF

X1

GPIO28

R25

510

CRS

CB3

0.1uF

PHY_MDC

Ethernet Front End

COL/RMII

LED mode 2

VDD33

PHY_RXD0

PHY_TXD0

LED2

LED_G

1 2

PHY_RXD1

nRESET

MDI_RN

PHY_REFCLK

R11

75,1%

CB16

0.01uF

CB14

TBD

MDI_RP

VDD33

Close U20

REGOUT

MDI_TP

C50M_O

TX-

CB4

0.1uF

R5

10K

RP1 8P4R-221 82 73 64 5

LED3/PHYAD3

COL/RMII

CB6

5pF

R14

50,1%

GPIO29

R21

0

PHY_TXD0

R10

75,1%

CB5

0.01uF

R16

5.1K

CB15

TBD

Close U2

REGIN

+ C4

10uF/16V

L2 FB

R19

510

GPIO20

NUC745


Revision B

13

4.7 EBI Test Interface This board reserved EBI testing interface for system development and testing. Refer the following for more detailed.

AD18

SDD7

nIRQ0

CB2

0.1uF

SDD12

nWBE1

AD20

AD3

CB1

0.1uF

GND

AD2

SDD5

nWBE0nWAIT

AD13

SDD2

SDD14

SDD11

VDD5V

AD7

nECS2

nRESET

AD8

AD11

SDD4SDD3

AD19

SDD15

AD9

AD4

AD15

C133uF/16V

SDD6SDD9

SDD1

AD1

VDD5V

SDD10

VDD5V

nOE

AD10

AD5

AD12AD14

CON1

EBI EXT. CON(DNE)

2468101214161820222426283032343638404244464850

13579

1113151719212325272931333537394143454749

SDD13

SDD0

AD17

nECS3

SDD8

AD0

nECS1 nECS0

AD16

AD6

NUC745


Revision B

14

5 Schematic

D1+

SDMC

LK

GPIO

[29.

.20]

USB

USB.

sch

D1+

D1-

D2+

D2-

USB_

ON/O

FFUS

B_FL

AG

nTRS

T

nOE

nSW

E

D2+

SDD[

15..0

]

D2-

I/O E

XT. I

NTER

FACE

I/O E

XT. I

NTER

FACE

.sch

GPIO

[10.

.7]

GPIO

[14.

.11]

GPIO

[4..0

]

GPIO

[29.

.20]

nRES

ET

GPIO

[19.

.18]

MEM

MEM.

sch

SDD[

15..0

]

AD[2

0..0

]

nWBE

[1..0

]

nSW

EnO

EnB

TCS

nSRA

SnS

CAS

SDMC

LKMC

KEnS

CS0

nRES

ET

nWBE

[1..0

]

MCKE

GPIO

[29.

.20]

UART

0/1

UART

0/1.

sch

RXD0

TXD0

GPIO

[10.

.7]

nBTC

S

TCK

JTAG

&RES

ET

JTAG

&RES

ET.s

ch

TMS

TDI

TDO

nTRS

TnR

ESET

TCK

nSRA

S

AD[2

0..0

]

RXD0

D1-

USB_

FLAG

nSCA

S

TDO

Ethe

rnet

Ethe

rnet

.sch

nRES

ET

GPIO

[29.

.20]

TXD0

nRES

ET

GPIO

[14.

.11]

GPIO

[19.

.18]

nIRQ

0nW

AIT

NUC7

45

NUC7

45.s

ch

nSCS

0

SDMC

LKMC

KE

nOE

nSW

E

nBTC

S

nSCA

SnS

RAS

nWBE

[1..0

]

SDD[

15..0

]

AD[2

0..0

]

nRXD

0nT

XD0

D1+

D2+

D2-

D1-

USB_

FLAG

USB_

ON/O

FF

TMS

TDI

TDO

TCK

nTRS

TnR

ESET

GPIO

[10.

.7]

GPIO

[14.

.11]

GPIO

[4..0

]

GPIO

[29.

.20]

nWAI

T

nECS

[3..0

]

nIRQ

0

GPIO

[19.

.18]

NU

C745

Eva

luat

ion

Boar

d: R

ev3.

0

nOE

GPIO

[10.

.7]

nECS

[3..0

]

GPIO

[10.

.7]

TMS

GPIO

[4..0

]

EBI E

XT. I

NTER

FACE

EBI E

XT. I

NTER

FACE

.sch

SDD[

15..0

]

AD[2

0..0

]

nWBE

[1..0

]

nRES

ET

nECS

[3..0

]

nOE

nWAI

TnI

RQ0

TDI

3.0

NUC7

45 EV

AL B

OARD

.SCH

Cust

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110

Tues

day,

Nov

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Title

Size

Docu

men

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ber

Rev

Date

:Sh

eet

of

POW

ER

POW

ER.s

ch

nSCS

0

USB_

ON/O

FF

NUC745


Revision B

15

GPIO

[29.

.20]

X1 25MH

z

CL2

0.01

uF/2

KV

CB4

0.1u

F

Clos

e U20

C50M

_OC2 20

pF

COL/

RMII

GPIO

23

L2FB

R11

75,1

%

PHY_

RXD0

R24

5.1K

LED0

/PHY

AD0

FULL

DUP

LEX/

COL

VDD3

3

LED2

/PHY

AD2

R2 5.1K

MDI_

TP

LED mo

de 2

CRS

X1PHY_

REFC

LK

PHY_

TXEN

PHY_

MDC

PHY_

TXD1

MDI_

TP

PHY_

MDC

Clos

e U2

REGO

UT

LED3

/PHY

AD3

U1 IP10

1A

123456 7 89 10 111225 26

27 2829 303132 33 343536

242322 21 20 19 18 1716 15 1413

37383940 41 4243 44

4546 47 48

COL/

RMII

TX_E

NTX

D3TX

D2TX

D1TX

D0

TX_C

LK/R

EF_C

LK

REGI

N

LED0

/PHY

AD0

LED1

/PHY

AD1

DGND

LED2

/PHY

AD2

MDC

MDIO

TEST

_ON

RTSE

T

AGND

MDI_

RNMD

I_RP

REGO

UT

MDI_

TNMD

I_TP

AGND

AVDD

33

RX_E

RCR

S/LE

DMOD

RX_D

V/CR

S_DV

RXD0

RXD1

RXD2

RXD3

DGND

RX_C

LK/C

50M_

O

LED4

/PHY

AD4

DVDD

33

LED3

/PHY

AD3

AN_E

NADP

LXSP

DRP

TR APS

RESE

T_N

ISOL

MII_

SNIB

DGND

X1 X2 INTR

RX+

CB15

TBD

PHY_

TXD0

LED1

/PHY

AD1

PHY_

RXER

R R16

5.1K

PHY_

CRSD

V

R25

510

ETHE

RNET

3.0

ETHE

RNET

.SCH

Cust

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Tues

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Nov

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r 11,

200

8

Title

Size

Docu

men

t Num

ber

Rev

Date

:Sh

eet

of

CB8

5pF

CB16

0.01

uF

CB18

0.1u

F

CB24

0.01

uF

GPIO

[29.

.20]

R22

510

PHY_

MDIO

GPIO

29

CB7

5pF

R15

5.1K

10/1

00 M

bps Fa

st E

therne

t PH

Y

PHY_

TXD0

VDD3

3

R6 50,1

%

R422

GPIO

21

LED1

LED_

G

12

nRES

ET

R13

50,1

%

VDD3

3 VDD

33

LED2

/PHY

AD2

X2

R1 1.5K

Chas

is Gro

und

PHY_

MDIO

CB14

TBD

PHY_

CRSD

V

CB23

0.1u

F

R12

75,1

%

R10

75,1

%

MDI_

TN

LED3

LED_

G

12

LINK

/ACT

R14

50,1

%

TX-

GPIO

26

GPIO

24

PHY_

REFC

LK

R26

5.1K

LAN_

AVDD

3.3

PHY_

RXD1

LED1

/PHY

AD1

MDI_

RP

PHY_

MDIO

C50M

_O

GPIO

25

R322

REGO

UT

CB3

0.1u

F

Ethe

rnet

Fro

nt E

nd

RX-

MDI_

RN

CB19

0.1u

F

CB11

TBD

CB17

0.1u

F

nRES

ET

GPIO

27

CON3 RJ

-45L

CON1 2 3 4 5 6 7 8

9 10

TX+

TX-

RX+

NC NC RX-

NC NC

Solder Solder

Powe

r-on

Set

tings

& L

ED d

iplay

PHY_

TXD1

R23

5.1K

CB12

0.1u

F

PHY

addres

s-->00

001H

REGO

UT

R17

0

R20

5.1K

GPIO

22

CB9

5pF

+C4 10

uF/1

6V

nRES

ET

LED0

/PHY

AD0

X2

CL1

0.1u

F/2K

V(DN

E)

LED3

/PHY

AD3

CRS

R18

0

RP2

8P4R

-22

18

27

36

45

VDD3

3

REGO

UT

PHY_

TXEN

GPIO

20

R9 75,1

%

MAC_

REFC

LK

TX+

REGI

N

C3 20pF

R8 6.2K

,1%

100B

ase

T

U2 TS61

21C

16 14 13

31 6 85

911

2 4 7101215

TX+

TX-

NC

TD-

TD+

RD+

RD-

NC

RX-

RX+

CT NC CT

CTNCCT

CB5

0.01

uF

LED2

LED_

G

12

R5 10K

MDI_

RP

GPIO

28

VDD3

3

CB6

5pF

PHY_

RXER

R

L1FB

COL/

RMII

R19

510

MDI_

RN

PHY_

RXD0

RP1

8P4R

-22

18

27

36

45

REGI

N

LED4

/PHY

AD4

CB22

0.1u

F

PHY_

RXD1

MDI_

TN

CB21

TBD

CB20

TBD

CB10

TBD

Band

Gap

resis

tor

LED4

/PHY

AD4

X1

MAC_

REFC

LK

R7 50,1

%

R21

0

CB13

0.1u

F

NUC745


Revision B

16

AD6

VDD5

V

CB1

0.1u

F

nIRQ

0

SDD8

nOE

nECS

2

SDD4

VDD5

V

AD16

CB2

0.1u

F

SDD1

1

AD[2

0..0

]

AD13

SDD[

15..0

]

AD18

nRES

ET

nWBE

1

AD3

AD0

nECS

[3..0

]

SDD3

CON1

EBI E

XT. C

ON(D

NE)

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49

SDD6

VDD5

V

AD2

nWBE

[1..0

]

SDD1

5

AD19

nOE

SDD5

AD8

nECS

3

nWAI

T

SDD1

4

AD7

AD20

nWAI

T

SDD9

SDD[

15..0

]

SDD0

AD1

SDD1

AD4

C133

uF/1

6V

nOE

nRES

ET

AD9

nWBE

[1..0

]

3.0

EBI E

XT. I

NTER

FACE

.SCH

Cust

om

210

Mond

ay, J

anua

ry 0

5, 2

009

Title

Size

Docu

men

t Num

ber

Rev

Date

:Sh

eet

of

nECS

[3..0

]

AD[2

0..0

]

SDD1

3

nECS

0

AD11

SDD1

0SD

D12

AD17

nIRQ

0

AD10

AD14

AD5

nRES

ET

nIRQ

0nW

AIT

SDD7

GND

AD15

SDD2

nWBE

0

AD12

nECS

1

NUC745


Revision B

17

CON4

I/O E

XT. C

ON(D

NE)

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

VDD5

V

CB25

0.1uF

GPIO

20

GPIO

28

GPIO

10

C5 33uF

/16V

GPIO

9

nRES

ET

GPIO

11

GPIO

26

GPIO

[4..0]

GPIO

25

GPIO

[19..1

8]

GND

GPIO

8

GPIO

18

GPIO

[14..1

1]

GPIO

23

GPIO

2

GPIO

[29..2

0]

GPIO

[19.

.18]

----

>XDM

A

GPIO

3

GPIO

[29.

.20]

----

>ETH

ERNET

PHY,

KPI

GPIO

[10..7

]

GPIO

27

GPIO

13

nRES

ET

GPIO

[4..

0]--

----

>AC-

97,I2S

,PWM

,UAR

T3

nRES

ET

GPIO

22

GPIO

4

GPIO

[10.

.7]-

----

>UAR

T1_2,P

S/2

GPIO

29

GPIO

7

GPIO

[4..0]

GPIO

24

GPIO

[29..2

0]GP

IO[19

..18]

GPIO

0

VDD5

V

GPIO

19

GPIO

[10..7

]

GPIO

1

GPIO

12

GPIO

[14..1

1]

GPIO

14

GPIO

[14.

.11]

----

>I2C

,SSP

GPIO

21

GND

CB26

0.1uF

3.0

I/O EX

T. IN

TERF

ACE.S

CH

Custo

m

410

Mond

ay, J

anua

ry 05

, 200

9

Title

Size

Docu

ment

Numb

erRe

v

Date:

Shee

tof

VDD5

V

C6 33uF

/16V

NUC745


Revision B

18

R28

10K

CB28

TBD

CB27

0.1u

F

3.0

JTAG

&RES

ET.S

CH

Cust

om

510

Tues

day,

Nov

embe

r 11,

200

8

Title

Size

Docu

men

t Num

ber

Rev

Date

:Sh

eet

of

VDD3

3

nSRS

T

R27

10K

RESE

T cir

cuit

TCK

TMS

nRES

ET

R30

10K

VDD3

3

R32

10K

nTRS

T

VDD3

3JT

AG C

ON

TDI

nTRS

T

R33

10K

CON5

10PX

2

1 3 5 7 9 11 13 15 17 19

2 4 6 8 10 12 14 16 18 20

VTre

fnT

RST

TDI

TMS

TCK

RTCK TD

OnS

RST

DBGR

QDB

GACK

VS GND

GND

GND

GND

GND

GND

GND

GND

GND

VDD3

3

VDD3

3

R29

10K

VDD3

3

VDD3

3

TDO

VDD3

3

TDI

TCK

R31

10K

CB30

0.1u

F

nSRS

T

VDD3

3

&U4 74

VHC1

G08

5 3

2 14

VDD3

3

CB29

0.1u

F

VDD3

3

TMS

U3 MIC8

11SU

2

3 1

4

RESE

T

MR GND

VCC

VDD3

3

SP1

SW P

USHB

UTTO

N

TDO

VDD3

3

Clos

e U3

nRES

ET

NUC745


Revision B

19

AD4

SDD5

CB33

0.1u

F

SDMC

LK

nBTC

S

SDD1

0

SDD4

MCKE

AD0

nSCS

0

SDD9

U5 W98

6416

EH

1

2 4

28

5 7 98 10 4911 13 315 16 17 18 19 20

2223 24 25 26 141229 30 31 32 33 34 463738

3941

4342 44

54

45 47

27

48 50

52

51 53

635

21

36 40

VDD

DQ0

DQ1

VSS

DQ2

DQ3

VDDQ

DQ4

DQ5

VDDQ

DQ6

DQ7

VDDQ

DQML

/WE

/CAS

/RAS

/CS

BA0

A10/

APA0 A1 A2 A3

VDD

VSSQA

4 A5 A6 A7 A8 A9

VSSQCK

ECL

K

DQMH

VSS

VDDQ

DQ8

DQ9

VSS

DQ10

DQ11

VDD

DQ12

DQ13

VSSQ

DQ14

DQ15

VSSQA1

1

BA1

A12

NC

GND

MCKE

C8 22uF

/10V

AD3

SDD1

5

AD[0

..20]

SDD1

2AD

20

SDD1

AD17

nRES

ET

VDD3

3

AD6

AD18

SDD2

AD4

VDD3

3

SDD1

0

SDD[

0..1

5]

SDD1

4

CB37

0.1u

F

SDD2

AD14

SDD[

0..1

5]

nBTC

S

SDMC

LK

AD0

CB36

0.1u

F

SDD1

1

SDD7

AD1

SDD3

SDD8

AD1

U6 W19

B320

ABT

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 2723 24

26 25

A15

A14

A13

A12

A11

A10

A9 A8 A19

A20

WE

RESE

T#VP

PW

P#RY

/BY#

A18

A17

A7 A6 A5 A4 A3

A16

BYTE

#VS

SDQ

15/A

-1DQ

7DQ

14DQ

6DQ

13DQ

5DQ

12DQ

4VC

CDQ

11DQ

3DQ

10DQ

2DQ

9DQ

1DQ

8DQ

0OE

#VS

SA2 A1

CE# A0

AD9

nSCA

S

SDD1

5

AD8

AD5

nSW

E

AD14

SDRA

M

nSW

E

AD7

SDD1

4

CB31

0.1u

F

AD13

nOE

nSRA

S

C7 22uF

/10V

BOOT

FLA

SH

SDD7

AD19

AD9

VDD3

3VD

D33

AD15

nRES

ET

nWBE

1

VDD3

3

SDD5

AD10

nWBE

[0..1

]

SDD0

CB34

0.1u

F

GND

nOE

VDD3

3

SDD8

AD8

nSCS

0

nOE

SDD1

3

AD2

AD13 CB

32

0.1u

F

SDD6

AD5

VDD3

3

SDD1

3

AD10

SDD1

1

SDD0

nSW

E

nWBE

0

AD7

AD[0

..20]

3.0

MEM

.SCH

Cust

om

610

Mond

ay, J

anua

ry 0

5, 2

009

Title

Size

Docu

men

t Num

ber

Rev

Date

:Sh

eet

of

nSRA

S

nRES

ET

SDD6

VDD3

3

SDD9

MCKE

CB35

0.1u

F

nWBE

1

nSCS

0

AD6

nSCA

S

nSRA

S

AD12

AD12

SDMC

LK

nBTC

S

nSCA

S

AD3

AD11

SDD4

AD2

SDD3

AD11

AD16

SDD1

nWBE

[0..1

]

SDD1

2

NUC745


Revision B

20

VDD5

V

R35

220

GND

C11

100u

F/16

V

LL1

FB

C10

33uF

/16V

TP5

GND

1

CVDD

33

GND

CB40

0.1u

F

+1.8

V 10

0mA

TP2

VDD3

3

1

CON6

Powe

r JAC

K

1

2

3

IN

GND

GND

LL4

FB

LED5

RED_

LED

12

VDD3

3

CVDD

18

U8 RT91

93-1

8PB

1 2 345

Vin

GND

ENBPVout

U7 RT91

64A-

33PG

312

4

INGNDOUT

OUT

VDD3

3TP

1

VDD

1

VDD3

3

GND

+3.3

V 1A

CVDD

18

LL2

FB

USBV

DD

LED4

RED_

LED

12

CB38

0.1u

F

CB42

22nF

CB39

0.1u

F

GND

C13

22uF

/10V

CVDD

18

TP4

GND

1

Powe

r LE

Ds

TP6

GND

1

TP3

CVDD

18

1

C9 22uF

/10V

CVDD

18

VDD5

V

CVDD

33

GND

POW

ER

AVDD

18

CB41

0.1u

F

TP7

GND

1

LL3

FB

C12

22uF

/10V

C14

22uF

/10V

3.0

POWE

R.SC

H

Cust

om

710

Tues

day,

Mar

ch 0

3, 2

009

Title

Size

Docu

men

t Num

ber

Rev

Date

:Sh

eet

of

R34

220

VDD5

V

LL5

FB

NUC745


Revision B

21

R37

1K

CB46

0.1u

F

LED6

GREE

N_LE

D1

2

URXD

0

U9 SP23

2ECA

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

C1+

V+ C1-

C2+

C2-

V- T2_O

UTR2

_IN

VCC

GND

T1_O

UTR1

_IN

R1_O

UTT1

_IN

T2_I

NR2

_OUT

CON8

DSUB

-9(M

ale)

5 9 4 8 3 7 2 6 1

RP3

8P4R

-22

18

27

36

45

LED8

GREE

N_LE

D1

2

TXD0

RXD1

CB52

0.1u

F

UTXD

0

CB48

0.1u

F

CB51

0.1u

F

VDD3

3

UTXD

0

RXD1

CB47

0.1u

F

GPIO

7

CB49

0.1u

F

TXD0

VDD5

V

TXD0

URXD

1

RXD0

GPIO

8R3

81K

LED7

GREE

N_LE

D1

2

RXD0

RXD0

U10

SP23

2ECA

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10 9

C1+

V+ C1-

C2+

C2-

V- T2_O

UTR2

_IN

VCC

GND

T1_O

UTR1

_IN

R1_O

UTT1

_IN

T2_I

NR2

_OUT

GND

R36

1K

RXD1

GPIO

[10.

.7]

CON7

DSUB

-9(F

eMale

)

1 6 2 7 3 8 4 9 5

UART

1(TX

/RX

only)

GPIO

[10.

.7]

CB50

0.1u

F

RXD0

UTXD

1

VDD3

3

URXD

0

TXD1

VDD5

V

UART

0(TX

/RX

only)

TXD1

TXD1

URXD

1

Fema

le a

nd Mal

e ar

e us

ediff

eren

ce pin

defi

ne!!

!

CB45

0.1u

F

LED9

GREE

N_LE

D1

2

TXD0

UTXD

1

Fema

le a

nd Mal

e ar

e us

ediff

eren

ce pin

defi

ne!!

!

CB43

0.1u

F

R39

1K

GND

3.0

UART

0/1.S

CH

Cust

om

810

Mond

ay, J

anua

ry 0

5, 2

009

Title

Size

Docu

men

t Num

ber

Rev

Date

:Sh

eet

of

CB44

0.1u

F

NUC745


Revision B

22

R43

15K

R41

10K

R40

10K

D1-

LL8

FB

CB55

0.1u

F

LL7

FB

C16

33uF

/16V

USB_

ON/O

FF

D1+

R44 1.5K

VDD3

3

VDD3

3

D2+

D2-

R42

15K

D2-

USB_

FLAG

D1+

C15

33uF

/16V

D2-

D2+

USB

HOST

U11

AIC1

525-

1

1 2 3 45678

CTL

FLAG

GND

NCIN

OUTIN

OUT

CON9

USB

A-TY

PE

1 2 3 4

VBUS

D- D+ GND

D1+

LL6

FB

USB

Devic

e

D1-

D1-

USB_

FLAG

VDD5

V

CB54

0.01

uF

CB53

0.1u

F

USB_

ON/O

FF

CON1

0

mim

i USB

B-T

YPE

1 2 3 4 5

VBUS

D- D+ NC GND

3.0

USB.

SCH

Cust

om

910

Tues

day,

Nov

embe

r 11,

200

8

Title

Size

Docu

men

t Num

ber

Rev

Date

:Sh

eet

of

D2+

NUC745


Revision B

23

DP1

nIRQ

0

D1

D1+

nRXD

0

EXTA

L_15

M

GND

A16

D0

AD2

A18

nECS0

nTXD

0

TCK

AD20

nECS3

GPIO

21

SDD1

5

nECS1

USBVDD

nBTC

S

USBG

ND

nRES

ET

nOE

GPIO

[19.

.18]

GND

GPIO

[10.

.7]

USB_

PWRE

N

GPIO

0

TMS

USB_

ON/O

FF

AD12

GPIO

22

SDD8

nECS

[3..0

]

CB66

0.1u

F

CB56

10pF

(DNE

)

AD[2

0..0

]

GND

CVDD

33

EXT.

I/O in

terfac

e

AD10

A2

nWAIT

GPIO[10..7]

nSW

E

RP6

8P4R

-22

18

27

36

45

D6

A16

MCLK

R50

22

GPIO7

A3

R49

27

CB61

0.1u

F

AD17

CVDD18

D2

USBGND

SDD1

2

GPIO

28

R53

1M

USB i

nterfa

ce

TEST

SDD9

AVDD18

A8

CB69

0.1u

F

Powe

r-ON

set

ting

s

DN0

GPIO

3D1

1

X2 15MH

z Cry

stal

CB72

0.1u

F

nSCS

0MC

KE

SDD8

CVDD

18

CB73

0.1u

F

nECS

[3..0

]

SDD1

4

A7

D5 D0

A9

A15

SDD[

15..0

]

GND

RP7

8P4R

-22

18

27

36

45

nBTC

S

D9

GPIO8

15MHZ

D1

GPIO

[19.

.18]

A11

CB68

0.1u

F

A8

TDI

RP12

8P4R

-22

18

27

36

45

D8

USBVDD

USBGND

GPIO

20

D2

A20

SDD1

2

AD0

AD3

DP1

A1

DN1

CB57

0.1u

F

nTRS

T

MCKE

A12

CB60

0.1u

F

RP9

8P4R

-22

18

27

36

45

nRES

ET

A6

GPIO

19

SDD6

SDD5

GPIO

1

R47

27

RP10

8P4R

-22

18

27

36

45

AD15

GPIO

29

GPIO13

D7

D2-

JTAG

inter

face

SDD7

USBV

DD

TMS

GPIO

[10.

.7]

CB67

0.1u

F

USB_

FLAG

C18

20pF

nSCS

0

GPIO[14..11]

GPIO

27

AD1

SDD1

4

GPIO

[29.

.20]

GPIO

23

DP0

CB65

0.1u

F

RP13

8P4R

-4.7

K

18

27

36

45

D9D4

AD6

C23

22uF

/10V

CB70

0.1u

F

UART

0

GPIO12

USB_

PWRE

N

A5

nSRA

S

nSW

E

D8

JP2

15M/

80M

1 2 3

GND

nRESET

LL10

FB

R54

4.7K

C21

22uF

/10V

80MHZ

A0

SDD1

5

RXD0

nECS2

AVDD18

nOE

AD[2

0..0

]

D14

LL9

FB

AD16

A19

D3

GPIO9

XTAL

_15M

USBG

ND

A9

GPIO14

UART

0

nTRS

T

SDD[

15..0

]

GND

TDO

A13

nIRQ1

GPIO10

CB64

0.1u

F

LITTLE

D3nS

CAS

AVDD18

AD[0

..20]

nTRS

T

GND

C19

22uF

/10V

SDMC

LK

SDD4

A4

D10

nSRA

S

AD5 CB

63

0.1u

F

CVDD

33

TDO

A20

BIG

AVDD

18

A15

D10

A10

CB58

0.1u

F

CB59

0.1u

F

CB71

0.1u

F

TDI

CVDD

33

CVDD

33

GND

D13

TXD0

GPIO

[4..0

]

A4

TDI

A6

GND

nIRQ0

CVDD33

GPIO

24

A14

A13

R46

27AD

11

CVDD

33

nWBE

1

R52

4.7K

JP1

15M/

80M

1 2 3US

B

RXD0

AD13

AD19

nWBE

0

TXD0

CVDD

18

A2

nSRA

S

D11

AD4

AD8

CVDD33

U12

NUC7

45

1234567891011121314151617181920212223242526272829303132

64 63 62 61 60 59 58 57 56 55 54 53 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

97 98 99 100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

9695949392

9091

89888786858483828180797877767574737271706968676665

5152

USBVDDDP1DN1USBVSSUSBVSSDN0DP0USBVDDVDD33TXD0/GPIO[5]RXD0/GPIO[6]TXD1/GPIO[7]RXD1/GPIO[8]CTS1/TXD2(IrDA)/PS2_CLK/GPIO[9]RTS1/RXD2(IrDA)/PS2_DAT/GPIO[10]VSS33SCL0/SFRM/TIMER0/GPIO[11]SDA0/SSPTXD/TIMER1/GPIO[12]SCL1/SCLK/GPIO[13]/KPROW[3]SDA1/SSPRXD/GPIO[14]/KPROW[2]VDD18VSS18VDD33VSS33nRESETTESTPLLVDD18PLLVSS18PLLVSS18PLLVDD18nIRQ[0]/GPIO[16]nIRQ[1]/GPIO[17]/USB_OVRCUR

PHY_

MDC/

GPIO

[29]

/KPR

OW[1

]PH

Y_MD

IO/G

PIO[

28]/K

PROW

[0]

PHY_

TXD[

1]/G

PIO[

27]/K

PCOL

[7]

VDD3

3PH

Y_TX

D[0]

/GPI

O[26

]/KPC

OL[6

]PH

Y_TX

EN/G

PIO[

25]/K

PCOL

[5]

PHY_

REFC

LK/G

PIO[

24]/K

PCOL

[4]

PHY_

RXD[

1]/G

PIO[

23]/K

PCOL

[3]

VSS3

3PH

Y_RX

D[0]

/GPI

O[22

]/KPC

OL[2

]PH

Y_CR

SDV/

GPIO

[21]

/KPC

OL[1

]PH

Y_RX

ERR/

GPIO

[20]

/KPI

OL[0

]

VSS1

8VD

D18

AC97

_BIT

CLK/

I2S_

BITC

LK/P

WM[

3]/R

XD3/

GPIO

[4]

AC97

_SYN

C/I2

S_LR

CLK/

PWM[

2]/T

XD3/

GPIO

[3]

AC97

_DAT

AO/I2

S_DA

TAO/

PWM[

1]/D

SR3/

GPIO

[2]

AC97

_DAT

AI/IS

2_DA

TAI/P

WM[

0]/D

TR3/

GPIO

[1]

AC97

_nRE

SET/

I2S_

MCLK

/GPI

O[0]

/nIR

Q[2]

/USB

_PW

REN

VDD1

8VD

D33

XTAL

(15M

)EX

TAL(

15M)

VSS3

3nW

DOG/

GPIO

[15]

/USB

_PW

REN

nTRS

TTC

KTD

OTD

ITM

S

nBTC

SMC

KEnS

CS[0

]nS

CS[1

]nS

RAS

nSCA

SVD

D33

MCLK

VSS3

3nS

WE

nWBE

[0]/S

DQM[

0]nW

BE[1

]/SDQ

M[1]

VSS1

8D[

15]

D[14

]VD

D18

D[13

]D[

12]

D[11

]D[

10]

VDD3

3D[

9]D[

8]D[

7]D[

6]D[

5]VS

S33

D[4]

D[3]

D[2]

D[1]

D[0]

nWAIT/nIRQ[3]nOE

nECS[0]nECS[1]nECS[2]

nECS[3]VSS33

A[20]A[19]A[18]A[17]

VDD18A[16]A[15]A[14]

VSS18A[13]A[12]A[11]A[10]

VDD33A[9]A[8]A[7]A[6]A[5]

VSS33A[4]A[3]A[2]A[1]A[0]

nXDR

EQ/G

PIO[

19]

nXDA

CK/G

PIO[

18]

nSCA

S

DP0

AVSS18C2

0

22uF

/10V

nIRQ

0

D5

nSCS

0

A14

A18

R51

22

TCK

XTAL

_15M

DN0

D2+

nSW

E

SDD[

0..1

5]

SDD1

D6

nWBE

[1..0

]

D4CVDD

18

C17

20pF

CVDD

18

nIRQ

1

A12

AD9

GPIO

4

nWAI

TD1

4

nBTC

S

AD7

A17

CVDD33

SDD1

3

A10

D15

GPIO

[14.

.11]

SDD0

GND

RP11

8P4R

-22

18

27

36

45

C22

22uF

/10V

MCKE

GPIO

26

JTAG

GPIO

25

GPIO

2

GPIO

[14.

.11]

TMS

A19

R48

27

SDD2

D13

nOE

D1-

3.0

NUC7

45 .S

CH

Cust

om

1010

Wed

nesd

ay, A

pril 0

1, 2

009

Title

Size

Docu

men

t Num

ber

Rev

Date

:Sh

eet

of

nWAI

T

nWBE

[1..0

]

A0

RP8

8P4R

-22

18

27

36

45

R55

4.7K

A5

GPIO

18

CB62

0.1u

F

SDD9

EXTA

L_15

M

TDO

D12

AVSS18

nSCA

S

D15

GND

nECS

[3..0

]

GPIO

[29.

.20]

AVSS

18

D7

SDD1

3

GPIO11

SDD3

TEST

GPIO

[4..0

]

SDD1

1

RP5

8P4R

-22

18

27

36

45

CVDD

33

A1D1

2

MCLK

AD18

GPIO

[19.

.18]

SDD1

0

GPIO

[29.

.20]

CVDD18

nWBE

[1..0

]

A17

CVDD

33

CVDD

18

R45

22

GPIO

[4..0

]

AD14

GND

DN1

EBI in

terfac

e

CVDD

33

A11

A3 A7

GND

RP4

8P4R

-22

18

27

36

45

TCK

nuc745 eval. board user's manual - open ip cam documents/doc... · 2009. 12. 25. · close u3 push...

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