November 3, 2015November 3, 2015 Embry Riddle PrescottEmbry Riddle Prescott

Team #TBDTeam #TBDMember1, Member2, Member3, Member1, Member2, Member3,

Member4 [Alphabetical]Member4 [Alphabetical]

Real-Time Systems Software Proof-of-Real-Time Systems Software Proof-of-ConceptConcept

[12+ Diagram Content Slides, Intro, [12+ Diagram Content Slides, Intro, Roadmap, Summary – Move Irrelevant Roadmap, Summary – Move Irrelevant

Slides to Backup Section]Slides to Backup Section]

Presentation RoadmapPresentation RoadmapCapability RequirementsCapability Requirements

Functional Design (Modelio, Visio Functional Design (Modelio, Visio Stencils, UML Stencils, MS Software Stencils, UML Stencils, MS Software Design Stencils, or Basic Drawing Tools Design Stencils, or Basic Drawing Tools in PowerPoint)in PowerPoint)

Real-Time Requirements: Service Rates Real-Time Requirements: Service Rates (T(Tii), Computational Load (C), Computational Load (C ii), and ), and Deadlines (DDeadlines (Dii) for 2 or More Services S) for 2 or More Services S ii– Cheddare Worst-Case AnalysisCheddare Worst-Case Analysis– Scheduling Point / Completion Point TestsScheduling Point / Completion Point Tests– Feasibility and Safety OverallFeasibility and Safety Overall

Real-Time Analysis & DesignReal-Time Analysis & Design– Cyclic ExecutiveCyclic Executive– RTOSRTOS– Linux POSIX Real-TimeLinux POSIX Real-Time

Proof-of-Concept and Time-stamp TraceProof-of-Concept and Time-stamp Trace

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https://www.modelio.org/

Real-Time Analysis•Timing Diagrams (Worst-Case Analysis)•Cheddar Analysis•Scheduling Point or Completion Test

System Models•Block Diagram

Software Functional Models•CFD/DFD•Entity Relationship Diagram (ERD)•Mealy/Moore State Machine•Flowchart

CASE TOOLS USED: Modelio, Cheddar, Other?

http://beru.univ-brest.fr/~singhoff/cheddar/

Key Functional SA/SD Models – Content #1Key Functional SA/SD Models – Content #1

CFD/DFD - CFD/DFD - Transformation/EvTransformation/Even-Drivenen-Driven

ER/EER - ER/EER - Information ModelInformation Model

State Machine – State Machine – BehavioralBehavioral

Flow-Charts – Flow-Charts – Detailed Detailed ProceduralProcedural

Sam SiewertSam Siewert 33

http://en.wikipedia.org/wiki/Finite-state_machine

http://en.wikipedia.org/wiki/Data_flow_diagram

http://en.wikipedia.org/wiki/Entity%E2%80%93relationship_model

http://en.wikipedia.org/wiki/Flowchart

CFD/DFD

ER/EER

SM/EFSM

Flowchart

System Block Diagram – Content #2System Block Diagram – Content #2Any Useful Information about SystemAny Useful Information about System

Keep it Simple – One Page View of EverythingKeep it Simple – One Page View of Everything

Users, IT, Software, External Systems and HardwareUsers, IT, Software, External Systems and Hardware

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Software System Service, Task, Process,

etc.

Hardware or Other System External

EntityI/O label I/O label

I/O label

End Users

System Administration

Cloud Service

Cloud Service

I/O label

Capability RequirementsCapability Requirements

1.1. Capability #1Capability #1

2.2. Capability #2Capability #2

3.3. Capability #3Capability #3

4.4. Capability #4Capability #4

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Real-Time RequirementsReal-Time Requirements

1.1. RT Requirement #1RT Requirement #1

2.2. RT Requirement #2RT Requirement #2

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Performance RequirementsPerformance Requirements

1.1. WCET Requirement #1WCET Requirement #1

2.2. WCET Requirement #2WCET Requirement #2

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Service Set Feasibility and Safety Service Set Feasibility and Safety ANALYSISANALYSIS

WCETWCET

Expected CiExpected Ci

RM LUB TestRM LUB Test

Cheddar Analysis for Worst-Case and SimulationCheddar Analysis for Worst-Case and Simulation

Scheduling Point, Completion TestScheduling Point, Completion Test

FeasibilityFeasibility

MarginMargin

SafetySafety

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SA/SD CFD/DFD DESIGNSA/SD CFD/DFD DESIGN

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ER/EER DESIGNER/EER DESIGN

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SA/SD State Machine DESIGNSA/SD State Machine DESIGN

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SA/SD Flowchart DESIGNSA/SD Flowchart DESIGN

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Proof-of-Concept ANALYSISProof-of-Concept ANALYSIS

Detailed Description of Platform Resources (Jetson TK1 Detailed Description of Platform Resources (Jetson TK1 or Texas Instruments Tiva TM4C Dev Board)or Texas Instruments Tiva TM4C Dev Board)

Prototype Implementation of Key Services (2+)Prototype Implementation of Key Services (2+)

Time-stamp Tracing of Key ServicesTime-stamp Tracing of Key Services

[Profiling of Key Services - Optional][Profiling of Key Services - Optional]

PurposePurpose– Addresses High Risk Design/ImplementationAddresses High Risk Design/Implementation– Real-Time Risks (Deadline, Deadlock, Inversion)Real-Time Risks (Deadline, Deadlock, Inversion)– Resource Use AnalysisResource Use Analysis– Resource Margin for SafetyResource Margin for Safety

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Highlight Concurrent Verification & Highlight Concurrent Verification & Validation PlansValidation Plans

Sam SiewertSam Siewert 1414

Software Engineering: A Practitioner’s Approach, 8/e (McGraw-Hill, 2014)

copyright 2014 by Roger Pressman

BacklogBacklog– Requirements, Design Requirements, Design

Validation, Validation, Requirements (RT and Requirements (RT and Funcional), Design Funcional), Design Verification PlansVerification Plans

– Acceptance Test PlansAcceptance Test Plans– System TestingSystem Testing– Integration TestingIntegration Testing– Unit TestingUnit Testing– Component DesignComponent Design– Code GenerationCode Generation

SummarySummary

Thank AudienceThank Audience

Encourage Submission of Deficiency SheetsEncourage Submission of Deficiency Sheets

Open to Q&A for 10 MinutesOpen to Q&A for 10 Minutes

Sam SiewertSam Siewert 1515

Backup SlidesBackup Slides

Move Slides Not Making MUST Move Slides Not Making MUST PRESENT Status to HERE for Q&APRESENT Status to HERE for Q&A

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