new transactional memory: myths and limitslpd · 2010. 10. 12. · transactional memory that will...
TRANSCRIPT
![Page 1: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/1.jpg)
Transactional Memory: Myths and Limits
R. Guerraoui, EPFL
![Page 2: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/2.jpg)
![Page 3: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/3.jpg)
![Page 4: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/4.jpg)
![Page 5: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/5.jpg)
This tutorial is about
Principles of transactional memory
![Page 6: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/6.jpg)
1. Why do we care?
Transactional memory
2. What should we expect?
3. What might we expect?
![Page 7: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/7.jpg)
1. Why do we care?
Transactional memory
![Page 8: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/8.jpg)
From the New York Times San Francisco, May 7, 2004
Intel announces a drastic change in its business strategy:
« Multicore is THE way to boost performance »
![Page 9: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/9.jpg)
10/12/10 Transactional Memory: Part I — P. Felber 9
• Transistor count still rising according to Moore’s Law
• Clock speed flattening
![Page 10: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/10.jpg)
10
" Multicores are the only way to increase performance
" Indeed single-thread performance doesn’t improve… … but we can put more cores on a chip
![Page 11: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/11.jpg)
" Dual-core commonplace in laptops " Quad-core in desktops " Dual quad-core in servers " All major chip manufacturers produce
multicore CPUs " SUN Niagara (8 cores, 32 concurrent threads) " Intel Xeon (4 cores) " AMD Opteron (4 cores) " …
![Page 12: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/12.jpg)
![Page 13: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/13.jpg)
L1 cache
L2 cache
L3 cache (shared)
![Page 14: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/14.jpg)
" Two fundamental components that fall apart: processors and memory
" The Interconnect links the processors with the memory:
" - SMP (symmetric): bus (a tiny Ethernet) " - NUMA (network): point-to-point network
![Page 15: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/15.jpg)
" The basic unit of time is the cycle: time to execute an instruction
" This changes with technology but the relative cost of instructions (local vs memory) does not
![Page 16: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/16.jpg)
Simple view
![Page 17: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/17.jpg)
" The basic unit of communication is the read and write to the memory (through the cache)
" More sophisticated objects are sometimes provided: C&S, T&S, LL/SC
![Page 18: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/18.jpg)
The free ride is over
![Page 19: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/19.jpg)
" Cannot rely on CPUs getting faster
" Utilizing more than one CPU core requires thread-level parallelism (TLP)
![Page 20: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/20.jpg)
Every one will need to fork threads
Travailler plus pour gagner plus
![Page 21: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/21.jpg)
Forking threads is easy
Handling their conflicts is hard
![Page 22: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/22.jpg)
1x 2x
4x
Time: Moore’s Law
Speedup
User code
Traditional CPU
![Page 23: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/23.jpg)
Speedup
1x 2x
4x
User code
Multicore CPU
Time: Moore’s Law
![Page 24: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/24.jpg)
Speedup
1x 1.4x
2.2x
User code
Multicore CPU
Time: Moore’s Law
Parallelization & synchronization require great care!
![Page 25: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/25.jpg)
The problem Sharing
![Page 26: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/26.jpg)
public class Counter
private long value;
public Counter(int i) { value = i;}
public long getAndIncrement() { return value++; }
Counter
![Page 27: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/27.jpg)
How to synchronize?
Shared object
Concurrent processes
![Page 28: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/28.jpg)
Locked object
Locking (mutual exclusion)
![Page 29: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/29.jpg)
Locking with compare&swap()
A Compare&Swap object maintains a value x, init to ⊥, and y;
It provides one operation: c&s(v,w);
Sequential spec: ● c&s(old,new) {y := x; if x = old then x := new; return(y)}
![Page 30: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/30.jpg)
lock() { repeat until unlocked = this.c&s(unlocked,locked) }
unlock() { this.c&s(locked,unlocked) }
Locking with compare&swap()
![Page 31: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/31.jpg)
lock() { while (true) { repeat until (unlocked = this.getState()); if unlocked = (this.c&s()) return(true); } }
unlock() { this.setState(0); }
Locking with compare&swap()
![Page 32: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/32.jpg)
Lock l = ...; l.lock(); try { // access the resource protected by this lock } finally { l.unlock(); }
Explicit use of a lock
![Page 33: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/33.jpg)
public class SynchronizedCounter { private int c = 0; public synchronized void increment() { c++; } public synchronized void getAndincrement() { c++; return c; } public synchronized int value() { return c; } }
Implicit use of a lock
![Page 34: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/34.jpg)
Locking is the current state of concurrency affairs
![Page 35: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/35.jpg)
The use of locks is dangerous
" 50% of the bugs reported in Java come from the mis-use of « synchronized »
![Page 36: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/36.jpg)
Coarse grained locks => slow
Fine grained locks => errors
![Page 37: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/37.jpg)
Double-ended queue
Enqueue Dequeue
![Page 38: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/38.jpg)
Fine-grained locking
" It took two years for the Java Standards Committee to approve (in Java 5) a fine-grained locking-based implementation of a hash-table
![Page 39: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/39.jpg)
Locks do not compose
Dequeue
Enqueue
![Page 40: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/40.jpg)
Lock-free computing?
Every lock-free data structure ⇒ podc/spaa/disc
![Page 41: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/41.jpg)
Wanted
A concurrency control abstraction that is simple and efficient
![Page 42: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/42.jpg)
Transactions
![Page 43: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/43.jpg)
Historical perspective " Eswaran et al (CACM’76) Databases " Papadimitriou (JACM’79) Theory " Liskov/Sheifler (TOPLAS’82) Language " Knight (ICFP’86) Architecture " Herlihy/Moss (ISCA’93) Hardware " Shavit/Touitou (PODC’95) Software " Herlihy et al (PODC’03) Software - Dynamic
" Now: DISC/PODC/POPL/PLDI/ECOOP/OOPSLA-SPLASH/CAV…Transact
![Page 44: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/44.jpg)
" accessing object 1; " accessing object 2;
Back to the undergraduate level
![Page 45: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/45.jpg)
" accessing object 1; " accessing object 2;
Back to the undergraduate level
atomic {
}
![Page 46: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/46.jpg)
" class Queue { " QNode head; " QNode tail; " public enq(Object x) { " atomic { " QNode q = new QNode(x); " q.next = head; " head = q; " } " } " ... }
![Page 47: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/47.jpg)
Simple example! (consistency invariant)
0 < x < y"
![Page 48: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/48.jpg)
" T: x := x+1 ; y:= y+1
Simple example! (transaction)
![Page 49: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/49.jpg)
" accessing object 1; " accessing object 2;
The illusion of a critical section
atomic {
}
![Page 50: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/50.jpg)
How to provide that illusion?
Software (STM) or Hardware (HTM)?
![Page 51: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/51.jpg)
The garbage-collection analogy " In the early times, the programmers had to take
care of allocating and de-allocating memory
" The GC gives the illusion of infinite memory
" A hardware support was initially expected, but now software solutions are very effective
![Page 52: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/52.jpg)
Hardware
Transactional Memory
Program
![Page 53: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/53.jpg)
Behind the scenes
![Page 54: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/54.jpg)
Two-phase locking (2PL)
" To write O, T requires a lock on O; T waits if some T’ acquired a lock on O
" To read O, T requires a lock on O; T waits if some T’ acquired a lock on O
" Before committing, T releases all its locks
![Page 55: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/55.jpg)
Two-phase locking (2PL)
" To write O, T wait to for a lock on O;
" To read O, T waits to for a lock on O;
" Before committing, T releases all its locks
![Page 56: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/56.jpg)
Two-phase locking (more details)
" Every object O, with state s(O) (a register), is protected by a lock l(O) (a c&s)
" Every transaction has local variables wSet and wLog
" Initially: l(O) = unlocked, wSet = wLog = empty
![Page 57: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/57.jpg)
Two-phase locking
Upon op = read() or write(v) on object O if O outside wSet then
wait until unlocked= l(O).c&s(unlocked,locked) wSet = wSet U O wLog = wLog U S(O).read() if op = read() then return S(O).read() S(O).write(v) return ok
![Page 58: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/58.jpg)
Two-phase locking (cont’d) Upon commit() cleanup() return ok
Upon abort() rollback() cleanup() return ok
![Page 59: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/59.jpg)
Two-phase locking (cont’d)
Upon rollback() for all O in wSet do S(O).write(wLog(O)) wLog = empty
Upon cleanup() for all O in wSet do l(O).c&s(locked,unlocked) wSet = empty
![Page 60: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/60.jpg)
Why two phases? (what if?)
" To write or read O, T requires a lock on O; T waits if some T’ acquired a lock on O
" T releases the lock on O when it is done with O
![Page 61: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/61.jpg)
Why two phases?
T1
T2
read(0) write(1)
O1 O2
read(0) write(1)
O2 O1
![Page 62: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/62.jpg)
No STM implements 2PL
All implement a variant of it
![Page 63: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/63.jpg)
Two-phase locking (read-write lock)
" To write O, T requires a write-lock on O; T waits if some T’ acquired a lock on O
" To read O, T requires a read-lock on O; T waits if some T’ acquired a write-lock on O
" Before committing, T releases all its locks
![Page 64: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/64.jpg)
Two-phase locking - better dead than wait -
" To write O, T requires a write-lock on O; " T aborts if some T’ acquired a lock on O
" To read O, T requires a read-lock on O; " T aborts if some T’ acquired a lock on O
" Before committing, T releases all its locks
![Page 65: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/65.jpg)
Two-phase locking - better kill than wait -
" To write O, T requires a write-lock on O; T aborts T’ if some T’ acquired a lock on O
" To read O, T requires a read-lock on O; T waits if some T’ acquired a write-lock on O
" Before committing, T releases all its locks " A transaction that is aborted restarts again
![Page 66: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/66.jpg)
Visible Read (SXM; RSTM)
" Write is mega killer: to write an object, a transaction aborts any live one which has read or written the object
" Read is visible: when a transaction reads an object, it says so
![Page 67: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/67.jpg)
Visible Read
" A visible read invalidates cache lines
" This reduces the throughput of read-dominated workloads, by inducing a lot of traffic on the bus
![Page 68: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/68.jpg)
Two-phase locking - invisible reads – DSTM -
" To write O, T requires a write-lock on O; T aborts T’ if some T’ acquired a write-lock on O
" To read O, T checks if all objects read remain valid - else T aborts
" Before committing, T checks if all objects read remain valid and releases all its locks
![Page 69: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/69.jpg)
Invisible reads (more details)
" Every object O, with state s(O) (register), is protected by a lock l(O) (c&s)
" Every transaction maintains, besides wSet and wLog:
" - a local variable rset(O) for every object
![Page 70: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/70.jpg)
Invisible reads
Upon write(v) on object O if O outside wSet then wait until unlocked= l(O).c&s(unlocked,locked) wSet = wSet U O wLog = wLog U S(O).read() (*,ts) = S(O).read() S(O).write(v,ts) return ok
![Page 71: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/71.jpg)
Invisible reads
Upon read() on object O (v,ts) = S(O).read() if O in wSet then return v if l(O) = locked or not validate() then abort() if rset(O) = 0 then rset(O) = ts return v
![Page 72: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/72.jpg)
Invisible reads
Upon validate() for all O s.t rset(O) > 0 do (v,ts) = S(O).read() if ts not rset(O) or (O outside wset and l(O) = locked) then return false else return true
![Page 73: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/73.jpg)
Invisible reads
Upon commit() s := validate() for all O in wset do (v,ts) = S(O).read() S(O).write(v,ts+1) cleanup() if s then commit() else abort()
![Page 74: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/74.jpg)
Invisible reads
Upon rollback() for all O in wSet do S(O).write(wLog(O)) wLog = empty
Upon cleanup() for all O in wset do l(O).c&s(locked,unlocked) wset = empty rset(O) = 0 for all O
![Page 75: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/75.jpg)
DSTM
" Killer write (ownership)
" Careful read (validation)
![Page 76: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/76.jpg)
Performance figures look good
![Page 77: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/77.jpg)
" “It is better for Intel to get involved in this [Transactional Memory] now so when we get to the point of having …tons… of cores we will have the answers”
" Justin Rattner, Intel Chief Technology Officer
![Page 78: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/78.jpg)
" “…we need to explore new techniques like transactional memory that will allow us to get the full benefit of all those transistors and map that into higher and higher performance.”
" Bill Gates, Businessman
![Page 79: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/79.jpg)
" “…manual synchronization is intractable…transactions are the only plausible solution….”
" Tim Sweeney, Epic Games
![Page 80: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/80.jpg)
" Sun, Intel, AMD, IBM, MSR, …
" Fortress (Sun); X10 (IBM); Chapel (Cray)
The TM Topic is VERY HOT
![Page 81: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/81.jpg)
All set?
Hmmm….
![Page 82: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/82.jpg)
Tests
" Micro-Benchmarks " Linked-lists; red-black trees, etc. " Consider specific loads: typically focus on read-only transactions
![Page 83: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/83.jpg)
Challenging TMs STMBench7 (GKV’07)
" Large data structure: challenge memory overhead
" Short and long operations: kills non-linear algorithms
" Complex access patterns"
![Page 84: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/84.jpg)
STMBench7
" Performance figures were not that good
" All TMs eventually collapsed because of memory usage (except X)
![Page 85: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/85.jpg)
A new generation
" SwissTM, " TL2, " TinySTM,…
![Page 86: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/86.jpg)
Speedup
1x 1.4x
2.2x
User code
Multicore CPU
Time: Moore’s Law
Parallelization & synchronization require great care!
![Page 87: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/87.jpg)
Software Transactional Memory: Why is it only a Research Toy (CACM 2009)
C. Cascaval, C. Blundell, M. Michael, H. Cain, P. Wu, S. Chiras, S. Chatterjee
![Page 88: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/88.jpg)
Why STM can be more than a Research Toy (CACM 2010)
A. Dragojević, P. Felber, V. Gramoli, R. Guerraoui
![Page 89: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/89.jpg)
![Page 90: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/90.jpg)
Wanted
Some principles
![Page 91: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/91.jpg)
1. Why do we care?
Transactional memory
2. What should we expect?
3. What might we expect?
Simplicity
What safety property?
![Page 92: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/92.jpg)
Transactional memory
Program
TM
Hardware
![Page 93: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/93.jpg)
Safety of a TM
Let’s recall the old good atomicity property
Gray,Papadimitriou,Weihl,..
![Page 94: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/94.jpg)
Transactions and objects
" Transactions invoke operations on shared objects
" Every operation invocation is expected to return a reply
" Every transaction is expected either to abort or commit
![Page 95: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/95.jpg)
Application Scheduler
TM
Hardware
![Page 96: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/96.jpg)
Transactions and objects
T1
T2
T3
operation
operation
operation
commit
abort
commit operation
![Page 97: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/97.jpg)
Transactions and objects
T1
T2
T3
operation
operation
operation
commit
abort
commit operation
O1
O1
O2
O2
![Page 98: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/98.jpg)
Transactions
" Transactions are sequential units of computations
" Transactions are asynchronous
(pre-emption, page faults, crashes)
![Page 99: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/99.jpg)
Histories
" The execution of a set of transactions on a set of objects is modeled by a history
" A history is a total order of operation, commit and abort events " H = (S,<)
The history depicts what the user sees
![Page 100: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/100.jpg)
History H1
T1
T2
read(0) write(1)
read(0)
commit
commit write(1)
O2
O1 O2
O1
![Page 101: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/101.jpg)
Histories " Two transactions are sequential (in a history) if
one invokes its first operation after the other one commits or aborts; they are concurrent otherwise
" A history is sequential if it has only sequential transactions; it is concurrent otherwise
" Two histories are equivalent if they have the same transactions
![Page 102: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/102.jpg)
Sequential history H2 <=> H1
read(0) write(1)
read(0) write(1)
O2
O1 O2
O1
T1
T2
commit
commit
![Page 103: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/103.jpg)
A history is atomic if its restriction to committed transactions is serializable
The old theory (Pap 79)
![Page 104: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/104.jpg)
A history H of committed transactions is serializable if there is a history S(H) that is (1) equivalent to H (2) sequential (3) has every read returns the last value written
![Page 105: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/105.jpg)
Atomic history?
T1
T2
read(0) write(1)
read(0)
commit
commit write(1)
O2
O1 O2
O1
![Page 106: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/106.jpg)
Sequential history?
T1
T2
read(0) write(1)
read(0) write(1)
O2
O1 O2
O1
![Page 107: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/107.jpg)
Sequential history?
T1
T2
read(0) write(1)
read(0) write(1)
O2
O1 O2
O1
![Page 108: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/108.jpg)
Atomic history?
T1
T2
read(0) write(0)
read(0)
commit
commit write(1)
O2
O1 O2
O1
![Page 109: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/109.jpg)
Sequential history
read(0) write(0)
read(0) write(1)
O2
O1 O2
O1
T1
T2
![Page 110: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/110.jpg)
A history H of committed transactions is serializable if there is a history S(H) that is (1) equivalent to H (2) sequential (3) has every read returns the last value written
![Page 111: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/111.jpg)
Atomic history
T1
T2
read(0) write(1)
read(0)
commit
abort write(1)
O2
O1 O2
O1
![Page 112: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/112.jpg)
A history H of committed transactions is serializable if there is a history S(H) that is (1) equivalent to H (2) sequential (3) has every read return the last value written
![Page 113: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/113.jpg)
There is more to shared objects than read/write registers, e.g., queues, compare&swap, counters, etc
All these objects have a sequential specification (Weihl)
![Page 114: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/114.jpg)
Sequential specification of a register
" Sequential specification
" read()
" return(x)
" write(v)
" x <- v;
" return(ok)
![Page 115: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/115.jpg)
Queue
" A queue has two operations: enqueue() and dequeue()
" A queue internally maintains a list x which exports operation appends() to put an item at the end of the list and remove() to remove an element from the head of the list
![Page 116: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/116.jpg)
Sequential specification
" dequeue()
" if(x=0) then return(nil);
" else return(x.remove())
" enqueue(v)
" x.append(v);
" return(ok)
![Page 117: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/117.jpg)
A sequential history is legal if each restriction to an object belongs to its sequential specification
Legal history
![Page 118: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/118.jpg)
Legal history
read(0) write(0)
read(0) write(1)
O2
O1 O2
O1
![Page 119: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/119.jpg)
Legal history
enq(a) deq(nil)
enq(b) deq(a)
O2
O1 O2
O1
![Page 120: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/120.jpg)
A history H of committed transactions is serializable if there is a history S(H) that is (1) equivalent to H (2) sequential (3) legal
![Page 121: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/121.jpg)
write(1)
read(0)
O1
O1
commit
commit
T1
T2
Real-time
![Page 122: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/122.jpg)
Histories " Two histories are equivalent if they have the
same transactions
" Two histories are strictly equivalent if they have the same transactions in the same order
![Page 123: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/123.jpg)
A history H of committed transactions is strictly serializable if there is a history S(H) that is (1) strictly equivalent to H (2) sequential (3) legal
Atomicity
![Page 124: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/124.jpg)
Is classical atomicity enough?
![Page 125: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/125.jpg)
![Page 126: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/126.jpg)
DSTM
" To write O, T requires a write-lock on O; T aborts T’ if some T’ acquired a write-lock on O
" To read O, T checks if all objects read remain valid - else abort
" At commit time, T checks if all objects read remain valid and releases all its locks
![Page 127: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/127.jpg)
DSTM
" Killer write (ownership)
" Careful read (validation)
![Page 128: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/128.jpg)
More efficient algorithm
Apologizing versus asking permission
" Killer write " Optimistic read
" validity check only at commit time
![Page 129: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/129.jpg)
Example!
Invariant: 0 < x < y"Initially: x := 1; y := 2"
![Page 130: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/130.jpg)
Division by zero
" T1: x := x+1 ; y:= y+1
" T2: z := 1 / (y - x)
![Page 131: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/131.jpg)
" T1: x := 3; y:= 6
Infinite loop
" T2: a := y; b:= x; repeat b:= b + 1 until a = b
![Page 132: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/132.jpg)
We need a theory that restricts ALL transactions: this is what critical sections give us
The old theory restricts committed transactions
![Page 133: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/133.jpg)
How can we capture that precisely?
Requirement: every operation sees a consistent state
![Page 134: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/134.jpg)
Histories
" Let H be any history (made of commited, aborted and pending transactions)
" Complete(H) is the history made of all transactions of H by removing all pending and aborted ones, except the last one, completed with a commit event
![Page 135: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/135.jpg)
A history H is opaque if every prefix H’ of H has a complete(H’) which is strictly serialisable
Opacity (GK’08)
![Page 136: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/136.jpg)
Opacity?
T1
T2
read(0)
write(1)
commit
abort read(0)
O2
O2
O1
write(1) O1
![Page 137: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/137.jpg)
Illegal
T1
T2
read(0)
write(1)
commit
read(0)
O2
O2
O1
write(1) O1
![Page 138: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/138.jpg)
Illegal
T1
T2
read(0)
write(1)
commit
read(0)
O2
O2
O1
write(1) O1
![Page 139: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/139.jpg)
Recoverable (no dirty reads)
T1
T2
read(0)
write(1) commit write(1)
O2
O2
O1
read(0) O1
abort
![Page 140: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/140.jpg)
Opacity < rigorous scheduling
T1
T2
write(0)
write(1)
commit
abort write(1)
O2
O2
O1
write(0) O1
![Page 141: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/141.jpg)
Most TMs ensure Opacity
![Page 142: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/142.jpg)
Simple algorithm (DSTM)
" Killer write (ownership)
" Careful read (validation)
![Page 143: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/143.jpg)
Visible Read (SXM; RSTM)
" Write is super killer: to write an object, a transaction aborts any live one which has read or written the object
" Visible but not so careful read: when a transaction reads an object, it says so
![Page 144: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/144.jpg)
Visible Read
" A visible read invalidates cache lines
" For read-dominated workloads, this means a lot of traffic on the bus between processors
" This would reduce the throughput
![Page 145: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/145.jpg)
Theorem (GK’08)
The read is either visible or careful
NB. Modulo a weak progress property and the assumption of a single version system
![Page 146: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/146.jpg)
Intuition of the proof
T1
T2
read()
write() commit
I1,I2,..,Im
O1,O2,..,On read() Ik
![Page 147: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/147.jpg)
Read invisibility
" The fact that the read is invisible means T1 cannot inform T2, which would in turn abort T1 if it accessed similar objects (SXM, RSTM)
![Page 148: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/148.jpg)
The theorem does not hold for classical atomicity
i.e., the theorem does not hold for database transactions
![Page 149: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/149.jpg)
![Page 150: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/150.jpg)
How can we verify the opacity of a TM?
" Check that the conflict graph is acyclic " Number of nodes is unbounded " NP-Complete problem
![Page 151: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/151.jpg)
Reduce the verification space
" Uniform system " All transactions are treated equally " All variables are treated equally
![Page 152: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/152.jpg)
TM verification theorem (GHS’08)
" A TM either violates opacity with 2 transactions and 3 variables or satisfies it with any number of variables and transactions
![Page 153: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/153.jpg)
Reference implementation " A finite-state transition system (12.500
states) generates all opaque histories for 2 transactions and 3 variables
" A TM is correct if its histories could be generated by the reference implementation
" Simulation relation between the TM (e.g., TL2 4500 states) and the reference implementation
![Page 154: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/154.jpg)
Examples
" It takes 15mn to check the correctness of TL2 and DSTM
" Reverse two lines in TL2: bug found in 10mn - a history not permitted by the reference implementation
![Page 155: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/155.jpg)
1. Why do we care?
Transactional memory
2. What should we expect?
3. What might we expect?
Opacity
What progress?
Simplicity
![Page 156: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/156.jpg)
What might we expect?
Program T1/T2/../Tn
TM
Block Abort
![Page 157: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/157.jpg)
We want progress
" Operations return
" Transactions commit
![Page 158: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/158.jpg)
Nevertheless
" We cannot require from a TM that it commits transactions: " from a dead process; i.e., a dead transaction " that infinitely loop
![Page 159: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/159.jpg)
Progress?
T2 read(0) ?
O2 crash
T1 read(0) ?
O2 read(0)
O2 read(0)
O2 read(0)
O2
![Page 160: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/160.jpg)
Progress
" We can only hope progress for correct transactions
" But what is a correct transaction exactly?
![Page 161: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/161.jpg)
Correctness depends on the scheduler and the application
Application R/W/C/A Scheduler
TM R/W/C&S/T&S/LL&SC/C/A
![Page 162: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/162.jpg)
History
" A history (as seen by the user) does not say what the scheduler does
" We need a refined notion of history
![Page 163: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/163.jpg)
Low-level history
" A low-level history depicts the events of the implementation
" It is also a total order of invocation, reply, and termination events " H = (S,<)
![Page 164: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/164.jpg)
Low-level history
" The invocations and replies include also low-level objects used in the implementation
" The low-level history is a refinement of the high-level one (seen by the user)
![Page 165: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/165.jpg)
Low-level history
" Well-formed (low-level) history: " Every transaction that aborts is immediately
repeated until it commits, i.e., :
Every process executes: T1:op1; T1.op2; ..; T1:Commit?; T1:Abort; T1:op1;.. …
![Page 166: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/166.jpg)
Low-level history
" A transaction T is correct if " (a) commit is invoked after a finite
number of invocation/reply events of T and " (b) either T commits or T performs an
infinite number of (low-level) steps
" (a) depends on the application " (b) depends on the scheduler
![Page 167: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/167.jpg)
Ideally
" Every correct transaction commits
![Page 168: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/168.jpg)
T1
T2
read()
write()
commit
O1
O1
write()
O2
Aborting is a fatality
read()
O2
abort
![Page 169: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/169.jpg)
Eventual progress - wait-freedom -
" Every correct transaction eventually commits
" NB. We allow the possibility for a transaction to abort a finite number of times as long as it eventually commits
![Page 170: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/170.jpg)
Eventual progress
T1
T2
read()
write()
commit
O1
O1
write()
O2
read()
O2
abort
![Page 171: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/171.jpg)
" Impossible in an asynchronous system
Eventual progress
" NB. This impossibility is fundamentally different from FLP: It holds for any underlying object
![Page 172: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/172.jpg)
Conditional progress - obstruction-freedom -
" A correct transaction that eventually does not encounter contention eventually commits
" Obstruction-freedom is indeed possible
![Page 173: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/173.jpg)
DSTM " To write O, T requires a write-lock on O (use C&S); T aborts T’ if some T’ acquired a write-lock on O (use C&S)
" To read O, T checks if all objects read remain valid - else abort (use C&S)
" Before committing, T releases all its locks (use C&S)
![Page 174: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/174.jpg)
DSTM uses C&S
" C&S is the strongest synchronization primitive
" Is OF-TM possible with less than C&S? e.g., R/W objects
![Page 175: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/175.jpg)
OF-TM
Program R/W/TC/A Scheduler
TM
Low-level objects?
![Page 176: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/176.jpg)
Compare&Swap
Register
Queue Test&Set
…
Fetch&Add
Snapshot (1)
(2)
(∞)
(..)
Consensus number of OF-TM?
![Page 177: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/177.jpg)
FO-consensus
A process can decide or abort " No two different values can be decided " A value decided was proposed
" If abort is returned from propose(v) then (1) there is contention and (2) v cannot be returned
![Page 178: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/178.jpg)
OF-TM <=> FO-consensus
" From OF-TM to FO-consensus: propose() is performed within a transaction
" From FO-consensus to OF-TM: slightly more tricky - as for DSTM but using a one shot object instead of C&S
![Page 179: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/179.jpg)
Consensus
propose(vi) returns a value vj (no abort)
" No two different values can be decided " A value decided was proposed
![Page 180: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/180.jpg)
OF-consensus vs consensus
" OF-consensus can implement consensus among exactly 2 processes
" Algorithm " P1 writes its value and keeps proposing until it
decides a value " P2 either decides or reads the value
![Page 181: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/181.jpg)
Computability
The consensus number of OF-TM is 2
" OF-TM cannot be implemented with R/W
" OF-TM does not need C&S
![Page 182: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/182.jpg)
Simplicity 1. Why do we care?
Transactional memory
2. What should we expect?
3. What might we expect? Opacity
Obstruction-freedom
![Page 183: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/183.jpg)
Those are my principles
If you don’t like them
I have others
G. Marx
![Page 184: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/184.jpg)
What opacity in the jungle ?
![Page 185: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/185.jpg)
Two ways compatibility (GHKS10)
Program
TM
Hardware
![Page 186: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/186.jpg)
What progress beyond OF?
![Page 187: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/187.jpg)
Boosting obstruction-freedom
OF-TM CM
![Page 188: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/188.jpg)
Contention managers " Aggressive: always aborts the victim
" Backoff: wait for some time (exponential backoff) and then abort the victim
" Karma: priority = cumulative number of shared objects accessed – work estimate. Abort the victim when number of retries exceeds difference in priorities.
" Polka: Karma + backoff waiting
![Page 189: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/189.jpg)
Greedy contention manager
" State " Priority (based on start time) " Waiting flag (set while waiting)
" Wait if other has " Higher priority AND not waiting
" Abort other if " Lower priority OR waiting
![Page 190: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/190.jpg)
Off-line scheduler (GHP’95)
" Compare the TM protocol with an off-line scheduler that knows:
" The starting time of transactions " Which objects are accessed (i.e., conflicts)
![Page 191: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/191.jpg)
Competitive ratio
" Let s be the number of objects accessed by all transactions
" Compare time to commit all transactions " Greedy is O(s)-competitive with the off-line
scheduler " GHP’05 O(s2) " AEST’06 O(s)
![Page 192: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/192.jpg)
What progress beyond OF?
![Page 193: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/193.jpg)
OF-TM CM: <>P
WF-TM
The weakest CM-FD to implement WF-TM (GKK’06)
![Page 194: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/194.jpg)
Eventual global progress - lock-freedom -
" Some correct transaction eventually commits
" NB. OSTM ensures eventual global progress
" Eventual global progress is the strongest liveness property that can be ensured by an STM
![Page 195: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/195.jpg)
Permissiveness (GHS’08)
A TM is permissive if it never aborts when it should not
![Page 196: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/196.jpg)
Permissiveness
" Let P be any safety property and H any P-safe history prefix of a deterministic TM
" We say that a TM is permissive w.r.t P if " Whenever <H;commit> satisfies P " <H;commit> can be generated by the TM
![Page 197: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/197.jpg)
Permissiveness
" No TM can be permissive with respect to opacity (or serializability)
![Page 198: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/198.jpg)
Probabilistic permissiveness
" Let P be any safety property and H any history generated by a TM
" The TM is probabilistic permissive with respect to P if " Whenever <H;commit> satisfies P: " <H;commit> can be generated by TM
with a positive probability
![Page 199: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/199.jpg)
Probabilistic permissiveness
" There is a probabilistically permissive TM with respect to opacity: AVSTM
" AVSTM should outperform all TMs
" In theory…
![Page 200: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/200.jpg)
Probabilistic permissiveness
" AVSTM indeed outperforms all TMs under very high contention
" AVSTM does not perform well under low contention
" AVSTM combined with a pragmatic TM: " TL2 under normal mode and then fall-
back to AVSTM
![Page 201: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/201.jpg)
Transactions are conquering the parallel programming world
They sound familiar and thus make the programmer happy
Getting them correct is in fact tricky and that should make YOU happy
A slide to remember
![Page 202: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/202.jpg)
![Page 203: New Transactional Memory: Myths and Limitslpd · 2010. 10. 12. · transactional memory that will allow us to get the full benefit of all those transistors and map that into higher](https://reader034.vdocuments.site/reader034/viewer/2022051904/5ff62ebcad45256f270af435/html5/thumbnails/203.jpg)
" lpdwww.epfl.ch
" Transactions@epfl
Biblio