neutral point potential control for three phase 3-level ... · interference with neighbouring...

International Journal on Electrical Engineering and Informatics - Volume 9, Number 2, June 2017

Neutral Point Potential Control for Three Phase 3-level Neutral Point

Clamped Active Front End Converter

Amit Ojha1, Pradyumn Chaturvedi2, Arvind Mittal3 and S. Jain4

1Department of Electrical Engineering, MANIT, Bhopal, India 2Department of Electrical

Engineering, NIT, Nagpur, India 3Department of Energy, MANIT, Bhopal, 4Department of

Electrical Engineering, MANIT, Bhopal, India

[email protected], [email protected] India, [email protected],

[email protected] e-mail

Abstract: The use of power electronic converters influences the generation of harmonics and

reactive power flow in power system. Therefore, three-phase multilevel improved power quality

AC-DC converters are gaining lot of popularity in power conversion applications. This work

deals with critical problem of multilevel structure i.e neutral point potential (NPP) variation. In

this paper, a simplified current controlled scheme is presented to ensure unity power factor

operation. Neutral point potential (NPP) of three-phase, 3-level NPC AC-DC converter is

controlled by modifying control signal in the controller using NPP regulator. An auxiliary circuit

is being presented in this paper as an alternative option for controlling the neutral point potential

of the converter. Comparison has been carried out between these control techniques in terms of

power quality. A complete mathematical model is presented for better understanding of both

techniques used for NPP control. The presented control techniques has been verified through

simulation investigations and validated experimentally on the developed laboratory prototype.

Keywords:AC-DC converters, Active Front End Converter, Multilevel Converter, Neutral Point

Clamped Converter, Unity Power Factor Controller (UPC).

1. Introduction

AC-DC power converters have been widely used in various applications like front end

converters in adjustable speed AC drives, High Voltage DC Transmission, Switch Mode Power

Supply, utility interface with non-conventional energy source etc. [1]. Traditionally

uncontrolled rectifier or SCRs used for AC-DC conversion suffer from some inherent problems

like drawing harmonic currents and reactive component of the current from the source

and offering highly nonlinear characteristic. Current harmonics generated by these

nonlinear loads further result in voltage distortion which is becoming troublesome for the

operation of many sensitive equipment and other consumer loads [2-3].

Therefore, high power factor converters (HPFC) has became the inherent part of AC-DC

conversion because of its important features like conversion at unity power factor with higher

efficiency, reduced size and well regulated dc output [4-8]. But these high power factor

converters using high voltage rating devices are having limitations such as large dv/dt, large

voltage stress across switching device, large common mode voltage generation, high switching

frequency etc. [9-12]. A new age of converters i.e. multilevel structure is gaining lot of popularity

because of its excellent performance in terms of improved power quality, less ripple in regulated

dc output voltage, reduced voltage stress across switch, reduced dv/dt and low electromagnetic

interference with neighbouring communication lines as compared to its counterpart 2-level

HPFCs [13-18].

Diode Clamped Multilevel Converter topology which is most widely used topology in

multilevel power conversion [9-11], suffers from the problem of unbalanced voltages across dc

link capacitors [19]. The voltage equalization of dc link capacitors is the necessary precondition

for stable operation of a diode clamped multilevel converters [20].

Several control techniques based on sinusoidal pulse width modulation (SPWM) and space

vector pulse width modulation (SVPWM) [21-25] have already been proposed to mitigate this

Received: November 15th, 2016. Accepted: June 13rd, 2017

DOI: 10.15676/ijeei.2017.9.2.10

342

mailto:[email protected]



problem. Another way to control neutral point potential in multilevel converters is the use of

additional voltage regulators, separate dc sources or additional circuit to balance the voltage

across the capacitors [19, 26]. The problem with the auxiliary circuits used for balancing purpose

is the extra cost of the switching devices, inductors, capacitors as well as higher switching losses.

Literatures are now available for reducing switching losses in multilevel structures [28, 29].

In this paper, unity power factor controller (UPC) is presented to ensure unity power factor

operation of three-phase, 3-level NPC AC-DC converter. A comparative study has been carried

out between neutral point potential (NPP) regulator in UPC and an auxiliary circuit for

controlling the NPP. The aim of this study is to address adverse effects of NPP regulator in UPC

to control NPP in terms of power quality. A simple concept based on ping-pong theory to control

NPP, is discussed in this paper as an alternative option for balancing of dc link capacitor voltages

on the cost of extra hardware and higher losses. The complete working with mathematical

modelling of auxiliary circuit based on ping-pong theory is presented. Experimentation is

performed on the prototype developed in the laboratory to validate the effective working of

controllers.

2. Neutral Point Clamped Active Front end 3-Level Converter

A three phase neutral-point clamped active front end 3-level converter is shown in Figure.1.

There are four power switches (Sa1, Sa2, S’a1 and S’

a2 for phase ‘a’) in one leg for each phase and

each leg is having two clamping diodes (Ds1 & D’s1 for phase ‘a’). Active front end rectifier is

fed by 3-phase AC source connected through boost inductor (Ls). C1 and C2 are the dc link

capacitors, midpoint of dc link capacitors and clamping diodes of each leg is connected to the

neutral of three phase AC source. Resistance R1 and R2 are connected across the dc link

capacitors to include loading effect of active front end converter [30].

Vsa

Vsb

Vsc

isa

isb

isc

C1

C2

V0

i01

Ls

i1

i0

Rs

LsRs

LsRs

Na

bc n

Vc1

Vc2

Sa1

Sa2

S’'a1

S’'a2

Sb1

Sb2

S’'b1

S’'b2

Sc1

Sc2

S’'c1

S’'c2

R1

R2

V01

i02

V02

DS1

D'S1

DS2

D'S2

DS3

D'S3

iP

2 ini

Figure 1. Neutral point clamped active front end 3-level converter

The independent power switches (Sx1, Sx2, S’x1 and S’

x2, x = a, b, c) are controlled in each leg

of the converter. The constraints for four power switches in each leg of the converter are defined

so as to avoid the conduction of a power switches of the same leg conducting simultaneously.

1SS 'xixi

(1)

where x = a, b, c and i = 1, 2.

xiS = 1, if the switch xiS is turned on or xiS = 0, if the switch xiS is turned off. The

equivalent switching function of the rectifier is given below-

Amit Ojha, et al.

343

1SSif1

1SSif0

1SSif1

T

'2x

'1x

2x'1x

2x1x

Sx

(2)

Therefore, three valid operating modes in leg ‘a’ of the converter are possible and Table 1

shows the valid switching states of the power switches of three legs and the corresponding

voltages on the ac side of the rectifier. Though, it has so many advantages over its counterpart

conventional 2-level converters, it suffers from serious problem of unbalance voltage of dc link

capacitors under unbalanced loading conditions.

Table 1. Switching States and Corresponding Voltages

T Sx1 Sx2 Sx1’ Sx2

’ Vxn

1 1 1 0 0 V c1 = V0/2

0 0 1 1 0 0

-1 0 0 1 1 - V c2 = V0/2

x = a, b, c.

In the following sections the working of UPC has been explained which includes the

explanation regarding the functioning of neutral point potential (NPP) regulator as well as the

concept to balance dc link voltage based on ping pong theory using auxiliary circuit.

The voltage equalization of dc link capacitors is the necessary precondition for stable

operation of a diode clamped multilevel converters. Therefore, an appropriate control is required

to balance the dc link voltage along with power factor control.

3. Unity Power Factor Controller

A simplified current control scheme as shown in Figure. 2 is implemented to ensure unity

power factor operation as well as improved power quality operation of the converter and termed

as unity power factor controller (UPC). The UPC comprises of a voltage controller, neutral point

potential regulator (NPP) and current controller [30].

PIV

*0

V0

Im Isa**

Isb**

Isc**

Isa*

Isb*

Isc*

PLL

Vsx

(x = a,b,c)

Vsa

u(t

)

Vsb

u(t

)

Vscu(t

)

PVc1

Vc2

Icomp(t)

Current controller

Voltage controller

Neutral Point Potential

Regulator

ΔV0

PI

Vcona

Vconb

Vconc

Sa1 S′a2 Sb1 S′b2Sc1 S′c2

PWM Modulator

PI

Isd Isq

Isa Isb Isc

abcdq0

ab

cd

q0

ab

cd

q0

Isd*

Isq*

Figure 2. Schematic diagram of neutral point clamped active front end 3-level converter

control scheme (UPC)

As shown in Figure. 2, a proportional integral voltage controller is used to balance AC side

power and DC side power of the rectifier, to obtain the amplitude of the line current command

i.e. Im. The current command can be written as,


344

0i0pm VkVkI (3)

where V = 0*V - 0V is the DC bus voltage error, 0

*V is the reference DC link voltage

command and 0V is the measured DC link voltage. The unit sinusoidal voltages generated

through PLL can be written as-

)3

2sin(

)3

2sin(

sin)(

)(

)(

tV

tV

ttV

tscu

tsbu

sau

(4)

The line current commands are derived from the multiplication of the output of the voltage

controller with the unit sinusoidal voltages and the resultant is then added to the output of the

NPP regulator as shown in Figure 2.

32sin)(

32sin)(

)sin()(

**

**

**

tIti

tIti

tIti

mc

mb

ma

(5)

(a)

The measured line current and respective reference line currents are transformed to dq

reference frame before feeding to current controller to track the source current commands.

Neglecting the high-frequency switching terms, we can write source voltage of phase ‘a’.

conasa

sasa Vdt

diLV

(6)

where Vcona is the modulated control signal of PWM converter derived from the proposed closed

loop control of the system. The carrier-based sinusoidal PWM scheme is employed for generating

proper switching signals as shown in Figure 3.

0 0.005 0.01 0.015 0.02-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

Time (secs)

Am

plitu

de

Amit Ojha, et al.

345

(b)

Figure 3. (a) Carrier-based PWM scheme for the generation of gating pulses (b) Obtained

gating pattern

Based on above control scheme and gating signals, the switching signals of the power

switches can be defined as-

conat

tconat

tcona

c

vvif

vvvif

vvif

T

2

21

1

1

0

1

(7)

Hence switching function can be written as-

'22

'2

1'1

1

1

2

)1(

1

2

)1(

aa

cca

aa

cca

SS

TTS

SS

TTS

(8)

Therefore for phase ‘a’, in the positive half of the control signals Vcona, the power switch Sa2

is turned on and the line current is controlled by turning on or off the power switch Sa1. In the

negative half of Vcona , Sa1 is turned off and turning on or off Sa2 can control the line current to

follow the current command. For equal capacitor voltages (Vc1 = Vc2 = V0/2), three voltage

levels (V0/2, 0, and - V0/2) are generated on the AC side of the rectifier phase voltage Van.

A. NPP Regulator in UPC

Neutral point potential (NPP) can be controlled using general law for the neutral point

current, the dc side quantities are given as under,

(assuming 1C = 2C )

dt

dVCi c1

1 (9)

dt

dVCi c2

2 (10)

0 0.005 0.01 0.015 0.020

0.5

1

S a1

0 0.005 0.01 0.015 0.020

0.5

1

S a2

0 0.005 0.01 0.015 0.020

0.5

1

S'a1

0 0.005 0.01 0.015 0.020

0.5

1

Time (secs)

S'a2


346

Neutral point current is given by

210 iii (11)

dt

)VV(dCi 2c1c

0

(12)

The equation yields

tconsdtiC

VV cc tan1

021 (13)

This signifies that a DC component in the neutral current i0, can be utilised to compensate

the voltage dc link capacitor voltages of the converter.

B. Auxiliary Circuit

As shown in the Figure.4 dc link capacitors C1 and C2 are connected to an auxiliary capacitor

Ca through four switches. A series resistance r is connected with auxiliary capacitor Ca to limit

the amplitude of the charging current for practical consideration. Whenever there is voltage

difference between C1 and C2 there will be always charging and discharging current between one

of the dc link capacitors (C1 or C2) and auxiliary capacitor Ca. To explain the balancing

phenomena the whole operation is divided in to four cases.

D2C1

Ca

ri1

i2C2

VC1

VC2

VCa

S2

S1D1

S4D4

S3D3

Auxiliary Circuit

Figure.4 Auxiliary circuit for dc link capacitor voltage balancing

Case 1: When Vc1 > Vca

In this condition, switch S1, S3 are turned on and switch S2, S4 are turned off. The charging

current ica pumps from C1 to Ca through S1, r and D3 as highlighted in Figure. 5a.

S2D2

S1D1

S3D3

S4D4

C1

Ca

ri1

i2C2

iCa

VC1

VC2

VCa

Figure 5a. Current flows from C1 to Ca

Amit Ojha, et al.

347

Case 2: When Vc1 < Vca

When voltage across auxiliary capacitor (Vca) is more than dc link capacitor Vc1, the switching

action will remain the same i.e. S1, S3 are on and charging current ica comes from Ca through r,

D1, C1 and S3 as highlighted in Figure 5b.

S2D2

S1D1

S3D3

S4D4

C1

Ca

ri1

i2C2

iCa

VC1

VC2

VCa

Figure 5b. Current flows from Ca to C1

Case 3: When Vc2 < Vca

Under this condition, the switch S1, S3 are turned off and S2, S4 are now turned on. The charging

current ica comes from Ca to C2 through r, S2, D4 as highlighted in Figure 5c.

D2C1

Ca

ri1

i2C2

iCa

VC1

VC2

VCa

S2

S1D1

S4D4

S3D3

Figure. 5c Current flows from Ca to C2

Case 4: When Vc2 > Vca

In this condition, switching action will again remain the same and the charging current ica pumps

from C2 to Ca through D2, r and S4 as highlighted in Figure. 5d.

D2C1

Ca

ri1

i2C2

iCa

VC1

VC2

VCa

S2

S1D1

S4D4

S3D3

Figure 5d. Current flows from C2 to Ca

The equivalent circuit for the Figure.4 is drawn and shown in the Figure.6. For the analysis

purpose the equivalent circuit is drawn for Case 1 and Case 2 and same analysis is applicable

for Case 3 and Case 4.


348

CaVCaC1 VC1

iCa

r

Figure 6. Equivalent circuit

If C1 and Ca are equal then the total capacitance of capacitors in series is equal to C/2. The

voltage and the charging current in the simple RC circuit will be given below for the time period

of t0 to t1.

𝑉(𝑡) = 𝑉(𝑡0) −2

𝐶∫ 𝑖𝑐1(𝑡)𝑑𝑡

𝑡1

𝑡0 (14)

𝑖𝑐1(𝑡) = 𝑉(𝑡𝑎)

𝑟𝑒−

2𝑡

𝑟𝑐 (15)

As explained earlier the balancing concept is based on ping pong operation and one ping

pong operation is divided in to two time steps. Step 1 starts from time t0 and finish at t1

corresponding to Case 1 & 2 of earlier section whereas time period for step 2 is t1-t2

corresponding to Case 3 & 4 of earlier section. Then, the voltages across the C1, C2 and Ca can

be expressed as,

𝑣𝑐1(𝑡) = 𝑣𝑐1(𝑡0) −

1

𝑐∫ 𝑖𝑐𝑎1(𝑡)𝑑𝑡, 𝑡0 ≤ 𝑡 ≤ 𝑡1

𝑡1

𝑡0

𝑣𝑐1(𝑡0), 𝑡1 ≤ 𝑡 ≤ 𝑡2

(16)

𝑣𝑐2(𝑡) = 𝑣𝑐2(𝑡0), 𝑡0 ≤ 𝑡 ≤ 𝑡1

𝑣𝑐2(𝑡1) −1

𝑐∫ 𝑖𝑐𝑎1(𝑡)𝑑𝑡,

𝑡2

𝑡1 𝑡1 ≤ 𝑡 ≤ 𝑡2

(17)

𝑣𝑐𝑎1(𝑡) = 𝑣𝑐1(𝑡0) +

1

𝑐∫ 𝑖𝑐𝑎1(𝑡)𝑑𝑡, 𝑡0 ≤ 𝑡 ≤ 𝑡1

𝑡1

𝑡0

𝑣𝑐1(𝑡1) −1

𝑐∫ 𝑖𝑐𝑎1(𝑡)𝑑𝑡,

𝑡2

𝑡1 𝑡1 ≤ 𝑡 ≤ 𝑡2

(18)

Where the balancing current ica is

𝑖𝑐1(𝑡) =

𝑣𝑐1(𝑡0)− 𝑣𝑐𝑎1(𝑡0)

𝑟𝑒−

2𝑡

𝑟𝑐 𝑡0 ≤ 𝑡 ≤ 𝑡1

𝑣𝑐2(𝑡1)− 𝑣𝑐𝑎1(𝑡1)

𝑟𝑒−

2(𝑡−𝑡1)

𝑟𝑐 𝑡1 ≤ 𝑡 ≤ 𝑡2

(19)

According to (16-19), the voltage difference between C1 & C2 will decrease after a number

of ping-pong operations.

Figure 7 shows the control scheme for the auxiliary circuit. This control scheme is generating

PWM pulses for auxiliary circuit switches by comparing a signal of constant magnitude with

triangular carrier wave such that S2 & S4 are the complimentary of S1& S3 respectively for

carrying out ping-pong operation.

Amit Ojha, et al.

349

Comparator

S1

S2

S3

S4

Figure 7. Control Scheme for auxiliary circuit.

4. Result and Discussion

In this section, simulation results are presented and verified experimentally by developing

laboratory prototype of neutral point clamped (NPC) active front end (AFE) 3-level converter.

A. Simulation Results

Simulation results are given for evaluating the performance of the neutral point clamped

(NPC) active front end (AFE) 3-level converter using UPC. The simulation is carried out with

and without NPP regulator in the UPC under balanced and unbalanced load conditions. The block

diagram of simulation model is shown in Figure. 8 and simulation parameters are given in Table

2. The optimized controller parameters are given in Table 3.

3- Level

NPC

AFF

P

PI PI

PLL

3- Phase

AC

Source

Line

Parameters

Rs & Ls

3- Level

PWM

Generator

Vc1

Vc2

Vc1

Vc2

iabc** iabc*

iabc

NPP

Regulator

Voltage

ControllerCurrent

Controller

Vsabcu

Vsabcu

Carrier

Signal

Vc1

Vc2

io1

io2

R1

R2

C1

Figure. 8 Block diagram of neutral point clamped active front end 3-level converter with UPC

Table 2. Simulation Parameters for NPC AFE 3-Level Converter with UPC

Line Voltage (RMS) VLL 50 V

Boost Inductor Ls 7.73mH

AC Link Resistance R 0.1 Ω

DC Link Voltage Vdc 80 V

DC Link Capacitance C1/ C2 2200 µF

Load Resistance

R1 || R1’ 15 Ω || 15 Ω

R2 || R2’ 15 Ω || 15 Ω

Carrier Frequency fc 2050 Hz


350

Table 3. Selected UPC Parameters for NPC AFE 3-Level Converter

Current Controller Parameters

Proportional Gain (Kcp) 0.5

Integral Gain (Kci) 10

Voltage Controller Parameters

Proportional Gain (Kvp) 2

Integral Gain (Kvi) 25

NPP Regulator Parameters

Proportional Gain (Knp) 2

A.1 Performance of NPC AFE with UPC

Phase voltage of phase ‘a’, line current of phase ‘a’, dc link capacitor voltages (Vc1 and Vc2)

and load current (i0) under steady state condition is shown in Figure. 9. This shows the stable

operation of neutral point clamped active front end 3-level converter with unity power factor

controller under steady state condition, which is essentially required for medium voltage, high

power applications.

Figure 9. Phase voltage (Vsa), Line current (isa), dc link capacitor voltages (Vc1 and Vc2) and

load current (i0) of NPC AFE 3-level converter under steady state condition

The dynamic performance of NPC AFE AC-DC converter is also evaluated with sudden load

change as shown in Figure. 10 & Figure. 11. It is observed that the dc link capacitor voltages

(Vc1 and Vc2) settled down to its desired value within 10 cycles, the supply

8 8.01 8.02 8.03 8.04 8.05 8.06 8.07 8.08-50

0

50

(a)

Vsa

(vo

lts)

8 8.01 8.02 8.03 8.04 8.05 8.06 8.07 8.08-10

0

10

(b)

i sa (

amps

)

6 6.5 7 7.5 8 8.5 9 9.5 1020

30

40

50

(c)

Vc1

(vo

lts)

6 6.5 7 7.5 8 8.5 9 9.5 1020

30

40

50

(d)

Vc2

(vo

lts)

6 6.5 7 7.5 8 8.5 9 9.5 100

5

(e)

Time (sec)

i o (

amps

)

Amit Ojha, et al.

351

Figure 10. DC link Capacitor Voltages (Vc1 and Vc2) , DC link Capacitor Voltage (Vc1) and

Source current (isa) for increase in load at t = 5 sec

Figure 11. DC link Capacitor Voltages (Vc1 and Vc2) , DC link Capacitor Voltage (Vc1) and

Source current (isa) for decrease in load at t = 10 sec

A.2. Neutral Point Potential (NPP) Control Using NPP Regulator

The neutral point potential is basically difference between two dc link capacitor voltages.

Ideally NPP should be zero i.e. balanced dc link capacitor voltages under transient and steady

state conditions. In this study, simulation is carried out with and without NPP regulator in UPC

under balanced and unbalanced load condition. The level of unbalance is measured by a factor

defined as depth of unbalance σ as [27]

5.9 5.95 6 6.05 6.1 6.15 6.2 6.25 6.339

39.5

40

40.5

(a)

Vc1 (

vo

lts)

5.9 5.95 6 6.05 6.1 6.15 6.2 6.25 6.339

39.5

40

40.5

(b)

Vc2 (

vo

lts)

5.9 5.95 6 6.05 6.1 6.15 6.2 6.25 6.3-10

0

10

(c)

Time (sec)

i sa (

amp

s)

5.9 6 6.1 6.2 6.3 6.4 6.539.5

40

40.5

41

(a)

Vc1 (

vo

lts)

5.9 6 6.1 6.2 6.3 6.4 6.539.5

40

40.5

41

(b)

Vc2 (

vo

lts)

5.9 6 6.1 6.2 6.3 6.4 6.5-10

0

10

(c)

Time (sec)

i sa (

amp

s)


352

𝜎 = 𝑅1− 𝑅2

𝑅1+ 𝑅2 × 100 (20)

Where 𝑅1 load resistance is across dc link capacitor C1 and 𝑅2 is load resistance across dc link

capacitor C2.

The study is carried out for different depth of unbalance (σ) to observe its effect on the

performance of NPP regulator in UPC. The system parameters for the simulation are same given

in Table 2. The details of loading parameters are given in Table 4

Table 4. Load Parameters

Resistance (R1)

(Ω)

Resistance (R2)

(Ω)

% Depth of unbalanced

load (σ)

15 15 0

15 10 20

15 7.5 33.33

Figure 12 shows the NPP variation with and without NPP regulator. It clearly shows that

there are variations in average of NPP under balanced load (σ = 0%). Even though the variation

is not large, but it is significant for high voltage and high power applications. When NPP

regulator is included in the UPC, the NPP variations got suppressed and NPP become almost

zero as shown in the Figure. 12. Figure. 13 and Figure. 14 shows the variations of NPP with and

without NPP regulator in UPC for σ = 20% and σ = 33.33% respectively. These Figure shows

that the variations of NPP increases with depth of unbalance. The NPP regulator in UPC is

capable to control the NPP variations as shown in Figure. 13 and Figure. 14.

Figure. 15 shows the dc link capacitor voltages (Vc1 & Vc2) before and after the NPP regulator

included in the UPC. It also confirms the balancing of dc link capacitor voltages using NPP

regulator in UPC.

Table 5 shows that, the NPP regulator in UPC removes the 2nd harmonic from supply line

current whereas the dc off-set appears in the supply line current as depth of unbalance increase.

The undesirable dc off-set in supply current will saturate the transformer on the utility side and

must be removed from the supply current. Therefore, the NPP regulator in the UPC controls the

variations in NPP under balanced load whereas for different depth of unbalance the NPP

regulator able to control NPP variations at the cost of dc off-set in supply line current.

Figure 12. NPP before and after NPP regulator is included in UPC at t = 6 sec for σ = 0%

5 5.5 6 6.5 7 7.5 8-0.2

-0.1

0

0.1

0.2

Time (sec)

NP

P (

vo

lt)

Amit Ojha, et al.

353

Figure 13. NPP before and after NPP regulator is included in UPC at t = 6 sec for σ = 20%

Figure 14. NPP before and after NPP regulator is included in UPC at t = 6 sec for σ = 33.33%

Figure 15. DC link capacitor voltages (Vc1 & Vc2) before and after NPP regulator is included in

UPC at t = 6 sec for σ = 33.33%

5 5.5 6 6.5 7 7.5 80

2

4

6

8

Time (sec)

NP

P (

vo

lts)

5 5.5 6 6.5 7 7.5 80

5

10

15

Time (sec)

NP

P (

vo

lts)

5 5.5 6 6.5 7 7.5 820

30

40

50

60

Time (sec)

Vc1

& V

c2 (

vo

lts)


354

Table 5. Variation of DC offset & 2nd Harmonic with depth of unbalance (σ) in Supply Line

Current of Phase a (isa) with and without NPP Regulator in UPC

Depth of

Unbalance (σ)

DC Off-set and 2nd Harmonic in Supply Line Current of Phase a (isa)

Without NPP Regulator With NPP Regulator (%)

DC Off-set (%) 2nd Harmonic (%) DC Off-set (%) 2nd Harmonic (%)

0% 0 0 0 0

20% 0 10 15% 0

33.33% 0 17 25% 0

A.3. Neutral Point Potential (NPP) Control Using Auxiliary Circuit

A simulation has been carried out for AC-DC multilevel converter with an auxiliary circuit for

σ = 33.33%. As shown in Figure.16 the average NPP is become almost zero when auxiliary

circuit is included at t = 6 sec. Figure.17 shows the voltage across the dc link capacitors (Vc1 &

Vc2) before and after the auxiliary circuit is included in system. The simulation confirms that the

adopted voltage balancing scheme using auxiliary circuit is maintaining almost equal voltage

across the dc link capacitors. Table 6 also shows that the auxiliary circuit balances dc link voltage

without dc offset in the input line current for different depth of unbalance load.

Figure 16. Average NPP when auxiliary circuit is included at t = 6 sec for σ = 33.33%

Figure.17 DC link voltages (Vc1 & Vc2) when auxiliary circuit is included at t = 6 sec for σ =

33.33%

5 5.5 6 6.5 7-20

-10

0

10

20

Time (sec)

AV

G.

NP

P (

Volt

s)

5 5.5 6 6.5 720

25

30

35

40

45

50

Time (sec)

Vc1

& V

c2 (

volt

s)

Amit Ojha, et al.

355

Table 6. Variation of DC offset & 2nd Harmonic with depth of unbalance (σ) in Supply Line

Current of Phase a (isa) with Auxiliary Circuit

Depth of Unbalance

(σ)

DC Off-set and 2nd Harmonic in Supply Line Current of Phase a (isa) with

Auxiliary Circuit

DC Off-set (%) 2nd Harmonic (%)

0% 0 0

20% 0 0

33.33% 0 0

B. Experimental Results

The performance of NPC AFE 3-level converter is verified experimentally on developed low

power prototype in laboratory. The experimental parameters for NPC AFE 3-level converter are

given in Table 7. The prototype of AC-DC converter includes twelve STGW30N120KD, 1200

volts, 30 amps IGBTs and six fast recovery diodes (16FM120) with two dc link capacitors of

2200mF, 600 V each at input side. The control algorithm is implemented through dSPACE real

time interface DS1103. The DS1103 real time hardware implementation board is based upon

Texas Instruments TMS320F240, 16 bit fixed point digital signal processor, 250 MHz CPU, 20

MHz clock frequency.

Table 7. Experimental Parameters

Line Voltage (RMS) VLL 50 V

Source Inductor Ls 7.73mH

AC Link Resistance R 0.4 Ω

DC Link Parameters

DC Link Voltage Vdc 80 V

DC Link Capacitors C1 and C2 2200 µF

Load Parameters

Load Resistance (R1 and R2) 15 Ω

Carrier Frequency fc 2050 Hz

B.1. Performance of NPC AFE with UPC

The line voltage (Vab) at supply end, supply phase voltage (Vsa) and line current (isa) are

shown in Figure. 18, which clearly shows unity power factor operation of the converter. The

harmonic profile of the line voltage (Vab) at supply end and line current (isa) are shown in Figure.

19 (a) and Figure. 19 (b) respectively. The line current (isa) drawn by NPC AFE 3-level converter

is having only 2.4% of THD, which is well below the limit imposed by standard IEEE 519.


356

Vab

Vsa

isa

Figure 18. Converter line voltage (Vab), phase voltage (Vsa) and line current (isa) of NPC AFE

3-level converter

X - axis: Time – 10ms/div, Y axis: Vab - 50 V/div, Vsa – 20V/div and isa – 4A/div

(a) (b)

Figure.19 Harmonic spectrum of (a) Line current (isa) and (b) converter line voltage.

The performance of NPC AFE 3-level converter under steady state condition has been

verified experimentally. The phase voltage (Van) at supply end is shown in Figure. 20 under

steady state condition which confirms one of the important features of multilevel converter

having half of the dc link voltage subjected across the devices. The voltage across the dc link

capacitors (Vc1 and Vc2) are shown in Figure. 21 under steady state condition. This shows stable

operation of converter under steady state condition.

Amit Ojha, et al.

357

Van

Figure 20. Phase voltage (Van) at supply end of NPC AFE 3-level converter under steady state

condition

X - axis: Time –10ms/div, Y - axis: Van - 20 V/div

Vc1

Vc2

Figure 21. DC link capacitor voltages (Vc1 and Vc2) of NPC AFE 3-level converter under

steady state condition

X axis: Time- 10ms/div, Y axis: Vc1 and Vc2 - 20 V/div

The transient response of the converter is evaluated with sudden change in load. The dc link

voltages (Vc1 and Vc2) and line current of phase ‘a’ (isa) has been observed when load is suddenly

increased as shown in Figure.22. It can be clearly observed that the dc link voltages (Vc1 and

Vc2) decreased when load is suddenly increased thereafter few cycles the dc link voltages recover

to its desired voltage. The behaviour of the converter is also observed when load is reduced. The


358

dc link voltages suddenly increased and after few cycles it gets back to its desired value, shown

in Figure.23. The response of the NPC AFE 3-level converter during transient found satisfactory

with UPC, and confirmed that UPC is effectively able to regulate dc link voltage quickly at

desired value during transient condition

Vc1

Vc2

isa

Figure 22. DC link capacitor voltages (Vc1 and Vc2) and line current (isa) of NPC AFE 3-level

converter when load is increased

X - axis: Time – 1s/div, Y - axis: Vc1 and Vc2 - 20 V/div, isa – 4 A/div

Vc1

Vc2

isa

Figure.23 DC link capacitor voltages (Vc1 and Vc2) and line current (isa) of NPC AFE 3-level

converter when load is decreased

X - axis: Time – 1s/div, Y- axis: Vc1 and Vc2 - 20 V/div, isa – 4 A/div

Amit Ojha, et al.

359

B.2 Neutral Point Potential (NPP) Control with NPP Regulator in UPC

It is experimentally verified that multilevel structures have inherent problem of NPP

variation. Figure. 24 shows variation of NPP before and after the NPP regulator included in t =

3 sec for σ = 33.33%, which verifies the effective working of NPP regulator in UPC.

Figure 24. NPP variation before and after NPP regulator included in UPC at t = 3 sec for σ =

33.33% (Control Desk Layout)

B.3 Neutral Point Potential (NPP) Control with Auxiliary Circuit

The function of auxiliary circuit has also been verified experimentally. Figure. 25 shows the

dc link capacitor voltages (Vc1 & Vc2) before and after auxiliary circuit included in the system

for σ = 33.33%. As shown in the Figure. 25 the dc link capacitors voltages are not completely

balanced because of series resistance r is connected with auxiliary capacitor Ca to limit the

amplitude of the charging current for practical consideration. The presented result confirms the

working of auxiliary circuit adopted to balance the dc link capacitors voltage.

Vc1

Vc2

Without Auxiliary

Circuit With Auxiliary

Circuit

Figure 25. DC link capacitor voltages (Vc1 and Vc2) before and after auxiliary circuit included

in the system for σ = 33.33%

0 2 4 6 8 10 126.4

7.4

8.4

9.4

10.4

Time (sec)

NP

P (

volt)


360

X - axis: Time – 1s/div, Y- axis: Vc1 and Vc2 - 20 V/div

4. Conclusion

The unity power factor controller (UPC) is presented to control NPC AFE 3-level converter

for improved power quality at input and load side. The performance of three-phase NPC AFE 3-

level converter has been evaluated with unity power factor controller. Simulation results are

presented to study the performance of the system during transients as well as in steady state. It

is observed that 3-level converter is operating at almost unity power factor with supply current

THD within the limits imposed by IEEE519 standard. Simulated results also show that NPP

regulator in conjunction with UPC is able to balance the capacitor voltages under balanced and

unbalanced load with the addition of dc off-set in supply line current. The simulation results

with an auxiliary circuit to balance the dc link capacitor voltages show effective balancing of dc

link capacitor voltages without any adverse effects in terms of power quality. The features of

UPC with NPP regulator and auxiliary circuit, observed in simulation study are also validated

through experimentation performed on the low power prototype developed in laboratory using

dSPACE DS 1103. Further, it can be concluded that the UPC with NPP regulator is suitable for

drives application where depth of unbalance is not much whereas an auxiliary circuit is effective

for active power filter where depth of unbalance is high.

5. References

[1]. Abdul Hamid Bhat, Pramod Agarwal, Three-phase, power quality improvement ac/dc

converters, Electric Power Systems Research, Volume 78, Issue 2, pp 276-289, Feb 2008

[2]. Rashid M. H., Power Electronics Handbook, Academic Press, New York, 2001.

[3]. Sen P. C., Power Electronics, Tata McGraw Hill Pub., 1998.

[4]. Akagi, H. , New Trends in Active Filters for Power Conditioning, Industry Applications,

IEEE Transactions on , vol.32, no.6, pp.1312-1322, Nov/Dec 1996.

[5]. El-Habrouk, M.; Darwish, M.K.; Mehta, P., Active power filters: A Review,"Electric

Power Applications, IEE Proceedings, vol.147, no.5, pp.403-413, Sep 2000.

[6]. Jain, S.K.; Agrawal, P.; Gupta, H.O.;, Fuzzy logic controlled shunt active power filter for

power quality improvement, Electric Power Applications, IEE Proceedings, vol.149, no.5,

pp. 317- 328, Sep 2002.

[7]. Yang, S.P.; Chen, S.J.; Lin, J.L., Dynamics analysis of a low-voltage stress single-stage

high-power factor correction ac/dc flyback converter, Power Electronics, IET, vol.5, no.9,

pp.1624,1633, November 2012

[8]. Lin Chengwu; Ba Dong, Research on AFE Technology in Multi-inverter System,

Measuring Technology and Mechatronics Automation (ICMTMA), 2013 Fifth

International Conference on, vol., no., pp.875,878, 16-17 Jan. 2013

[9]. Xiaofeng Yang; Zheng, T.Q.; Zhiqin Lin; Tao Xiong; Xiaojie You, Power quality controller

based on hybrid modular multilevel converter, Industrial Electronics (ISIE), 2012 IEEE

International Symposium on , vol., no., pp.1997,2002, 28-31 May 2012

[10]. Marchesoni M. and Tenca P., Diode-clamped multilevel converters: A practicable way to

balance dc-link voltages,” IEEE Trans. on Industrial Electronics, vol. 49, no. 4,August

2002.

[11]. Midavaine H., Moigne P. L., and Bartholomeus P., “Multilevel three-phase rectifier with

sinusoidal input currents, in Proc. IEEE PESC’96, 1996, pp. 1595-1599.

[12]. Ridriguez J. Rodriguez D., Silva C., and Wiechmann E., A simple Neutral Point Control

for Three-Level PWM Rectifiers, European Power Electronics Conference, EPE’99, 1999,

pp. 1-8.

[13]. J S Lai and F Z Peng. Multilevel Converters: A New Breed of Power Converters, IEEE

Transactions on Industry Applications, vol 32, no 3, May/June 1996, pp 509-517.

Amit Ojha, et al.

361

[14]. Fanquelo, L.G.; Rodriguez, J.; Leon, J.I.; Kouro, S.; Portillo, R.; Prats, M.A.M.; , The age

of multilevel converters arrives, Industrial Electronics Magazine, IEEE, vol.2, no.2, pp.28-

39, June 2008

[15]. Krishna Kumar Gupta, Shailendra Jain, A Multilevel Voltage Source Inverter (VSI) to

maximize the number of levels in output waveform, International Journal of Electrical

Power & Energy Systems, Volume 44, Issue 1, January 2013, Pages 25-36.

[16]. Ojha, Amit; Chaturvedi, P.K.; Mittal, Arvind; Jain, S., Carrier Based Common Mode

Voltage Reduction Techniques in Neutral Point Clamped Inverter Based AC-DC-AC Drive

System, Journal of Power Electronics, Vol. 16, Issue 1, pp 142-152, Jan. 2016

[17]. Karuppusamy, P.;Vijayakumar, G.; Sathishkumar, S., Certain Investigation on Multilevel

Inverters for Photovoltaic Grid Connected System, Journal of Circuits, Systems and

Computers, doi:10.1142/S0218126616501085

[18]. Bhat, A.H.; Agarwal, P., An Improved Performance Three-Phase Neutral-Point Clamped

Rectifier with Simplified Control Scheme, Industrial Electronics, 2006 IEEE International

Symposium on, vol.2, no., pp.1019-1024, 9-13 July 2006

[19]. Kanaan, H.Y.; Al-Haddad, K.; Fnaiech, F., DC load unbalance and mains disturbances

effects on a three-phase three-switch three-level boost rectifier, Industrial Electronics,

2003. ISIE '03. 2003 IEEE International Symposium on, vol.2, no., pp. 1043- 1048 vol. 2,

9-11 June 2003

[20]. Shu, Z.; He, X.; Wang, Z.; Qiu, D.; Jing, Y.; , Voltage Balancing Approaches for Diode-

Clamped Multilevel Converters Using Auxiliary Capacitor-Based Circuits, Power

Electronics, IEEE Transactions on , vol.28, no.5, pp.2111-2124, May 2013

[21]. Pou Josep, Boroyevich Dushan, and Pindado Rafael, New Feed forward Space-Vector

PWM Method to Obtain Balanced AC Output Voltage in a Three-Level Neutral-Point-

Clamped Converter, IEEE Trans. on Industrial Electronics, Vol. 49, No. 5, Oct. 2002,

pp.1026-1034.

[22]. Ojo Olorunfemi, and Konduru Srikanth, A Discontinuous Carrier Based PWM Modulation

Method for the Control of Neutral Point Voltage of Three-Phase Three-Level Diode

Clamped Converters, Proc. PESC 2005, Vol. 1, pp. 1652-1658.

[23]. Li Jun, Huang Alex Q. Qian Zhaoming, and Zhao Huijie, A Novel Carrier Based PWM

Method for 3-Level NPC Inverter Utilizing Control Freedom Degree, Proc. of NPSC 2007,

pp. 1899-1904.

[24]. Ishida, T.; Matsuse, K.; Sugita, K.; Lipei Huang; Sasagawa, K., DC voltage control strategy

for a five-level converter, Power Electronics, IEEE Transactions on, vol.15, no.3, pp.508-

515, May 2000

[25]. Kouro, S.; Malinowski, M.; Gopakumar, K.; Pou, J.; Franquelo, L.G.; Bin Wu; Rodriguez,

J.; Perez, M.A.; Leon, J.I.; , Recent Advances and Industrial Applications of Multilevel

Converters, Industrial Electronics, IEEE Transactions on, vol.57, no.8, pp.2553-2580, Aug.

2010

[26]. Sano Kenichiro, and Fujita Hideaki, Voltage Balancing Circuit Based on a Resonant

Switched Capacitor Converter for Multilevel Inverters, IEEE Trans. on Industrial

Electronics, Vol. 44, No. 6, Nov/Dec. 2008, pp. 1768-1776.

[27]. Chaturvedi, P.K.; Jain, S.; Agarwal, P.; Reduced switching loss pulse width modulation

technique for three-level diode clamped inverter, Power Electronics, IET, vol.4, no.4,

pp.393-399, April 2011

[28]. Chaturvedi PK, Jain S, Agrawal P, Nema RK, Sao KK., Switching losses and harmonic

investigations in multilevel inverters, IETE Journal of Research, Vol. 54, Issue 4, pp. 297-

307, Jul/Aug 2008,

[29]. Shu, Z.; He, X.; Wang, Z.; Qiu, D.; Jing, Y.;, Voltage Balancing Approaches for Diode-

Clamped Multilevel Converters Using Auxiliary Capacitor-Based Circuits, Power

Electronics, IEEE Transactions on , vol.28, no.5, pp.2111-2124, May 2013


362

http://www.dbpia.co.kr/Article/NODE06592589



[30]. P. Chaturvedi, A. Ojha, S. Jain and A. Mittal, Unity power factor controller for neutral point

clamped active front end converter with DC voltage balancing, 2016 IEEE International

Conference on Industrial Technology (ICIT), Taipei, Taiwan, 2016, pp. 384-389.

Amit Ojha was born in India, in 1974. He received B.E degree in Electrical

Engineering from MACT, Bhopal, India, in 1998. He received M. Tech. and

Ph. D. degrees from Maulana Azad National Institute of Technology (MANIT),

Bhopal, India, in 2002 and 2013, respectively. He studied multilevel converter

fed induction motor drives while working towards his Ph. D. He has had more

than 15 years of teaching experience and more than 5 years of research

experience. He is presently working as an Assistant Professor in Department of

Electrical Engineering, MANIT. His current research interests include

electrical machines, power electronics, electric drives, high-power-factor converters, and

multilevel converters.

Pradyumn Chaturvedi received B.E. degree in Electrical Engineering from

Barkatullah University, Bhopal, India, in 1996; M.E. degree in Power

Electronics from the Rajiv Gandhi Technical University, Bhopal, India, in

2001; and Ph.D. degree from the National Institute of Technology, Bhopal,

India, in 2010. He has had 14 years of teaching experience. He is presently

working as an Assistant Professor in the Department of Electrical Engineering,

NIT, Nagpur, India. He has published more than 45 research papers in

referenced national and international journals and conferences. His current

research interests include electrical drives, high-power-factor converters, photovoltaic power

conditioning systems, and multilevel inverters.

Arvind Mitralobtained B.E. degree in Electrical Engineering from Maulana

Azad National Institute of Technology(MANIT), Bhopal, India, in 1991,

securing first position in the university (Gold Medallist). He is a post graduated

in Power Apparatus and Electrical Drives (PAED) atthe Indian Institute of

Technology Roorkee, Roorkee, India, in1993, and obtained Ph.D. degreefrom

Barkatullah University, Bhopal India, in 2002. He is presently an Associate

Professor in the Energy Centre, MANIT, Bhopal, India. He has had more than

23 years of experience in teaching undergraduate and postgraduate students.

He is a life member of the ISTE and an Associate Member of the Institution of Engineers. He

has guided two Ph.D. candidates and published several papers in various national and

international conferences and journals. He has also authored seven engineering books.

Shailendra Jain received B.E. degree in Electrical Engineering from Samrat

Ashok Technological Institute (SATI), Vidisha, India, in 1990; M.E. degree in

Power Electronics from the Shri Govindram Seksaria Institute of Technology

and Science, Indore, India, in 1994; Ph.D. degree from the Indian Institute of

Technology, Roorkee, India, in 2003; and Post-Doctoral Fellowship from the

University of Western Ontario, London, ON, Canada, in 2007. He is presently

a Professor in the Department of Electrical Engineering, National Institute of

Technology, Bhopal, India. His current research interests include power

electronics and electric drives, power quality improvement, active power filters, high-power-

factor converters, and fuel-cell-based distributed generation. Dr. Jain was a recipient of the

“Career Award for Young Teachers” from the All India Council for Technical Education

(AICTE), New Delhi, India, for the year 2003–2004.

Amit Ojha, et al.

363

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