ndg-l39introduction to asic design1 design of a simple customizable microprocessor * chapter 7 and...
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NDG-L39 Introduction to ASIC Design 1
Design of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable Microprocessor
* C
hapt
er 7
and
15,
“D
igit
al S
yste
m D
esig
n an
d P
roto
typi
ng”
Pipelined SIMP Pipelining – An Architectural Solution to Achieve
Performance Instruction Parallelism Triples Performance (Almost) Introduces Latencies Additional Resources + Problems?
Fig-16 Instruction Parallelism with Three Stage Pipelining
NDG-L39 Introduction to ASIC Design 2
Design of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable Microprocessor
* C
hapt
er 7
and
15,
“D
igit
al S
yste
m D
esig
n an
d P
roto
typi
ng”
Pipelined SIMP – Cont’d Problems with Pipelined Architecture
Memory Conflicts – Von Neumann Architecture Fails
Fig-17 Original von Neumann Architecture and Pipelined Harvard Architecture
NDG-L39 Introduction to ASIC Design 3
Design of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable Microprocessor
* C
hapt
er 7
and
15,
“D
igit
al S
yste
m D
esig
n an
d P
roto
typi
ng”
Pipelined SIMP – Cont’d Problems with Pipelined Architecture – Cont’d
Stage Registers – additional resources + latency Branching Instructions – Flushing of Pipeline
Fig-18 Pipeline Stages and Stage Registers
NDG-L39 Introduction to ASIC Design 4
Design of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable Microprocessor
* C
hapt
er 7
and
15,
“D
igit
al S
yste
m D
esig
n an
d P
roto
typi
ng”
Pipelined SIMP – Cont’d Pipelined SIMP Design- Datapath
Fig-19 Pipelined SIMP Datapath
NDG-L39 Introduction to ASIC Design 5
Design of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable Microprocessor
* C
hapt
er 7
and
15,
“D
igit
al S
yste
m D
esig
n an
d P
roto
typi
ng”
Pipelined SIMP – Cont’d Pipelined SIMP Design- Control Flow
Fig-20 Pipelined SIMP Control Flow
NDG-L39 Introduction to ASIC Design 6
Design of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable Microprocessor
* C
hapt
er 7
and
15,
“D
igit
al S
yste
m D
esig
n an
d P
roto
typi
ng”
Pipelined SIMP – Cont’d Pipelined SIMP Design- Processor Initialization
Operations
Table-1 Processor Initialization Operations
NDG-L39 Introduction to ASIC Design 7
Design of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable Microprocessor
* C
hapt
er 7
and
15,
“D
igit
al S
yste
m D
esig
n an
d P
roto
typi
ng”
Pipelined SIMP – Cont’d Pipelined SIMP Design- Pipeline Initialization
Operations After Processor Initialization and Every Branch Instruction
+Interruption
Table-2 Pipeline Initialization Operations
NDG-L39 Introduction to ASIC Design 8
Design of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable Microprocessor
* C
hapt
er 7
and
15,
“D
igit
al S
yste
m D
esig
n an
d P
roto
typi
ng”
Pipelined SIMP – Cont’d Pipelined SIMP Design- Pipeline Instruction
Execution Operations
Table-3 Pipeline Update Operations
NDG-L40-41 Introduction to ASIC Design 9
Design of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable Microprocessor
* C
hapt
er 7
and
15,
“D
igit
al S
yste
m D
esig
n an
d P
roto
typi
ng”
Pipelined SIMP – Cont’d Pipelined SIMP Implementation
NDG-L39 Introduction to ASIC Design 10
I Wish You All Very Successful Carrier in ASIC Design Field!