national radio astronomy observatory green bank, … · 6. turn off power. 7. transfer rom to...
TRANSCRIPT
NATIONAL RADIO ASTRONOMY OBSERVATORYGreen Bank, West Virginia
Electronics Division Internal Report No. 132
A READ-ONLY MEMORY PROGRAMMER/VERIFIER
J. Ray Hallman
OCTOBER 1973
NUMBER OF COPIES: 150
READ-ONLY MEMORY PROGRAMMER/VERIFIER
J. Ray Hallman
Technological achievement has provided us with the programmable/erasable
read-only memory! A programmer for this type of memory has been built and is
shown in the picture.
The ROM (Read Only Memory) operates by means of the stored charge principle
and will retain data for up to ten years. Or, the ROM may be erased with intense
ultra-violet light which discharges the small gate capacitance of the memory cell
field effect transistors.
The ROM provides an easy and compact means for code conversion. Any com.-
bination and number (up to eight for a single ROM) of binary input lines may be
translated to any other combination and number (up to eight for a single ROM)
output binary lines:
AiA2 -ail
A3
A 4
A5 ----Jaw
A6 --311Ib
A7
A8 -----1110
INTELTYPE 1702
ROM
Thus, the Intel ROM Type 1702 is an 8 x 8 array of memory cells which is
2048 bits in size. It is anticipated that the ROM system will find many uses in
many areas of digital design where complex combinatorial logic comprising multi-
gate trees are employed. The advantages are a saving in electronic P.C. board
real estate, cost and offer the ability to reconfigure an electronic system by
simply unplugging a ROM and plugging in a new one. The 1702 ROM may then be
erased for reuse in about 5 minutes with the model UVS-11 ultra-violet light source
manufactured by Ultra Light Products, Inc.
Operation
1. Turn off power switch.
2. Plug in ROM in verify socket (pin - 1 key in upper left corner).
3. Turn on power.
4. Move mode selector toggle to "Verify".
5. Advance through all 256 addresses and verify clear memory (all
zeros) by using the thumbwheels and address entering push-button.
6. Turn off power.
7. Transfer ROM to program socket.
8. To copy a ROM go to step 18, otherwise go to next step.
9. Turn on power.
10. Move mode selector toggle to "manual program".
11. Set thumbwheels to desired starting address.
12. Push "enter address" and verify that correct address has been
entered into the display. (Thumbwheels are notorious mechanical
beasts and hence sometimes a little shaking is necessary to get
the correct address entered.)
13. Set up the data with the "data entry" switches according to your
truth table.
14. Push the "program sequence" push-button. (Verify that faint flicker-
ing of the selected address and data bits V , Prog, and V DD occurs.GG
VDD
is rather bright.)
15. After about 5 seconds the machine will stop with the next address
displayed.
16. When 256 is reached, turn off power and go to step 27.
17. Repeat back to step 13 if the next memory address is to be pro-
grammed. If not, repeat back to step 11.
18. Move mode selector toggle to "copy program".
19. Insert master ROM in verify socket.
20. Turn on power.
21. Set thumbwheels to 000.
22. Push "program sequence" push-button.
23. Do step 14 and then step 24.
24. In about 20 minutes the machine will stop with 256 displayed in the
address display.
25. Turn off power.
26. Remove master ROM from verify socket.
27. Transfer programmed ROM to verify socket.
28. Move mode switch to "verify".
29. Turn on power.
30. Advance through all 256 addresses and verify data according to your
truth table.
31. End.
Circuit Description
The ROM programmer comprises address sequence control, program data handling,
high voltage program power supply control, and various displays and switches to
interface with humans. Circuit card 1 contains a 3-decade address counter-latch
(chips K, L, and M) with inputs connected to the thumbwheels (see schematic).
P,1-1 90
21, IL/
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ALL IC
' s/i 4--->< -
- A, e, c, v, , j- A Ad /6 Fi/iy/ Pr /c • r-k. = / 4 /e p/// /c -
7 — GA/L.2 =
ROM PRo GRA/VIMER/ VERIFIER4- JD/RE:3S SEQUENCE CONTROL C 1
A8 :1_7
A 9
022REiCFRN
1_0 D vAHCE
A D.0 RESS
Aii IC!, A, 11- Pin &I" RUn /es s Noted
Vcc — / 4GNU- 7 1 U H P508 4770.a.,',
Wv3 I
, I N914-'s 4 7 KI
-1- 50vDc
RA-7
RAG
RA5
RA4
RA3
RA2
RAI
MI
TEDDELAYED
74,0
I ,Di5CRETE COMPONENTS LIN Sl_orS M e N Dire, 450.:0
TEDLED
ILI
131
SWITCHCoNrROL
PRoG.EN B
ILI ERR° R
1111 ENBe1CROR TasT
scSc as c
Si NGL
111
4-7K
/2
ca, Bc, 8280
p
4+550
052/I3 47OR
1 3C CR
96o/ ai
8
6 8
NC
so Ktcw NC
5 17-i- A 8C,
c
R ":°1/3 p
4-
CLOCK100 k
CI
CI
RAO
VGG
VDD
PROGRAM
ERRoR
5 7402
-7K
5 /0 I{ /213
1
5
The "enter address" push-button grounds pin F-9 when pushed which "latches in"
the thumbwheel preset address to the counters. The counter outputs drive the
displays (card output pins P-Z) and "BCD" to binary code converter chips A, B,
C, D, E, and J. The code converter provides binary sequence outputs to inverters
F and H and "verify" ROM address inputs. The inverters drive the address (verify)
LED's and are also connected to card C-2 high voltage driver inputs (chips H and
J). See schematic for card C-2. The driver outputs are connected to the
"programmed" ROM address inputs. This ROM "sits up" at +50 volts so that the
driver outputs provide negative pulses to the ROM. The 10 ms pulses occur in
+5 GND
Rom PROGRAMER/ VERIFIERCONTROL LOGIC
4 ADDRESS C-2
6
groups of ten with a 2% duty factor so that 5 seconds of time is required for
each address. This sequence is controlled by the rest of the logic on card C-2.
The oscillator (chip D) sets the speed. Decade dividers (chips C and B) provide
timing to gate K-12 which provides a 2% duty factor waveform (time) which enables
ultimately the address and data high voltage drivers. Gate K-8 delays the trail-
ing edge of time whereas gate E-10 delays the leading edge of time. These gates
operate in such a way that the program pulse occurs fully inside the time span
between set-up and release time of all other logic and signals applied to the pro-
grammed ROM. This precludes the possibility of spikes occurring internal to the
ROM due to race conditions yielding erroneous results. Flip-flops (F) maintain
the run status of the machine. Divider (chip A) counts the sequence of ten pro-
gram pulses and stops and/or advances the address accordingly. The outputs of
this counter also drive the serializer comprising chips H and C on card C-3 which
provide serial data to a chart recorder for recording. See card schematic C-3.
Data entry switch data and "verify" ROM data are both connected to chips M and N
which provide program data to the high voltage drivers (chips A and B) providing
appropriate negative voltage pulses to the programmed ROM. Chips K and L drive
the verify data LED's for display purposes. The "program" address and data dis-
play LED's are series connected with the appropriate programmed ROM terminals
which provides a monitor of current flow from the ROM. If the ROM is shorted the
corresponding LED will light brightly; if open, it will not light at all.
Normally during program sequence the LED's flicker dimly according to logic status
of the high voltage signals driving the "programmed" ROM. Diodes 1N914 and 470
ohm resistors provide a clamping to -45 V action to the high voltage drivers,
thus limiting the negative amplitude according to Intel specification. The error
gate J-8 checks the status of the data entry switches and provides a logical
zero signal to gate L-11 on card C-2 when all data toggles are set to 1. This
is a necessary condition to operate the programmer in the "copy" mode. When the
ERROR100/25
S D7
SD6SOSSD4SD3SD2SDISDO <
X 0 <X 1 <X 2 <X 3 <X 4 < X 5 <X6 <X7 <
6910II12
+5
GND
sd1
SC2 211
SC4
ADDRESSADVANCE 2
82107400 4 7400
SERIALDATAOUT
20
10
12
34567
H
BC
OUT
7400SPARES
7400
13
13 212 13
_11 UHP508 1N914 47K
5
RD3 F
S D3 6
R D2 E
S 02
RD1
SD1 4
47K
47K
47K
(I +50V DC
19 RPD7
W 07
18 RPD6
3 06
17 RPD5
05
16 RPD4
T 04
15
X7
X6
47K\
OK
X510
12 1113 A
13 12X4
X3
4
X2
10
XI
12 II 470
13
8 220X0
UHF 5088H90
8H905 >6.Z2,„?..._
47 K
b—wv—I-113 I
47K
14
1--F7
47K
iN_I2 RDP000
+5VDC
8H90 8H90
1>2 310K
SWITCHCONTROL
RD7 I L
SD7
LOCATE DISCRETECOMPONENTS INSLOTS E a F
470
RD6 rIT1
SD7
RD5
SD 5
R D 4
S 04
R00
9
10
10K
1—"AA99 10
10K1213
10K
2
10K4
5
10K
10
10K
r\A—'
13
12 ))11
7408V
+ 5 V
74087408
J L
7
ROM PROGRAMER / VERIFIER
DATA HANDLER, SERIALIZER, a ERROR CHECK LOGIC C — 3
4
5
6
S3-8
SO II ° Al / 41. S2-3
/SO-12 S2-4
00-13 .0- 2 Al
•
S2-5
SO-14 3 Di / .- S2-6
4SO 15 • DI 52-7
50 -17 • 6 S2 - 9
SO-18 .• 7 101 0. S2 10
\- NOTCH
PROGRAM DATAADDRESS PROGRAM
LAMPS SWITCHES
--To. +50
iemomV5ovm
SIBON/OF F
S2-1.1S3-1I
AC +V
AD902 C NC
AC
/ +50 INDICATOR
NCAC
AD 902AC -v
+65
AC J-CAD 902
AC
..5 C- v - NC INDICAToR
CvER ADDRESS SECTioN
3.3I WATT
S ° 1 vcc INDICATORSI- 2
• +5
10 .58-A
TVINE
68 0Pe, W
GND
PROGRAM SEQUENCEER 0
52 A _DATA SWITCH ERROR LAMP
5 2 -
NOTCH
VERIFYADDRESSLAMPS
ENTER ADDRESS SWITCHRE D
SI- I .11-0 21
MODE SWITCHcropyr,...
S2 -MovERIFy
MANUAL -P-410 a22A M
S2 - 1 S 2 - 18
CLOCKBNC
.s3 - 2oDATABNC
PROG,
SO-W . Di . S2 ,
VDD
SO-2O .4 ,4 . S2-IS
.A.„,SO- X 52-16
NOTCH
3 INDICATORS OVER THEPROGRAM SEQUENCE SWITCH
TOP VIEW PIN NO FUNCTION TO PIN
S3,
I /SO -N si S3-13 S3 - P
2 1>1 7 .S3-14 S3- RSG P •
SO -R 3 El .S3 15 S 3 S
SO S 3-16 S3 -T
5 /SO- T S3 -U
So -U Oi • S3-18 53-V
SO- V 7 (>1 .S3 -19 S3-W
- NOTCH
PROGRAM VERIFYDATA DATALAMPS LAMPS
14 -14 H-8 SI - A
13 - - -13 --> H-4 A2 > T I
12 12 - --> T-2 V 3 > H 2II T -44 ---> +5VDC
10 10 ----> T- 8 X 5 > GND A
9 9 > U 26 > U I
Rp
8 U 47 U- 8 SI - T
TCH FLATCABLE
FOR: 3 DIGIT GENERAL PURPOSE DISPLAY -
INDEPENDENT/ PARALLEL BCD DATANO DEC. POT OR STROBE
14 PIN AUGAT / SCOTCH CABLE FAN OUT -
FOR ADDRESS DISPLAY
AUGATPLUG
8
mode toggle is placed in the "copy ROM' position, gate L-11 is enabled which
drives the error indicator accordingly.
The following schematic presents the various interface, display, and power
supply circuits.
24 -VDD (-48 TO- 50V) '-
23
2222
21
20
19 A 518 —A617 —A7
16 -VGG (-35 TO- 40) -IF15 — Vas (+ 12 V)I4 — CS 0-13 — PROG (-48T0 50V) -Li-
LOGIC "0"=(- 40T0- 48V)LOGIC "I" =(0V)
2
3
4 INTEL5 17026
'7PROM
8
9
1 0
11
1 2
10 X 10ms PULSES ALLOW
ADDRESS,VDD, V66, a DATA
TO BRACKET THIS PULSE
BY 10 /.1. s
ADDRESS C2LOGIC "0"- 0.3V AtLOGIC "I "- 3 V Ao
3V • LOGIC NI"
0 V = LOGIC "0"
DATA OUTPUT
I TT L LOAD+ 5V
24
2 233 224 INTEL 215 1702 2067 PROM 188 179 1610 15
11 1412 13
UI
02
0304
050607DeVcc
The next three pages provide specifications for the Intel series ROM's.
Some specifications vary in the data (i.e., program time of 2 minutes instead of
20) since some older, low serial number ROM's required more relaxed variables.
The programmer should remain timed to provide 20 minute programming time to
accommodate the older ROM'
the equipment.
. The last pages provide pictures and wire lists of
ROM PROGRAMER/ VERIFIERPROGRAM:
ADDRESS
(-40 TO-48V) .S AsLOGIc no" . - 40VLOGIC N I" = OV Ao
(-40 TO- 48V) D2= LOGIC 03
D4
OV = LOGIC H On 105Ds
DATA INPUT D7DeVcc
VERIFY:
- VDD- 9V— # 1 + 5 V— 2' 5V—A3—44 ADDRESS
LOGIC "0" "0 0.3 VLOGIC "I" "e 3V
—A5—A—A7- VGG 9V— Vas + 5V
PROG +5 V
intr
Sil
icon
Gat
e M
OS
16
02
A/1
70
2A
RO
Ms
2048
BIT
ELE
CTRI
CALL
Y PR
OG
RAM
MAB
LERE
AD O
NLY
MEM
ORY
1602
A --
ELE
CTRIC
ALLY
PRO
GRAM
MAB
LE17
02A--
ERASA
BLE
& E
LECTR
ICALL
Y REP
RO
GRAM
MABL
E
•Fa
st P
rogr
amm
ing-
- 2 m
inut
esfo
r all
2048
bits
•Al
l 204
8 bi
ts g
uara
ntee
d*pr
ogra
mm
able
--10
0% fa
ctor
y te
sted
•Fu
lly D
ecod
ed, 2
56x8
org
aniz
atio
n•
Stat
ic M
OS
-- N
o C
lock
s R
equi
red
•In
puts
and
Out
puts
DTL
and
TTL
com
patib
le•
Thre
e-st
ate
Out
put--
OR
-tie
Cap
abilit
y•
Sim
ple
Mem
ory
Expa
nsio
n--
Chi
p se
lect
inpu
t lea
d
The
160
2A a
nd 1
702A
are
256
wor
d by
8 b
it e
lect
rica
lly p
rogr
amm
able
RO
Ms
idea
lly s
uite
d fo
r us
es w
here
fas
t tur
n-ar
ound
and
patt
ern
expe
rim
enta
tion
are
impo
rtan
t. T
he 1
602A
and
170
2A u
nder
go c
ompl
ete
prog
ram
min
g an
d fu
ncti
onal
test
ing
on e
ach
bit p
osit
ion
prio
r to
shi
pmen
t, th
us in
suri
ng 1
00%
pro
gram
mab
ility
.
The
160
2A a
nd 1
702A
use
iden
tica
l chi
ps. T
he 1
702A
is p
acka
ged
in a
24
pin
dual
in-l
ine
pack
age
wit
h a
tran
spar
ent q
uart
z lid
.T
he tr
ansp
aren
t qua
rtz
lid
allo
ws
the
user
to e
xpos
e th
e ch
ip to
ult
ravi
olet
ligh
t to
eras
e th
e bi
t pat
tern
. A n
ew p
atte
rn c
an th
enbe
wri
tten
into
the
devi
ce. T
his
proc
edur
e ca
n be
rep
eate
d as
man
y ti
mes
as
requ
ired
. The
160
2A is
pac
kage
d in
a 2
4 pi
n du
alin
-lin
e pa
ckag
e w
ith a
met
al li
d an
d is
not
era
sabl
e.
The
cir
cuit
ry o
f th
e 16
02A
/170
2A is
ent
irel
y st
atic
; no
cloc
ks a
re r
equi
red.
A p
in-f
or-p
in m
etal
mas
k pr
ogra
mm
ed R
OM
, the
Int
el 1
302,
is id
eal f
or la
rge
volu
me
prod
ucti
on r
uns
of s
yste
ms
init
ially
usi
ngth
e 16
02A
or
1702
A.
The
160
2A11
702A
is f
abri
cate
d w
ith
silic
on g
ate
tech
nolo
gy. T
his
low
thre
shol
d te
chno
logy
allo
ws
the
desi
gn a
nd p
rodu
ctio
n of
high
er p
erfo
rman
ce M
OS
circ
uits
and
pro
vide
s a
high
er f
unct
iona
l den
sity
on
a m
onol
ithic
chi
p th
an c
onve
ntio
nal M
OS
tech
nolo
gies
.
PIN
CO
NF
IGU
RA
TIO
NP
IN N
AM
ES
BL
OC
K D
IAG
RA
M
DA
TA O
UT
1D
AT
A O
UT
8-
VD
°A
0—
A7
Add
ress
Inp
uts
2V
CC
CS
Chi
p S
elec
t Inp
utO
UTP
UT
322
VC
C
DO
UT
1—D
OU
T8
Dat
a O
utpu
tsB
UFF
ERS
•D
ATA
OU
T 1
-
•D
AT
A O
UT
2 -
4 IL
5131
20-
•D
AT
A O
UT
3 -
619
A,
2048
BIT
PRO
GR
AM
RO
M M
ATR
IX•D
AT
A O
UT
4 -
712
56 x
81
•D
AT
A O
UT
58
17A
7
•D
AT
A O
UT
6
•D
AT
A O
UT
7 -
15V
BB
DEC
OD
ER
*DA
TA
OU
T 8
-1/
(M
SBI
14 13
CS
PRO
GR
AM
•TH
IS P
IN I
S TH
E D
ATA
INPU
T LE
AD D
URIN
G P
ROG
RAM
MIN
GIN
PU
TD
RIV
ERS
See
pag
e 3-
8 fo
r op
erat
iona
l con
nect
ion.
tt
Ao
AiA
,
NO
TE
: In
the
rea
d m
ode
a lo
gic
1 at
the
add
ress
inpu
ts
.Int
el's
liab
ility
sha
ll be
lim
ited
to r
epla
cing
and
data
out
puts
is a
hig
h an
d lo
gic
0 is
a lo
w.
any
unit
whi
ch f
ails
to p
rogr
am a
s de
sire
d.U
.S. P
aten
t No.
366
0819
PIN
CO
NN
ECTI
ON
S
The
ext
erna
l lea
d co
nnec
tion
s to
the
1602
A/1
702A
dif
fer,
dep
endi
ng o
n w
heth
er th
e de
vice
is b
eing
pro
gram
med
") o
r us
ed in
read
mod
e. (
See
fol
low
ing
tabl
e)
PIN
MO
DE
12(V
cc )
13(P
rogr
am)
14 (ei)
15 (V13
6 )
16)V
00
)
22(V
6c )
23(V
cc )
Rea
dVCC
VCC
GN
DV
ccVG
GVC
CVC
CPr
ogra
mm
ing
GN
DPr
ogra
m P
ulse
GN
DV B
BPu
lsed
VG
G (
V,,,,,,
)G
ND
GN
D
Abso
lute
Max
imum
Rat
ings
"A
mbJ
ent T
empe
ratu
re U
nder
Bia
s...
......
.0°
C to
+70
°CSt
orag
e T
empe
ratu
re...
......
......
......
......
..—
65°C
to +
125°
CSo
lder
ing
Tem
pera
ture
of
Lea
ds (
10 s
ec)
+300
°CPo
wer
Dis
sipa
tion
......
......
......
......
......
....
2 W
atts
Rea
d O
pera
tion
: Inp
ut V
olta
ges
and
Sup
ply
Vol
tage
s w
ith
resp
ect t
o V
cc ..
......
......
.....
...+0
.5V
to —
20V
Prog
ram
Ope
ratio
n:In
put V
olta
ges
and
Supp
lyV
Olt
ages
wit
h re
spec
t to
Vcc
....
......
.....
......
......
......
.....
—48
V
*CO
MM
ENT
Stre
sses
abo
ve th
ose
liste
d un
der
"Abs
olut
e M
axim
um R
at-
ings
" m
ay c
ause
per
man
ent d
amag
e to
the
devi
ce. T
his
is a
stre
ss r
atin
g on
ly a
nd f
unct
iona
l ope
rati
on o
f th
e de
vice
at
thes
e or
at
any
othe
r co
ndit
ion
abov
e th
ose
indi
cate
d in
the
oper
atio
nal s
ecti
ons
of th
is s
peci
fica
tion
is n
ot im
plie
d.E
xpos
ure
to A
bsol
ute
Max
imum
Rat
ing
cond
itio
ns f
or e
x-te
nded
per
iods
may
aff
ect d
evic
e re
liab
ilit
y.
READ
OPE
RATI
ON
D.C
. and
Ope
ratin
g C
hara
cter
istic
sT
A =
0°C
to 7
0°C
, Vcc
= +
5V
+5%
, V
DD
= —
9V+
5%
, Vg=
—9V
+5%
, unl
ess
othe
rwis
e no
ted.
SYM
BO
LT
EST
MIN
.T
YP
P) M
AX
.U
NIT
CO
ND
ITIO
NS
luA
ddre
ss a
nd C
hip
Sele
ctIn
put L
oad
Cur
rent
1H
AVIN
= 0
.0V
1L0
Out
put L
eaka
ge C
urre
nt1
P A
'1O
UT
=C
S =
VC
C —
2'D
OD
Pow
er S
uppl
y C
urre
nt5
10m
AV
GG
=V
cc, .
CS
=V
cc —
21 0
L=
0.0m
A ,
TA
= 2
5°C
1001
Pow
er S
uppl
y C
urre
nt35
50m
A- a
=V
cc —
2lo
t_ =
0.0m
A ,
TA
= 2
5°C
Con
tinuo
usO
pera
tion
1002
Pow
er S
uppl
y C
urre
nt32
46m
Aa=
O.0
'DL
=0.
0mA
, T
A =
25°
C
1003
Pow
er S
uppl
y C
urre
nt38
.560
mA
a=
V c0 —
2l o
t_ =
0.0m
A ,
TA =
0°C
ICF1
Outp
ut
Cla
mp C
urr
ent
814
mA
Vo
uT
= —
1.0
V,
TA =
0°C
I CF2
Out
put C
lam
p C
urre
nt13
mA
Vo
ir,. =
—1
.0V
, T
A =
25°
C
'GO
Gat
e Su
pply
Cur
rent
1pA
ViL
iIn
put L
ow V
olta
ge f
orT
T L
Inte
rfac
e—
1.0
0.65
V
V I L
2
_
Inpu
t Low
Vol
tage
for
MO
S In
terf
ace
VD
DV
Cc
—6
V
VIH
Add
ress
and
Chi
p Se
lect
Inpu
t Hig
h V
olta
geV
00-2
Vcc
+°.
3V
lot_
Out
put S
ink
Cur
rent
1.6
4m
AV
OU
T =
0.4
5V
'OH
Out
put S
ourc
e C
urre
nt—
2.0
mA
VO
UT
— 0
.0V
VO
LO
utpu
t Low
Vol
tage
—.7
0.45
V10
L =
1.6
mA
VO
HO
utpu
t Hig
h V
olta
ge3.
54.
5V
10=
—10
0 pA
Not
e 1:
In t
he p
rogr
amm
ing
mod
e, t
he d
ata
inpu
ts 1
-8 a
re p
ins
4-11
res
pect
ivel
y. e
- § =
GN
D.
Not
e 2:
VG
G m
ay b
e cl
ocke
d to
red
uce
pow
er d
issi
pati
on. I
n th
is m
ode
aver
age
ID
D in
crea
ses
in p
ropo
rtio
n to
VG
G.d
uty
cycl
e. (
See
p. 5
1N
ote
3:T
ypic
al v
alue
s ar
e at
nom
inal
vol
tage
s an
d T
A =
25°
C.
3.7
3-8
3-9
3-10
A.C
. Cha
ract
eris
tics
TA
=
0°C
to
+70
°C, V
c,
= +
5V ±
5%,
VD
D=
—9V
±5%
, V
G,
= —
9V
+5%
unle
ss o
therw
ise n
ote
d
SYM
BO
LT
EST
MIN
IMU
MT
YPI
CA
LM
AX
IMU
MU
NIT
Freq
.R
epet
itio
n R
ate
1M
Hz
t O
HPr
evio
us r
ead
data
val
id10
0ns
'AC
CA
ddre
ss to
out
put d
elay
.700
1Ps
tDvG
OC
lock
ed V
GG
se
t up
opt
s
tcs
Chi
p se
lect
del
ay10
0ns
tC0
Out
put d
elay
fro
m C
S90
0ns
too
Out
put d
esel
ect
300
nst
OH
CD
ata
out h
old
in c
lock
ed V
GG
m
ode
(Not
e 11
5pi
sN
ote
1.T
he o
utpu
t w
ill r
emai
n va
lid
for
t0H
c as
long
as
cloc
ked
VG
G is
at
Vcc
. An
addr
ess
chan
ge m
ay o
ccur
as
soon
as
the
outp
ut is
sen
sed
(clo
cked
VG
, may
sti
ll b
e at
Vcc
). D
ata
beco
mes
inv
alid
for
the
old
add
ress
whe
n cl
ocke
d V
GG
Is
retu
rned
to
VG
G.
Capacit
an
ce*
TA
=
25°
C
SYM
BO
LT
EST
MIN
IMU
MT
YPI
CA
LM
AX
IMU
MU
NIT
CO
ND
ITIO
NS
CiN
Inpu
t Cap
acit
ance
815
pFM
N =
VC
C —
All
CO
UT
Out
put C
apac
itan
ce10
15pF
CS
= V
ccun
used
pin
s
—V
OU
T =
Vcc
VG
G =
VC
C_
are
at A
.C.
grou
ndC
voo
VG
G C
apac
itanc
e(C
lock
ed V
GG
M
ode)
30pF
'Thi
s pa
ram
eter
is p
erio
dica
lly
sam
pled
and
is n
ot 1
00%
tes
ted.
B)C
lock
ed V
GG
Ope
ratio
n
Sw
itch
ing
Ch
ara
cte
risti
cs
V.
t-C
YC
LE
TIM
E ,
FR
EO
-----.1
I10
%
Con
diti
ons
of T
est:
AD
DR
ESS ,,
Inpu
t pu
lse
ampl
itud
es:
0 to
4V
; t,
, t,
5_
50 n
sO
utpu
t loa
d is
1 T
TL
gat
e; m
easu
rem
ents
mad
eV
I,.
—"\it
P.On
sat
out
put
of T
TL
gat
e (t
i, D 5
_ 15
ns)
CS
Al
Con
stan
t V
GG
Op
era
tio
n..-
44
- tov
Vcc
I 1
..,
CY
CL
E T
IME
= i
/FR
EO
--.1
V.
I
CLO
CKED
VG
G
I(S
EEin
AD
DR
ESS
9C
I%
VG
GI
I..-
-- 'A
CC
----. 1
-.4
IV
o.
NO
TE 1
)to
Hc
I .-
1
V, L,
DA
TAD
ATA
OU
TD
AT
A O
UT
-P.,J
CS
I..—
I 1
OU
TIN
VA
LID
INV
AL
ID
aI
i DES
ELEC
TIO
N O
F D
ATA
OU
TPU
T IN
OR
-TIE
OPE
RA
TIO
NVi
i.V
,„
AD
DR
ESS
:
y
Vo.
DA
TAD
AT
A O
UT
ViL
1'
if---
OU
TIN
VA
LID
It
NO
TE 2
T_
-,,,
,,--,
...--
- 2 O
ns
'AC
CD
AT
A O
UT
INV
AL
IDCS
/
V,.
AD
DR
ESS
DES
ELEC
TIO
N O
F D
ATA
OU
TPU
T IN
OR
. TIE
OPE
RA
TIO
NVI
I.
-.4,
VCC
'
i r."--
4- tO
VG
GI
'007 ,
CLO
CKED
IV
..V
",
VGG
a
10%
SO%
2,50 n
s --..1
vo.
OU
TI
DA
TAV
..i
I,
-.I to
. f--
-l''
.—,A
ccvo
L
NO
TE 1
: Th
e ou
tput
will
rem
ain
valid
for t
o.c
as lo
ng a
s cl
ocke
dV
..( ,) ,:Jr
Iis
at V
cc. A
n ad
dres
s ch
ange
may o
ccur
as
soon
as
the
outp
ut is
sen
sed
(clo
cked
V..
may s
till b
e at
Vcc
). D
ata
beco
mes
inva
lid fo
r the
old
Voi.
tco
II.-
-e-:
addr
ess
whe
n cl
ocke
d V
.. is
ret
urne
d to
VG
G.
NO
TE
2: I
f a m
akes
a t
ran
siti
on
fro
m V
, to
V,
H w
hile
clo
cked
VG
Gis
at V
... th
en d
esel
ectio
n of
out
put
occ
urs
at tc
, as
show
n in
sta
ticop
erat
ion
with
con
stan
t V...
RO
Ms
RO
Ms
Iflt
el®
Silic
on G
ate
MO
S 16
02A
/170
2Ain
tI®
Silic
on G
ate
MO
S 16
02A/
1702
A
Vcc .V
VG,
,,= -
9V
VG
G= -
9V
VO
L +
.45V
a....v
20 3
0 4
0 5
0 6
0 7
0 6
0 9
0AM
BIE
NT T
EM
PERATU
RE 1
°C,
VCc +
5V
VG
G =
-9V
V0,,
0.0
V
45
11
11
1
-2-1
0+1
+2
OU
TPU
T V
OLT
AG
E (
VO
LTS)
+3
1020
3040
5060
DU
TY C
YC
LE 1
10
so70
so10
0
Typ
ical
Cha
ract
eris
tics
I DO
CU
RR
EN
T V
S. T
EM
PE
RA
TU
RE
OU
TP
UT
CU
RR
EN
T V
S.
VD
D S
UP
PL
Y V
OL
TA
GE
OU
TP
UT
CU
RR
EN
T V
S.
TE
MP
ER
AT
UR
E
V
OU
TP
UT
SIN
K C
UR
RE
NT
VS
. OU
TP
UT
VO
LT
AG
E
AV
ER
AG
E C
UR
RE
NT
VS
. DU
TY
CY
CL
E F
OR
CL
OC
KE
D V
GG
800
900
700
1 60
0 Ws'
ELO
AD
20 /31
1 TTL
Vcc
ri 3
00+
5V
VD
°
200
VG
G-9
V10
0
0 10 , 0
30 4
0 5
0 6
0 7
0 8
0 9
0A
MBI
ENT
TEM
PERA
TURE
I T
T,
LOAD
VG,
= +
5V
Voc
, = -
9V
V GG
-9
y
T A -2
50c
= +
5V
V00 =
-9V
VG
G =
-9V
—
TA =
25°C-
g 8
.0
o.ov
s.o
4.0
2.0
l Ooi 35
I
30 2s
1 :
: 10I m
o 5
900
800
700
1 .
0
III
00
io
20
30
40 5
0 8
0 7
0 B
O 9
0 1
00
LOA
D C
APA
CITA
NCE
(PP,
AC
CE
SS T
IME
VS.
LO
AD
CA
PAC
ITA
NC
EA
CC
ESS
TIM
E V
S.T
EM
PE
RA
TU
RE
400
200
100
14
.0
12.0
10.0
a
-6-7
-V.
SU
PPLY V
OLTAG
E W
I
2040
6080
100
120
AM
BIE
NT T
EM
PERATU
RE,.
395 4
3s1
11
11
1V
G,
= +
5V
Vop
= -9V
37
MIN
IM
1111
1111
111
IN
NEN
36V
GG
= -9V
INPU
TS =
VG
Ga
35
I. ,: 33
tE 32
B 3
1
_2 30 20 28 27
OU
TPU
TS A
RE O
PEN
"
Um, 111
1.2
8 •Zi
-3
i ntI
®S
ilic
on G
ate
MO
S 1
602A
/170
2A
RO
Ms
tACW
tAC
HL
.—
P;11
BIN
AR
Y C
OM
PLE
ME
NT
AD
DR
ESS
OF
WO
RD
TO
BE
PR
OG
RA
MM
ED
BIN
AR
Y A
DD
RE
SSO
F W
OR
D T
O B
EPR
OG
RA
MM
ED
0
PUL
SED
VG
,PO
WER
SU
PPL
Y
-35
to
-40
PRO
GR
AM
MIN
GPU
LSE
-46 t
o -
48
DA
TA IN
PUT)
71/
(DEV
ICE
DA
TA
CA
NO
UT
PUT
CH
AN
GE
LIN
ES)
A-4
6 t
o -
48
1
DA
TA
ST
AB
LE
TIM
ED
AT
A C
AN
CH
ANV
AD
DR
ESS
-40
to
-48 0
PULS
ED V
Dc,
POW
ER S
UPP
LY
-46 t
o -
48
—.1
1tV
D
Sw
itch
ing
Cha
ract
eris
tics
for
Pro
gram
min
g O
pera
tion
PR
OG
RA
M O
PE
RA
TIO
N
Con
ditio
ns o
f Tes
t:In
put p
ulse
rise
and
fall
times
5_
1pse
cC
S =
OV
PR
OG
RA
M W
AV
EFO
RM
S
Pro
gram
min
g O
pera
tion
of
the
1602
A/1
702A
Whe
n th
e D
ata
Inpu
t for
the
Pro
gram
Mod
e is
:T
hen
the
Dat
a O
utpu
tdu
ring
the
Rea
d M
ode
is:
VI
LI
P =
'"--
48V
pul
sed
VIH
P =
^' O
V
Log
ic 1
= V
0H = 9
3 ' on t
ape
Log
ic 0
= V
0L=
'N' o
n ta
pe
WO
RD
A7
A6
A5
AD
DR
ES
S
A4
A3
A2
A1
AO
00
00
00
00
0
10
00
00
00
11
11
11
11
1
11
11
11
11
125
51
11
11
11
1
Add
ress
Log
ic L
evel
Dur
ing
Rea
d M
ode:
Log
ic 0
= V
IL (
"-.3
V)
Log
ic 1
= V
I H (
'`"
3V)
Add
ress
Log
ic L
evel
Dur
ing
Pro
gram
Mod
e:L
ogic
0 =
VIL
2P
( "
--4
0V
) L
og
ic 1
=V
IHP
("-
'0V
)
PRO
GRAM
MIN
G O
PERAT
ION
D.C
. and
Ope
rati
ng C
hara
cter
isti
cs f
or P
rogr
amm
ing
Ope
rati
onT
A =
25°
C, V
OV
, VB
B =
+12V
± 1
0%, C
S =
OV
unl
ess
othe
rwis
e no
ted
SY
MB
OL
TES
TM
IN.
TYP
.M
AX
.U
NIT
CO
ND
ITIO
NS
ILi
i pA
ddre
ss a
nd D
ata
Inpu
tLo
ad C
urre
nt10
mA
iN =
—48
V
ILI2
PP
rogr
am a
nd V
, GLo
ad C
urre
nt10
mA
VIN
= —
48
V
'BB
VB
B S
uppl
y Lo
ad C
urre
nt.0
5m
A
'DDP
11)
Peak
ID
, Sup
ply
Load
Cur
rent
200
mA
VD
D =
Vp
ro,.= —
48V
VG
G =
—35
VV
mp
Inpu
t Hig
h V
olta
ge0.
3
VIL
1PP
ulse
d D
ata
Inpu
tLo
w V
olta
ge—
46—
48
VI L
2PA
ddre
ss In
put L
owV
olta
ge—
40—
48
ViL
,,,
Pul
sed
Inpu
t Low
VD
E,
and
Pro
gram
Vol
tage
—46
—48
VI L
4PP
ulse
d In
put L
owV
GG
Vol
tage
—35
—40
Not
e 1:
IDD
p fl
ows
only
dur
ing
VD
D, V
00 o
n ti
me.
ID
Dp
shou
ld n
ot b
e al
low
ed t
o ex
ceed
300
mA
for
gre
ater
tha
n 10
0p,s
ec. A
vera
ge p
ower
supp
ly c
urre
nt I
DD
p i s
typ
ical
ly 4
0mA
at 2
0% d
uty
cycl
e.
A.C
. Cha
ract
eris
tics
for
Pro
gram
min
g O
pera
tion
TA
MB
IEN
T =
25°
C, V
cc =
OV
, VB
B =
+ 1
2V +
10%
, CS
= O
V u
nles
s ot
herw
ise
note
d
SY
MB
OL
TES
TM
IN.
TYP
.M
AX
.U
NIT
CO
ND
ITIO
NS
Dut
y C
ycle
(VD
D ,
VG
G) .
20%
t o
pw
Pro
gram
Pul
se W
idth
3M
sVG
G =
—35
V, V
DD
=V
prog =
—48
V
t D
wD
ata
Set
Up
Tim
e25
ps
t D
HD
ata
Hol
d Ti
me
10ps
tvw
VD
D , V
GG
Set
Up
100
/IS
t V
DV
DD
, V
GG
Hol
d10
100
ps
t A
CW
121
Add
ress
Com
plem
ent
Set
Up
25p
s
t A
CH
121
Add
ress
Com
plem
ent
Hol
d25
/IS
t A
TW
Add
ress
Tru
e S
et U
p10
ps
tAT
HA
ddre
ss T
rue
Hol
d10
ps
Not
e 2.
All
8 a
ddre
ss b
its
mus
t be
in
the
com
plem
ent
stat
e w
hen
puls
ed V
DD
and
.VG
G m
ove
to t
heir
neg
ativ
e le
vels
. The
add
ress
es 1
0 th
roug
h25
51 m
ust b
e pr
ogra
mm
ed a
s sh
own
in th
e ti
min
g di
agra
m f
or a
min
imum
of
32 ti
mes
.
intI
®S
ilic
on G
ate
MO
S 1
602A
/170
2A
RO
Ms
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3.1
13-1
2
1N91
4
1N91
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0)
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13A
2
LA
l
AO DO
9A
7D
1
8A
602
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503
6A
4D
4
5A
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5
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13 14 15 16 17 18 19 20 21 22 23 24
From
To
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MS
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12
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13 14 1522
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12
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Abb
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C C
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C C
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40010,,„„
•
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