Nanocomputer Nanocomputer Systems EngineeringSystems EngineeringLaying the Key Methodological Laying the Key Methodological Foundations for the Design of Foundations for the Design of 2121stst-Century Computer Technology-Century Computer Technology

Michael P. FrankMichael P. FrankCISE & ECE DepartmentsCISE & ECE DepartmentsUniversity of FloridaUniversity of Florida<mpf@cise.ufl.edu><mpf@cise.ufl.edu>

The full paper is available at:The full paper is available at:http://www.cise.ufl.edu/research/revcomp/theory/NanoTech2003/Frank-NanoTech-2003.doc, , .ps..

Cost-Efficiency:Cost-Efficiency:The Key Figure of MeritThe Key Figure of Merit

AllAll practical engineering design-optimization practical engineering design-optimization can ultimately be reduced to maximization of can ultimately be reduced to maximization of generalized, system-level cost-efficiency.generalized, system-level cost-efficiency. Given appropriate models of cost “Given appropriate models of cost “$$”.”.

Definition of Cost-Efficiency Definition of Cost-Efficiency %%$$ a Process: a Process:

%%$$ : :≡≡ $$minmin//$$actualactual

Maximize Maximize %%$$ by minimizing by minimizing $$actualactual

This is valid even when This is valid even when $$minmin is unknown is unknown

Important Cost Important Cost Categories in ComputingCategories in Computing Hardware-Proportional Costs:Hardware-Proportional Costs:

Initial Manufacturing CostInitial Manufacturing Cost Time-Proportional Costs:Time-Proportional Costs:

Inconvenience to User Waiting for ResultInconvenience to User Waiting for Result (Hardware(HardwareTime)-Proportional Costs:Time)-Proportional Costs:

Lifetime-Amortized Manufacturing CostLifetime-Amortized Manufacturing Cost Maintenance & Operation CostsMaintenance & Operation Costs Opportunity CostsOpportunity Costs

Energy-Proportional Costs:Energy-Proportional Costs: Adiabatic LossesAdiabatic Losses Non-adiabatic Losses From Bit ErasureNon-adiabatic Losses From Bit Erasure Note: These may both vary Note: These may both vary

independentlyindependently of (HW of (HWTime)!Time)!

Focus oftraditionaltheories ofso-called“computationalcomplexity”

These costsneed to beincluded also in practicaltheoreticalmodels ofnanocomputing

Two-Pass System Two-Pass System OptimizationOptimization

A general methodology for the interdisciplinary A general methodology for the interdisciplinary optimization of the design of complex systems.optimization of the design of complex systems.

Performance characteristicsPerformance characteristicsof system are expressed asof system are expressed asfunctions of system’s design functions of system’s design parameters, & subsystems’ parameters, & subsystems’ own characteristics.own characteristics.

Then, optimize designThen, optimize designparameters from top downparameters from top downto maximize overall system-to maximize overall system-wide cost-efficiency.wide cost-efficiency.

Mid-levelcomponents

High-levelsubsystems

Top-levelsystems design

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Lowest-leveldesign elements

Computer Modeling AreasComputer Modeling Areas

1.1. Logic DevicesLogic Devices

2.2. Technology ScalingTechnology Scaling

3.3. InterconnectionsInterconnections

4.4. SynchronizationSynchronization

5.5. Processor ArchitectureProcessor Architecture

6.6. Capacity ScalingCapacity Scaling

7.7. Energy TransferEnergy Transfer8.8. ProgrammingProgramming9.9. Error HandlingError Handling10.10.PerformancePerformance11.11.CostCost

An Optimal, Physically Realistic Model of Compu-ting Must Accurately Address All these Areas!

Fundamental Physical Fundamental Physical Constraints on Constraints on ComputingComputing

Speed-of-LightLimit

Thoroughly Confirmed

Physical Theories

UncertaintyPrinciple

Definitionof Energy

Reversibility

2nd Law ofThermodynamics

Adiabatic Theorem

Gravity

Theory ofRelativity

QuantumTheory

ImpliedUniversal Facts

Affected Quantities in Information Processing

Communications Latency

Information Capacity

Information Bandwidth

Memory Access Times

Processing Rate

Energy Loss per Operation

Landauer’s Principle (1961):Landauer’s Principle (1961):Bit Erasure Creates EntropyBit Erasure Creates Entropy

0

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Nstates

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Unitary(1-1)

evolution

Before bit erasure: After bit erasure:

Increase in entropy: S = log 2 = k ln 2Energy lost to heat: ST = kT ln 2

Reversible / Adiabatic Chips Reversible / Adiabatic Chips Designed @ MIT, 1995-1999Designed @ MIT, 1995-1999By the author and other then-students in the MIT Reversible Computing group,under AI/LCS lab faculty members Tom Knight and Norm Margolus.

Example Application of Our Example Application of Our Engineering Methodology Engineering Methodology

A research question to be answered:A research question to be answered: As nanocomputing technology advances,As nanocomputing technology advances,

will will reversible computingreversible computing become become very cost-effective, and if so, when?very cost-effective, and if so, when?

We applied our methodology as follows:We applied our methodology as follows: Made Realistic Model (Obeying Constraints)Made Realistic Model (Obeying Constraints) Optimized Cost-Efficiency in the ModelOptimized Cost-Efficiency in the Model Swept Model Parameters over Future YearsSwept Model Parameters over Future Years

Important Factors Important Factors Included in Our ModelIncluded in Our Model Entropic cost of irreversibilityEntropic cost of irreversibility Algorithmic overheads of reversible logicAlgorithmic overheads of reversible logic Adiabatic speed vs. energy-loss tradeoffAdiabatic speed vs. energy-loss tradeoff Optimized degree of reversibilityOptimized degree of reversibility Limited quality factors of real devicesLimited quality factors of real devices Communications latencies in parallel Communications latencies in parallel

algorithmsalgorithms Realistic heat flux constraintsRealistic heat flux constraints

Technology-Independent Technology-Independent Model of Nanoscale Logic Model of Nanoscale Logic DevicesDevices

IIdd – Bits of internal logical state information per – Bits of internal logical state information per nano-devicenano-device

SSiopiop – Entropy generated per irreversible nano-– Entropy generated per irreversible nano-device operationdevice operation

tticic – Time per device cycle (irreversible case)– Time per device cycle (irreversible case)SSd,td,t – Entropy generated per device per unit time – Entropy generated per device per unit time

(standby rate, from leakage/decay)(standby rate, from leakage/decay)SSrop,frop,f – Entropy generated per reversible op per unit – Entropy generated per reversible op per unit

frequencyfrequencydd – Length (pitch) between neighboring – Length (pitch) between neighboring

nanodevicesnanodevicesSSA,tA,t – Entropy flux per unit area per unit time– Entropy flux per unit area per unit time

Technological TrendTechnological TrendAssumptionsAssumptions

1E-17

1E-16

1E-15

1E-14

1E-13

1E-12

1E-11

1E-10

1E-09

1E-08

1E-07

1E-06

0.00001

0.0001

0.001

0.01

0.1

1

10

100

1000

10000

100000

2000 2010 2020 2030 2040 2050 2060

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Entropy generatedper irreversible bittransition, nats

Minimum time perirreversible bit-devicetransition, secs.

Minimum pitch (separation between centers of adjacent bit-devices), meters.

Minimum cost perbit-device, US$.

Absolute Absolute thermodynamicthermodynamiclower limit!lower limit!

Nanometer pitch limitNanometer pitch limit

Example Example quantum limitquantum limit

Fixed TechnologyFixed TechnologyAssumptionsAssumptions Total cost of manufacture: US$1,000.00Total cost of manufacture: US$1,000.00

User will pay this for a high-performance desktop CPU.User will pay this for a high-performance desktop CPU. Expected lifetime of hardware: 3 yearsExpected lifetime of hardware: 3 years

After which obsolescence sets in.After which obsolescence sets in. Total power limit: 100 WattsTotal power limit: 100 Watts

Any more would burn up your lap. Ouch!Any more would burn up your lap. Ouch! Power flux limit: 100 Watts per square centimeterPower flux limit: 100 Watts per square centimeter

Approximate limit of air-cooling capabilitiesApproximate limit of air-cooling capabilities Standby entropy generation rate: Standby entropy generation rate:

1,000 nat/s/device1,000 nat/s/device Arbitrarily chosen, but achievableArbitrarily chosen, but achievable

Cost-Efficiency Benefits Cost-Efficiency Benefits of Reversible Computingof Reversible Computing

1.00E+22

1.00E+23

1.00E+24

1.00E+25

1.00E+26

1.00E+27

1.00E+28

1.00E+29

1.00E+30

1.00E+31

1.00E+32

1.00E+33

2000 2010 2020 2030 2040 2050 2060

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Scenario: $1,000/3-years, 100-Watt conventional computer, vs. reversible computers w. same capacity.

All curves would →0 if leakage

not reduced.

~1,000×

~100,000×

More Recent WorkMore Recent Work

Optimizing device size toOptimizing device size tominimize entropy generationminimize entropy generation

Minimizing Entropy GenerationMinimizing Entropy Generationin Field-Effect Nano-devicesin Field-Effect Nano-devices

Lower Limit to Entropy Lower Limit to Entropy Generation Per Bit-Generation Per Bit-OperationOperation

Scaling withdevice’s quantum“quality” factor q.

• The optimal redundancyfactor scales as: 1.1248(ln q)

• The minimumentropy gener-ation scales as: q −0.9039

ConclusionsConclusions

We have developed an integrated and We have developed an integrated and principled methodology for analysis of principled methodology for analysis of nanocomputer systems engineeringnanocomputer systems engineering.. Techniques such as this are needed to address Techniques such as this are needed to address

difficult but important questions.difficult but important questions. E.g.E.g., the cost-efficiency of reversible computing., the cost-efficiency of reversible computing.

Preliminary results indicate that Preliminary results indicate that reversible reversible computingcomputing offers offers extremeextreme cost-efficiency cost-efficiency advantages for future nanocomputing.advantages for future nanocomputing. EvenEven when taking its overheads into account! when taking its overheads into account!