my slides on line - jaist...

My slides on line:http://brian.kurkoski.org

<#>

Overview of Codes

for Re-writing and Error Correction

in Flash Memories

第３３回　情報理論とその応用シンポジウムワークショップ33rd Symposium on Information Theory and Applications —

Night Workshop

Brian M. [email protected]

Dept. of Information and Communications Engineering University of Electro-Communications

Tokyo, Japan

2010 December 1

Kurkoski: University of Electro-Communications /44

Hard Drives vs. Flash-Based Storage

4

versus

Hard disk drive Solid state drive (SSD)based on flash memory


Hard Drives vs. Flash-Based Storage

5

Hard Disk Drive Flash Memory Drive

Spinning disk—the only moving part inside your computer Mechanically durable

Fast sequential access

But, future increases limited by rotational speed

Very fast random reading and writing (~100 times faster than disk)

High power Low power

must buy a whole drive

• cannot buy drive for ¥900

small memories possible

• 2 GB for ¥900

Lowest cost per GB High cost per GB

Long-term performance: mechanical failure Long-term performance: semiconductor failure


Average Price Per GB

6

2007 2008 2009 2010 2011 2012

$1000

$100

$10

$1

0.10

DRAM-based SSD

Flash SSD1.8 inch HDD2.5 inch HDD

Pric

e pe

r GB

ProjectedSource: IDC Worldwide Solid State Drive, 2008-2012 Forecast and Analysis: Entering the No-Spin Zone, Doc #212736. As used in Khaled Amer, http://nvmw.ucsd.edu/2010/Program.htm


7-month Price Drop of a 40 GB SSD

7

フラッシュメモリ符号化に関するワークショップの前日

April 2010第３３回　情報理論とその応用シンポジウムワークショップの前日

November 2010


Goal of This Presentation

• Storage systems are communication systems For a long time, communication theory and information theory have been used in

magnetic recording (hard drives) PRML: Partial response-maximum likelihood detection RLL: Run-length limited codes, constrained codes Error-correction: Reed-Solomon, LDPC codes turbo equalization and equalizer design Capacity of Intersymbol-interference channels

Flash memory is a new, alternative storage system

• The goal of this talk is: show that flash memory is also a communication system to convince you that coding for flash memories is an interesting problem

8


Recent Research Interest in Flash Memory Coding

• At ISIT 2007, 2008, 2009, 2010 there have been sessions dedicated to coding for memories

• April 2010: Nonvolatile Memory Workshop was held at UC San Diego

45 presentations, on topics from coding techniques to system-level considerations Second workshop is planned for 2011. http://nvmw.ucsd.edu/

• 6 December 2010: Application of Communication Theory to Emerging Memory Technologies Globecom Workshop

24 presentations in two parallel sessions; plenary talk by Jack Wolf

• IT Transactions in 2010: at least five papers on flash coding

• Numerous papers at conferences such as ITW and ISITA

• Note: NVMW and ACTEMT cover various types of non-volatile memories

Phase-Change memory (PCM) MRAM/magnetic spin memory

Memristor-based System-level considerations (data movement, disk arrays, computer architecture)

9


Outline

• Background on flash memory• Describe channel models and problems of flash memory:

Channel models data-dependent models asymmetrical noise

Decreasing SNR due to increased data density Flash memory longevity is shortened by erasures — “Write-once” model

• Current coding solutions: Classical error-correction Codes for asymmetrical errors Codes for rewriting without erasing

10


Flash Memory History

Flash is a semiconductor memory whose price has been rapidly decreasing. History: 1980 NOR Flash invented by Fujio Masuoka at Toshiba 1986 NAND Flash also invented by Fujio Masuoka 1988 Intel introduces commercial NOR Flash (PC BIOS, etc.) 1998 Early MP3 Player (32 MB, Korean SaeHan Information Systems) 2000 First USB Flash drive (8MB IBM) 2004 First flash-based iPod: 2 GB

11

http://www.storagesearch.com/semico-art1.html


About Flash: Memory Organization

• NAND Flash Higher density Has very large blocks “Sequential” access Widely used: cameras to SSDs

• NAND Flash is arranged: one page consists of 512-4096 bytes one block consists of 32-128 pages one plane consists of 1024 blocks

• NOR Flash Small sizes blocks — “random” access is possible Relatively low density — quickly being forgotten

12

http://www.linux-mag.com/cache/7590/1.html


About Flash: Charge is easily added

• In flash memories, charge is stored on a “floating gate”, and read as a voltage.

• Two very important things about flash:

1. Charge can easily be increased, but can only be decreased by an erasure operation. Only whole blocks of ~512 KB can be erased.

2. Each block has a limited number of erase cycles it can handle. After 10,000 - 100,000 erasures, the block cannot be reliably be used. Also, erasures are slow.

• Thus, erasures should be avoided.

13

http://elec424.rice.edu


Flash Memory “Wears Out”

• Like clothes you wear often, flash memories can “wear out”• As the number of erase cycles increases, the bit error rate increases• ECC is needed at 10,000 erase cycles

14

19

0.0E+00

5.0E‐06

1.0E‐05

1.5E‐05

2.0E‐05

2.5E‐05

3.0E‐05

3.5E‐05

0 2,000 4,000 6,000 8,000 10,000 12,000 14,000

Bit E

rror Rate

Program/Erase Cycles

D‐MLC32

C‐MLC64 (43nm)

B‐MLC32 (50nm)

E‐MLC8

B‐MLC8 (72nm)

MLC Wear OutLifetime

Gru

pp, e

t al.

5 different manufacturersMLC flash

Worn out flash

Worn out jeans


About Flash: Single-Level and Multi-Level Cells

15

Intel Technology Journal Q4’97

4

1

10

100

1000

10000

100000

1.5 2 2.5 3 3.5 4 4.5 5 5.5 6

Cell Threshold Voltage in Volts

Num

ber o

f Cel

ls

Erase

Program

Data = 1 0

Figure 6: Single bit/cell array threshold voltagehistogram

The charge storage ability of the flash memory cell is akey to the storage of multiple bits in a single cell. Theflash cell is an analog storage device not a digital storagedevice. It stores charge (quantized at a single electron)not bits. By using a controlled programming technique,it is possible to place a precise amount of charge on thefloating gate. If charge can be accurately placed to one offour charge states (or ranges), then the cell can be said tostore two bits. Each of the four charge states isassociated with a two-bit data pattern. Figure 7illustrates the threshold voltage distributions for a 1/2Mcblock for two bit per cell storage. After erasure or preciseprogramming to one of three program states, thethreshold of each of the 1/2Mc is measured and plotted asa histogram. Notice the precise control of the center twostates, each of which is approximately 0.3v (or 3,000)electrons in width.

1

10

100

1000

10000

100000

1 2 3 4 5 6 7Cell Threshold Voltage in Volts

Num

ber o

f Cel

ls

1 1 1 0 0 1 0 0Data =

Figure 7: Two bit/cell array threshold voltagehistogram

Higher bit per cell densities are possible by even moreprecise charge placement control. Three bits per cellrequires eight distinct charge states; four bits per cell

requires sixteen distinct charge states. In general, thenumber of states required is equal to 2N where N is thedesired number of bits.

The ability to precisely place charge on the floating gateand at some later time sense the amount of charge thatwas stored has required substantial innovations andextensive characterization and understanding of celldevice physics, memory design, and memory test. Theseinnovations are discussed in detail in the paper entitled“Intel StrataFlash Memory Technology Development andImplementation” also published in this issue of the IntelTechnology Journal.

Evolution of the Intel StrataFlash MemoryTechnology DevelopmentThis section will outline the development of the IntelStrataFlash memory technology from conception in 1992to productization in 1997, highlighting the keyinnovations along the way. The 64Mbit product recentlyintroduced differs markedly from the 1992 view of what atwo bit/cell product might look like. The learning thathas occurred over the past four years has enabled thedevelopment of a two bit/cell memory device thatfunctionally looks almost identical to a one bit/celldevice, far exceeding the capability that was consideredpossible when the development program started. Figure8 shows the timeline of the major Intel StrataFlashmemory technology development milestones.

Figure 8: Intel StrataFlash development program

The Multi-Level-Cell (M.L.C.) Concept

92 93 94 95 96 97 98

MLCTechnologyAnnounced

2b/c 32MISSCC Paper

2b/c MiniatureCard Demo

2b/c ProductIntroduced

MLC R&DStarted

Atw

ood,

et a

l.

SLC MLC (2 bits)


4

1

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100000

1.5 2 2.5 3 3.5 4 4.5 5 5.5 6


Num

ber o

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ls

Erase

Program

Data = 1 0



1

10

100

1000

10000

100000


Num

ber o

f Cel

ls

1 1 1 0 0 1 0 0Data =








92 93 94 95 96 97 98


2b/c 32MISSCC Paper



MLC R&DStarted

• SLC Single-Level cells: one bit per cell• 100,000 erase cycles

• lower density, higher cost• Applications: high-performance

servers, industrial

• MLC Multi-level cell: two bits per cell• 10,000 erasure cycles

• higher density, lower cost• Applications: consumer cell

phones, cameras, music players

• The transistor where change is stored is called a “cell”

• 8 levels (3 bits per cell) seem to be coming. Proposals as high as 256 levels.


Channel Models

• PAM with Data-Dependent Noise With Hard Decisions

• Asymmetric Noise• q-ary “write once” model

16


PAM with Data-Dependent Noise

• A simple channel model for q-level flash is q-ary PAM: maximum is q-1, minimum is 0

• A slightly more advanced model emulates Atwood, et al.:

17

Sun, Devarajan and Zhang, IET Circuits Devices Syst., 2007

0 1 2 30

1

2

3

Model:

• level 0: ! N(0, 4!2)

• level 1 to q " 2 : ! N(0, !2)

• level q " 1 : ! N(0, 2!2)

programming scheme to accordingly tighten each thresholdvoltage window and (ii) use much stronger ECC. Along thefirst direction, researchers have developed high-accuracy pro-gramming techniques to realise 3bits/cell and even 4bits/cellstorage capacity [14, 15], which however complicates thedesign of the peripheral programming mixed signal circuitsand degrades the programming throughput.To the best of our knowledge, the potential of using much

stronger ECC to improve NAND flash storage capacity hasnot been addressed in the open literature. This workattempts to fill this gap by investigating the use of strongBCH codes to enable a relatively large l (6, 8 and 12 inthis work). With the advantages of simplifying the program-ming circuits and maintaining or even increasing the pro-gramming throughput, the use of strong ECC is subject totwo main drawbacks: (i) strong ECC requires a highercoding redundancy that will inevitably degrade the storagecapacity improvement gained by a larger l and (ii) theECC decoder may incur non-negligible silicon area over-head and increase read latency. In general, to realise thesame error correction performance (or to achieve the samecoding gain), the longer the ECC code length, the lesswill be the relative coding redundancy (or higher coderate). Therefore strong ECCs are only suitable for NANDflash memories that have long data block length andhence may tolerate longer read latency. Using 2 bits/cellNAND flash memories that employ single-error-correctingHamming codes as a benchmark, we investigated the effec-tiveness of using strong BCH codes to ensure storagereliability when increasing the value of l to 6, 8 and 12,respectively. With the same programming scheme, andhence the same threshold voltage distribution characteristicsas the 2 bits/cell benchmark, the larger value of l will resultin a worse raw storage reliability and demands a strongerBCH code. To investigate the trade-off between designcomplexities and storage capacity improvements, wedesigned BCH decoders using 0.13 mm complementarymetal–oxide–semiconductor (CMOS) standard cell andstatic random access memory (SRAM) libraries. Theresults show that strong BCH codes can enable a relativelylarge increase of the number of storage levels per cell andhence a potentially significant memory storage capacityimprovement. Finally, a scheme is proposed to leveragestrong BCH codes to improve NAND flash memorydefect tolerance by trading off the memory cell program-ming time.The paper is organised as follows: We briefly present the

basics of multilevel flash memories in Section 2. The pro-posed TCM-based on-chip error correction systems for mul-tilevel NOR flash memories is presented in Section 3, andSection 4 discusses the use of strong BCH codes in multile-vel NAND flash memories. Conclusions are drawn inSection 5.

2 Multilevel flash memories

This section briefly presents some basics of multilevel flashmemory programming/read and the memory cell thresholdvoltage distribution model to be used in this work.Interested readers are referred to [3] for a comprehensivediscussion on multilevel flash memories. Multilevel flashmemory programming is typically realised by combininga program-and-verify technique with a staircase Vpp rampas illustrated in Fig. 1. The tightness of each programmingthreshold voltage window is proportional to Vpp, whereasthe cell programming time is roughly proportional to1/Vpp. The read circuit in l levels/cell NAND flashmemories usually has a serial sensing structure that takes

l2 1 cycles to finish the read operation. Higher readspeed can be realised by increasing the sensing parallelismat the cost of silicon area, which is typically preferred inlatency-critical NOR flash memories.On the basis of the results published in [16] for 2 bits/cell

NOR flash memory, the cell threshold voltage approxi-mately follows a Gaussian distribution as illustrated inFig. 2: the two inner distributions have the same standarddeviation, denoted as s; the standard deviations of thetwo outer distributions are 4s and 2s, respectively. Thelocations of the means of the two inner distributions aredetermined to minimise the raw bit error rate. Let Vmax

denote the voltage difference between the means of thetwo outer distributions. We assume that this model is alsovalid for NAND flash memories.

3 TCM-based on-chip error correction for NORflash

3.1 TCM system structure

The basic idea of TCM is to jointly design trellis codes (i.e.convolutional codes) and signal mapping (i.e. modulation)processes to maximise the free Euclidean distance(Similar to the Hamming distance of linear block codes,free Euclidean distance determines the error correctioncapability of convolutional codes, that is, a convolutionalcode with free Euclidean distance of dfree can correct atleast b(dfree2 1)/2c code symbol errors) between codedsignal sequences. As illustrated in Fig. 3, given anl-level/cell memory core, an m-dimensional TCM encoderreceives a sequence of n-bit input data, adds r-bit redun-dancy and hence generates a sequence of (n! r)-bit data,where each (n! r)-bit data are stored in m memory cellsand 2n!r " lm. The encoding process can be outlined asfollows: (1) A convolutional encoder convolves the inputk bits sequence with r linear algebraic functions and gener-ates k! r coded bits. (2) Each k! r coded bits select one ofthe 2k!r subsets of an m2D signal constellation, whereeach subset contains 2n2k signal points. (3) The additionaln2 k uncoded bits select an individual m2 D signalpoint from the selected subset.

Fig. 1 Schematic illustration of program-and-verify cellprogramming

Fig. 2 Approximate cell threshold voltage distribution model in2 bits/cell memory

IET Circuits Devices Syst., Vol. 1, No. 3, June 2007242

Authorized licensed use limited to: UNIVERSITY OF ELECTRO COMMUNICATIONS. Downloaded on March 31,2010 at 00:09:20 EDT from IEEE Xplore. Restrictions apply.


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Program

Data = 1 0



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92 93 94 95 96 97 98


2b/c 32MISSCC Paper



MLC R&DStarted


Flash IC Makes Hard Decisions

• ECC is performed outside of the flash IC• Flash IC makes hard decisions

• Performance could be improved if soft information is available! On-chip ECC External soft information

18

0 1 2 30

1

2

3

External controller with ECC Flash Memory IC

Simplified Architecture Model

to PC

Threshold decisions


Asymmetric Noise

• Flash state is electrons stored onthe floating gate

• Read state as a voltage• Electrons can leak out,

reducing the voltage• Electrons do not “leak in”

Asymmetric noise channel model

19

0 0

1 1

2 2

3 3

q-ary Asymmetric Channel

inpu

t

outp

ut0 0

1 1

2 2

3 3

q-ary Asymmetric Channelwith limited magnitude (l = 1)

inpu

t

outp

ut


“Write Once” cell model

• “Write Once Memory” (Rivest and Shamir, 1982)

• Arbitrary Directed Acyclic Graph (DAG) Fiat and Shamir, 1984. Other capacity results.

• q-ary “Write Asymmetric Memory”, Jiang et al 2007 Motivated by erasure problem for flash memories

20

4

6

52

3

1

10

q-1...3210

Most important!


Flash Suffers from 2D Intersymbol Interference

• Flash cells are arranged in an array,• there is interference between the cells• First item in CFP was “2D ISI cancelation”• No published papers on this topic!• Only patent applications

21


Three Types of Codes for Flash

• Three types of code for flash Conventional ECC for Flash Memories Codes for asymmetrical errors Codes for rewriting memory

22


Conventional ECC for Flash Memories

• Error-correction is being used now for multi-level (MLC) flash MLC errors are not bursty BCH codes can correct random errors well (R > 0.98) Extensive VLSI literature:

Liu, Rho and Sung (2006): BCH (4148,4096) to correct 4 bit errors with 52 parity bits

Micheloni, et al. (2006): BCH (32767,32692) to correct 5 errors

• Reed-Solomon Codes GF(210) Reed-Solomon has more efficient decoder than GF(214) BCH; same capability

[Chen et al., 2008]

• LDPC Codes Maeda and Kaneko (2009): Use non-binary LDPC codes of field size q

q=8, 16. R=1/2, 5/8. Found slight improvement in BER by using average column weight of 2.5

23


Codes for Asymmetrical Errors

• Codes for the asymmetric Z-channel have been studied for some time Fujiwara (1990), Blaum (1993), Klove (1995)

• One very recent code construction Noha & Bose (2010): q-ary codes correcting all asymmetric errors of limited magnitude Integer-type code; compute parity as:

24

00.150.300.450.600.75

1 2 3 4 5 6 7 8 9 10

a =!xk!1 mod L

"Lk!1 +

!xk!2 mod L

"Lk!2 + · · ·+

!x0 mod L

"L0

Text

q=16Code

Rat

e

Channel: Magnitude Limit L-1

q=8


An Interesting Problem:Rewriting for Flash

• The problem of “write once memories” storage systems is not new!

• Motivated by CD-R, Rivest and Shamirproposed “WOM Codes” in 1982 A “simple scheme” writes memory two times

with rate 1/2 code Rivest and Shamir showed rate → 0.77

25

1980 1990 2000 2010

Zemor and Cohen, IT TransCohen et al., IT

Heegard, IT Trans

1. Wolf et al, Bell Labs TR2. Fiat and Shamir, IT Trans

Rivest and Shamir, Inf. and Contr

Fu and Han Vinck, IT Trans

• Pre-2007 history of papers on “WOM Codes” and capacity

Punch cards

Flash memory

CD-R


Toy example: 3 storage “cells”

Initially (0,0,0) state 0 → 1 is allowed 1 → 0 is not allowed

Store 2 bits of information. Can write data 2 times:

first write can be any two bits second write can be any two bits

Example: store 01, then store 00

Code rate is 2/3

Guaranteed minimum of two writes

26

100

110

001

011101

111

000

010

Rivest and Shamir: “How to Reuse a ‘Write Once’ Memory” 1982

00

0111

10

0111

10

00


Outline of Rewriting Codes

• Since 2007, many rewriting codes have been proposed Names: floating codes, flash code, WOM codes, rewriting codes, etc.

• In the remainder of the talk: give bounds give a few code constructions compare codes and bounds binary q=2 first, then non-binary codes

• Coding theorists are familiar with the proposition: “minimum distance increases linearly with the block length”

• My hypothesis: Rewriting capability does not depend heavily on the block length

27

My Hypothesis


You Say ポテト

28

Word Writing (Rivest-Shamir).

• all k information bits are writtensimultaneously.

• A code allows at least T word writes,before the memory is “full”.

Bit Writing (Jiang et al).

• Only 1 bit written at a time.

• A code allows at least t bit writes,before the memory is “full”.

• 1 word write performed by k bitwrites,

T =t

k

I Say Potato

You Say トマト I Say TomatoMinimum number of writes

• Most codes specify the number ofguaranteed writes

Average number of writes

• Finucane, et al. suggested expected,or average writes as a metric


Codes for Binary Memory, q=2

29

For other values of T, estimate are given

Asymptotic bounds

Rivest & Shamir use w!!2k"T

"to mean “the length of an optimal code”.

For T = 2 word writes, the rate as k # $ is:

“capacity” = limk!"

k

w!!2k"2

" = 0.7729

Interestingly, 0.7729 is the solution to the equation H(1% p) = p.

T Achievable log(T )/TRate (est.)

3 0.6456 0.52834 0.5609 0.55 0.4993 0.464410 0.3352 0.332220 0.2142 0.216150 0.1116 0.1129100 0.0658 0.0664200 0.0380 0.0382


Binary WOM CodesCode Rate vs. Number of Writes

30

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

1

2

3

4

5

6

7

8

9

10Nu

mbe

r of W

rites

, T

Code rate, R

Binary WOM Codes

Numerical Bound

log(T)/T

Uncoded

RS (3,2,2)

Simple


A Binary Index-Type Scheme

31

info = 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

index 1 2 3

info = 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0

info = 0 1 1 1 0 1 1 0 0 0 0 0 0 0 0

info = 0 0 1 1 0 1 1 1 0 0 0 0 0 0 0

info = 1 0 1 1 0 1 1 1 0 0 1 0 0 0 0

. . .

The following codes was given by Mahdavifar, et al [MSVWY] at ISIT 2009to illustrate a more complicated code.

Has poor rate, but explains an index-type scheme.

Encoding: partition n cells into blocks of size log2 k. When an information bitchanges, record its index in the next available block.

Example: n = 12, R = 14 , k = 3. Results in T = 1

R log2 k word writes.


Binary WOM CodesIndex-Type Scheme

• d32

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

1

2

3

4

5

6

7

8

9

10Nu

mbe

r of W

rites

, T

Code rate, R

Binary WOM Codes

Numerical Bound

log(T)/T

Uncoded

RS (3,2,2)

Simple

MSVWY n=4MSVWY n=12

MSVWY k=2


A Linear Scheme

33

① ② ③

Cohen, Godlewski and Merkx, “Linear Binary Code for Write-Once Memo-ries,” IT Trans., 1986.

Use coset coding to encode information. Pick a linear code. Encoding:

1. Information is encoded as the syndrome of a sequence

2. From the coset of that syndrome, select the coset codeword with the min-imum weight.

3. Write that coset codeword to memory.

Decoding:

1. Compute the syndrome of the recorded sequence.

Example: Use Hamming (7,4) code to encode information with T = 3 writes:

(0, 0, 0)! (1, 0, 1)! (1, 1, 0)! (0, 0, 0)

000 001 010 100 111 011 101 110

0000000 0000001 0000010 0000100 0001000 0010000 0100000 1000000

0001111 0000111 0101111 1001111

0010011 0011011 0110011 1010011

0011100 0010100 0111100 1011100

0100101 0101101 0000101 1100101

0101010 0100010 0001010 1101010

0110110 0111110 0010110 1110110

0111001 0110001 0011001 1111001

1000110 1001110 1100110 0000110

1001001 1000001 1101001 0001001

1010101 1011101 1110101 0010101

1011010 1010010 1111010 0011010

1100011 1101011 1000011 0100011

1101100 1100100 1001100 0101100

1110000 1110000 1010000 0110000

1111111 1110111 1011111 0111111

Hamming Codewords = stored dataSy

ndro

mes

= In

form

atio

n

①

②③

① ② ③(0, 0, 0) ! (1, 0, 1) ! (1, 1, 0) ! (0, 0, 0)


Binary WOM CodesLinear Hamming (7,4) Code

35

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

1

2

3

4

5

6

7

8

9

10Nu

mbe

r of W

rites

, T

Code rate, R

Binary WOM Codes

Numerical Bound

log(T)/T

Uncoded

RS (3,2,2)

Simple

MSVWY n=4MSVWY n=12

MSVWY k=2

Hamm (7,4)


Binary WOM CodesMore Linear Codes

36

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

1

2

3

4

5

6

7

8

9

10Nu

mbe

r of W

rites

, T

Code rate, R

Binary WOM Codes

Numerical Bound

log(T)/T

Uncoded

RS (3,2,2)

Simple

MSVWY n=4MSVWY n=12

MSVWY k=2

Hamm (7,4)

Hamm (15,11)

Hamm (31,26)

Golay

Leavitt 7


Codes for Multilevel Flash: q > 2Bounds

37

Trivial bound: n=2, q=8Image: Eitan Yaakobi

By increasing q, can we get better codes?

This is recent work, since 2007.

Trivial upper bound:

t ! n(q " 1) (bit writes)

T ! (q " 1)R

(word writes)

Tighter upper bound (approximate) Jiang, Bohos-sian, Bruck, ISIT 2007 (JBB07):

t ! n(q " 1)" 12(q " 1) min

!n, k " 1

"

T ! (q " 1)R

" 12(q " 1) min

! 1R

, 1"


Rewriting Codes for q=8: Bounds

38

0 0.5 1 1.5 2 2.5 30

5

10

15

20

25

30

35q=8

Num

ber o

f Writ

es, T

Code rate, R

JBB07 n=2JBB07 n=4JBB07 n=1000

T !! q

2k

"Simple Code:

Upper bound, really?


Various Codes for q>2

39

• Jiang, Bohossian and Bruck [ISIT 2007] also proposed a re-writing code for k=2 bits It complicated and hard to understand. It is a low rate code It achieves:

• Yaakobi, Vardy, Siegel and Wolf [Allerton 2008] proposed “multidimensional codes” Achieves the same re-writing rate. Easier to understand the construction

• Jiang, et al. [ISIT 2009] “Trajectory Code” :• Mahdavifar, et al. [ISIT 2009]

• Most constructions appear to be low rate!

t = (n! 1)(q ! 1) +!q ! 1

2"

2k ! 2!

n " R ! 1k


0 0.5 1 1.5 2 2.5 30

5

10

15

20

25

30

35q=8

Num

ber o

f Writ

es, T

Code rate, R

JBB07 n=2JBB07 n=4JBB07 n=1000

YVSW−II n=8

YVSW−II n=4

YVSW−II n=2

YVSW−III n=36

Rewriting Codes for q=8: YVSW Code

40


Number of Writes increases in q!

41

0 1 2 3 4 50123456789

101112131415

Num

ber o

f Writ

es, T

Code rate, R

JBB07 q=4JBB07 q=8

JBB07 q=16

JBB07 q=32

DAG is directed acyclic graph, the memory model.

“The significant improvement in memory capability is linear with the DAG depth. For a fixed number of states a ‘deep and narrow’ DAG cell is always preferable to a ‘shallow and wide’ DAG cell.”

-Fiat and Shamir, 1984

Tight bound, really?


Summary of Rewriting Codes

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Codes for binary memories:

• Binary codes: Rivest and Shamir showed that R = log TT is possible.

• Optimal rate at T = 2 is 0.77. This is fairly low rate. Practical?

Codes for q-ary memories (with fixed rate):

• For ECC codes, we know dmin ! n

• For Rewriting codes, rewrites T increases as q increases

• But, rewrites T does not appear to heavily depend upon n.

• And, many constructions are low rate,

• Higher rate constructions are needed

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

1

2

3

4

5

6

7

8

9

10

Num

ber o

f Writ

es, T

Code rate, R

Binary WOM Codes

Numerical Bound

log(T)/T

Uncoded

RS (3,2,2)

Simple

MSVWY n=4MSVWY n=12

MSVWY k=2

Hamm (7,4)

Hamm (15,11)

Hamm (31,26)

Golay

Leavitt 7


• Rewriting codes plus ECC• Several conference papers in 2010. But, a serious problem (think RLL in hard drives)

• Each “WOM code” gets one symbol of GF(q) LDPC Code. See Zhang, Pfister, Jiang (ISIT 2010).

More Open Problems

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ECC SingleRewriting Code

dmin not guaranteed

Systematic

ECC

Rewriting Code

no rewriting in parity

ECC

Many short Rewriting Codes

WOM W WOMW W W W


Conclusion

• Flash memories are: rapidly increasing in density, widespread in the future.

• Flash memory is a type of communication system Traditional Error CorrectionAsymmetric errorsRewriting codes

• Goal: convince you that coding for flash memories

is an interesting problem

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My slides on line:http://brian.kurkoski.org

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my slides on line - jaist...

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