mx29gl512g / mx68gl1g0g - macronix · 2018-08-15 · mx29gl512g mx68gl1g0g p/n: pm1910 maroni...

1Rev. 1.3, July 05, 2018

MX29GL512GMX68GL1G0G

P/N: PM1910 Macronix Proprietary

MX29GL512G / MX68GL1G0GSINGLE VOLTAGE 3V ONLY FLASH MEMORY

Key Features • 2.7 to 3.6 volt for read, erase, and program operations

• 64KW/128KB uniform equal sectors architecture• 16 word page read buffer/256 word write buffer• Program/Erase Suspend & Program/Erase Resume

2Rev. 1.3, July 05, 2018



Contents

1. FEATURES .......................................................................................................................................................62. PIN CONFIGURATION .....................................................................................................................................83. PIN DESCRIPTION ..........................................................................................................................................94. BLOCK DIAGRAM .........................................................................................................................................105. BLOCK DIAGRAM DESCRIPTION ............................................................................................................... 116. BLOCK STRUCTURE ....................................................................................................................................127. BUS OPERATION ..........................................................................................................................................138. FUNCTIONAL OPERATION DESCRIPTION .................................................................................................14

8-1. READ OPERATION ..........................................................................................................................148-2. PAGE READ .....................................................................................................................................148-3. WRITE OPERATION ........................................................................................................................148-4. DEVICE RESET ................................................................................................................................148-5. STANDBY MODE ..............................................................................................................................148-6. OUTPUT DISABLE ...........................................................................................................................158-7. BYTE/WORD SELECTION ...............................................................................................................158-8. HARDWARE WRITE PROTECT ......................................................................................................158-9. ACCELERATED PROGRAM OPERATION .....................................................................................158-10. WRITE BUFFER PROGRAM OPERATION .....................................................................................158-11. SECTOR PROTECT OPERATION ...................................................................................................178-12. AUTOMATIC SELECT OPERATIONS ..............................................................................................178-13. INHERENT DATA PROTECTION .....................................................................................................178-14. COMMAND COMPLETION ..............................................................................................................178-15. LOW VCC WRITE INHIBIT ...............................................................................................................178-16. WRITE PULSE "GLITCH" PROTECTION ........................................................................................178-17. LOGICAL INHIBIT .............................................................................................................................178-18. POWER-UP SEQUENCE .................................................................................................................188-19. POWER-UP WRITE INHIBIT ............................................................................................................188-20. POWER SUPPLY DECOUPLING .....................................................................................................18

9. COMMAND OPERATIONS ............................................................................................................................199-1. READING THE MEMORY ARRAY ....................................................................................................199-2. AUTOMATIC PROGRAM OF THE MEMORY ARRAY .....................................................................199-3. ERASING THE MEMORY ARRAY ....................................................................................................219-4. SECTOR ERASE ..............................................................................................................................219-5. CHIP ERASE ...................................................................................................................................239-6. ERASE SUSPEND/RESUME ...........................................................................................................249-7. SECTOR ERASE RESUME .............................................................................................................249-8. PROGRAM SUSPEND/RESUME .....................................................................................................249-9. PROGRAM RESUME .......................................................................................................................249-10. BLANK CHECK .................................................................................................................................25

3Rev. 1.3, July 05, 2018



9-11. BUFFER WRITE ABORT ..................................................................................................................269-12. PROGRAM/ERASE STATUS CHECKING METHOD .......................................................................269-13. STATUS REGISTER .........................................................................................................................319-14. AUTOMATIC SELECT OPERATIONS ..............................................................................................329-15. COMMON FLASH MEMORY INTERFACE (CFI) QUERY COMMAND ...........................................349-16. RESET .............................................................................................................................................349-17. ADVANCED SECTOR PROTECTION/UNPROTECTION ................................................................359-18. SECURITY SECTOR FLASH MEMORY REGION ...........................................................................419-19. FACTORY LOCKED: CAN BE PROGRAMMED AND PROTECTED AT THE FACTORY ................ 419-20. CUSTOMER LOCKED: NOT PROGRAMMED AND NOT PROTECTED AT FACTORY ..................41

10. COMMAND REFERENCE SUMMARY ..........................................................................................................4210-1. COMMAND DEFINITIONS ...............................................................................................................4210-2. COMMON FLASH MEMORY INTERFACE (CFI) MODE .................................................................45

11. ELECTRICAL CHARACTERISTICS ..............................................................................................................4811-1. ABSOLUTE MAXIMUM STRESS RATINGS ....................................................................................4811-2. OPERATING TEMPERATURE AND VOLTAGE ...............................................................................4811-3. TEST CONDITIONS .........................................................................................................................4911-4. DC CHARACTERISTICS ..................................................................................................................5011-5. AC CHARACTERISTICS ..................................................................................................................5211-6. WRITE COMMAND OPERATION ....................................................................................................5411-7. READ/RESET OPERATION .............................................................................................................5611-8. ERASE/PROGRAM OPERATION ....................................................................................................6111-9. WRITE STATUS OPERATION ..........................................................................................................6511-10. RECOMMENDED OPERATING CONDITIONS ...............................................................................6711-11. ERASE AND PROGRAM PERFORMANCE .....................................................................................6911-12. DATA RETENTION ...........................................................................................................................6911-13. LATCH-UP CHARACTERISTICS .....................................................................................................6911-14. PIN CAPACITANCE ..........................................................................................................................70

12. ORDERING INFORMATION...........................................................................................................................7113. PART NAME DESCRIPTION .........................................................................................................................7214. PACKAGE INFORMATION ............................................................................................................................7315. REVISION HISTORY .....................................................................................................................................75

4Rev. 1.3, July 05, 2018



Figures

Figure 1. WRITE BUFFER PROGRAM FLOWCHART ........................................................................................ 16Figure 2. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART ............................................................... 20Figure 3. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART ............................................................... 22Figure 4. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART ..................................................................... 23Figure 5. PROGRAM/ERASE SUSPEND/RESUME ALGORITHM FLOWCHART .............................................. 25Figure 6. STATUS POLLING FOR WORD PROGRAM/ERASE .......................................................................... 26Figure 7. STATUS POLLING FOR WRITE BUFFER PROGRAM ........................................................................ 27Figure 8. TOGGLE BIT ALGORITHM ................................................................................................................... 28Figure 9. EXTENDED STATUS REGISTER FOR WRITE BUFFER PROGRAM ................................................ 30Figure 10. EXTENDED STATUS REGISTER FOR SECTOR ERASE ................................................................. 30Figure 11. ADVANCE SECTOR PROTECTION/UNPROTECTION SPB PROGRAM ALGORITHM ................... 35Figure 12. LOCK REGISTER PROGRAM ALGORITHM ..................................................................................... 36Figure 13. SPB PROGRAM ALGORITHM ........................................................................................................... 38Figure 14. MAXIMUM NEGATIVE OVERSHOOT WAVEFORM .......................................................................... 48Figure 15. MAXIMUM POSITIVE OVERSHOOT WAVEFORM ............................................................................ 48Figure 16. SWITCHING TEST CIRCUITS ............................................................................................................ 49Figure 17. SWITCHING TEST WAVEFORMS .................................................................................................... 49Figure 18. COMMAND WRITE TIMING WAVEFORM (WE# CONTROLLED) ..................................................... 54Figure 19. COMMAND WRITE TIMING WAVEFORM (CE# CONTROLLED) ..................................................... 55Figure 20. READ TIMING WAVEFORM ............................................................................................................... 56Figure 21. PAGE READ TIMING WAVEFORM .................................................................................................... 57Figure 22. READ MANUFACTURER ID OR DEVICE ID ..................................................................................... 58Figure 23. RESET# TIMING WAVEFORM .......................................................................................................... 59Figure 24. DEEP POWER DOWN MODE TIMING WAVEFORM ........................................................................ 60Figure 25. AUTOMATIC CHIP ERASE TIMING WAVEFORM .............................................................................. 61Figure 26. AUTOMATIC SECTOR ERASE TIMING WAVEFORM ....................................................................... 62Figure 27. AUTOMATIC PROGRAM TIMING WAVEFORM ................................................................................. 63Figure 28. ACCELERATED PROGRAM TIMING WAVEFORM ........................................................................... 64Figure 29. DATA# POLLING TIMING WAVEFORM (for AUTOMATIC MODE) .................................................... 65Figure 30. TOGGLE BIT TIMING WAVEFORM .................................................................................................... 66Figure 31. AC TIMING AT DEVICE POWER-UP .................................................................................................. 67Figure 32. POWER UP/DOWN AND VOLTAGE DROP ....................................................................................... 68

5Rev. 1.3, July 05, 2018



Tables

Table 1. MX29GL512G SECTOR ARCHITECTURE ........................................................................................... 12Table 2. MX68GL1G0G SECTOR ARCHITECTURE .......................................................................................... 12Table 3. BUS OPERATION ...................................................................................................................................13Table 4. EXTENDED STATUS REGISTER .......................................................................................................... 29Table 5. STATUS REGISTER ...............................................................................................................................31Table 6. AUTOMATIC SELECT ID VALUE ........................................................................................................... 32Table 7. AUTOMATIC SELECT HIGH VOLTAGE OPERATION ........................................................................... 33Table 8. SECTOR PROTECTION STATUS TABLE .............................................................................................. 40Table 9. COMMAND DEFINITIONS ..................................................................................................................... 42Table 10. CFI MODE: IDENTIFICATION DATA VALUES .................................................................................... 45Table 11. CFI MODE: SYSTEM INTERFACE DATA VALUES .............................................................................. 45Table 12. CFI MODE: DEVICE GEOMETRY DATA VALUES ............................................................................... 46Table 13. CFI MODE: PRIMARY VENDOR-SPECIFIC EXTENDED QUERY DATA VALUES ............................. 47Table 14. DC CHARACTERISTICS ......................................................................................................................50Table 15. AC CHARACTERISTICS ...................................................................................................................... 52Table 16. AC CHARACTERISTICS (RESET# TIMING) ...................................................................................... 59Table 17. AC CHARACTERISTICS (Deep Power Down Mode TIMING) ............................................................. 60Table 18. AC CHARACTERISTICS (AC TIMING AT DEVICE POWER-UP) ........................................................ 67Table 19. AC CHARACTERISTICS (POWER UP/DOWN AND VOLTAGE DROP) ............................................. 68Table 20. PIN CAPACITANCE: 56-TSOP ............................................................................................................. 70Table 21. PIN CAPACITANCE: 64-LFBGA ........................................................................................................... 70

6Rev. 1.3, July 05, 2018



1. FEATURES

GENERAL FEATURES• PowerSupplyOperation -2.7to3.6voltforread,erase,andprogramoperations -H/L:VI/O=VCC=2.7V~3.6V,VI/OvoltagemusttightwithVCC -U/D:VI/O=1.65V~3.6VforInput/Output• Byte/Wordmodeswitchable -512Mb:67,108,864x8/33,554,432x16 -1Gb:134,217,728x8/67,108,864x16• 64KW/128KBuniformequalsectorsarchitecture• 32byte/16wordpagereadbuffer• 256wordwritebuffer• Extra512wordsectorforsecurity -Featuresfactorylockedandidentifiable,andcustomerlockable• Latch-upprotectedto100mAfrom-1Vto1.5xVcc• LowVccwriteinhibit:Vcc≤VLKO• CompatiblewithJEDECstandard -PinoutandsoftwarecompatibletosinglepowersupplyFlash

PERFORMANCE• HighPerformance -Fastaccesstime: -H/L:100ns -U/D:110ns -Pageaccesstime: -H/L:15ns -U/D:25ns -Wordprogramtime:30us -WriteBufferProgramThrough:1.8MB/Sec,2.6MB/SecwithAcceleratedProgrammode -Sectorerasetime:0.25sec• LowPowerConsumption -Lowactivereadcurrent:12mA(typ.)at5MHz -Lowstandbycurrent:512Mb/1Gb:20/40uA(typ.) -Deeppowerdowncurrent:3uA(typ.)• 100,000erase/programcycle• 20yearsdataretention

SOFTWARE FEATURES• Program/EraseSuspend&Program/EraseResume -Suspendssectoreraseoperationtoreaddatafromorprogramdatatoanothersectorwhichisnotbeingerased

-Suspendssectorprogramoperationtoreaddatafromanothersectorwhichisnotbeingprogram• SupportCommonFlashInterface(CFI)•Advancedsectorprotectionfunction(SolidandPasswordProtect)•StatusRegister(DataPolling/Toggle),ExtendedStatusRegister(volatilebit)andReady/Busypinmethodstodeterminedevicestatus

•Deeppowerdownmode

SINGLE VOLTAGE 3V ONLY FLASH MEMORY

7Rev. 1.3, July 05, 2018



HARDWARE FEATURES• Ready/Busy#(RY/BY#)Output -Providesahardwaremethodofdetectingprogramanderaseoperationcompletion• HardwareReset(RESET#)Input -Providesahardwaremethodtoresettheinternalstatemachinetoreadmode• WP#/ACCinputpin -Hardwarewriteprotectpin/Providesacceleratedprogramcapability•BYTE#inputpin-Selects8bitsor16bitsmode

PACKAGE• 56-PinTSOP• 64-BallLFBGA(11mmx13mm)• All devices are RoHS Compliant and Halogen-free

8Rev. 1.3, July 05, 2018



2. PIN CONFIGURATION

56 TSOP

64 LFBGA

A B C D E F G H

NC8

7

6

5

4

3

2

1

A22 A23 VI/O A25*A24 NC

A13 A12 A14 A15 A16 BYTE# Q15/A-1

A9 A8 A10 A11 Q7 Q14 Q13 Q6

WE# A21 A19RES-ET#

Q5 Q12 VCC Q4

WP#/ACC

A18 A20 Q2 Q10 Q11RY/BY#

A7 A17 A6 A5 Q0 Q8 Q9 Q1

Q3

A3 A4 A2 A1 A0 CE# OE# GND

GND

GND

NC NC NC NC NC VI/O NC NC

A23A22A15A14A13A12A11A10

A9A8

A19A20

WE#RESET#

A21WP#/ACC

RY/BY#A18A17

A7A6A5A4A3A2A1NCNC

12345678910111213141516171819202122232425262728

A24A25, NC for MX29GL512GA16BYTE#GNDQ15/A-1Q7Q14Q6Q13Q5Q12Q4VCCQ11Q3Q10Q2Q9Q1Q8Q0OE#GNDCE#A0NCVI/O

56555453525150494847464544434241403938373635343332313029

Note:*G8(A25)isNCforMX29GL512G

Top View

Top View

9Rev. 1.3, July 05, 2018



3. PIN DESCRIPTIONSYMBOL PIN NAME

A0~A25AddressInputA0~A24isforMX29GL512GA0~A25isforMX68GL1G0G

Q0~Q14 DataInputs/OutputsQ15/A-1 Q15(WordMode)/LSBaddr(ByteMode)

CE# ChipEnableInputWE# WriteEnableInputOE# OutputEnableInput

RESET# HardwareResetPin,ActiveLow

WP#/ACC* HardwareWriteProtect/ProgramAccelerationinput

RY/BY# Ready/BusyOutputBYTE#* Selects8bitsor16bitsmode

VCC +3.0VsinglepowersupplyGND DeviceGroundNC PinNotConnectedInternally

VI/O PowerSupplyforInput/Output

LOGIC SYMBOL

16 or 8Q0-Q15

(A-1)

RY/BY#

A0-A25

CE#

OE#

WE#

RESET#

WP#/ACC

BYTE#

VI/O

26

*Note:WP#/ACCandBYTE#hasinternalpullup.

10Rev. 1.3, July 05, 2018



4. BLOCK DIAGRAM

CONTROLINPUTLOGIC

PROGRAM/ERASE

HIGH VOLTAGE

WRITE

STATE

MACHINE

(WSM)

STATE

REGISTERFLASHARRAY

X-D

EC

OD

ER

ADDRESS

LATCH

AND

BUFFER Y-PASS GATE

Y-DE

CO

DE

R

ARRAYSOURCE

HVCOMMANDDATA

DECODER

COMMAND

DATA LATCH

I/O BUFFER

PGMDATA

HV

PROGRAMDATA LATCH

SENSEAMPLIFIER

Q0-Q15/A-1

A0-AM

AM: MSB address

CE#OE#WE#

RESET#BYTE#

WP#/ACC

11Rev. 1.3, July 05, 2018



5. BLOCK DIAGRAM DESCRIPTION The"4. BLOCK DIAGRAM"illustratesasimplifiedarchitectureofthisdevice.Eachblockintheblockdiagramrepresentsoneormorecircuitmodulesintherealchipusedtoaccess,erase,program,andreadthememoryarray.

The"CONTROLINPUTLOGIC"blockreceivesinputpinsCE#,OE#,WE#,RESET#,BYTE#,andWP#/ACC.Itcreatesinternaltimingcontrolsignalsaccordingtotheinputpinsandoutputstothe"ADDRESSLATCHANDBUFFER"tolatchtheexternaladdresspinsA0-AM(AM=A24isforMX29GL512G,AM=A25isforMX68GL1G0G).Theinternaladdressesareoutputfromthisblocktothemainarrayanddecoderscomposedof"X-DECODER","Y-DECODER","Y-PASSGATE",AND"FLASHARRAY".TheX-DECODERdecodestheword-linesoftheflasharray,whiletheY-DECODERdecodesthebit-linesoftheflasharray.Thebitlinesareelectricallyconnectedtothe"SENSEAMPLIFIER"and"PGMDATAHV"selectivelythroughtheY-PASSGATES.SENSEAMPLIFIERSareusedtoreadoutthecontentsoftheflashmemory,whilethe"PGMDATAHV"blockisusedtoselectivelydeliverhighpowertobit-linesduringprogramming.The"I/OBUFFER"controlstheinputandoutputontheQ0-Q15/A-1pads.Duringreadoperation,theI/OBUFFERreceivesdatafromSENSEAMPLIFIERSanddrivestheoutputpadsaccordingly.Inthelastcycleofprogramcommand,theI/OBUFFERtransmitsthedataonQ0-Q15/A-1to"PROGRAMDATALATCH",whichcontrolsthehighpowerdriversin"PGMDATAHV"toselectivelyprogramthebitsinawordorbyteaccordingtotheuserinputpattern.

The"PROGRAM/ERASEHIGHVOLTAGE"blockcomprisesthecircuitstogenerateanddeliverthenecessaryhighvoltagetotheX-DECODER,FLASHARRAY,and"PGMDATAHV"blocks.Thelogiccontrolmodulecomprisesofthe"WRITESTATEMACHINE,WSM","STATEREGISTER","COMMANDDATADECODER",and"COMMANDDATALATCH".WhentheuserissuesacommandbytogglingWE#,thecommandonQ0-Q15/A-1islatchedintheCOMMANDDATALATCHandisdecodedbytheCOMMANDDATADECODER.TheSTATEREGISTERreceivesthecommandandrecordsthecurrentstateofthedevice.TheWSMimplementstheinternalalgorithmsforprogramoreraseaccordingtothecurrentcommandstatebycontrollingeachblockintheblockdiagram.

ARRAY ARCHITECTURE ThemainflashmemoryarraycanbeorganizedasBytemode(x8)orWordmode(x16).Thedetailsoftheaddressrangesandthecorrespondingsectoraddressesareshownin"6. BLOCK STRUCTURE".

12Rev. 1.3, July 05, 2018



6. BLOCK STRUCTURE

Table 1. MX29GL512G SECTOR ARCHITECTURE

Sector SizeSector Sector Address

A24-A16Address Range

(x16)Kbytes Kwords128 64 SA0 000000000 0000000h-000FFFFh128 64 SA1 000000001 0010000h-001FFFFh128 64 SA2 000000010 0020000h-002FFFFh

::

::

::

::

::

128 64 SA511 111111111 1FF0000h-1FFFFFFh

Sector SizeSector Sector Address

A25-A16Address Range

(x16)Kbytes Kwords128 64 SA0 0000000000 0000000h-000FFFFh128 64 SA1 0000000001 0010000h-001FFFFh128 64 SA2 0000000010 0020000h-002FFFFh

::

::

::

::

::

128 64 SA1023 1111111111 3FF0000h-3FFFFFFh

Table 2. MX68GL1G0G SECTOR ARCHITECTURE

13Rev. 1.3, July 05, 2018



Table 3. BUS OPERATION

Notes:1.ThefirstorlastsectorwasprotectedifWP#/ACC=Vil.2. WhenWP#/ACC=Vih,theprotectionconditionsoftheoutmostsectordependsonpreviousprotection

conditions.Refertotheadvancedprotectfeature.3. Q0~Q15areinput(DIN)oroutput(DOUT)pinsaccordingtotherequestsofcommandsequence,sector

protection,ordatapollingalgorithm.4. InWordMode(Byte#=Vih),theaddressesareAMtoA0,AM:MSBofaddress. InByteMode(Byte#=Vil),theaddressesareAMtoA-1(Q15),AM:MSBofaddress.

Mode Select RE- SET# CE# WE# OE# Address

(Note4)

Data I/O

Q7~Q0

Byte#WP#/ ACC

Vil VihData (I/O) Q15~Q8

DeviceReset L X X X X HighZ HighZ HighZ L/H

StandbyMode Vcc±0.3V

Vcc±0.3V X X X HighZ HighZ HighZ H

OutputDisable H L H H X HighZ HighZ HighZ L/H

Read Mode H L H L AIN DOUT Q8-Q14=HighZ,

Q15=A-1

DOUT L/H

Write H L L H AIN DIN DIN Note1,2

AccelerateProgram H L L H AIN DIN DIN Vhv

7. BUS OPERATION

14Rev. 1.3, July 05, 2018



8. FUNCTIONAL OPERATION DESCRIPTION

8-1. READ OPERATION Toperformareadoperation,thesystemaddressesthedesiredmemoryarrayorstatusregisterlocationbyprovidingitsaddressontheaddresspinsandsimultaneouslyenablingthechipbydrivingCE#&OE#LOW,andWE#HIGH.AftertheTceandToetimingrequirementshavebeenmet,thesystemcanreadthecontentsoftheaddressedlocationbyreadingtheData(I/O)pins.IfeithertheCE#orOE#isheldHIGH,theoutputswillremaintri-statedandnodatawillappearontheoutputpins.

8-2. PAGE READ

ThisdeviceisabletoconductMacronixcompatiblehighperformancepageread.Pagesizeis32bytesor16words.ThehigheraddressAmax~A4selectthecertainpage,whileA3~A0forwordmode,A3~A-1forbytemodeselecttheparticularwordorbyteinapage.ThepageaccesstimeisTaaorTce,followingbyTpafortherestofthepagereadtime.WhenCE#toggles,accesstimeisTaaorTce.Pagemodecanbeturnedonbykeeping"page-readaddress"constantandchangingthe"intra-readpage"addresses.

8-3. WRITE OPERATION

Toperformawriteoperation,thesystemprovidesthedesiredaddressontheaddresspins,enablesthechipbyassertingCE#LOW,anddisablestheData(I/O)pinsbyholdingOE#HIGH.ThesystemthenplacesdatatobewrittenontheData(I/O)pinsandpulsesWE#LOW.ThedevicecapturestheaddressinformationonthefallingedgeofWE#andthedataontherisingedgeofWE#.Toseeanexample,pleaserefertothetimingdiagramin "Figure 18. COMMAND WRITE TIMING WAVEFORM (WE# CONTROLLED)".Thesystemisnotallowedtowriteinvalidcommands(commandsnotdefinedinthisdatasheet)tothedevice.Writinganinvalidcommandmayputthedeviceinanundefinedstate.

8-4. DEVICE RESET

DrivingtheRESET#pinLOWforaperiodofTrpormorewillreturnthedevicetoReadmode.Ifthedeviceisinthemiddleofaprogramoreraseoperation,theresetoperationwilltakeatmostaperiodofTready1beforethedevicereturnstoReadmode.UntilthedevicedoesreturnstoReadmode,theRY/BY#pinwillremainLow(BusyStatus).

WhentheRESET#pinisheldatGND±0.3V,thedeviceonlyconsumesstandby(Isbr)current.However,thedevicedrawslargercurrentiftheRESET#pinisheldatavoltagegreaterthanGND+0.3VandlessthanorequaltoVil.

ItisrecommendedtotiethesystemresetsignaltotheRESET#pinoftheflashmemory.Thisallowsthedevicetoberesetwiththesystemandputsitinastatewherethesystemcanimmediatelybeginreadingbootcodefromit.

8-5. STANDBY MODE

ThedeviceentersStandbymodewhenevertheRESET#andCE#pinsarebothheldHighexceptintheembeddedmode.Whileinthismode,WE#andOE#willbeignored,allDataOutputpinswillbeinahighimpedancestate,andthedevicewilldrawminimal(Isb)current.

15Rev. 1.3, July 05, 2018



8-6. OUTPUT DISABLE

Whileinactivemode(RESET#HIGHandCE#LOW),theOE#pincontrolsthestateoftheoutputpins.IfOE#isheldHIGH,allData(I/O)pinswillremaintri-stated.IfheldLOW,theByteorWordData(I/O)pinswilldrivedata.

8-7. BYTE/WORD SELECTION

TheBYTE#inputpinisusedtoselecttheorganizationofthearraydataandhowthedataisinput/outputontheData(I/O)pins.IftheBYTE#pinisheldHIGH,Wordmodewillbeselectedandall16datalines(Q0toQ15)willbeactive.

IfBYTE#isforcedLOW,BytemodewillbeactiveandonlydatalinesQ0toQ7willbeactive.DatalinesQ8toQ14willremaininahighimpedancestateandQ15becomestheA-1addressinputpin.

8-8. HARDWARE WRITE PROTECT

BydrivingtheWP#/ACCpinLOW.Thehighestorlowestwasprotectedfromallerase/programoperations.IfWP#/ACCisheldHIGH(VihtoVCC),thesesectorsreverttotheirpreviouslyprotected/unprotectedstatus.

8-9. ACCELERATED PROGRAM OPERATION

Byapplyinghighvoltage(Vhv)totheWP#/ACCpin,thedevicewillentertheAcceleratedProgrammode.Thismodepermitsthesystemtoskipthenormalcommandunlocksequencesandprogrambyte/wordlocationsdirectly.Duringacceleratedprogram,thecurrentdrawnfromtheWP#/ACCpinisnomorethanIcp1.

8-10. WRITE BUFFER PROGRAM OPERATION

Programs256wordinwordmodeprogramand256byteinbytemodeprogramoperation.TotriggertheWriteBufferProgram,startbythefirsttwounlockcycles,thenthirdcyclewritestheWriteBufferLoadcommandatthedestinedprogramSectorAddress.Theforthcyclewritesthe"wordlocationssubtractone"number.

Followingaboveoperations,systemstartstowritetheminglingofaddressanddata.Aftertheprogrammingofthefirstaddressordata,the"write-buffer-page"isselected.Thefollowingdatashouldbewithintheabovementionedpage.

The"write-buffer-page"isselectedbychoosingaddressAmax~A8.

"Write-Buffer-Page"addresshastobethesameforalladdress/datawriteintothewritebuffer.Ifnot,operationwill ABORT.

ToprogramthecontentofthewritebufferpagethiscommandmustbefollowedbyawritetobufferProgramconfirmcommand.

Theoperationofwrite-buffercanbesuspendedorresumedbythestandardcommands,oncethewritebufferprogramoperationisfinished,it’llreturntonormalREADmode.

16Rev. 1.3, July 05, 2018



ABORTwillbeexecutedfortheWriteBufferProgramSequenceiffollowingconditionoccurs:• Thevalueloadedisbiggerthanthepagebuffersizeduring"NumberofLocationstoProgram"• AddresswritteninasectorisnotthesameastheoneassignedduringtheWrite-Buffer-Loadcommand.• Address/Datapairwrittentoadifferentwrite-buffer-pagethantheoneassignedbythe"StartingAddress"

duringthe"writebufferdataloading"operation.• Writingnot"ConfirmCommand"aftertheassignednumberof"dataload"cycles.

AtWriteBufferAbortmode,thestatusregisterwillbeQ1=1,Q7=DATA#(lastaddresswritten),Q6=toggle.AWrite-to-Buffer-AbortResetcommandsequencehastobewrittentoresetthedeviceforthenextoperation.

Writebufferprogramcanbeconductedinanysequence.HowevertheCFIfunctions,autoselect,Securitysectorarenotfunctionalwhenprogramoperationisinprogress.Multiplewritebufferprogramoperationsonthesamewritebufferaddressrangewithoutinterveningerasesisavailable.Anybitinawritebufferaddressrangecan’tbeprogrammedfrom0backto1.

Figure 1. WRITE BUFFER PROGRAM FLOWCHART

Write CMD: Data=AAh, Addr=555h

Write CMD: Data=55h, Addr=2AAh

Write CMD: Data=25h, Addr=SA

SA: Sector Address of to be Programmed page

Write CMD: Data=PWC, Addr=SA

PWC: Program Word Count

Write CMD:Data=PGM_data, Addr=PGM_addr

PWC =0?

Write CMD: Data=29h, Addr=SA

Yes

Pass

No

No

Write Buffer Abort

Write reset CMD to return to read Mode

PWC=PWC-1 NoFail

YesWant to Abort ?

Yes

NoNo

Yes

Return to read Mode

Write Abort reset CMD to return to read Mode

Write a different sector address to cause Abort

Yes

Status Checking(Data # Polling or Extended

Status Register Method)

17Rev. 1.3, July 05, 2018



8-11. SECTOR PROTECT OPERATION

Thedeviceprovidesuserprogrammableprotectionoperationsforselectedsectors.Pleasereferto"6. BLOCK STRUCTURE" whichshowallSectorassignments.

Duringtheprotectionoperation,thesectoraddressofanysectormaybeusedtospecifythesectorbeingprotected.

8-12. AUTOMATIC SELECT OPERATIONS

AutomaticSelectmodeisusedtoaccessthemanufacturerID,deviceIDandCFIcode.Theautomaticselectmodehasfourcommandcycles.Thereare2methodstoenterautomaticselectmode,usercanissuestheautoselectcommandsorappliesthehighvoltageontheA9pin.PleaseseeAUTOMATICSELECTOPERATIONSintheCOMMANDOPERATIONSsection.

8-13. INHERENT DATA PROTECTION

Toavoidaccidentaleraseorprogramofthedevice,thedeviceisautomaticallyresettoReadmodeduringpowerup.Additionally,thefollowingdesignfeaturesprotectthedevicefromunintendeddatacorruption.

8-14. COMMAND COMPLETION

Onlyafterthesuccessfulcompletionofthespecifiedcommandsetswillthedevicebeginitseraseorprogramoperation.Thefailureinobservingvalidcommandsetswillresultinthememoryreturningtoreadmode.

8-15. LOW VCC WRITE INHIBIT

ThedevicerefusestoacceptanywritecommandwhenVccislessthanVLKO.Thispreventsdatafromspuriouslybeingalteredduringpower-up,power-down,ortemporarypowerinterruptions.ThedeviceautomaticallyresetsitselfwhenVccislowerthanVLKOandwritecommandsareignoreduntilVccisgreaterthanVLKO.ThesystemmustprovidepropersignalsoncontrolpinsafterVccrisesaboveVLKOtoavoidunintentionalprogramoreraseoperations.

8-16. WRITE PULSE "GLITCH" PROTECTION

CE#,WE#,OE#pulsesshorterthan5nsaretreatedasglitchesandwillnotberegardedasaneffectivewritecycle.

8-17. LOGICAL INHIBIT

AvalidwritecyclerequiresbothCE#andWE#atVilwithOE#atVih.WritecycleisignoredwheneitherCE#atVih,WE#atVih,orOE#atVil.

18Rev. 1.3, July 05, 2018



8-18. POWER-UP SEQUENCE

Uponpowerup,thedeviceisplacedinReadmode.Furthermore,programoreraseoperationwillbeginonlyaftersuccessfulcompletionofspecifiedcommandsequences.

8-19. POWER-UP WRITE INHIBIT

WhenWE#,CE#isheldatVilandOE#isheldatVihduringpowerup,thedeviceignoresthefirstcommandontherisingedgeofWE#.

8-20. POWER SUPPLY DECOUPLING

A0.1uFcapacitorshouldbeconnectedbetweentheVccandGNDtoreducethenoiseeffect.

19Rev. 1.3, July 05, 2018



9. COMMAND OPERATIONS

9-1. READING THE MEMORY ARRAY Readmodeisthedefaultstateafterpoweruporafteraresetoperation.Toperformareadoperation,pleaserefertoREADOPERATIONintheBUSOPERATIONSsectionabove.

IfthedevicereceivesanEraseSuspendcommandwhileintheSectorErasestate,theeraseoperationwillpause(afteratimedelaynotexceedingTeslperiod)andthedevicewillenterErase-SuspendedReadmode.WhileintheErase-SuspendedReadmode,datacanbeprogrammedorreadfromanysectornotbeingerased.Readingfromaddresseswithinsector(s)beingerasedwillonlyreturnthecontentsofthestatusregister,whichisinfacthowthecurrentstatusofthedevicecanbedetermined.

Ifaprogramcommandisissuedtoanyinactive(notcurrentlybeingerased)sectorduringErase-SuspendedReadmode,thedevicewillperformtheprogramoperationandautomaticallyreturntoErase-SuspendedReadmodeaftertheprogramoperationcompletessuccessfully.

WhileinErase-SuspendedReadmode,anEraseResumecommandmustbeissuedbythesystemtoreactivatetheeraseoperation.TheeraseoperationwillresumefromwhereiswassuspendedandwillcontinueuntilitcompletessuccessfullyoranotherEraseSuspendcommandisreceived.

Afterthememorydevicecompletesanembeddedoperation(automaticChipErase,SectorErase,orProgram)successfully,itwillautomaticallyreturntoReadmodeanddatacanbereadfromanyaddressinthearray.Iftheembeddedoperationfailstocomplete,asindicatedbystatusregisterbitQ5(exceedstimelimitflag)goingHIGHduringtheoperations,thesystemmustperformaresetoperationtoreturnthedevicetoReadmode.

ThereareseveralstatesthatrequirearesetoperationtoreturntoReadmode:

1.Aprogramorerasefailure--indicatedbystatusregisterbitQ5goingHIGHduringtheoperation.FailuresduringeitherofthesestateswillpreventthedevicefromautomaticallyreturningtoReadmode.

2.ThedeviceisinAutoSelectmodeorCFImode.Thesetwostatesremainactiveuntiltheyareterminatedbyaresetoperation.

Inthetwosituationsabove,ifaresetoperation(eitherhardwareresetorsoftwareresetcommand)isnotperformed,thedevicewillnotreturntoReadmodeandthesystemwillnotbeabletoreadarraydata.

9-2. AUTOMATIC PROGRAM OF THE MEMORY ARRAY

ThedeviceprovidestheusertheabilitytoprogramthememoryarrayinBytemodeorWordmode.Aslongastheusersentersthecorrectcycledefinedinthe"Table 9. COMMAND DEFINITIONS"(including2unlockcyclesandtheA0Hprogramcommand),anybyteorworddataprovidedonthedatalinesbythesystemwillautomaticallybeprogrammedintothearrayatthespecifiedlocation.

Aftertheprogramcommandsequencehasbeenexecuted,theinternalwritestatemachine(WSM)automaticallyexecutesthealgorithmsandtimingsnecessaryforprogramandverification,whichincludesgeneratingsuitableprogrampulses,checkingcellthresholdvoltagemargins,andrepeatingtheprogrampulseifanycellsdonotpassverificationorhavelowmargins.Theinternalcontrollerprotectscellsthatdopassverificationandmargintestsfrombeingover-programmedbyinhibitingfurtherprogrampulsestothesepassingcellsasweakercellscontinuetobeprogrammed.

WiththeinternalWSMautomaticallycontrollingtheprogramprocess,theuseronlyneedstoentertheprogramcommandanddataonce.

20Rev. 1.3, July 05, 2018



Programwillonlychangethebitstatusfrom"1"to"0".Itisnotpossibletochangethebitstatusfrom"0"to"1"byprogram.Thiscanonlybedonebyaneraseoperation.Furthermore,theinternalwriteverificationonlychecksanddetectserrorsincaseswherea"1"isnotsuccessfullyprogrammedto"0".

Anycommandswrittentothedeviceduringprogrammingwillbeignoredexcepthardwareresetorprogramsuspend.Hardwareresetwillterminatetheprogramoperationafteraperiodoftimenomorethan10us.Whentheembeddedprogramalgorithmiscompleteortheprogramoperationisterminatedbyahardwarereset,thedevicewillreturntoReadmode.Programsuspendready,thedevicewillenterprogramsuspendreadmode.

Pleaserefertothefollowingfigureforautomaticprogrammingflowchart.

Aftertheembeddedprogramoperationhasbegun,theusercancheckforcompletionbyreadingthefollowingbitsinthestatusregister.

Figure 2. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Program Data/Address

Write Data A0H Address 555H

YES

Verify Data = Program Data?

YES

Auto Program Completed

Data# Polling or Toggle Bit or Extended Status Register

Methodnext address

Last Word to beProgramed

No

No

21Rev. 1.3, July 05, 2018



9-3. ERASING THE MEMORY ARRAY

Therearetwotypesoferaseoperationsperformedonthememoryarray--SectorEraseandChipErase.IntheSectorEraseoperation,theselectedsectorshallbeerased.IntheChipEraseoperation,thecompletememoryarrayiserasedexceptforanyprotectedsectors.MoredetailsoftheprotectedsectorsareexplainedinSection"9-17. ADVANCED SECTOR PROTECTION/UNPROTECTION".

9-4. SECTOR ERASE

Thesectoreraseoperationisusedtocleardatawithinasectorbyreturningallofitsmemorylocationstothe"1"state.Itrequiressixcommandcyclestoinitiatetheeraseoperation.Thefirsttwocyclesare"unlockcycles",thethirdisaconfigurationcycle,thefourthandfiftharealso"unlockcycles",andthesixthcycleistheSectorErasecommand.

Aftertheembeddedsectoreraseoperationbegins,allcommandsexceptEraseSuspendandExtendedStatusRegisterReadwillbeignored.TheonlywaytointerrupttheoperationiswithanEraseSuspendcommandorwithahardwarereset.ThehardwareresetwillcompletelyaborttheoperationandreturnthedevicetoReadmode.Pleaserefertothefollowingfigureforsectoreraseflowchart.

22Rev. 1.3, July 05, 2018



Figure 3. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

START




Write Data 80H Address 555H

Write Data 30H Sector Address


Data# Polling or Toggle Bit or Extended Status Register Algorithm

Auto Sector Erase Completed

YES

NOData=FFh

Thesystemcandeterminethestatusoftheautomaticsectoreraseoperationbythestatusregister,seetheSTATUSREGISTERforthedetails.

23Rev. 1.3, July 05, 2018



9-5. CHIP ERASE

TheChipEraseoperationisusederaseallthedatawithinthememoryarray.Allmemorycellscontaininga"0"willbereturnedtotheerasedstateof"1".Thisoperationrequires6writecyclestoinitiatetheaction.Thefirsttwocyclesare"unlock"cycles,thethirdisaconfigurationcycle,thefourthandfiftharealso"unlock"cycles,andthesixthcycleinitiatesthechiperaseoperation.

Duringthechiperaseoperation,noothersoftwarecommandswillbeaccepted,butifahardwareresetisreceivedortheworkingvoltageistoolow,thatchiperasewillbeterminated.AfterChipErase,thechipwillautomaticallyreturntoReadmode.Seefollowingfigureforchiperaseflowchart.

Thesystemcandeterminethestatusoftheembeddedchiperaseoperationbythestatusregister,seetheSTATUSREGISTERforthedetails.

Figure 4. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

START





Yes

YesPass



Data# Polling or Erase Status Checking orExtended Status Register Method

Chip Erase Failed Write reset CMD to return to read mode

Fail

No

No

Chip Erase CompletedReturn to read mode

24Rev. 1.3, July 05, 2018



9-6. ERASE SUSPEND/RESUME

Afterbeginningasectoreraseoperation,EraseSuspendandreadExtendedStatusRegisterarethevalidcommandsthatmaybeissued.IfthesystemissuesanEraseSuspendcommandafterthesectoreraseoperationhasalreadybegun,thedevicewillnotenterErase-SuspendedReadmodeuntilTeslperiodhaselapsed.ThesystemcandetermineifthedevicehasenteredtheErase-SuspendedReadmodethroughQ6,Q7,andRY/BY#ofStatusRegisterorExtendedStatusRegister.

AfterthedevicehasenteredErase-SuspendedReadmode,thesystemcanreadorprogramanysector(s)exceptthissuspendedsector.Readingthissectorbeingerasedwillreturnthecontentsofstatusregister.Wheneverasuspendcommandisissued,usermustissuearesumecommandandcheckQ6togglebitstatus,beforeissueanothererasecommand.Seefollowingfigureforerasesuspend/resumeflowchart.

9-7. SECTOR ERASE RESUME

ThesectorEraseResumecommandisvalidonlywhenthedeviceisinErase-SuspendedReadmode.Aftereraseresumes,theusercanissueanotherEaseSuspendcommand,butthereshouldbeaTersintervalbe-tweenEaseResumeandthenextEraseSuspendcommand.

9-8. PROGRAM SUSPEND/RESUME

Afterbeginningaprogramoperation,ProgramSuspendandreadExtendedStatusRegisterarethevalidcommandsthatmaybeissued.IfthesystemissuesanProgramSuspendcommandaftertheprogramoperationhasalreadybegun,thedevicewillnotenterProgram-SuspendedReadmodeuntilTpslperiodhaselapsed.ThesystemcandetermineifthedevicehasenteredtheProgram-SuspendedReadmodethroughQ6andRY/BY#ofStatusRegisterorExtendedStatusRegister.

AfterthedevicehasenteredProgram-Suspendedmode,thesystemcanreadanysector(s)exceptthosebeingprogrammedbythesuspendedprogramoperation.Readingthesectorbeingprogramsuspendedisinvalid.Wheneverasuspendcommandisissued,usermustissuearesumecommandandcheckQ6togglebitstatus,beforeissueanotherprogramcommand.Thesystemcanusethestatusregisterbitsshowninthefollowingtabletodeterminethecurrentstateofthedevice,seetheSTATUSREGISTERforthedetails.

WhenthedevicehasProgram/Erasesuspended,usercanexecutereadarray,auto-select,readCFI,readsecuritysector.

9-9. PROGRAM RESUME

TheProgramResumecommandisvalidonlywhenthedeviceisinProgram-Suspendedmode.Afterprogramresumes,theusercanissueanotherProgramSuspendcommand,butthereshouldbeaTprsintervalbetweenProgramResumeandthenextProgramSuspendcommand.

25Rev. 1.3, July 05, 2018



Figure 5. PROGRAM/ERASE SUSPEND/RESUME ALGORITHM FLOWCHART

START

Write Data B0H

Toggle Bit checking Q6 not toggled

PROGRAM/ERASE SUSPEND

YES

NO

Write Data 30H

Continue Erase

Reading or Programming End

Read Array orProgram

AnotherErase Suspend ?

NO

YES

YES

NO

PROGRAM/ERASE RESUME

Thesystemcanusethestatusregisterbitsshowninthefollowingtabletodeterminethecurrentstateofthedevice,seetheSTATUSREGISTERforthedetails.

Whenthedevicehassuspendederasing,usercanexecutethecommandsetsexceptsectoreraseandchiperase,suchasAutomaticselect,program,CFIqueryanderaseresume.

9-10. BLANK CHECK

BlankCheckcommandcancheckiftheeraseoperationworkscorrectlyintheselectedsector.DuringtheBlankCheck,arrayreadoperationwillreturnthecontentsofstatusregister.

Writedata33htoaddress555hintothesectortostarttheBlankCheck.

Inthefollowingoperations,BlankCheckmaynotbewrittensuccessfully: 1.program 2.erase 3.suspend

DeviceReady(bit7)ofExtendedStatusRegisterorStatusRegistercandisplayiftheBlankCheckisinprogressornot.Erasestatus(bit5)oftheExtendedStatusRegisterorStatusRegistercandisplaytheblankcheckresult.

26Rev. 1.3, July 05, 2018



9-11. BUFFER WRITE ABORT

StatusregisterQ1istheindicatorofBufferWriteAbort.WhenQ1=1,thedevicewillabortfrombufferwriteandgobacktoread,seeWRITEBUFFERPROGRAMMINGOPERATIONforthedetails.

9-12. PROGRAM/ERASE STATUS CHECKING METHOD

Whenthedeviceprogram/eraseoperationisinprogress,eitherthe"PollingMethod","ToggleBitMethod"orExtendedStatusRegister"maybeusedtomonitortheoperation:

9-12-1. Polling Method:

ThepollingmethodchecksQ7(datacomplementbit)andQ5(timeoutbit)valuesduringtheoperation.Aftertheoperationhasfisnished,Q7willoutputtruedata.Seethefollowingfiguresforthewordprogram/eraseandwritebufferprogramflowchartrespectively.

Figure 6. STATUS POLLING FOR WORD PROGRAM/ERASE

Read Q7~Q0 at valid address(Note 1)

Read Q7~Q0 at valid address

Start

Q7 = Data# ?

Q5 = 1 ?

Q7 = Data# ?(Note 2)

FAIL Pass

No

No

No

Yes

Yes

Yes

Notes: 1.Forprogram,validaddressmeansprogramaddress.Forerasing,validaddressmeanserasesectorsaddress.2.Q7shouldberecheckedevenQ5="1"becauseQ7maychangesimultaneouslywithQ5.

27Rev. 1.3, July 05, 2018



Figure 7. STATUS POLLING FOR WRITE BUFFER PROGRAM

Read Q7~Q0 at last writeaddress (Note 1)

Start

Q7 = Data# ?

Q1=1 ?Only for write

buffer program


FAIL Pass

Write Buffer Abort

No

No

No

No

No

Yes

Yes

Q5=1 ?

Yes

Yes

Yes




Notes:1.Forwritetobufferprogramming,validaddressmeanslastwriteaddress.2.Q7shouldberecheckedevenQ5="1"becauseQ7maychangesimultaneouslywithQ5.

28Rev. 1.3, July 05, 2018



9-12-2. Toggle Bit Method:

ThetogglebitmethodchecksQ6(togglebit)valueduringtheoperation.Aftertheoperationhasfisnished,Q6willstoptoggling.Pleaserefertothefollowingfigureforthetogglebitflowchart.

Figure 8. TOGGLE BIT ALGORITHM

Notes:1.RepeatQ7~Q0readcommand2timestoverifytogglingstatus.2.Q6maystoptogglingwhenQ5switchesto"1",needtoverifytogglingstatusonceagain.

PGM/ERS Complete

Start

Read Q7-Q0 2 times (Note 1)

Q6 Toggle? Read Q7-Q0 2 times (Note 2)

PGM/ERS fail Write Reset CMDQ6 Toggle?Q5=1?

NoNo

No

YesYes Yes

9-12-3. Extended Status Register

ExtendedStatusRegisterisa16-bitsregister,whichcontainstheprogramanderasestatus.Thesebitsindicatewhetherthespecificoperationshascompletedsuccessfullythroughthefollowingbits:

•EraseStatus(bit5),•ProgramStatus(bit4),•WriteBufferAbortStatus(bit3),•SectorLockedStatus(bit1)

29Rev. 1.3, July 05, 2018



ExtendedStatusRegistercanalsorefertowhetherthecurrentstatusisinprocess,suspended,orcompletedthrough:•DeviceReady(bit7),•EraseSuspendedStatus(bit6)•ProgramSuspendedStatus(bit2)

Bits15:8andbits0arereservedandmustberegardedasdon'tcarefromanysoftwarereadingstatus.PleaserefertoExtendedStatusRegisterTableforfurtherinformation.

Table 4. EXTENDED STATUS REGISTER

Notes:1. Whileanyoperationisinprogress,Bit7=0(busy).Bits6thru1areinvalidwhilebit7=02. UsermustreadstatuscontinuouslyuntilDRB(DeviceReady)becomesready(=1)beforeissuingtheErase

SuspendorProgramSuspendCommand.3. EraseResumeCommandwillclearESSB(EraseSuspendStatus)to0.ProgramResumeCommandwill

clearPSSB(ProgramSuspendStatus)to0.4. ProgramonerasesuspendedsectorwillresultinProgramfail(PSB[ProgramStatus]=1).5. SLSB(SectorLockStatus)representsthestatusofprogramoreraseoperation.WhileSLSB=1,itindicates

thataprogramoreraseoperationhasfailedsincethesectorwaslocked.

Bit# 15:8 7 6 5 4 3 2 1 0

Description ReservedDRB

(DeviceReady)

ESSB (EraseSuspendStatus)

ESB (EraseStatus)

PSB (ProgramStatus)

WBASB (Write

BufferAbortStatus)

PSSB (ProgramSuspendStatus)

SLSB (SectorLockStatus)

Reserved

ResetStatus X 1 0 0 0 0 0 0 X

StatusDescription X 1=Ready,

0=Busy

0=No Erasein

Suspension1=EraseinSuspension

0=Erasesuccessful1=Erase

fail

0=Programsuccessful1=Program

fail

0=Programnotaborted1=Programabortedduring WritetoBuffer

command

0=No Programinsuspension1=Program

in suspension

0=Sectornotlocked

during operation1=Sectorlockederror

X

30Rev. 1.3, July 05, 2018



Figure 9. EXTENDED STATUS REGISTER FOR WRITE BUFFER PROGRAM

StartStart

Read Extended Status Register

DRB = 1

PSB = 1 Program Fail WBASB=1WBASB=1 SLSB=1SLSB=1

Program Completed

Program Aborted During Write to Buffer

Sector Locked Error Program Fail

Yes

No

No

No Yes

Yes

Yes

No

TheStatusinformationcouldberetrievedbyperformingtheReadExtendedStatusRegistercommandandafollowingreadoperation.WhenReadExtendedStatusRegisterCommandhasbeenwritten,thedevicecapturesthestatusinformationontherisingedgeofWE#,andthenplacesthestatusinformationinthedeviceaddresslocations.

TheClearExtendedStatusRegisterCommandorresetcommandwillcleartheseresultsrelatedExtendedStatusRegisterbits(bit5,bit4,bit3andbit1)to0withoutaffectingthecurrentstatebits(bit7,bit6,andbit2).

It'srecommendedtouseExtendedStatusRegisterinsteadofDataPollingStatusfeaturetodeterminedevicestatus.SeethefollowingfigurefortheWriteBufferProgramandsectoreraseflowchart.

Figure 10. EXTENDED STATUS REGISTER FOR SECTOR ERASE

StartStart

Read Extended Status Register

DRB = 1

ESB = 1 Erase Fail SLSB=1SLSB=1

Erase Completed

Sector Locked Error Erase Fail

Yes

No

No

No

Yes

Yes

31Rev. 1.3, July 05, 2018



9-13. STATUS REGISTER

Thehostsystemcanusethestatusregisterbitsshowninthefollowingtabletodeterminethecurrentstateofthedevice.

Status Q7 Q6 Q5 Q3 Q2 Q1 RY/BY#Automaticprogramming

Inprogress Q7# Toggle 0 N/A N/A 0 0Exceedtimelimit Q7# Toggle 1 N/A N/A N/A 0

SectoreraseInprogress 0 Toggle 0 1 Toggle N/A 0Exceedtimelimit 0 Toggle 1 1 Toggle N/A 0

ChiperaseInprogress 0 Toggle 0 N/A Toggle N/A 0Exceedtimelimit 0 Toggle 1 N/A Toggle N/A 0

Programsuspendread

programsuspendedsector Invalid 1non-programsuspendedsector Data 1

Erasesuspendreaderasesuspendedsector 1 No

toggle 0 N/A Toggle N/A 1

non-erasesuspendedsector Data 1Erasesuspendprograminnon-erasesuspendedsector Q7# Toggle 0 N/A N/A N/A 0

BufferWriteBusy Q7# Toggle 0 N/A N/A 0 0Abort Q7# Toggle 0 N/A N/A 1 0Exceedtimelimit Q7# Toggle 1 N/A N/A 0 0

Notes:1.RY/BY#isopendrainoutputpinandshouldbeconnectedtoVCCthroughahighvaluepull-upresistor.2.EraseSuspendandReadExtendedStatusRegisterarethevalidcommandsthatmaybeissuedoncethe

sectoreraseoperationisinprogress.3.RY/BY#isopendrainoutputpinandshouldbeconnectedtoVCCthroughahighvaluepull-upresistor.4.Whenanattemptismadetoeraseonlyprotectedsector(s),theeraseoperationwillabortthuspreventing

anydatachangesintheprotectedsector(s).Q7willoutput"0"andQ6willtogglebriefly(100usorless)beforeabortingandreturningthedevicetoReadmode.

5.Q2isalocalizedindicatorshowingaspecifiedsectorisundergoingeraseoperationornot.Q2toggleswhenuserreadsataddresseswherethesectorsareactivelybeingerased(inerasemode)ortobeerased(inerasesuspendmode).

Table 5. STATUS REGISTER

32Rev. 1.3, July 05, 2018



9-14. AUTOMATIC SELECT OPERATIONS

WhenthedeviceisinReadmode,ProgramSuspendedmode,Erase-SuspendedReadmode,orCFImode,theusercanissuetheAutomaticSelectcommandshownin"Table 9. COMMAND DEFINITIONS"(twounlockcyclesfollowedbytheAutomaticSelectcommand90h)toenterAutomaticSelectmode.AfterenteringAutomaticSelectmode,theusercanquerytheManufacturerID,DeviceID,SecuritySectorlockedstatus,orSectorprotectedstatusmultipletimeswithoutissuinganewAutomaticSelectcommand.

WhileInAutomaticSelectmode,issuingaResetcommand(F0h)willreturnthedevicetoReadmode(orEase-SuspendedReadmodeifErase-Suspendwasactive)orProgramSuspendedReadmodeifProgramSuspendwasactive.

Notes: Pagereadfeatureisnotsupport,whilereadaddress02horreadbetweenanyotherIDaddressesand02h.Afterenteringautomaticselectmode,noothercommandsareallowedexcepttheresetcommand.

Address (h) Data (h)Word Mode ByteMode

ManufacturerID 00 00 C2

DeviceID 01/0E/0F 02/1C/1EWord Mode ByteMode

512Mb1Gb

227E/2223/2201227E/2228/2201

7E/23/017E/28/01

SectorProtectVerify (Sectoraddress)02

(Sectoraddress)04

0:SectorUnprotected1:SectorProtected

SecuritySectorStatus 03 06

Bit15-Bit8=1(Reserved)Bit7:FactoryLockedArea

1=Locked,0=UnlockedBit6:CustomerLockedArea

1=Locked,0=UnlockedBit5=1(Reserved)Bit4:WP#Protects

0=lowestaddressSectorprotected1=highestaddressSectorprotected

Bit3-Bit0=1(Reserved)

CommandSetSupport 0C 18

Bit15-Bit4=0(Reserved)Bit3-Bit2:CommandSet

11/10=reserved,01=Shortversion,00=Fullversion

Bit1:Data#Polling1=support,0=notsupport

Bit0:ExtendedStatusRegister1=support,0=notsupport

9-14-1. AUTOMATIC SELECT COMMAND SEQUENCE

Theautomaticselectmodehasfourcommandcycles.Thefirsttwoareunlockcycles,andfollowedbyaspecificcommand.Thefourthcycleisanormalreadcycle,andusercanreadatanyaddressanynumberoftimeswithoutenteringanothercommandsequence.TheResetcommandisnecessarytoexittheAutomaticSelectmodeandbacktoreadarray.Thefollowingtableshowstheidentificationcodewithcorrespondingaddress.

Table 6. AUTOMATIC SELECT ID VALUE

33Rev. 1.3, July 05, 2018



Notes:1.Sectorunprotectedcode:00h.Sectorprotectedcode:01h.2.ThefactorylockstatusshouldbepresentedondatabitQ7,andcustomerlockstatusshouldbepresentedon

databitQ6,referTable6fordetailvalue.3.AM:MSBofaddress.4.Pagereadfeatureisnotsupportedinautomaticselecthighvoltageoperation.

Table 7. AUTOMATIC SELECT HIGH VOLTAGE OPERATION

ItemControl Input AM

to A12

A11 to

A10A9

A8 to A7

A6A5 to A4

A3 to A2

A1 A0 Q7 ~ Q0 Q15 ~ Q8CE# WE# OE#

SectorProtectVerify L H L SA X Vhv X L X L H L 01hor00h

(Note 1) X

SecuritySectorStatus L H L X X Vhv X L X L H H (Note 2) X

Read ManufacturerID L H L X X Vhv X L X L L L C2H X

ReadDeviceID--512Mb/1Gb

Cycle1 L H L X X Vhv X L X L L H 7EH 22H(Word),XXH(Byte)

Cycle2 L H L X X Vhv X L X H H L 23H 512Mb28H 1Gb

22H(Word),XXH(Byte)

Cycle3 L H L X X Vhv X L X H H H 01H 22H(Word),XXH(Byte)

9-14-2. AUTOMATIC SELECT HIGH VOLTAGE OPERATION

AnotherwaytoenterAutomaticSelectmodeistousehighvoltageoperationsasfollowingTable.Afterthehighvoltage(Vhv)isremovedfromtheA9pin,thedevicewillautomaticallyreturntoReadmodeorErase-SuspendedReadmode.

READ MANUFACTURER ID OR DEVICE ID

TheManufacturerID(identification)isauniquehexadecimalnumberassignedtoeachmanufacturerbytheJEDECcommittee.EachcompanyhasitsownmanufacturerID,whichisdifferentfromtheIDofallothercompanies.ThenumberassignedtoMacronixisC2h.

TodeterminetheManufacturerIDCode,thesystemperformsaREADOPERATIONwithA9raisedtoVhvandaddresspinsA6,A3,A2,A1,&A0heldLOW.TheMacronixIDcodeofC2hshouldbepresentedondatabitsQ7toQ0.

34Rev. 1.3, July 05, 2018



SECTOR LOCK STATUS VERIFICATION

Todeterminetheprotectedstateofanysectorusingbusoperations,thesystemperformsaREADOPERATIONwithA9raisedtoVhv,thesectoraddressappliedtothehighestaddresspinsA24/A25(512Mb/1Gb),addresspinsA6,A3,A2&A0heldLOW,andaddresspinA1heldHIGH.IfdatabitQ0isLOW,thesectorisnotprotected,andifQ0isHIGH,thesectorisprotected.

READ SECURITY SECTOR STATUS

TodetermineiftheSecuritySectorhasbeenlockedatthefactory,thesystemperformsaREADOPERATIONwithA9raisedtoVhv,addresspinA6,A3&A2heldLOW,andaddresspinsA1&A0heldHIGH.ThefactorylockstatusshouldbepresentedondatabitQ7,andcustomerlockstatusshouldbepresentedondatabitQ6,referTable4fordetailvalue.

9-15. COMMON FLASH MEMORY INTERFACE (CFI) QUERY COMMAND

ThedevicefeaturesCFImode.Hostsystemcanretrievetheoperatingcharacteristics,structureandvendor-specifiedinformationsuchasidentifyinginformation,memorysize,byte/wordconfiguration,operatingvoltagesandtiminginformationofthisdevicebyCFImode.IfthesystemwritestheCFIQuerycommand"98h",toaddress"55h"/"AAh"(dependingonWord/Bytemode),thedevicewillentertheCFIQueryMode,anytimethedeviceisreadytoreadarraydata.ThesystemcanreadCFIinformationattheaddressesgiveninTable 10 ~Table 13.

OnceuserentersCFIquerymode,usercanissueresetcommandtoexitCFImodeandreturntoreadarraymode.

9-16. RESET

Inthefollowingsituations,executingresetcommandwillresetdevicebacktoReadmode:

•Amongerasecommandsequence(beforethefullcommandsetiscompleted)•Sectorerasetime-outperiod•Erasefail(whileQ5ishigh)•Amongprogramcommandsequence(beforethefullcommandsetiscompleted,erase-suspendedprogram included)•Programfail(whileQ5ishigh,anderase-suspendedprogramfailisincluded)•Auto-selectmode•CFImode

Whiledeviceisatthestatusofprogramfailorerasefail(Q5ishigh),usermustissueresetcommandtoresetdevicebacktoreadarraymode.WhilethedeviceisinAuto-Selectmode,CFImode,usermustissueresetcommandtoresetdevicebacktoreadarraymode.

Whenthedeviceisintheprogressofprogramming(notprogramfail)orerasing(noterasefail),devicewillignoreresetcommand.

35Rev. 1.3, July 05, 2018



9-17. ADVANCED SECTOR PROTECTION/UNPROTECTION

Thereare twoways to implement softwareAdvancedSectorProtectionon this device:PasswordmethodorSolidmethods.Throughthesetwoprotectionmethods,usercandisableorenabletheprogrammingorerasingoperation toany individualsectoror thewholechip.Thefigurebelowhelps todescribeanoverviewof thesemethods.

ThedeviceisdefaulttotheSolidmode.Allsectorsaredefaultasunprotectedwhenshippedfromfactory.Thedetailedalgorithmofadvancesectorprotectionisshownasfollows:

Figure 11. ADVANCE SECTOR PROTECTION/UNPROTECTION SPB PROGRAM ALGORITHM

Start

Q1=0 Q2=0

Password Protection Mode

To chooseprotection mode

set lock register bit(Q1/Q2)

SPB Lock bit UnlockedAll SPBs are changeable

Solid write Protect bit (SPB)

SPB=0 sector protect

SPB=1 sector unprotect

Temporary Unprotect SPB bit (USPB)

USPB=0 SPB bit is disabled

USPB=1 SPB bit is enabled

USPB 0

USPB 1

USPB 2

::

USPB N-1

USPB N

SPB 0

SPB 1

SPB 2

::

SPB N-1

SPB N

SA 0

SA 1

SA 2

::

SA N-1

SA N

DPB 0

DPB 1

DPB 2

::

DPB N-1

DPB N

SPB Lock bit lockedAll SPBs are unchangeable

Solid Protection Mode

Set 64 bit Password

Sector Array

Dynamic write Protect bit (DPB)

DPB=0 sector protect

DPB=1 sector unprotect

SetSPB Lock Bit

SPBLK = 0

SPBLK = 1

36Rev. 1.3, July 05, 2018



9-17-1. Lock Register

UsercanchoosethesectorprotectingmethodviasettingLockRegisterbitsasQ1andQ2.LockRegisterisa16-bitone-timeprogrammableregister.OnceprogrammingeitherQ1andQ2,theywillbelockedinthatmodeandtheotherswillbedisabledpermanently.Q1andQ2cannotbeprogrammedatthesametime,otherwisethedevicewillaborttheoperation.

IfusersselectPasswordProtectionmode,thepasswordsettingisrequired.Userscansetpasswordbyissuingpasswordprogramcommand.

Lock Register bitsQ15~Q7, Q5~Q3 Q6 Q2 Q1 Q0

Reserved SecuritySectorCustomerLockbit

PasswordProtectionModeLockBit

SolidProtectionModeLockBit

SecuritySectorFactoryLockbit

PleaserefertothecommandforLockRegistercommandsettoreadandprogramtheLockregister.

Figure 12. LOCK REGISTER PROGRAM ALGORITHM

START

Pass

Exit Lock Register command

Done YES

YES

NO

Q5 = 1NO

Write Data AAH, Address 555H

Lock register command set EntryWrite Data 55H, Address 2AAH

Write Data 40H, Address 555H

Write Data A0H, Address don’t care

Write Program Data, Address don’t care

Data # Polling Algorithm

Fail

Reset command

Lock register data program

37Rev. 1.3, July 05, 2018



9-17-2. Solid Protection Mode

Solid write Protection Bits (SPB)

TheSolidwriteProtectionbits(SPB)arenonvolatilebitwiththesameendurancesastheFlashmemory.EachSPBisassignedtoeachsectorindividually.TheSPBispreprogrammed,andverifiedpriortoerasurearemanagedbythedevice,sosystemmonitoringisnotnecessary.

WhenSPBissetto"0",theassociatedsectormaybeprotected,preventinganyprogramoreraseoperationonthissector.WhetherthesectorisprotecteddependsalsouponthevalueoftheUSPB,asdescribedelsewhere.TheSPBbitsaresetindividuallybySPBprogramcommand.However,itcannotbeclearedindividually.IssuingtheAllSPBErasecommandwilleraseallSPBinthesametime.DuringSPBprogrammingperiod,thereadandwriteoperationsaredisabledfornormalsectoruntilexitingthismode.

Tounprotectaprotectedsector,theSPBlockbitmustbeclearedfirstbyusingahardwareresetorapower-upcycle.AftertheSPBlockbitiscleared,theSPBstatuscanbechangedtothedesiredsettings.TolocktheSolidProtectionBitsafterthemodificationhasfinished,theSPBLockBitmustbesetonceagain.

ToverifythestateoftheSPBforagivensector,issuingaSPBStatusReadCommandtothedeviceisrequired.RefertotheflowchartfordetailsofSPBProgramin"Figure 13. SPB PROGRAM ALGORITHM".

Dynamic Protection Bits (DPB)

TheDynamicProtectionfeaturesavolatiletypeprotectiontoeachindividualsector.Itcanprotectsectorsfrombeingunintentionallychanged,andiseasytodisable.

AllDynamicwriteProtectionbit(DPB)canbemodifiedindividually.DPBsprotecttheunprotectedsectorswiththeirSPBscleared.TomodifytheDPBstatusbyissuingtheDPBSet(to"0")orDPBClear(to"1")commands,andplaceeachsectorintheprotectedorunprotectedstateseparately.AftertheDPBClear(to"1")commandisissued,thesectormaybemodifieddependingontheSPBstateofthatsector.

TheDPBsaredefaulttobecleared(to"1")whenfirstshippedfromfactory.

38Rev. 1.3, July 05, 2018



Temporary Un-protect Solid write Protect Bits (USPB)

TemporaryUn-protectSolidwriteProtectBitsarevolatile.Theyareuniqueforeachsectorandcanbeindividuallymodified.SoftwarecantemporarilyunprotectwriteprotectsectorsdespiteofSPB'spropertywhenDPBsarecleared.WhiletheUSPBisset(to"0"),thecorrespondingsector'sSPBpropertyismasked.

Notes:1.Uponpowerup,theUSPBsarecleared(all"1").TheUSPBscanbeset(to"0")orcleared(to"1")asoftenas

needed.ThehardwareresetwillresetUSPB/DPBtotheirdefaultvalues.

2.Tochangetheprotectedsectorstatusofsolidwriteprotectbit,usersdon'tneedtoclearallSPBs.TheuserscanjustimplementsoftwaretosetcorrespondingUSPBto"0",inwhichthecorrespondingDPBstatusisclearedtoo.Consequently,theoriginalsolidwriteprotectstatusofprotectedsectorscanbetemporarilychanged.

Note:SPBprogram/erasestatuspollingflowchart:checkQ6toggle,whenQ6stoptoggle,thereadstatusis00H/01H(00Hforprogram/01Hforerase),otherwise,thestatusis"fail"and"exit".

Figure 13. SPB PROGRAM ALGORITHM

Q6 Toggle ?

Q6 Toggle ?

Q5 = 1 ?

NO

NO

YES

NO

NO

SPB commandset entry

Program SPB

Read Q7~Q0Twice

Read Q7~Q0Twice

Read Q7~Q0Twice

YES

YES

YES

Wait 500 µs

Program Fail Write Reset CMD

Pass

Q0='1' (Erase)'0' (Program)

SPB commandset Exit

39Rev. 1.3, July 05, 2018



9-17-3. Solid Protection Bit Lock Bit

TheSolidProtectionBitLockBit(SPBLK)isassignedtocontrolallSPBstatus.Itisanuniqueandvolatile.WhenSPBLK=0(set),allSPBsarelockedandcannotbechanged.WhenSPBLK=1(cleared),allSPBsareallowedtobechanged.

Thereisnosoftwarecommandsequencerequestedtounlockthisbit,unlessthedeviceisinthepasswordprotectionmode.TocleartheSPBLockBit,justexecuteahardwareresetorapower-upcycle.Inordertopreventmodification,theSPBLockBitmustbeset(SPBLK=0)afterallSPBsaresettodesiredstatus.

9-17-4. Password Protection Method

ThesecuritylevelofPasswordProtectionMethodishigherthantheSolidprotectionmode.The64bitpasswordisrequestedbeforemodifyingSPBlockbitstatus.Whendeviceisunderpasswordprotectionmode,theSPBlockbitissetas"0",afterapower-upcycleorResetCommand.

AcorrectpasswordisrequiredforpasswordUnlockcommandtounlocktheSPBlockbit.Await100usisnecessarytounlockthedeviceafteravalidpasswordisgiven.Afterthat,theSPBbitsareallowedtobechanged.ThePasswordUnlockcommandisissuedslowerthan100μseverytime,topreventhackerfromtryingallthe64-bitpasswordcombinations.

Thereareafewstepstostartpasswordprotectionmode:(1).Seta64-bitpasswordforverificationbeforeenteringthepasswordprotectionmode.Thisverificationisonly

allowedinpasswordprogramming.(2).SetthePasswordProtectionModeLockBitto"0"toactivatethepasswordprotectionmode.

Oncethepasswordprotectionmodelockbitisprogrammed,theprogrammedQ2bitcannotbeerasedanymoreandthedevicewillremainpermanentlyinpasswordprotectionmode.Thepreviousset64-bitpasswordcannotberetrievedorprogrammed.Allthecommandstothepassword-protectedaddresswillalsobedisabled.

Allthecombinationsofthe64-bitpasswordcanbeusedasapassword,andprogrammingthepassworddoesnotrequirespecialaddress.Thepasswordisdefaultedtobeall"1"whenshippedfromthefactory.Underpasswordprogramcommand,only"0"canbeprogrammed.Inordertopreventaccess,thePasswordModeLockingBitmustbesetafterthePasswordisprogrammedandverified.TosetthePasswordModeLockBitwillpreventthis64-bitspasswordtobereadonthedatabus.Anymodificationisimpossiblethen,andthepasswordcannotbecheckedanymoreafterthePasswordModeLockBitisset.

40Rev. 1.3, July 05, 2018



Table 8. SECTOR PROTECTION STATUS TABLE

Protection Bit StatusSector Status

DPB SPB USPBclear(1) clear(1) clear(1) Unprotectedclear(1) clear(1) set(0) Unprotectedclear(1) set(0) clear(1) Protectedclear(1) set(0) set(0) Unprotectedset(0) clear(1) clear(1) Protectedset(0) clear(1) set(0) Protectedset(0) set(0) clear(1) Protectedset(0) set(0) set(0) Protected

Notes: IfSPBLKisset,SPBwillbeunchangeable. IfSPBLKiscleared,SPBwillbechangeable.

41Rev. 1.3, July 05, 2018



9-18. SECURITY SECTOR FLASH MEMORY REGION

TheSecuritySectorregion isanextraOTPmemoryspaceof512word in length.Thesecuritysectorcanbelockeduponshippingfromfactory,oritcanbelockedbycustomeraftershipping.CustomercanissueSecuritySectorStatusand/orSecuritySectorProtectVerifytoquerythelockstatusofthedevice.

Thedevicewillhavea512word(1024byte)inthesecurityregion00000hto003FEhinbytemodeor00000hto001FFhinwordmode.

9-19. FACTORY LOCKED: CAN BE PROGRAMMED AND PROTECTED AT THE FACTORY

IInfactorylockedarea,securitysectorregionisprotectedwhenshippedfromfactoryandpermanentlylockedTheLockRegister"SecuritySectorFactoryLockbit"DQ0issetto"0".

9-20. CUSTOMER LOCKED: NOT PROGRAMMED AND NOT PROTECTED AT FACTORY

IncustomerLockedarea,securitysectorregionisunprotectedwhenshippedfromfactory.TheLockRegister"SecuritySectorCustomerLockbit"DQ6issetto"1"bydefault.Notethatoncethesecuritysectorisprotected,thereisnowaytounprotectthesecuritysectorandthecontentofitcannolongerbealtered.

Afterthesecuritysectorislockedandverified,systemmustwriteExitSecuritySectorRegion,gothroughapow-ercycle,orissueahardwareresettoreturnthedevicetoreadnormalarraymode.

Security Sector Address Range OTP Area Definition OTP Length

000000h-0000FFh FactoryLockedArea 256 word

000100h-0001FFh CustomerLockedArea 256 word

42Rev. 1.3, July 05, 2018



Table 9. COMMAND DEFINITIONS

WA=WriteAddressWD=WriteDataSA=SectorAddressN-1=WordCountWBL=WriteBufferLocationPWD=PasswordPWDn=Passwordword0,word1,wordnID1/ID2/ID3:Referto"Table 7. AUTOMATIC SELECT HIGH VOLTAGE OPERATION"fordetailedID.

Command Read Mode

ResetMode

EnterAutomaticSelectMode

EnterCFIMode

SecuritySectorRegion

ExitSecuritySector

ReadExtendedStatusRegister

ClearExtendedStatusRegister

Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte

1stBusCycle

Addr Addr xxx 555 AAA (SA)55

(SA)AA 555 AAA 555 AAA 555 AAA 555 AAA

Data Data F0 AA AA 98 98 AA AA AA AA 70 70 71 712ndBusCycle

Addr 2AA 555 2AA 555 2AA 555 xxx xxxData 55 55 55 55 55 55 Data Data

3rdBusCycle

Addr (SA)555

(SA)AAA

(SA)555

(SA)AAA 555 AAA

Data 90 90 88 88 90 90

4thBusCycle

Addr XXX XXX

Data 00 00

5thBusCycle

AddrData

6thBusCycle

AddrData

CommandProgram WritetoBuffer

Program

WritetoBufferProgram

AbortReset

WritetoBufferProgramconfirm

Word Byte Word Byte Word Byte Word Byte

1stBusCycle

Addr 555 AAA 555 AAA 555 AAA SA SA

Data AA AA AA AA AA AA 29 292ndBusCycle

Addr 2AA 555 2AA 555 2AA 555 Data 55 55 55 55 55 55

3rdBusCycle

Addr 555 AAA SA SA 555 AAA Data A0 A0 25 25 F0 F0

4thBusCycle

Addr Addr Addr SA SA Data Data Data N-1 N-1

5thBusCycle

Addr WA WA Data WD WD

6thBusCycle

Addr WBL WBL Data WD WD

10. COMMAND REFERENCE SUMMARY

10-1. COMMAND DEFINITIONS

43Rev. 1.3, July 05, 2018



Command

Deep Power Down PasswordProtection

Enter ExitPassword

CommandSetEntry

PasswordProgram

PasswordRead

PasswordUnlock

PasswordCommandSet

ExitWord Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte

1stBusCycle

Addr 555 AAA XXX XXX 555 AAA XXX XXX 00 00 00 00 XXX XXXData AA AA AB AB AA AA A0 A0 PWD0 PWD0 25 25 90 90

2ndBusCycle

Addr 2AA 555 2AA 555 PWA PWA 01 01 00 00 XXX XXXData 55 55 55 55 PWD PWD PWD1 PWD1 03 03 00 00

3rdBusCycle

Addr XXX XXX 555 AAA 02 02 00 00Data B9 B9 60 60 PWD2 PWD2 PWD0 PWD0

4thBusCycle

Addr 03 03 01 01Data PWD3 PWD3 PWD1 PWD1

5thBusCycle

Addr 04 02 02Data PWD4 PWD2 PWD2

6thBusCycle

Addr 05 03 03Data PWD5 PWD3 PWD3

7thBusCycle

Addr 06 00 04Data PWD6 29 PWD4

8thBusCycle

Addr 07 05Data PWD7 PWD5

9thBusCycle

Addr 06Data PWD6

10thBusCycle

Addr 07Data PWD7

11thBusCycle

Addr 00Data 29

CommandBlankCheck ChipErase SectorErase

Program/Erase

Suspend

Program/EraseResume

ProgramSuspendSpecificMethod

ProgramResumeSpecificMethod

Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte

1stBusCycle

Addr (SA)555

(SA)AAA 555 AAA 555 AAA xxx xxx xxx xxx xxx xxx xxx xxx

Data 33 33 AA AA AA AA B0 B0 30 30 51 51 50 502ndBusCycle

Addr 2AA 555 2AA 555Data 55 55 55 55

3rdBusCycle

Addr 555 AAA 555 AAAData 80 80 80 80

4thBusCycle

Addr 555 AAA 555 AAAData AA AA AA AA

5thBusCycle

Addr 2AA 555 2AA 555Data 55 55 55 55

6thBusCycle

Addr 555 AAA Sector SectorData 10 10 30 30

44Rev. 1.3, July 05, 2018



Command

LockRegister GlobalNon-Volatile

LockregisterCommandSetEntry

Program ReadLockregisterCommandSetExit

SPB CommandSetEntry

SPB Program

All SPB Erase

SPBStatusRead

Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte1stBusCycle

Addr 555 AAA XXX XXX XXX XXX XXX XXX 555 AAA XXX XXX XXX XXX SA SAData AA AA A0 A0 DATA DATA 90 90 AA AA A0 A0 80 80 00/01 00/01

2ndBusCycle

Addr 2AA 555 XXX XXX XXX XXX 2AA 555 SA SA 00 00Data 55 55 Data Data 00 00 55 55 00 00 30 30

3rdBusCycle

Addr 555 AAA 555 AAA Data 40 40 C0 C0

4thBusCycle

AddrData

5thBusCycle

AddrData

Command

Global Non-Volatile GlobalVolatileFreeze Volatile

SPB CommandSetExit

SPBLockCommandSetEntry

SPBLockSet

SPBLockStatusRead

SPBLockCommandSetExit

DPB CommandSetEntry

DPBSet DPB Clear

Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte1stBusCycle

Addr XXX XXX 555 AAA XXX XXX XXX XXX XXX XXX 555 AAA XXX XXX XXX XXXData 90 90 AA AA A0 A0 00/01 00/01 90 90 AA AA A0 A0 A0 A0

2ndBusCycle

Addr XXX XXX 2AA 555 XXX XXX XXX XXX 2AA 555 SA SA SA SAData 00 00 55 55 00 00 00 00 55 55 00 00 01 01

3rdBusCycle

Addr 555 AAA 555 AAA Data 50 50 E0 E0

4thBusCycle

AddrData

5thBusCycle

AddrData

Command

Volatile

DPBStatusRead

DPBCommandSetExit

Word Byte Word Byte1stBusCycle

Addr SA SA XXX XXXData 00/01 00/01 90 90

2ndBusCycle

Addr XXX XXXData 00 00

3rdBusCycle

AddrData

4thBusCycle

AddrData

5thBusCycle

AddrData

Notes: *Itisnotrecommendedtoadoptanyothercodenotinthecommanddefinitiontablewhichwillpotentiallyenterthehiddenmode.*FortheSPBLockandDPBStatusRead"00"meanslock(protect),"01"meansunlock(unprotect).

45Rev. 1.3, July 05, 2018



Table 10. CFI MODE: IDENTIFICATION DATA VALUES (Allvaluesinthesetablesareinhexadecimal)

Table 11. CFI MODE: SYSTEM INTERFACE DATA VALUES

10-2. COMMON FLASH MEMORY INTERFACE (CFI) MODE

ThehostsystemcanreadCFIinformationattheaddressesgiveninthefollowingTable 10~Table 13,thequerydataisalwayspresentedonthelowestorderdataoutputs.

DescriptionAddress (h) (Word Mode)

Address (h)(Byte Mode)

Data (h)

Query-uniqueASCIIstring"QRY"10 20 005111 22 005212 24 0059

PrimaryvendorcommandsetandcontrolinterfaceIDcode 13 26 000214 28 0000

Addressforprimaryalgorithmextendedquerytable 15 2A 004016 2C 0000

AlternatevendorcommandsetandcontrolinterfaceIDcode 17 2E 000018 30 0000

Addressforalternatealgorithmextendedquerytable 19 32 00001A 34 0000



Data (h)

Vccsupplyminimumprogram/erasevoltage 1B 36 0027Vccsupplymaximumprogram/erasevoltage 1C 38 0036VPPsupplyminimumprogram/erasevoltage 1D 3A 0000VPPsupplymaximumprogram/erasevoltage 1E 3C 0000Typicaltimeoutpersingleword/bytewrite,2nus 1F 3E 0005Typicaltimeoutformaximum-sizebufferwrite,2nus(00h,notsupport) 20 40 0009

Typicaltimeoutperindividualblockerase,2nms 21 42 0008Typicaltimeoutforfullchiperase,2nms(00h,notsupport)

22 44512Mb 0011

1Gb 0012Maximumtimeoutforword/bytewrite,2n timestypical 23 46 0003Maximumtimeoutforbufferwrite,2n timestypical 24 48 0002Maximumtimeoutperindividualblockerase,2n timestypical 25 4A 0003Maximumtimeoutforchiperase,2n timestypical(00h,notsupport) 26 4C 0001

46Rev. 1.3, July 05, 2018



Table 12. CFI MODE: DEVICE GEOMETRY DATA VALUES



Data (h)

Devicesize=2ninnumberofbytes 27 4E512Mb 001A

1Gb 001BFlashDeviceInterfaceDescription0=x8-only,1=x16-only,2=x8/x16capable

28 50 000229 52 0000

Maximumnumberofbytesinbufferwrite=2n (00h,notsupport)2A 54 00092B 56 0000

Numberoferaseregionswithindevice(01h:uniform,02h:boot) 2C 58 0001

IndexforEraseBankArea1:[2E,2D]=#ofsame-sizesectorsinregion1-1[30,2F]=sectorsizeinmultiplesof256-bytes

2D 5A 00FF

2E 5C512Mb 0001

1Gb 00032F 5E 000030 60 0002

IndexforEraseBankArea2

31 62 000032 64 000033 66 000034 68 0000


35 6A 000036 6C 000037 6E 000038 70 0000


39 72 00003A 74 00003B 76 00003C 78 0000

Reserved3D 7A FFFF3E 7C FFFF3F 7E FFFF

47Rev. 1.3, July 05, 2018



Table 13. CFI MODE: PRIMARY VENDOR-SPECIFIC EXTENDED QUERY DATA VALUES



Data (h)

Query-Primaryextendedtable,uniqueASCIIstring,PRI40 80 005041 82 005242 84 0049

Majorversionnumber,ASCII 43 86 0031Minorversionnumber,ASCII 44 88 0035Addresssensitiveunlock(bits1to0)00=supported,01=notsupportedProcessTechnology(bits7to2)

45 8A 001C

Erasesuspend(2=tobothreadandprogram) 46 8C 0002Sectorprotect(N=#ofsectors/group) 47 8E 0001Temporarysectorunprotect(1=supported) 48 90 0001Sectorprotect/Chipunprotectscheme 49 92 0008SimultaneousR/Woperation(0=notsupported) 4A 94 0000Burstmode(0=notsupported) 4B 96 0000Pagemode(0=notsupported,01=4wordpage,02=8wordpage,03=16 word page) 4C 98 0003

MinimumACC(acceleration)supply(0=notsupported),[D7:D4]forvolt,[D3:D0]for100mV 4D 9A 0095

MaximumACC(acceleration)supply(0=notsupported),[D7:D4]forvolt,[D3:D0]for100mV 4E 9C 00A5

WP#Protection04=UniformsectorsbottomWP#protect05=UniformsectorstopWP#protect

4F 9E 0004/0005

ProgramSuspend(0=notsupported,1=supported) 50 A0 0001UnlockBypass00=NotSupported01=Supported 51 A2 0000SecuritySector(CustomerOTPArea)Size2N(bytes) 52 A4 0009SoftwareFeaturesbit0:extendedstatusregister(1=supported,0=notsupported)bit1:DQpolling(1=supported,0=notsupported)bit2:newprogramsuspend/resumecommands(1=supported,0=notsupported)bit3:wordprogram(1=supported,0=notsupported)bit4:bit-fieldprogram(1=supported,0=notsupported)bit5:autodetectprogram(1=supported,0=notsupported)bit6:RFUbit7:multiplewritesperLine(1=supported,0=notsupported)

53 A6 008F

PageSize=2Nbytes 54 A8 0005EraseSuspendTimeoutMaximum<2N(us) 55 AA 0005ProgramSuspendTimeoutMaximum<2N(us) 56 AC 0005Reserved 57-77 AE-EE FFFFEmbeddedHardwareResetTimeoutMaximum<2N(us)ResetwithResetPin 78 F0 0005

Non-EmbeddedHardwareResetTimeoutMaximum<2N(us)PoweronReset 79 F2 0009

Note:Querydataarealwayspresentedonthelowest-orderdataoutputsonly.

48Rev. 1.3, July 05, 2018



11. ELECTRICAL CHARACTERISTICS

Figure 14. MAXIMUM NEGATIVE OVERSHOOT WAVEFORM Figure 15. MAXIMUM POSITIVE OVERSHOOT WAVEFORM

GND

GND - 2.0V

20ns 20ns

20ns

Vcc + 2.0V

Vcc

20ns 20ns

20ns

11-1. ABSOLUTE MAXIMUM STRESS RATINGS

11-2. OPERATING TEMPERATURE AND VOLTAGE

SurroundingTemperaturewithBias -65°Cto+125°CStorageTemperature -65°Cto+150°C

VoltageRange

VCC -0.5Vto+4.0V

VI/O -0.5Vto+4.0VA9,WP#/ACC -0.5Vto+10.5VTheotherpins. -0.5VtoVcc+0.5V

OutputShortCircuitCurrent(lessthanonesecond) 200mA

Industrial (I) Grade SurroundingTemperature(TA ) -40°Cto+85°C

VCC Supply Voltages

Full VCC range +2.7Vto3.6VRegulatedVCC range +3.0Vto3.6VVI/O range 1.65VtoVCC

NOTICE:1.Stressesgreater than those listedunderABSOLUTEMAXIMUMRATINGSmaycausepermanentdamagetothedevice.Thisisstressratingonlyandfunctionaloperationalsectionsofthisspecificationisnotimplied.Exposuretoabsolutemaximumratingconditionsforextendedperiodmayaffectreliability.

2.Specificationscontainedwithinthefollowingtablesaresubjecttochange.3.Duringvoltagetransitions,allpinsmayovershootGNDto-2.0VandVccto+2.0Vforperiodsupto20ns,see

below Figure.

49Rev. 1.3, July 05, 2018



Figure 16. SWITCHING TEST CIRCUITS

Figure 17. SWITCHING TEST WAVEFORMS

Test Condition OutputLoadCapacitance,CL:1TTLgate,30pFRise/FallTimes:5nsInputPulselevels:0.0~VI/OIn/Outreferencelevels:0.5VI/O

Test Points

VI/O

VI/O / 2VI/O / 2

0.0VOUTPUTINPUT

DEVICE UNDERTEST

CL

3.3V

6.2KΩ

2.7KΩ

11-3. TEST CONDITIONS

50Rev. 1.3, July 05, 2018



Table 14. DC CHARACTERISTICS

11-4. DC CHARACTERISTICS

Symbol Description Min. Typ. Max. Unit RemarkIilk InputLeak ±2.0 uA

Iilkw WP#/ACCLeak512Mb ±4.0 uA1Gb ±8.0 uA

Iilk9 A9Leak512Mb 20 uA

A9=10.5V1Gb 40 uA

Iolk OutputLeak ±1.0 uA

Icr1 ReadCurrent

1MHz512Mb 5 10 mA CE#=Vil,OE#=Vih,

VCC=VCCmax;f=1MHz1Gb 5 15 mA





Icr2 VCC Page Read Current





Iio VI/Onon-activecurrent512Mb 0.2 10 mA

1Gb 0.4 20 mA

Icw WriteCurrent512Mb 35 55 mA CE#=Vil,OE#=Vih,

WE#=Vil1Gb 35 55 mA

Isb StandbyCurrent512Mb 20 90 uA VCC=VCCmax,

CE#=OE#=RESET#=VIO1Gb 40 180 uA

Isbr ResetCurrent512Mb 20 90 uA VCC=VCCmax,

RESET#=GND,CE#=Vih1Gb 40 180 uA

Isbs SleepModeCurrent512Mb 20 90 uA VCC=VCCmax,

Vil=GND,Vih=VI/O1Gb 40 180 uA

Idpd Vccdeeppowerdowncurrent512Mb 3 15 uA VCC=VCCmax,

CE#=OE#=RESET#=VIO1Gb 6 30 uA

51Rev. 1.3, July 05, 2018



Symbol Description Min. Typ. Max. Unit Remark

Icp1 AcceleratedPgmCurrent,WP#/ACCpin(Word/Byte) 2 5 mA CE#=Vil,OE#=Vih

Icp2 AcceleratedPgmCurrent,VCCpin,(Word/Byte) 14 28 mA CE#=Vil,OE#=Vih

Vil InputLowVoltage -0.1V 0.3xVI/O VVih InputHighVoltage 0.7xVI/O VI/O+0.3V V

Vhv VeryHighVoltageforAutoSelect/AcceleratedProgram 9.5 10.5 V

Vol OutputLowVoltage 0.45 V Iol=100uA

Voh OuputHighVoltage 0.85xVI/O V Ioh=-100uA

Vlko LowVccLock-outvoltage 2.1 2.4 V

Note: Sleepmodeenablesthelowerpowerwhenaddressremainstablefortaa+1us.

52Rev. 1.3, July 05, 2018



Table 15. AC CHARACTERISTICS

11-5. AC CHARACTERISTICS

Symbol DescriptionVCC=2.7V~3.6V

UnitMin. Typ. Max.

Taa Validdataoutputafteraddress VI/O=VCC 100 nsVI/O=1.65toVCC 110 ns

Tpa PageaccesstimeVI/O=VCC 15 nsVI/O=1.65toVCC 25 ns

Tce ValiddataoutputafterCE#lowVI/O=VCC 100 nsVI/O=1.65toVCC 110 ns

Toe ValiddataoutputafterOE#lowVI/O=VCC 25 nsVI/O=1.65toVCC 30 ns

Tdf DataoutputfloatingafterOE#highorCE#high 20 nsTsrw Latencybetweenreadandwriteoperation(Note) 35 ns

Toh Outputholdtimefromtheearliestrisingedgeofaddress,CE#,OE# 0 ns

Trc Readperiodtime 100 nsTwc Writeperiodtime 100 nsTcwc Commandwriteperiodtime 100 nsTas Addresssetuptime 0 nsTaso AddresssetuptimetoOE#lowduringtogglebitpolling 15 nsTah Addressholdtime 45 ns

Taht AddressholdtimefromCE#orOE#highduringtogglebitpolling 0 ns

Tds Datasetuptime 30 nsTdh Dataholdtime 0 nsTvcs Vccsetuptime 500 usTcs ChipenableSetuptime 0 nsTch Chipenableholdtime 0 nsToes Outputenablesetuptime 0 ns

Toeh OutputenableholdtimeRead 0 nsToggle&Data#Polling 10 ns

53Rev. 1.3, July 05, 2018



Symbol DescriptionVCC=2.7V~3.6V

UnitMin. Typ. Max.

Tws WE#setuptime 0 nsTwh WE#holdtime 0 nsTcepw CE#pulsewidth 35 nsTcepwh CE#pulsewidthhigh 30 ns

Twp WE#pulsewidth 35 nsTwph WE#pulsewidthhigh 30 ns

Tbusy Program/EraseactivetimebyRY/BY#

VI/O=VCC 100 nsVI/O=1.65toVCC 110 ns

Tghwl Readrecovertimebeforewrite 0 nsTghel Readrecovertimebeforewrite 0 ns

Toeph Outputenablehighduringtogglebitpollingorfollowingextendedstatusregisterread 20 ns

Tceph Chipenablehighduringtogglebitpollingorfollowingextendedstatusregisterread 20 ns

Twhwh1 ProgramoperationByte 30 usWord 30 us

Twhwh2 Sectoreraseoperation 0.25 2 sec

Note: Not100%tested.

54Rev. 1.3, July 05, 2018



Figure 18. COMMAND WRITE TIMING WAVEFORM (WE# CONTROLLED)

Addresses

CE#

OE#

WE#

DIN

Tds

Tah

Data

Tdh

Tcs Tch

Tcwc

TwphTwpToes

Tas

Vih

Vil

Vih

Vil

Vih

Vil

Vih

Vil

Vih

Vil

VA

VA: Valid Address

11-6. WRITE COMMAND OPERATION

55Rev. 1.3, July 05, 2018



Figure 19. COMMAND WRITE TIMING WAVEFORM (CE# CONTROLLED)

Address

OE#

CE#

A0h

555h PA

PD Status DOUT

VA VA

Tas Tah

Tghwl

Tcepw

Tds Tdh

Twhwh1 or Twhwh2

Tbusy

Tcepwh

WE#

Data

RY/BY#

Tws Twh

56Rev. 1.3, July 05, 2018



11-7. READ/RESET OPERATION

Figure 20. READ TIMING WAVEFORM

Addresses

CE#

OE#

Taa

WE#

Vih

Vil

Vih

Vil

Vih

Vil

Vih

Vil

Voh

Vol

Tsrw

HIGH Z HIGH ZDATA Valid

ToeToeh Tdf

Tce

Trc

Outputs

Toh

ADD Valid

57Rev. 1.3, July 05, 2018



Figure 21. PAGE READ TIMING WAVEFORM

Amax:A4

(A-1),A0~A3

DATA

CE#

Note: CE#, OE# are enable. Page size is 16 words in Word mode, 32 bytes in Byte mode. Address are A3~A0 for Word mode, A3~A-1 for Byte mode.

VALID ADD

Data 1 Data 2 Data 3

1'st ADD 2'nd ADD

Tpa Taa

3'rd ADD

Tpa

OE#

Tce

Toe

58Rev. 1.3, July 05, 2018



Figure 22. READ MANUFACTURER ID OR DEVICE ID

Taa Taa Taa Taa

Tce

Toe

Toh Toh Toh Toh

Tdf

DATA OUT

Manufacturer ID Device IDCycle 1

Device IDCycle 2

Device IDCycle 3

VhvVihVil

ADDA9

ADD

CE#

A1

OE#

WE#

ADDA0

DATA OUT DATA OUT DATA OUTDATAQ15-Q0

VCC3V

Vih

Vil

Vih

Vil

Vih

Vil

Vih

Vil

Vih

Vil

Vih

Vil

Vih

Vil

A2

Disable

Enable

59Rev. 1.3, July 05, 2018



Figure 23. RESET# TIMING WAVEFORM

Trh

Trb1

Trp2

Trp1

Tready2

Tready1

RY/BY#

CE#, OE#

RESET#

Reset Timing NOT during Automatic Algorithms

Reset Timing during Automatic Algorithms

RY/BY#

CE#, OE#

Trb2

WE#

RESET#

Symbol Description Min. Typ. Max. UnitTrp1 RESET#PulseWidth(DuringAutomaticAlgorithms) 10 us

Trp2 RESET#PulseWidth(NOTDuringAutomaticAlgorithms) 200 ns

Trh RESET#HighTimeBeforeRead 50 ns

Trb1 RY/BY#RecoveryTime(toCE#,OE#golow) 0 ns

Trb2 RY/BY#RecoveryTime(toWE#golow) 50 ns

Tready1 RESET#PINLow(DuringAutomaticAlgorithms)toReadorWrite 30 us

Tready2 RESET#PINLow(NOTDuringAutomaticAlgorithms)toReadorWrite 500 ns

Tesl EraseSuspend/ResumeLatency 30 us

Tpsl ProgramSuspend/ResumeLatency 30 us

Tprs Latencybetweenprogramresumeandnextsuspend 30 us

Ters Latencybetweeneraseresumeandnextsuspend 400 us

Table 16. AC CHARACTERISTICS (RESET# TIMING)

60Rev. 1.3, July 05, 2018



Figure 24. DEEP POWER DOWN MODE TIMING WAVEFORM

CE#

WE#

ADD

DATA

XX

B9

2AA55

Tdp

XX (don't care)

AB

Standby mode

AA 55

Deep power down mode

Trdp

Standby mode

Symbol Description Typ. Max. UnitTrdp WE#hightoreleasefromdeeppowerdownmode 100us 200us us

Tdp WE#hightodeeppowerdownmode 10us 20us us

Table 17. AC CHARACTERISTICS (Deep Power Down Mode TIMING)

61Rev. 1.3, July 05, 2018



Figure 25. AUTOMATIC CHIP ERASE TIMING WAVEFORM

Twc

Address

OE#

CE#

55h

2AAh 555h

10h

InProgress Complete

VA VA

Tas Tah

Tghwl

Tch

Twp

Tds Tdh

Twhwh2

Read StatusLast 2 Erase Command Cycle

Tbusy Trb

Tcs TwphWE#

Data

RY/BY#

11-8. ERASE/PROGRAM OPERATION

62Rev. 1.3, July 05, 2018



Twc

Address

OE#

CE#

55h

2AAh SectorAddress

30h

InProgress Complete

VA VA

Tas

Tah

Tghwl

Tch

Twp

Tds Tdh

Twhwh2

Read Status

Last 2 Erase Command Cycle

TbusyTrb

Tcs TwphWE#

Data

RY/BY#

≈≈

≈≈

≈≈

≈

Figure 26. AUTOMATIC SECTOR ERASE TIMING WAVEFORM

63Rev. 1.3, July 05, 2018



Figure 27. AUTOMATIC PROGRAM TIMING WAVEFORM

Address

OE#

CE#

A0h

555h PA

PD Status DOUT

VA VA

Tas Tah

Tghwl

Tch

Twp

Tds Tdh

Twhwh1

Last 2 Read Status CycleLast 2 Program Command Cycle

TbusyTrb

Tcs TwphWE#

Data

RY/BY#

64Rev. 1.3, July 05, 2018



Figure 28. ACCELERATED PROGRAM TIMING WAVEFORM

WP#/ACC

Vcc

250ns 250ns

Vhv (9.5V ~ 10.5V)

Vil or Vih Vil or Vih

Tvcs

Vcc (min)

GND

65Rev. 1.3, July 05, 2018



Figure 29. DATA# POLLING TIMING WAVEFORM (for AUTOMATIC MODE)

Tdf

Tce

Tch

Toe Toeph

Toeh

Toh

CE#

OE#

WE#

Q7

Q6-Q0

RY/BY#

Tbusy

Status Data Status Data

ComplementComplement True Valid Data

Taa

Trc

Address VAVA

High Z

High ZValid DataTrue

Tceph

11-9. WRITE STATUS OPERATION

66Rev. 1.3, July 05, 2018



Figure 30. TOGGLE BIT TIMING WAVEFORM

Tdf

Taht Taso

Tce

Tch

Toe

Toeh

Taa

Trc

Toh

Address

CE#

OE#

WE#

Q6/Q2

RY/BY#

Tbusy

Valid Status

(first read)

Valid Status

(second read) (stops toggling)

Valid Data

VA VAVA

VA : Valid Address

VA

Valid Data

67Rev. 1.3, July 05, 2018



11-10. RECOMMENDED OPERATING CONDITIONS

11-10-1. At Device Power-Up

ACtimingillustratedin"Figure 31. AC TIMING AT DEVICE POWER-UP"isrecommendedforthesupplyvoltagesandthecontrolsignalsatdevicepower-up(e.g.VccandCE#rampupsimultaneously).Ifthetiminginthefigureisignored,thedevicemaynotoperatecorrectly.

Symbol Parameter Min. Max. UnitTvr VCCRiseTime 500000 us/VTr InputSignalRiseTime 20 us/VTf InputSignalFallTime 20 us/V

Tvcs/Tvcr VCCSetupTime 300 usTvios/Tvior VI/OSetupTime 300 us

Notes: 1.Not100%test.2.VI/O<VCC+200mV.

VCC

CE#

Tvr

Tf

VCC(min)

GND

Vih

Vil

Vih

VilRESET#

Tvcs

VI/O

Tvr

VI/O(min)

GNDTvios

Tvcr

Tvior

Tr

Figure 31. AC TIMING AT DEVICE POWER-UP

Table 18. AC CHARACTERISTICS (AC TIMING AT DEVICE POWER-UP)

68Rev. 1.3, July 05, 2018



11-10-2. Power Up/Down and Voltage Drop

Symbol Parameter Min. Max. UnitVpwd Voltagelevelbelowwhichdeviceneedstobere-initialized 0.9 V

Tpwd TimeintervalforVCCisbelowVpwd 300 us

Tvcs VCCSetupTime 300 us

Tvr VCCRiseTime 500000 us/V

VCC VCCPowerSupply 2.7 3.6 V

VCC

Time

VCC (max.)

VCC (min.)

Vpwd

Chip Select is not allowed

Full DeviceAccessAllowed

(max.)

Tvcs

Tpwd

Whenpoweringdownthedevice,VCCmustdropbelowVPWDforatleastTPWDtoensurethedevicewillinitializecorrectlyduringpowerup.Pleasereferto"Figure 32. POWER UP/DOWN AND VOLTAGE DROP" and "Table 19. AC CHARACTERISTICS (POWER UP/DOWN AND VOLTAGE DROP)"belowformoredetails.

Notes: 1.Not100%test.

Figure 32. POWER UP/DOWN AND VOLTAGE DROP

Table 19. AC CHARACTERISTICS (POWER UP/DOWN AND VOLTAGE DROP)

69Rev. 1.3, July 05, 2018



11-11. ERASE AND PROGRAM PERFORMANCE

Notes:1. Typicalprogramanderasetimesassumethefollowingconditions:25°C,3.0VVCC.Programspecifications

assumecheckboarddatapattern.2.MaximumvaluesaremeasuredatVCC=3.0V,worstcasetemperature.Maximumvaluesarevaliduptoand

including100,000program/erasecycles.3.Erase/ProgramcyclescomplywithJEDECJESD-47&JESD22-A117standard.4.Exclude00hprogrambeforeeraseoperation.

Description Limits UnitsTyp.(1) Max.(2)

ChipEraseTime512Mb 100 250 sec

1Gb 200 500 sec

SectorEraseTime 0.25 1.4 sec

WordProgramTime 30 230 us

TotalWriteBufferTime 284 us

TotalACCWriteBufferTime 200 us

Erase/ProgramCycles 100,000 Cycles

BlankCheck 10 ms

11-12. DATA RETENTION

Description Condition Min. Max. UnitDataretention 55˚C 20 years

11-13. LATCH-UP CHARACTERISTICS

Description Min. Max.InputVoltagevoltagedifferencewithGNDonWP#/ACCandA9pins -1.0V 10.5VInputVoltagevoltagedifferencewithGNDonallnormalpinsinput -1.0V 1.5VccVccCurrent -100mA +100mANotes: 1. AllpinsincludedexceptVCC.Testconditions:VCC=3.0V,onepinpertesting

70Rev. 1.3, July 05, 2018



11-14. PIN CAPACITANCE

Table 20. PIN CAPACITANCE: 56-TSOP

Table 21. PIN CAPACITANCE: 64-LFBGA

Symbol Description Typ. Max. Unit Remark

CIN2 ControlPinCapacitance512Mb 3 7 pF

VIN=01Gb 6 14 pF

CIN InputCapacitance512Mb 7 8 pF

VIN=01Gb 14 16 pF

COUT OutputCapacitance512Mb 5 6 pF

VOUT=01Gb 10 12 pF

RY/BY# OutputCapacitance512Mb 3 4 pF

VOUT=01Gb 6 8 pFNotes: 1. Not100%tested,WP#/ACCpinnotincluded.

Symbol Description Typ. Max. Unit Remark

CIN2 ControlPinCapacitance512Mb 4 9 pF

VIN=01Gb 8 18 pF

CIN InputCapacitance512Mb 8 9 pF

VIN=01Gb 16 18 pF

COUT OutputCapacitance512Mb 5 7 pF

VOUT=01Gb 10 14 pF

RY/BY# OutputCapacitance512Mb 3 4 pF

VOUT=01Gb 6 8 pFNotes: 1. Not100%tested,WP#/ACCpinnotincluded.

71Rev. 1.3, July 05, 2018



12. ORDERING INFORMATION

PART NO.ACCESS TIME (ns)

PACKAGE RemarkVcc=3.0 to 3.6V Vcc=2.7 to 3.6V

MX29GL512GMX29GL512GHXFI-10G 100 100 64 LFBGA VI/O=VCCMX29GL512GLXFI-10G 100 100 64 LFBGA VI/O=VCCMX29GL512GHT2I-10G 100 100 56 Pin TSOP VI/O=VCCMX29GL512GLT2I-10G 100 100 56 Pin TSOP VI/O=VCCMX29GL512GUXFI-11G 110 110 64 LFBGA VI/O=1.65toVCCMX29GL512GDXFI-11G 110 110 64 LFBGA VI/O=1.65toVCCMX29GL512GUT2I-11G 110 110 56 Pin TSOP VI/O=1.65toVCCMX29GL512GDT2I-11G 110 110 56 Pin TSOP VI/O=1.65toVCCMX29GL512GHXFI-10Q* 95 100 64 LFBGA VI/O=VCCMX29GL512GLXFI-10Q* 95 100 64 LFBGA VI/O=VCCMX29GL512GHT2I-10Q* 95 100 56 Pin TSOP VI/O=VCCMX29GL512GLT2I-10Q* 95 100 56 Pin TSOP VI/O=VCCMX29GL512GUXFI-11Q* 105 110 64 LFBGA VI/O=1.65toVCCMX29GL512GDXFI-11Q* 105 110 64 LFBGA VI/O=1.65toVCCMX29GL512GUT2I-11Q* 105 110 56 Pin TSOP VI/O=1.65toVCCMX29GL512GDT2I-11Q* 105 110 56 Pin TSOP VI/O=1.65toVCCMX68GL1G0G MX68GL1G0GHT2I-10G 100 100 56 Pin TSOP VI/O=VCCMX68GL1G0GLT2I-10G 100 100 56 Pin TSOP VI/O=VCCMX68GL1G0GUT2I-11G 110 110 56 Pin TSOP VI/O=1.65toVCCMX68GL1G0GDT2I-11G 110 110 56 Pin TSOP VI/O=1.65toVCCMX68GL1G0GHT2I-10Q* 95 100 56 Pin TSOP VI/O=VCCMX68GL1G0GLT2I-10Q* 95 100 56 Pin TSOP VI/O=VCCMX68GL1G0GUT2I-11Q* 105 110 56 Pin TSOP VI/O=1.65toVCCMX68GL1G0GDT2I-11Q* 105 110 56 Pin TSOP VI/O=1.65toVCC

PleasecontactMacronixregionalsalesforthelatestproductselectionandavailableformfactors.

Notes: *Advanced Information

72Rev. 1.3, July 05, 2018



13. PART NAME DESCRIPTION

MX 29 GL 10G H T2 I GOPTION:G: RoHS Compliant & Halogen-freeQ: RoHS Compliant & Halogen-free with Fast Speed under Vcc: 3.0V to 3.6V condition (Note)

SPEED:10: 100ns11: 110ns

TEMPERATURE RANGE:I: Industrial (-40° C to 85° C)

PACKAGE:

PRODUCT TYPE: (WP#=VIL)H: VI/O=VCC=2.7 to 3.6V, Highest Address Sector ProtectedL: VI/O=VCC=2.7 to 3.6V, Lowest Address Sector ProtectedU: VI/O=1.65 to VCC, VCC=2.7 to 3.6V, Highest Address Sector ProtectedD: VI/O=1.65 to VCC, VCC=2.7 to 3.6V, Lowest Address Sector Protected

REVISION:G

DENSITY & MODE:512: 512Mb x8/x16 Architecture1G0: 1Gb x8/x16 Architecture

GL: 3V Page ModeTYPE:

DEVICE:29: Monolithic Die Flash68: Stack Die Flash

512

T2: 56-TSOPXF: LFBGA (11mm x 13mm x 1.4mm, 0.6 ball size, 1.0 ball-pitch)

Note:10Q covers 2.7~3.6V for 100ns and 3.0~3.6V for 95ns 11Q covers 2.7~3.6V for 110ns and 3.0~3.6V for 105ns

73Rev. 1.3, July 05, 2018



14. PACKAGE INFORMATION56-Pin TSOP

74Rev. 1.3, July 05, 2018



64-Ball LFBGA (11mm x 13mm)

75Rev. 1.3, July 05, 2018



15. REVISION HISTORY

Revision No. Description Page Date0.01 1.Modifieddescriptions,figuresandtables All JAN/23/2014 2.RemovedMulti-sectorEraseFunction P21,22,62 3.Modifiedparametersof"CFIMode"Table P45~47 4.Modifiedparametersof"ERASEANDPROGRAMPERFORMANCE"Table P6,53,69 5.ModifiedDCCharacteristics,Resettiming&Program,EraseSuspend/ P50,51,59 Resumelatency1.0 1.Removed56-BallFBGAPackage P7,9 MAY/29/2014 2. ModifiedDCCharacteristicsTable P50 3.ModifiedReset#,ACPower-Up,PowerUp/DownTimingTable P59,67,68 4.Modifiedparametersof"EraseandProgramPerformance"Table P69 5.ModifiedPINCapacitance P70 6.Separate256Mbpartfromthisdatasheetrevision All 7.RemovedPreliminarystatus All1.1 1.ModifiedtheorderinginformationofMX68GL1G0G P71 NOV/26/2015 2.Contentcorrection P371.2 1.Addedastatementforproductorderinginformation P71 FEB/17/2017 2.ModifiedtheorderinginformationofMX68GL1G0G P71 3.UpdatedtVRdescriptions. P67-68 4.Descriptionmodifications. P54-551.3 1.Added"MacronixProprietary"footnote. All JUL/05/2018 2.AddedpartnumbersofwithFastSpeedunderVcc3.0Vto3.6Vcondition P71-72 3.Formatmodification. P73-74

76

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

Exceptforcustomizedproductswhichhavebeenexpresslyidentifiedintheapplicableagreement,Macronix'sproductsaredesigned,developed,and/ormanufacturedforordinarybusiness,industrial,personal,and/orhouseholdapplicationsonly,andnotforuseinanyapplicationswhichmay,directlyorindirectly,causedeath,personalinjury,orseverepropertydamages.IntheeventMacronixproductsareusedincontradictedtotheirtargetusageabove,thebuyershalltakeanyandallactionstoensuresaidMacronix'sproductqualifiedforitsactualuseinaccordancewiththeapplicablelawsandregulations;andMacronixaswellasit’ssuppliersand/ordistributorsshallbereleasedfromanyandallliabilityarisentherefrom.

Copyright©MacronixInternationalCo.,Ltd.2012-2018.Allrightsreserved,includingthetrademarksandtradenamethereof,suchasMacronix,MXIC,MXICLogo,MXLogo,IntegratedSolutionsProvider,Nbit,MacronixNBit,HybridNVM,HybridFlash,HybridXFlash,XtraROM,KHLogo,BE-SONOS,KSMC,Kingtech,MXSMIO,MacronixvEE,MacronixMAP,RichBook,RichTV,OctaRAM,OctaBus,OctaFlash,andFitCAM.Thenamesandbrandsofthirdpartyreferredthereto(ifany)areforidentificationpurposesonly.

Forthecontactandorderinformation,pleasevisitMacronix’sWebsiteat:http://www.macronix.com


mx29gl512g / mx68gl1g0g - macronix · 2018-08-15 · mx29gl512g mx68gl1g0g p/n: pm1910 maroni...

Documents