muon trigger electronics in the counting roomacosta/cms/acosta_tf_lm00.pdf · muon trigger...
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US CMS DOE/NSF Review: April 11-13, 2000 1
Muon Trigger Electronics in the Counting Room
Muon Trigger Electronics in the Muon Trigger Electronics in the Counting RoomCounting Room
Darin Acosta
University of FloridaApril 2000
US CMS DOE/NSF Review: April 11-13, 2000 2
OutlineOutlineOutline
Overview of the CSC trigger systemSector Receiver (WBS: 3.1.1.2)
Sector Processor (WBS: 3.1.1.3, 3.1.1.4)
Backplane (WBS: 3.1.1.7)
Muon Sorter (WBS: 3.1.1.15)
Schedule
US CMS DOE/NSF Review: April 11-13, 2000 3
Strip FE cards
Wire FE cards
Port Card
PC
Sector Receiver
Sector Processor
OPTICAL
SR SP
CSC Track-Finder
CSC Muon Sorter
Global µ Trigger
DTRPC
FE
FE
Global L1
2µ / chamber
3µ / port card
3µ / sector
4µ
4µ
4µ4µ
LCT
Strip LCT + Motherboard card
Wire LCT card
On chamber In peripheral crate
In counting
house
TMB
LCT
RPC Interface Module
RIM
CSC Muon Trigger SchemeCSC Muon Trigger SchemeCSC Muon Trigger Scheme
US CMS DOE/NSF Review: April 11-13, 2000 4
Muon Track-FindingMuon TrackMuon Track --FindingFinding
θ
ϕ
• Link trigger primitives into tracks• Assign p T, ϕ, and η• Send highest quality candidates to Global L1
US CMS DOE/NSF Review: April 11-13, 2000 5
CSC Track-Finder RequirementsCSC TrackCSC Track --Finder RequirementsFinder Requirements
High EfficiencyLow Trigger Rate:
• Single muon rate < several kHz at L = 1034cm-2 s-1
Resolution: σPt / Pt = 20% • Requires η information (non-uniform B-field)• Requires ≥3 CSC stations
Multi-muon Identification:• ≤ 3 muons per 60° sector• ≤ 4 muons total for both endcaps
ProgrammableMinimal latency
US CMS DOE/NSF Review: April 11-13, 2000 6
Separation of DT/CSC CoverageSeparation of DT/CSC CoverageSeparation of DT/CSC Coverage
• Hard boundary defined η=1.04
• Separate Track-Finders optimized for each system
• Information shared across boundary for maximum efficiency
• Agreement with Vienna reached on DT/CSC interface Feb’00
Slow simulation of CMS detector in GEANT 3.21
0
100
200
300
400
500
600
700
800
0 200 400 600 800 1000 1200Z (cm)
R (
cm)
η = 1.04
ME1/3
MB2/1
US CMS DOE/NSF Review: April 11-13, 2000 7
OPTICAL
SP
1 Muon Sorter
3µ / port card
3µ / sector
ME1
ME2-ME3
ME4
SR
DT TF
SP
From CSC Port Cards
MS
MB1
PC
From DT Track-Finder
24 Sector Receivers (+12 for ME4)
12 Sector Processors
To Global Muon Trigger
GMT
RPC
4µ
4µ
8µ
The CSC Track-FinderThe CSC TrackThe CSC Track --FinderFinder
12 sectors
(UCLA) (Florida) (Rice)
(Vienna)
(Vienna)
From DT Track-Finder
3.1.1.2 3.1.1.3,3.1.1.4
3.1.1.153.1.1.1WBS:
US CMS DOE/NSF Review: April 11-13, 2000 8
Sector Receiver FunctionalitySector Receiver FunctionalitySector Receiver Functionality
1. Receive 6 µ segments via 12 optical links from 2 Muon Port Cards• Require 3 Sector Receivers for one 60°
sector2. Synchronize the data3. Reformat the data into track segment
variables• LCT bit pattern → η, ϕ, ϕb, ...
4. Apply corrections for alignment5. Communicate to Sector Processor via
custom backplane (Channel Link)6. Fan out ME1/3 µ segments to DT Track-
Finder
} via LUTs
UC
LA
3.1.1.2
US CMS DOE/NSF Review: April 11-13, 2000 9
Sector Receiver LogicSector Receiver LogicSector Receiver Logic
UC
LA
JTAG interface
Controller FPGA
Front Panel
Optical Receiver
Optical Fiber from MPC
Deserializer
Optical Receiver
Optical Fiber from MPC
Deserializer
Front FPGA
LUTS
LUTS
Back FPGA
To Barrel
To Backplane
VME
Repeat for each Muon
3.1.1.2
US CMS DOE/NSF Review: April 11-13, 2000 10
Sector ReceiverSector ReceiverSector Receiver
• Fell behind schedule after postdoc departure.
• Personnel added in December/January:• Robert Cousins, physicist, 50% time• Vladislav Sedov, electronics engineer, 90% time
(10% residual work on ALCT board)• Also using paid consultant for some FPGA work
(UCLA CS Ph.D. candidate)
• Schematics now well underway.
• Long-lead-time parts ordered.
• Layout planned by beginning of May.
• Plan to be ready for summer Track Finder test.
UC
LA
3.1.1.2
US CMS DOE/NSF Review: April 11-13, 2000 11
Sector Processor FunctionalitySector Processor FunctionalitySector Processor Functionality
1. Accumulate track segments for possibly more than one B.X.
2. Extrapolate in 3D from one station to another for all possible track segment combinations
3. Assemble tracks from extrapolation results4. Select best 3 tracks and cancel ghosts5. Assign track parameters: p T, ϕ, η, quality
New since last Review:
• Combined DT/CSC overlap region onto same boardas CSC-only region (add MB1–ME2 extrap.)
• Improved P T assignment technique
• Ghost-busting when 2 muons enter 1 CSC chamber (try all combinations)
ϕ 1 ϕ 2
η 1
η 2
Flor
ida
3.1.1.3, 3.1.1.4
US CMS DOE/NSF Review: April 11-13, 2000 12
To Front panel
EU1-2
EU1-3
EU2-3
EU2-4
EU3-4
EU MB1-2
TAU1
TAU2
TAU3
FSUBXA
FIFO MUX
AU
FromBackplane
Bunch Crossing Analyzer
Track Assembler Units
Final Selection Unit
Extrapolation Units
Assignment Unit
busbus
Sector Processor LogicSector Processor LogicSector Processor Logic
Flor
ida
3.1.1.3, 3.1.1.4
US CMS DOE/NSF Review: April 11-13, 2000 13
SP Prototype LayoutSP Prototype LayoutSP Prototype Layout
Bunch Crossing Analyzer
Extrapolation Units
Track Assembler Units
Final Selection Unit
Assignment Units
VME/JTAG interface (developed separately)
XCV50BG256 XCV400BG560 XCV150BG352
XCV50BG256
SRAM
SRAM
Cus
tom
Cha
nnel
Link
bac
kpla
neS
tand
ard
VM
E
• Layoutcomplete
• 12 layers
• Tests setfor 6/1/00
Flor
ida
US CMS DOE/NSF Review: April 11-13, 2000 13
Prototype Crate LayoutPrototype Crate LayoutPrototype Crate Layout
One sector is half of Track-Finder crate
SPSRSR SR CCB
Six crates for entire system
Fully routed for summer tests
Flor
ida
Smaller prototype tested already
3.1.1.7
US CMS DOE/NSF Review: April 11-13, 2000 15
Pre-Prototype TestsPrePre--Prototype TestsPrototype Tests
Flor
ida
VME / JTAG interface for SR and SP:
Software & hardware for FPGA and SRAM downloading through VME works
Channel Link backplane and connector tests:
No errors found up to 58 MHz clock (400 MHz on backplane)
US CMS DOE/NSF Review: April 11-13, 2000 16
Muon Sorter FunctionalityMuon Sorter FunctionalityMuon Sorter Functionality
1. Receive 36 muons from 12 Sector Processors• 36 × 18 bits = 648 bits (& control bits)
2. Sort and rank the best 4 muons• Sort is based on 7 bits (5 bits for pT and 2 bits
for quality)3. Send the output to the Global Muon Trigger for
association with RPC and DT triggers• 4 × 22 bits = 88 bits
Ric
e
New since last Review:
• Reduction in muon count from 72 to 36 (inclusion of CSC/DT overlap in Sector Processor)allows sorting to be accomplished in one FPGA
3.1.1.15
US CMS DOE/NSF Review: April 11-13, 2000 17
FF SORTER 4 out of 18
153comparisonsin parallel
SORTER 4 out of 8
28comparisonsin parallel
FF
FF
FF
FF
FF
28
28
28
28
28
28
28
2814
28
7+6
ALTERA EP20K200EFC484-1
10 2 3 4“4 out of 36” SINGLE-CHIP SORTER BLOCK DIAGRAM AND TIMING
FF
FF
FF
28
28
28
28
28 28
7+6
LUT
ADR1
PAT1
LUT
LUT
LUT
ADR2
ADR3
ADR4
PAT2
PAT3
PAT4
SORTER 4 out of 18
153comparisonsin parallel
14
FF
FF
FF
FF
6
6
6
6
7
7
7
7 8
8
8
8
CLK
28
7+6
7+6
7+6
7+6
7+6
7+6
40MHz
6
6
6
6
VME INTERFACE FOR LUT READ/WRITE
28
FF- FLIP-FLOP, LUT - LOOK-UP TABLE RAM
Muon Sorter LogicMuon Sorter LogicMuon Sorter Logic Ric
e
3.1.1.15
US CMS DOE/NSF Review: April 11-13, 2000 18
VMEINTERFACE
VME J1CONNECTOR
SORTERPLD
CONNECTORTO CUSTOM BACKPLANE
252
56
9U * 400 MM BOARD
CCB INTERFACE
CONNECTORSTO GMT
CONNECTOR TORECEIVER BOARDS
GMT LVDSDRIVERS
Sorter Board Block DiagramSorter Board Block DiagramSorter Board Block Diagram Ric
e
3.1.1.15
US CMS DOE/NSF Review: April 11-13, 2000 19
CONNECTORSTO GMT
12 CONNECTORS TORECEIVER BOARDS
S R R R R
Muon Sorter Crate LayoutMuon Sorter Crate LayoutMuon Sorter Crate Layout Ric
e
3.1.1.15
US CMS DOE/NSF Review: April 11-13, 2000 20
CONNECTOR TO SP
CONNECTOR TO SP
Rx
PIPELINEPLD
10K130Eor
20K200E
Rx
CONNECTOR TOSORTER BOARD
CONNECTOR TO SP
RECEIVERS
Rx
21
2121
2760
60
6084
CLOCK
POWER
Sorter Receiver Board Block Diagram
Sorter Receiver Board Sorter Receiver Board Block DiagramBlock Diagram R
ice
3.1.1.15
US CMS DOE/NSF Review: April 11-13, 2000 21
Summer PlansSummer PlansSummer Plans
Crate test with prototype SR, SP, CCB (and TMB, MPC) scheduled for summer 2000
• Bench tests start June 1• Integration tests start July 1• Will test optical link connections and trigger algorithms
at 40 MHz, verify output and latency
All designs are proceeding well, and we should be able to make milestone
• Conceptual design, schematics, and some layouts already exist
Development of test software started
US CMS DOE/NSF Review: April 11-13, 2000 22
Allocated ResourcesAllocated ResourcesAllocated Resources
• UCLA (Sector Receiver)• Robert Cousins, physicist, co-PI, 0.5 FTE• Jay Hauser, physicist, co-PI, 0.5 FTE• Benn Tannenbaum, physicist, 0.5 FTE• Vladislav Sedov, electronics engineer, 0.9 FTE• Consultant for some FPGA work (UCLA CS Ph.D. candidate)
• Florida (Sector Processor)• Darin Acosta, physicist, PI, 0.5 FTE• Song Ming Wang, physicist, 0.5 FTE• Alex Madorsky, electronics engineer, 1 FTE• Victor Golovtsov, electronics engineer, 1 FTE• Boris Razmyslovich, electronics engineer, 1 FTE• Alex Atamanchook, electronics engineer, 0.5 FTE
• Rice (Sorter, Port Card)• B. Paul Padley, physicist, PI, 0.5 FTE• Mike Matveev, electronics engineer, 1 FTE• Ted Nussbaum, electronics engineer, 0.5 FTE• Nick Adams, electronics engineer, 0.5 FTE
US CMS DOE/NSF Review: April 11-13, 2000 23
ConclusionsConclusionsConclusions
Some schedule slippage with Sector Receiver (and Port Card) due to personnel shortage and optical testing
Additional engineering resources assigned:UCLA: hired new engineer and consultant Rice: hired new engineer (and test optics for SR)Florida: hired new engineer & collaborate with 3
engineers at PNPI (provide VME interface for SR)Additional physicist resources assigned:
UCLA: Bob Cousins joins, and DOE base support for postdoc
Florida: DOE base support for postdocSo, things will definitely heat up in Florida this summer
for the pilot test!