multipler and multipler accumulator

8/3/2019 Multipler and Multipler Accumulator

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MULTIPLER AND MULTIPLER ACCUMULATOR

Array multiplication is the common operation to be performed inthe digital signal processing applications.

Array multiplication can be done using the single multiplier and adder.

The requirement of array multiplication is it has to process thesignals in real time.

A dedicated MAC unit can be implemented using the hardwareelements, which integrates multiplier and accumulator in thesingle hardware unit.

The other approach is to have multiplier and accumulator separate.


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MULTIPLER AND MULTIPLER ACCUMULATOR

In fig 2.1 the output at the nthsampling instant, is obtained by multiplying the array

xn=[xn,xn-1,xn-2,.xn- m+2,xn-m+1] corresponding tothe present and past m-1samples of the input with thearray h=[h0,h1,h2,hm- 2,hm-1] corresponding to theimpulse response sequence.To obtain yn+1, the input signal array xn+1 is multiplied with the array h.


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MULTIPLE ACCESS MEMORY

The number of memory access can be increased by using the highspeed memory that permits more than one memory access/clock

periods.For eg: DARAM, the dual access RAM permits two memory access/clock periods.Multiple access RAM may be connected to the processing unit of the P-DSP by using the Harvard architecture.For eg: DARAM connected to P-DSP with two independent data and address buses can be used to achieve four memory accesses/clock

periods.


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MULTI PORT MEMORY

Multi ported memory is adopted for increasing the number of accesses/clock periods and it is requires for storing the program and datain two different memory chips in order to permit simultaneous access toboth program and data memories.Disadvantages of dual port memory:

Increase in the cost Large number of the input pins require larger and more expensive package.


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ON CHIP PERIPHERALS

The P-DSPs have a number of the on-chip peripherals the relievethe CPU from routine functions.The help to reduce the chip count on the DSP system based around P-DSP.

Some the on-chip peripherals in the P-DSPs and there functions areas follows:On-chip timer :Two of the common applications are generation of the periodic interrupts to the P-DSPs and generation of the sampling clocks for the A/D converters.


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ON CHIP PERIPHERALS

Serial port:This enables the data communication between the P-DSP and anexternal peripheral such as A/D converter, D/A converter or anRS232 C device.These ports normally have input and output buffers so that the P- DSP writes or reads from the serial port in parallel form and theserial port sends and receives data to the peripherals in the serial form.The serial ports can operate either in the asynchronous mode or inthe synchronous mode.In the asynchronous mode, the transmit data and receive data lines

alone are used for communication and bit clock transmitted fromthe other end.In case of the synchronous mode, both bit clock and a frame synindicating the first bit of the data to be transmitted from serial port to i/o device or i/o device to the serial port.


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ON CHIP PERIPHERALS

Serial port:


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ON CHIP PERIPHERALS

TDM SERIAL PORT :

TDM serial port permits a P-DSP to communicate with the other devices by using the TDM.one of the device can generate the frame syn pulse indicating the beginning

of the TDM frame and bit clock for which the bit is to be transmitted.


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ON CHIP PERIPHERALS

TDM serial port:TFRM: The frame sync signal TCLOCK: The bit clock TADD: The address of the serial device that is outputting the datain a particular TDM channel TDAT: The data transmitted intothe TDM channel by theauthorized device


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ON CHIP PERIPHERALS

Parallel port: It enables communication between the P-DSP and other devices to be faster compared to the serial communicationmaking use of additional lines for strobing and handshaking

purposes.Bit i/o ports: The P-DSPS have additional i/o ports that are single bit wide and these bits are used for the control purposes and datatransfer.Host ports: The P-DSPS have special parallel port that enablesthem to communicate with a microprocessor or PC, which is called as the host .

Comm ports: These are the parallel pots used for theinterprocessor communication between a number of the identical DSP in a multiprocessor system.


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pipelining

Instruction pipelining is adopted for increasing the efficiency of themicroprocessors and P-DSPS.

An instruction cycling requiring four microinstructions can becarried out in the four phases:

Fetch phaseDecode phaseMemory read phaseExecution phase


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pipelining

In case of the conventional microprocessor with no pipelining, eachof the functional units is busy only 25% of the time as only oneinstruction can be processed at a time.In a period of 12T only 3 instructions can be executed in a machinewithout pipelining.


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pipelining

For eg:in a machine with four instructions I1,I2,I3,I4 can be processed simultaneously as shown in fig 2.8 In a period of 12T,nine instructions can be executed.


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ON CHIP PERIPHERALS

P-DSPs may be implemented using the RISC or the CISC processor RISC advantages:The chip area dedicated to the realization of the control unit isconsiderably reduced by reduced number of the microinstructions.

In RISC there is more area for incorporating other features.CISC advantages:The CISC processor has a very rich instruction set that supportshigh level language.The P-DSPS with CISC also has instructions specifically required for the digital-signal processing applications such asMACD,FIRS,etc.

multipler and multipler accumulator

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