multiple-input multiple-output converters for …
TRANSCRIPT
MULTIPLE-INPUT MULTIPLE-OUTPUT CONVERTERS FOR FUTURE LOW-
VOLTAGE DC POWER DISTRIBUTION ARCHITECTURES
by
Yajian Tong
A THESIS SUBMITTED IN PARTIAL FULFILLMENT OF
THE REQUIREMENTS FOR THE DEGREE OF
MASTER OF APPLIED SCIENCE
in
The Faculty of Graduate and Postdoctoral Studies
(Electrical and Computer Engineering)
THE UNIVERSITY OF BRITISH COLUMBIA
(Vancouver)
April 2015
© Yajian Tong, 2015
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ABSTRACT
Multiple-input multiple-output (MIMO) converters have been identified as a cost-effective
approach for energy harvesting and dispatching in hybrid power systems such as those envisioned
in future smart homes and DC microgrids. Compared with relatively complex set-up of single-
input single-output (SISO) converters linked at a common DC bus to exchange power, the MIMO
converters possess promising features of fewer components, higher power density, and
centralized control. This thesis addresses various issues regarding the development of MIMO
converters. Both non-isolated and isolated MIMO converter topologies are proposed. Steady-state
analysis and dynamic modeling of MIMO non-inverting buck–boost and flyback converters are
introduced and presented in detail. Specific switching strategies are proposed and appropriate
control algorithms are presented to enable power budgeting between diverse sources and loads in
addition to regulating output voltages. Furthermore, a simple method is put forward for deriving
the non-isolated MIMO converters with DC-link inductor (DLI) and DC-link capacitor (DLC).
Based on a basic structure, a set of rules is listed for the synthesis of MIMO converters. Using the
time-sharing concept, multiple sources provide energy in one period, and multiple loads draw
energy in the subsequent period. In the end, general techniques are introduced for extending the
SISO converters to their MIMO versions, where parts of the conventional SISO converters are
replaced with multiport structures. It is envisioned that MIMO converters presented in this thesis
will find their acceptance in the future in various applications with DC distribution, which are
becoming increasingly accepted by industry.
iii
PREFACE
Some of the research results presented in this thesis have been published in or submitted to
several conference proceedings. In all publications, I was responsible for developing the
topologies, deriving the mathematical formulations, implementing the models, conducting the
simulations and compiling the results, as well as writing the drafts of manuscripts. My research
advisor, Dr. J. Jatskevich, provided the overall supervisory comments and editing during the
process of conducting the research and writing the manuscripts. The contributions of other co-
authors are explained below as applies for each manuscript:
A version of chapter 2 has been published. Y. Tong and J. Jatskevich, “A transformerless
multiple-port DC-DC converter for energy harvesting and dispatching” in Proceedings of IEEE
15th Workshop on Control and Modeling for Power Electronics, Santander, Spain, June 22–25,
2014, pp. 1–9.
A version of chapter 3 has been published. Y. Tong, Z. Shan, J. Jatskevich, and C. K. Tse, “A
flyback converter with multiple ports for power management in DC distribution systems” in
Proceedings of IEEE International Power Electronics and Applications Conference and
Exposition, Shanghai, China, Nov. 5–8, 2014, pp. 1531–1536. Dr. Shan and Dr. Tse provided
useful discussions, then revised and proofread the manuscript.
A part of chapter 4 has been published. Y. Tong and J. Jatskevich, “A methodology to derive
single-stage multiple-input multiple-output DC–DC converters,” in Proceedings of IEEE 36th
International Telecommunication Energy Conference, Vancouver, Canada, Sept. 28–Oct. 2, 2014,
pp. 1–7.
Another part of chapter 4 has been published. Y. Tong, Z. Shan, J. Jatskevich, and A. Davoudi,
“A nonisolated multiple-input multiple-output DC–DC converter for DC distribution of future
energy efficient homes,” in Proceedings of the 40th Annual Conference of the IEEE Industrial
Electronics Society, Dallas, TX, USA, Oct. 29–Nov. 1, 2014, pp. 4126–4132. Dr. Shan provided
comments and corrections. Dr. Davoudi provided very useful feedback and revised the
manuscript.
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A part of chapter 5 has been published. Y. Tong, J. Jatskevich, and A. Davoudi, “Topology
design of isolated multiport converters for smart DC distribution systems,” in Proceedings of the
30th Annual IEEE Applied Power Electronics Conference and Exposition, Charlotte, NC, USA,
Mar. 15–19, 2015, pp. 2678–2683. Dr. Davoudi provided useful discussions of results,
comments, and helped to revise the manuscript.
A part of chapter 5 has been submitted for peer review. Y. Tong, Z. Shan, N. M. Ho, and J.
Jatskevich, “Concept of synthesizing modular power supply for interfacing diverse energy
sources and loads.” Dr. Shan proofread the manuscript. Dr. Ho provided comments, suggestions,
and constructive feedback.
v
TABLE OF CONTENTS
ABSTRACT .................................................................................................................................... ii
PREFACE ...................................................................................................................................... iii
TABLE OF CONTENTS ................................................................................................................. v
LIST OF TABLES ....................................................................................................................... viii
LIST OF FIGURES ......................................................................................................................... ix
LIST OF ABBREVIATIONS ....................................................................................................... xii
ACKNOWLEDGEMENTS ......................................................................................................... xiii
CHAPTER 1: INTRODUCTION ..................................................................................................... 1
1.1 Motivation ....................................................................................................................... 1
1.2 Literature Review ............................................................................................................ 3
1.2.1 MISO Converters ................................................................................................... 4
1.2.2 SIMO Converters ................................................................................................... 5
1.3 Research Objectives of This Thesis ................................................................................ 5
1.4 Composition of the Thesis .............................................................................................. 6
CHAPTER 2: MIMO BUCK–BOOST CONVERTER WITH INDEPENDENT OUTPUTS ........ 8
2.1 Circuit Configuration and Operation Principle ............................................................... 8
2.2 Static Characteristics ....................................................................................................... 9
2.2.1 Operational Analysis of the Circuit ........................................................................ 9
2.2.2 Steady-State Analysis ............................................................................................. 9
2.2.2.1 CCM ............................................................................................................. 10
2.2.2.2 DCM ............................................................................................................. 13
2.3 Average-Value Modeling .............................................................................................. 15
2.4 Power Management and Control Strategy .................................................................... 17
2.4.1 Power Budgeting .................................................................................................. 17
2.4.2 Controller Design ................................................................................................. 17
2.5 Computer Studies .......................................................................................................... 19
2.5.1 System Response to Input Voltage Variation ....................................................... 19
vi
2.5.2 System Response to Output Load Variation ........................................................ 19
2.5.3 System Response to Input Power Variation ......................................................... 20
CHAPTER 3: MIMO FLYBACK CONVERTER WITH STACKED CAPACITORS ................ 24
3.1 Circuit Configuration and Operation Principle ............................................................. 24
3.2 Static Characteristics ..................................................................................................... 25
3.2.1 Operational Analysis of the Circuit ...................................................................... 25
3.2.2 Steady-State Analysis ........................................................................................... 26
3.2.2.1 CCM ............................................................................................................. 26
3.2.2.2 DCM ............................................................................................................. 27
3.3 Average-Value Modeling .............................................................................................. 30
3.4 Power Management and Control Strategy .................................................................... 31
3.5 Computer Studies .......................................................................................................... 33
3.5.1 System Response to Input Voltage Variation ....................................................... 33
3.5.2 System Response to Output Load Variation ........................................................ 34
3.5.3 System Response to Input Power Variation ......................................................... 34
CHAPTER 4: DERIVATION OF MIMO CONVERTERS BASED ON DC LINK ..................... 38
4.1 Basic Ideas for Deriving DLI- or DLC-Coupled MIMO Converters ............................ 38
4.2 Non-Isolated PSCs and Their Connection Rules .......................................................... 38
4.2.1 Basic PSCs ........................................................................................................... 38
4.2.2 Hybrid PSCs ......................................................................................................... 40
4.2.3 Connection Rules of PSCs ................................................................................... 41
4.2.3.1 Connection Rules of PVSCs ........................................................................ 41
4.2.3.2 Connection Rules of PCSCs ......................................................................... 41
4.3 Central Energy Buffer Element—DLI and DLC .......................................................... 42
4.3.1 DLI Cell ................................................................................................................ 42
4.3.2 DLC Cell .............................................................................................................. 42
4.4 FCs and Their Connection Rules .................................................................................. 43
4.4.1 C-FCs and Their Connection Rules ...................................................................... 43
4.4.2 LC-FCs and Their Connection Rules ................................................................... 44
4.5 Synthesis of Non-Isolated MIMO Converters .............................................................. 45
4.5.1 DLI-Coupled MIMO Converters .......................................................................... 45
4.5.2 DLC-Coupled MIMO Converters ........................................................................ 46
4.6 Zeta-Derived DLI-Coupled MIMO Converter .............................................................. 48
vii
4.6.1 State-Space Averaging ......................................................................................... 49
4.6.2 Design Considerations .......................................................................................... 51
4.6.3 Power Flow Management ..................................................................................... 52
4.6.4 Control Scheme .................................................................................................... 52
4.6.5 Case Studies ......................................................................................................... 54
CHAPTER 5: EXTENSION OF SISO CONVERTERS TO THEIR MIMO VERSIONS ............ 59
5.1 Isolated PSCs and Their Connection Rules .................................................................. 59
5.2 Basic Configuration of Conventional SISO Converters ............................................... 59
5.3 Realization of Multiport Structure ................................................................................ 61
5.3.1 Multiple-Input Structure ....................................................................................... 61
5.3.2 Multiple-Output Structure .................................................................................... 61
5.4 Synthesis of MIMO Converters .................................................................................... 62
5.5 Transformer-Coupled MIMO Converters ..................................................................... 66
CHAPTER 6: CONCLUSIONS ..................................................................................................... 70
6.1 Contributions of the Thesis ........................................................................................... 70
6.2 Future Work .................................................................................................................. 70
6.2.1 Practical Implementation ...................................................................................... 70
6.2.2 Controller Optimization ....................................................................................... 71
6.2.3 Non-Ideal MIMO Converters ............................................................................... 71
6.2.4 Bidirectional Multiport Converters ...................................................................... 71
REFERENCES ............................................................................................................................... 72
viii
LIST OF TABLES
5.1 Eligible blocks that can be replaced with multiport structure.............................................. 62
ix
LIST OF FIGURES
1.1 Example of residential low-voltage DC power distribution system. ...................................... 2
1.2 Conventional DC distribution system with multiple SISO converters. .................................. 3
1.3 Proposed DC distribution system with MIMO converter. ...................................................... 4
2.1 MIMO non-inverting buck–boost converter. .......................................................................... 9
2.2 Example switching strategy of MIMO non-inverting buck–boost converter. ...................... 10
2.3 Two operating stages of MIMO non-inverting buck–boost converter. ................................ 11
2.4 Discontinuous inductor current example. ............................................................................. 14
2.5 Control block diagram of the MIMO non-inverting buck–boost converter. ........................ 17
2.6 Simulated system response of the MIMO non-inverting buck–boost converter to
input voltage change. ............................................................................................................ 21
2.7 Simulated system response of the MIMO non-inverting buck–boost converter to load
change. .................................................................................................................................. 22
2.8 Simulated system response of the MIMO non-inverting buck–boost converter to
input power change. .............................................................................................................. 23
3.1 Example of MIMO flyback converter with a separate winding for each port. ..................... 25
3.2 Proposed MIMO flyback converter that minimizes the number of windings. ..................... 26
3.3 Gating signals of the MOSFETs for the proposed MIMO flyback converter. ..................... 27
3.4 Equivalent circuits of the MIMO flyback converter at two operating stages. ...................... 28
3.5 Block diagram of the proposed control structure for the MIMO flyback converter. ............ 33
3.6 Simulated system response of the MIMO flyback converter to input voltage variation. ..... 35
3.7 Simulated system response of the MIMO flyback converter to load variation. ................... 36
3.8 Simulated system response of the MIMO flyback converter to input power variation. ....... 37
4.1 Basic structure of MIMO converters based on DLI or DLC. ............................................... 39
4.2 Non-isolated basic PVSCs: (a) buck; (b) Ćuk; and (c) Zeta. ................................................ 39
4.3 Non-isolated basic PCSCs: (a) boost; (b) buck-boost; and (c) SEPIC. ................................ 39
4.4 Non-isolated hybrid PVSCs: (a) buck-Zeta; (b) Ćuk-Zeta; and (c) Zeta-Zeta. .................... 40
4.5 Non-isolated hybrid PVSCs: (a) boost-Ćuk; (b) buck–boost-Zeta; and (c) SEPIC-
Ćuk. ...................................................................................................................................... 40
4.6 Non-isolated hybrid PCSCs: (a) buck-buck–boost; (b) Ćuk-Buck–boost; and (c) Zeta-
buck–boost. ........................................................................................................................... 41
x
4.7 Non-isolated hybrid PCSCs: (a) boost-SEPIC; (b) buck-SEPIC; and (c) SEPIC-
SEPIC. .................................................................................................................................. 41
4.8 Combination of PSCs: (a) PVSCs in series; (b) PVSCs in parallel; (c) PCSCs in
series; and (d) PCSCs in parallel. ......................................................................................... 42
4.9 DC-link configurations: (a) DLI cell; and (b) DLC cell. ...................................................... 42
4.10 FCs: (a) C-FC; and (b) LC-FC.............................................................................................. 43
4.11 Combination of FCs: (a) C-FCs in series; (b) C-FCs in parallel; (c) LC-FCs in series;
and (d) LC-FCs in parallel. ................................................................................................... 43
4.12 Outputs taken from C-FCs: (a) series-connected C-FCs and series outputs; (b) series-
connected C-FCs and parallel outputs; and (c) parallel-connected C-FCs and parallel
outputs. ................................................................................................................................. 44
4.13 Outputs taken from LC-FCs: (a) series-connected LC-FCs and outputs; and (b)
parallel-connected LC-FCs and outputs. .............................................................................. 44
4.14 Buck-derived DLI-coupled MIMO Converters: (a) buck PVSCs in series and C-FCs
in series with series outputs; (b) buck PVSCs in parallel and C-FCs in series with
series outputs; (c) buck PVSCs in series and C-FCs in series with parallel outputs; (d)
buck PVSCs in parallel and C-FCs in series with parallel outputs; (e) buck PVSCs in
series and C-FCs in parallel with parallel outputs; and (f) buck PVSCs in parallel and
C-FCs in parallel with parallel outputs. ................................................................................ 46
4.15 Boost-derived DLC-coupled MIMO Converters: (a) boost PCSCs in series and LC-
FCs in series; (b) boost PCSCs in parallel and LC-FCs in series; (c) boost PCSCs in
series and LC-FCs in parallel; and (d) boost PCSCs in parallel and C-FCs in parallel. ....... 47
4.16 Zeta-derived DLI-coupled MIMO converter example. ........................................................ 48
4.17 Switching pattern for the Zeta-derived DLI-coupled MIMO converter. .............................. 48
4.18 Block diagram of the closed-loop system. ............................................................................ 53
4.19 Simulated waveforms of the Zeta-derived DLI-coupled MIMO converter in response
to step change in input voltage. ............................................................................................ 56
4.20 Simulated waveforms of the Zeta-derived DLI-coupled MIMO converter in response
to step change in load. .......................................................................................................... 57
4.21 Simulated waveforms of the Zeta-derived DLI-coupled MIMO converter in response
to one source missing. .......................................................................................................... 58
5.1 Isolated PVSCs: (a) full-bridge isolated buck; (b) push–pull isolated buck; and (c)
forward.................................................................................................................................. 60
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5.2 Isolated PCSCs: (a) full-bridge isolated boost; (b) push–pull isolated boost; and (c)
flyback. ................................................................................................................................. 60
5.3 General configuration of a SISO converter. ......................................................................... 61
5.4 Basic configuration of non-isolated SISO converter. ........................................................... 61
5.5 Basic configuration of isolated SISO converter. .................................................................. 61
5.6 Circuit configurations: (a) SISO buck converter; and (b) PVSC-source MIMO
converter generated by several buck PVSC in series and LC-FCs in series. ........................ 63
5.7 Circuit configurations: (a) SISO flyback converter; and (b) PCSC-source MIMO
converter generated by several flyback PCSCs in parallel and C-FCs in parallel. ............... 63
5.8 Circuit configurations: (a) SISO Zeta converter; and (b) MIMO Zeta converter with
parallel-connected buck PVSCs as inputs and parallel-connected LC-FCs as outputs. ....... 64
5.9 Circuit configurations: (a) SISO push–pull isolated boost converter; and (b) MIMO
push–pull isolated boost converter with parallel-connected boost PCSCs as inputs
and series-connected C-FCs as outputs. ............................................................................... 65
5.10 Circuit configurations: (a) SISO forward converter; and (b) PVSC-source MIMO
converter generated by several forward PVSCs in series and C-FCs in series. .................... 66
5.11 Circuit configurations: (a) SISO full-bridge isolated buck converter; and (b) MIMO
full-bridge isolated buck converter with series-connected buck PVSCs as inputs and
parallel-connected C-FCs as outputs. ................................................................................... 67
5.12 Basic structure of SPSSWTC MIMO converter. .................................................................. 68
5.13 Basic structure of SPMSWTC MIMO converter. ................................................................. 68
5.14 Basic structure of MPSSWTC MIMO converter. ................................................................. 68
5.15 Basic structure of MPMSWTC MIMO converter. ............................................................... 68
xii
LIST OF ABBREVIATIONS
AVM Average-Value Model
CCM Continuous Conduction Mode
C-FC Capacitor Filter Cell
DCM Discontinuous Conduction Mode
DLC DC-Link Capacitor
DLI DC-Link Inductor
DM Detailed Model
LC-FC Inductor-Capacitor Filter Cell
MIMO Multiple-Input Multiple-Output
MISO Multiple-Input Single-Output
MPMSWTC Multiple-Primary-Multiple-Secondary-Winding-Transformer-Coupled
MPSSWTC Multiple-Primary-Single-Secondary-Winding-Transformer-Coupled
FC Filter Cell
PCSC Pulsating Current Source Cell
PSC Pulsating Source Cell
PVSC Pulsating Voltage Source Cell
PWM Pulse-Width Modulation
SIMO Single-Input Multiple-Output
SISO Single-Input Single-Output
SPMSWTC Single-Primary-Multiple-Secondary-Winding-Transformer-Coupled
SPSSWTC Single-Primary-Single-Secondary-Winding-Transformer-Coupled
xiii
ACKNOWLEDGEMENTS
I offer my enduring gratitude to my advisor, Dr. J. Jatskevich, for his invaluable guidance and
strong support. He has provided me immense help and excellent advices. His kindness will
always be remembered. The financial support for this research was provided through the Natural
Science and Engineering Research Council (NSERC) of Canada, Collaborative Research and
Development Grant entitled “People and Planet Friendly Home” led by Dr. P. Nasiopoulos, and
the Institute for Computing, Information and Cognitive Systems (ICICS) of the University of
British Columbia.
I am also grateful to Dr. J. R. Martí and Dr. Y. Chen for dedicating their valuable time to serve
on my examining committee, and for all their useful comments and feedback that have helped to
improve the quality of this thesis.
Many special thanks go to Dr. Z. Shan, Dr. A. Davoudi, Dr. N. M. Ho, and Dr. C. K. Tse for
their helpful discussions and support.
I would also like to thank all my peers in the Electric Power and Energy Systems Group for
their technical support and wonderful friendship: Mr. H. Chang, Dr. M. Chapariha, Mr. C. L.
Chaw, Mr. L. Dong, Mr. Q. Han, Mr. Y. Huang, Mr. Y. Lei, Mr. M. Liu, Ms. S. Ren, Mr. J. C.
Shen, Mr. F. Therrien, Mr. Z. Wang, Ms. T. Xu, Mr. Y. Xu, Mr. B. Zhang, and Mr. K. Zhang. In
addition, I would like to extend my gratitude to the many friends and people who cared: Dr. C. He,
Ms. N. Rong, Ms. X. Sun, Ms. Y. Yang, and Mr. C. Zhu. I am also grateful to everyone who has
ever helped me. Although I am not able to mention all your names here, I want you to know this
thesis would not have been possible without your help.
Finally, warmest thanks go to my parents and my brother, for their understanding,
unconditional support, and endless love.
1
CHAPTER 1: INTRODUCTION
This chapter provides brief discussions of multiport DC–DC converters, which are envisioned as
key components that interact with other elements such as distributed generation and modern
electronic loads in future residential buildings and commercial facilities. Also included in this
chapter is a description of thesis objective and structure.
1.1 Motivation
Utilization of renewable energy sources on user premises has attracted a significant interest for
many commercial and industrial applications owing to their merits of non-pollution and rich
reserves. Due to the intermittent nature of renewable energy, storage and standby sources are
usually required to function as backup. A hybrid power system may lower environmental impacts
and improve security of supply. Besides, a simultaneous combination of sources is available for
optimal energy/economic dispatch. At the same time, many loads and appliances used in offices,
commercial facilities, and residential buildings often dictate the need of power supply with
different gains. Thus, the need of technology for distributing power to a variety of consumption
loads whose voltage levels are different motivates the development of supply structure with
multiple voltages.
Many distributed energy resources include but are not limited to solar panels and fuel cells
generate DC voltages, and a growing number of consumption loads and appliances are using DC,
e.g. data centers, portable devices, LED lights, etc. Thus, DC distribution systems are envisioned
to interact with different energy sources, modern electronic loads and storage units for simplicity
and efficiency [1]–[3]. Figure 1.1 shows a conceptual DC power distribution architecture for
future residential applications where wind and solar energy are interfaced, storage devices are
installed, and different loads are powered. Usually, there are two approaches to form such a
system with multiple ports. Conventionally, single-input single-output (SISO) converters are
arranged in parallel at a common DC bus to exchange power (Figure 1.2). In this architecture,
separate conversion stages are employed for individual sources and loads, and the converters
would be controlled independently. Thus, a communication system may be included to exchange
information and manage the power flow between different ports. Although such a configuration is
prevalent in distribution systems today, complex configurations generally result in a large number
of modules and high costs. In addition, the communication-based control system may cause
software delays and data errors, which would also degrade the performance of the system [4]. As
2
a prominent alternative, multiple-input multiple-output (MIMO) converter can replace the
complicated set-up, as pictured in Figure 1.3. In this integrated and single-stage conversion
architecture, voltage regulation and power management can be carried out simultaneously.
Additionally, compact packaging and relatively straightforward control become possible.
Though less attention has been given to the development of MIMO converters so far [5]–[8],
multiple-input single-output (MISO) converters and single-input multiple-output (SIMO)
converters have been well studied. In the established literature, MISO converters are identified as
a cost-effective and modular technology to incorporate more than one source. Applications of
using MISO converters for integrating sources with complementary nature have been found in
photovoltaic-utility systems [9]–[12], photovoltaic-wind systems [13]–[16], renewable generation
systems with battery backup [17]–[22], and hybrid electric vehicles [23]–[30]. Meanwhile, SIMO
converters are seen as an efficient power router to feed several loads. Many SIMO converters
have been reported in the literature for various applications, such as portable and electronic
devices [31]–[38], telecom and computer systems [39]–[41], fuel cell generation systems [42],
diode-clamped multilevel inverters [43]–[45], and others [46], [47].
The motivation of this thesis is to design MIMO converters, which can combine the
advantages of MISO and SIMO converters. The proposed MIMO converters can be a substitute
of the conventional architecture consisting of SISO converters to simplify the conversion
Figure 1.1. Example of residential low-voltage DC power distribution system.
3°C
AC
DC
3
structure and provide easy energy management. The reduced conversion stage may also improve
the power density and eliminate complicated conventional communication-based control issues
between individual conversion stages. With proper design, flexibility of source integration and
power dispatching may be enhanced for the distribution systems, while savings in manufacturing
cost and mass become achievable. Although the MIMO converter topologies discussed in this
thesis may only allow for unidirectional inputs, bidirectional power flow can be done extrinsically
by using additional converters (which is outside the scope of this thesis).
1.2 Literature Review
In general, the multiport converters, including MISO, SIMO, and MIMO converters, can be
classified into two categories: non-isolated topologies and isolated topologies.
The non-isolated topologies possess advantages of compact structure, low cost, high power
density and straightforward power flow control. A drawback of this kind of structure lies in the
fact that a wild range of voltage transformation is not easily obtainable and galvanic isolation is
not provided (even when it may be a requirement). Non-isolated MISO converters can be derived
from a single converter, i.e. buck [48], boost [49], buck–boost [50]–[52], Ćuk [53] and SEPIC
[54], [55], or a combination of several converters, such as buck/buck–boost [15], buck/SEPIC
[56]. Non-isolated SIMO converters can be obtained by connecting multiple outputs in an
independent manner [57], or piling them up [44].
Figure 1.2. Conventional DC distribution system with multiple SISO converters.
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Washing Machine Refrigerator LED Lighting
Solar Panels Wind Turbine Li-on Batteries
Electric Vehicle
4
Isolated topologies include a transformer and adjustment of voltage levels through changing
the transformer turns ratio could be beneficial to avoid the device handling high voltage and
current. However, complex circuitry and control strategy may mitigate the converters’
performance. Isolated MISO converters can be derived from flyback [9], [10], and bridge [58]–
[62] converters. Isolated SIMO converters may be generated from flyback [31], [32], [63],
forward [39], push-pull [64], and bridge [40] topologies. Moreover, derivations of isolated SIMO
converters can be based on a combination of flyback and forward converters [65], [66].
1.2.1 MISO Converters
Multiple input sub-circuits can be placed in parallel or series. In parallel configurations, MISO
converters can be obtained by adding primary windings and primary side sub-circuits of a
conventional flyback converter [9], [10], or paralleling the input sub-circuits of a buck–boost
converter [12], [50]. As these converters are designed in a time shared operation mode, only one
source is allowed to deliver power at a time. This limitation can be overcome by using current-
source converters. For example, [58] presented a full-bridge isolated boost converter, but the
number of required switches is four times the input ports. Reference [67] proposed a half-bridge
isolate boost topology. Though the number of switches is reduced by half, the need of inductors is
doubled. Therefore, it still makes the design inherently complex and costly. Other alternatives
include connecting the multiple input sub-circuits at trivial points, such as linking the SISO
converters by paralleling them at the output capacitor [24], [26]. Moreover, connection of
Figure 1.3. Proposed DC distribution system with MIMO converter.
Electric Vehicle Washing Machine Refrigerator LED Lighting
Multiple-Input Multiple-Output Converter
Solar Panels Wind Turbine Li-on Batteries
5
multiple input sub-circuits may occur in a series way [13], [14] to achieve simultaneous power
transfer. The authors of [68] and [69] also proposed a method in which the MISO converters are
accomplished by means of series-connected H-bridge cells.
1.2.2 SIMO Converters
SIMO converters can be obtained by placing sub-circuits in parallel or series at the output side. In
parallel configurations, a straightforward method to provide multiple outputs is to use a
transformer with multiple secondary windings. Based on this approach, two topologies are
commonly used due to simplicity and effectiveness, i.e. SIMO flyback and forward converters.
The SISO flyback converter topologies have fewer components, but face a cross-regulation
problem [70]. In order to keep all the output voltages tightly regulated, various approaches have
been proposed [71], [72]. Likely, SIMO forward converters also have a drawback of poor
regulation, and several methods are readily taken to improve the converters’ performance [73]–
[75]. Instead of using a transformer, the authors of [34] came up with a method to realize a
controlled current source and distribute the current to the outputs on an interleaving basis.
Authors of [57] introduced a class of topologies where only one inductor was implemented while
several outputs were regulated. The inductor is sequentially connected in a parallel output
arrangement with a number of loads via a switch-network. Some of the proposed topologies are
also capable of producing bipolar output voltages. In series configurations, the authors of [44] and
[46] presented a SIMO converter topology for applications in feeding multilevel inverters.
1.3 Research Objectives of This Thesis
The aim of this research project is to explore feasible power electronic converters for energy
harvesting and dispatching, which could be applied for the development of future low-voltage DC
distribution systems. The work presented in this thesis is mostly theoretical and it is supported
using the computer simulations wherever it is necessary.
In view of the current situation in DC microgrids, characteristics of distributed energy
resources and modern electronic loads, and the prospect in applications of multiport DC–DC
converters, the proposed converters should be able to accommodate variable energy sources, and
provide multiple outputs at different voltage levels. Specifically, this work shall include:
1) Topology design and detailed analysis of MIMO converters with/without a transformer. If
there is no requirement of galvanic isolation, compact structure and manufacturing cost are the
priority to be considered. Thus, topologies without incorporating transformers would be
6
preferred. Otherwise, isolated topologies should be implemented. Therefore, at least one non-
isolated and one isolated topologies shall be proposed and demonstrated.
2) Coordination and management of generation units connected to the converter, and tight
regulation of output voltages at different levels. Power flow control strategy needs to be
formulated, and the controller design and tuning for multivariable systems shall be investigated.
3) Simulation and dynamic modeling of MIMO converters. Detailed models (DMs) shall be
established to verify the converters’ feasibility. Analytical state-space averaging method and
numerically-constructed average-value models (AVMs) shall be derived for studying the dynamic
behavior of the new proposed converters in system-level analysis and transients.
4) Exploration and derivation of various feasible multiport DC power converter topologies. As
each converter has its own advantages and disadvantages, a systematic approach for constructing
MIMO converters for various applications and specifications is of significant value for the future
designers.
1.4 Composition of the Thesis
This thesis is organized in four parts. The first part comprises Chapter 1, which gives a literature
review on the previous and current developments of multiport DC–DC converters. The
motivation of pursuing research in this direction and objectives of this thesis are described.
The second part of this thesis, consisting of Chapter 2 and 3, outlines the concepts, features,
operating principles, control methods, and modeling of two typical MIMO converters.
Specifically, Chapter 2 presents a MIMO non-inverting buck–boost converter, where multiple
sources can supply power either individually or simultaneously. Also, positively referenced
output voltages are obtained without using any transformer, and sources with equal and unequal
voltages can be accommodated. Chapter 3 presents a MIMO flyback converter, which offers
galvanic isolation and precise voltage regulation. This topology is flexible and configurable to
provide double-polarity outputs and isolation, where it may be required.
The third part of this thesis, comprising of Chapter 4 and 5, introduces some approaches for
derivation of MIMO converters. Specifically, Chapter 4 presents the concept of pulsating source
cells (PSCs) [76] and filter cell (FCs) [77], which are used for interfacing sources and loads,
respectively. Various forms of PSCs and FCs are discussed. Derivation principles for non-isolated
topologies based on DC-link inductor (DLI) and DC-link capacitor (DLC) are presented. A
unified operation principle can be applied on these newly designed converters. The pursuit of
other approaches for synthesizing general MIMO converters is continued in Chapter 5, which
presents a set of rules to construct MIMO converters from existing basic SISO converters.
7
Finally, the forth part of this thesis, Chapter 6, gives conclusions by summarizing the major
findings and contributions of this work. The various areas for future work are highlighted.
8
CHAPTER 2: MIMO BUCK–BOOST CONVERTER WITH INDEPENDENT OUTPUTS
This chapter presents a non-isolated MIMO converter derived from non-inverting buck–boost
converter. The operation principle, pulse-width modulation, feed-back control strategy, and
dynamic modeling are presented and analyzed in detail. The AVM is demonstrated and compared
with DM.
2.1 Circuit Configuration and Operation Principle
The schematic diagram of the proposed MIMO non-inverting buck–boost converter is depicted in
Figure 2.1. The input voltages are Vin,i (i = 1,…, m) and the output voltages are Vout, j ( j = 1,…, n).
All the input switches Sin,i (i = 1,…, m) are bidirectional-carrying forward-blocking, and all the
output switches Sout, j ( j = 2,…, n) are forward-conducting bidirectional-blocking, except for Sout,1.
The bidirectional-carrying forward-blocking switch is realized by a MOSFET, and the forward-
conducting bidirectional-blocking switch is realized by a series MOSFET and diode pair. The
inputs can be arbitrarily ordered. For simplicity of analysis, the inputs are arranged in an
descending order of duty ratios; that is Din,1 > Din,2 > ··· > Din,m. The outputs are assumed to be
regulated such that Vout,1 > Vout,2 > ··· > Vout,n. All the MOSFETs operate at the same switching
frequency, and the gating signals are depicted in Figure 2.2. The trailing edges of the input and
output MOSFETs’ gating signals are synchronized, respectively. Switch S is on whenever any
input switch Sin,i (i = 1,…, or m) is on. It is off only when all the input switches are off.
The concept of the overlapping duty ratio Din, olp, i (i = 1,…, or m) of the input switch is defined
as the portion of time when there are i inputs supplying power at a time
, , 1
, ,,
, 1,..., 1
, .in i in i
in olp iin i
D D i mD
D i m+− = −
= = (2.1)
If two or more output switches conduct at a time, only the one connected to the lowest-voltage
output is on, and the others are off. The concept of the effective duty ratio Dout,eff , j ( j = 1,…, or n)
of the output switch is defined as the portion of time when the jth output switch Sout, j carries
nonzero current
, , 1
, ,, , 1 , , 1
0, 1,..., 1
, out j out j
out eff jout j out j out j out j
D DD j n
D D D D+
+ +
≤= = − − > (2.2)
where Dout,1 = 1 Din,1 and Dout, eff, n = Dout, n.
9
2.2 Static Characteristics
2.2.1 Operational Analysis of the Circuit
The basic principle of the MIMO non-inverting buck–boost converter is to charge the inductor L
from Vin,i (i = 1,…, or m) or their combination in one period, and discharge it to the output
capacitors C j and loads R j ( j = 1,…, n) in the subsequent period of a switching cycle Ts. Thus, the
converter exhibits two operating stages depending on the state of the inductor (refer to Figure 2.3).
Stage 1: The inductor is in charge-state. Switch S is on, at least one input switch Sin,i (i = 1,…,
or m) is on, and all the output switches Sout, j ( j = 1,…, n) are off. The inductor L is energized, and
power demands for the loads R j ( j = 1,…, n) are satisfied by discharging the output capacitors C j (
j = 1,…, n). There are m subintervals in this stage. If k input switches Sin,i (i = 1,…, k) are on,
power is delivered from the k inputs Vin,i (i = 1,…, k) simultaneously, and the inductor voltage VL is
Vin,1 + Vin,2 + ··· + Vin,k.
Stage 2: The inductor is in discharge-state. Switch S is off, and all the input switches Sin, i (i =
1,…, m) are off. The inductor L is discharged. If several output switches are on at a time, the
inductor voltage is equal to the lowest of the output voltages for which respective switch is on. In
this stage, there are n subintervals. The energy storage in inductor L is released to the output
capacitors C j and loads Rj ( j = 1,…, n) in a sequential manner.
2.2.2 Steady-State Analysis
In the following derivations, the converter is assumed to be lossless. The lower-case variables
represent the large-signal states, upper-case variables represent the equilibrium points, and the
hatted variables denote the small-signal perturbations. Both continuous conduction mode (CCM)
and discontinuous conduction mode (DCM) are analyzed.
Figure 2.1. MIMO non-inverting buck–boost converter.
S
+−
+
−
+
−
+
−+−
L
Vin, 1
Vin, m S in, m
S in, 1
S out, 1 S out, 2 S out, n
C1 C2 CnR1 R2 Rn
Vout , 1 Vout , 2 Vout , n
10
2.2.2.1 CCM
If the inductor carries nonzero current in steady state, CCM results. Assuming the output
capacitors are sufficiently large, averaging the inductor voltage over one switching cycle based on
the volt-second balance principle yields
, , , , , ,1 1 1
0.m i n
L in olp i in k out eff j out ji k j
V D V D V= = =
= − =∑ ∑ ∑ (2.3)
Applying the amp-second balance theorem on the output capacitors C j ( j = 1,…, n), the average
capacitor currents over one switching cycle are zero in steady state
,, , 0, 1,..., .
j
out jC out eff j L
j
VI D I j n
R= − = = (2.4)
The duty ratios usually vary with time, but for a given set of values one obtains
, , ,
1 1
2, ,
1
m i
in olp i in ki k
L n
out eff j jj
D VI
D R
= =
=
=∑∑
∑ (2.5)
, , ,
1 1, , ,
2, ,
1
, 1,..., .
m i
in olp i in ki k
out j j out eff j n
out eff j jj
D VV R D j n
D R
= =
=
= =∑∑
∑ (2.6)
Figure 2.2. Example switching strategy of MIMO non-inverting buck–boost converter.
Sin,1
Sin,2
Sin,m
Sout,n
Sout,2
Dout,eff,1Ts
Ts
S
Din,olp,1Ts Din,olp,mTs Dout,eff,nTs
11
Figure 2.3. Two operating stages of MIMO non-inverting buck–boost converter.
S
+−
+−
+−
+−
+−
+−
+−
+−
L
Stage 1
Stage 2
Vin, 1
Vin, m S in, m
S in, 1
+
−
S out, 1
C1 R1
Vout , 1
+
−
S out, n
Cn Rn
Vout , n
S
L
Vin, 1
Vin, m S in, m
S in, 1
+
−
S out, 1
C1 R1
Vout , 1
+
−
S out, n
Cn Rn
Vout , n
S
L
Vin, 1
Vin, m S in, m
S in, 1
+
−
S out, 1
C1 R1
Vout , 1
+
−
Cn Rn
Vout , n
S
L
Vin, 1
Vin, m S in, m
S in, 1
+
−
S out, 1
C1 R1
Vout , 1
+
−
S out, n
Cn Rn
Vout , n
S out, n
12
Provided the inductor current is piecewise-linear, the change in inductor current during its ith
charge subintervals Din,olp,iTs and its jth discharge subintervals Dout,eff, jTs are
, ,, ,
1
, 1,...,i
in olp i sL i in k
k
D Ti V i m
L+=
∆ = =∑ (2.7)
, ,, , , 1,..., .out eff j s
L j out j
D Ti V j n
L−∆ = = (2.8)
The total peak-to-peak inductor current ripple is the sum of (2.7) in the positive direction or
(2.8) in the negative direction
, , , ,1 1 1
m m is
L L i in olp i in ki i k
Ti i D V
L+= = =
∆ = ∆ =∑ ∑∑ (2.9)
, , , ,1 1
.n n
sL L j out eff j out j
j j
Ti i D V
L−= =
∆ = ∆ =∑ ∑ (2.10)
There are several forms in which the peak inductor current IL, peak can be expressed. On
simplification, it can be estimated by
, .2
LL peak L
iI I
∆= + (2.11)
Alternatively, identifying the area under the iL curve yields
( ) ( ), ,max , ,min, ,max , ,min
, , , ,1 12 2
m nL j L jL i L i
L s in olp i s out eff j si j
I II II T D T D T
− −+ +
= =
++= +∑ ∑ (2.12)
where IL+,i,max, IL+,i , min, IL, j, max and IL, j,min represent the maximum and minimum values of the
inductor current during its respective charge and discharge subintervals
, ,1, ,max
,
, 1,..., 1
,
m
L peak L kk iL i
L peak
I i i mI
I i m
+= ++
− ∆ = −= =
∑ (2.13)
, ,min , , , 1,...,m
L i L peak L kk i
I I i i m+ +=
= − ∆ =∑ (2.14)
,
1, ,max
, ,1
, 1
, 2,...,
L peak
jL j
L peak L kk
I j
II i j n
−−
−=
== − ∆ =
∑ (2.15)
, ,min , ,1
, 1,..., .j
L j L peak L kk
I I i j n− −=
= − ∆ =∑ (2.16)
13
Substitute (2.13)–(2.16) into (2.12) and solving
1
, , ,1 ,1 , , , , ,2 1
1
, , , , , , , ,1 1
1 1( )
2 2
1 1( ) .
2 2
m i
L peak L in olp L in olp k in olp i L ii k
n n
out eff k out eff j L j out eff n L nj k j
I I D i D D i
D D i D i
−
+ += =
−
− −= = +
= + ∆ + + ∆ +
+ ∆ + ∆
∑ ∑
∑ ∑ (2.17)
Expressions of IL+,i,max, IL+,i,min, IL, j,max and IL, j,min can be found by substituting (2.7)–(2.8) and
(2.17) into (2.13)–(2.16). Also, the average inductor currents over each charge and discharge
subintervals satisfy
, ,max , ,min, , 1,...,
2L i L i
L i
I II i m+ +
+
+= = (2.18)
, ,max , ,min, , 1,...,
2L j L j
L j
I II j n− −
−
+= = (2.19)
resulting in different form of the output voltage equations
, , , , , 1,..., .out j j out eff j L jV R D I j n−= = (2.20)
Again, to approximate the peak-to-peak voltage ripples on the output capacitors, the time constants
are assumed to be relatively large compared to the switching cycle Ts. The discharge of the
capacitor Cj occurs when the related output switch Sout, j is off. The linear-ripple approximation
leads to
, , ,,
(1 ), 1,2,..., .out eff j s out j
C jj j
D T Vv j n
C R
−∆ = = (2.21)
2.2.2.2 DCM
If the inductor current collapses to zero in its pth discharge subinterval (refer to Figure 2.4), the
MIMO converter is defined to operate in the pth discontinuous mode. Similar to CCM, the
inductor current is assumed to change linearly in each subinterval. Since the inductor current
starts from zero each switching cycle in DCM, the peak inductor current is given by
, , , , ,1 1 1
m m is
L peak L i in olp i in ki i k
TI i D V
L+= = =
= ∆ =∑ ∑∑ (2.22)
and the energy stored in the inductor at the very beginning when the inductor gets discharged is
0.5LI ²L, peak.
14
Assuming the converter is in the pth discontinuous mode, the effective duty ratio of the last
conducting output switch Sout,p may not be Dout,eff,p. The duration that takes the inductor to
completely discharge after p1 discharge subintervals is determined by
, ,max,
,
L pp
out p
It L
V−
−∆ = (2.23)
which is also the length of time when the inductor discharges to the pth output. Thus, the actual
effective duty ratio of Sout, p is
, , ,max, ,
,
' .p L peff out p
s out p s
t LID
T V T− −∆
= = (2.24)
Regarding Section 2.2.1, the inductor discharges to the first p outputs sequentially. The first
discharge state is illustrated for example. It takes the inductor Dout,eff ,1Ts to discharge to the first
output. At the end of this subinterval, the energy stored in the inductor is 0.5LI ²L ,1,min. Thus, the
amount of energy passing to the capacitor C1 and load R1 during Dout,eff ,1Ts is
2 2 2,1 , , ,1 , ,1 ,1
1 1 1( )
2 2 2L L peak L peak L L peak L LW LI L I i LI i L i− − − −∆ = − − ∆ = ∆ − ∆ (2.25)
where ∆iL ,1 = Dout,eff,1TsVout,1 / L. The energy stored in the capacitor C1 increases by
1
,1 ,12 21 ,1 1 ,1 1 ,1 ,1
1 1( ) ( )
2 2 2 2out out
C out out out out
v vW C V C V C V v
∆ ∆∆ = + − − = ∆ (2.26)
where ∆vout,1 = (1 Dout, eff, 1) Ts Vout,1 / C1R1, and the energy delivering to the load R1 is
1
2,1
, ,11
.outR out eff s
VW D T
R∆ = (2.27)
Figure 2.4. Discontinuous inductor current example.
∆iL_, j
0 t
iL
t_, p
IL, peak
IL_, p, max
Din, olp, iTs
∆iL+, i
Ts
∆Dout, eff, jTs
15
Applying the energy conservation law1 1,1L C RW W W−∆ = ∆ + ∆ , and performing several substitutions
and manipulations, the following equation is obtained
1 , , ,1,1 2
1 , ,1
2.
2L peak out eff
outout eff s
LR I DV
L R D T=
+ (2.28)
The variation of the inductor current in Dout, eff, 1Ts is then expressed as
2
, 1 , ,1
21 ,
,1,1
2.
2L peak out eff s
out eff sL
I R D T
L R Ti
D− +∆ = (2.29)
From (2.29), it can be observed that the inductor current decreases from IL ,2,max = IL, peak – ∆iL,1 in
the second discharge subinterval.
To summarize, the output voltages can be calculated as follows:
Step 1: Update the output effective duty ratios. The first p1 output effective duty ratios remain
at the commanded values, whereas the pth output effective duty ratio is modified as (2.24).
Step 2: Find out the starting-point of the inductor current in its jth discharge subinterval, that is,
IL, j,max, using (2.15).
Step 3: Solve the jth output voltage Vout, j according to (2.30).
Step 4: Determine ∆iL, j in terms of Vout, j (2.8).
Step 5: Repeat Step 2 to 4 until j reaches p.
, ,max , ,, 2
, ,
2.
2j L j out eff j
out jj out eff j s
LR I DV
L R D T−=
+ (2.30)
It is worth noting Vout, j ( j = p+1,…, n) are zero since the last n p outputs receive no power from
the inductor. The first p1 output voltages are in the form of (2.30), and the express ion of the pth
output voltage can be further simplified as
, , ,max .2
pout p L p
s
LRV I
T−= (2.31)
2.3 Average-Value Modeling
Average-value modeling is considered as an option to analyze nonlinear time-varying power
electronic systems. Although a number of techniques have been reported to acquire AVMs, state-
space averaging is a prevalent method. The resulting AVM is valid in a frequency range
adequately below the switching frequency. The following equations in this chapter are expressed
16
with respect to the commanded input duty ratios Din, i (i = 1,…, m) and output duty ratios Dout, j ( j
= 1,…, n), which can be alternatively constructed from the input overlapping duty ratios Din,olp,i (i
= 1,…, m) and output effective duty ratios Dout,eff , j ( j = 1,…, n).
If the inductor current and capacitor voltages are selected as state variables, the state equations
can be derived as
( )1
, , , , 1 , , ,1 1
m nL
in i in i out j out j C j out n C ni j
diL d v d d v d v
dt
−
+= =
= − − −∑ ∑ (2.32)
( ) ,, , 1
,
,,
, 1,..., 1
, .
C jout j out j L
jC jj
C jout j L
j
vd d i j n
RdvC
vdtd i j n
R
+
− − = −
= − =
(2.33)
When the input powers and output voltages are taken as the outputs, the output equations are
, , , , , , 1,...,in i in i in i in i L in ip v i v i d i m= = = (2.34)
, , , 1,..., .out j C jv v j n= = (2.35)
The input voltages vin,i (i = 1,…, m), input switch duty ratios din,i (i = 1,…, m), and output switch
duty ratios dout, j ( j = 1,…, n) are considered time variant, which can be represented as
, , ,ˆ , 1,...,in i in i in iv V v i m= + = (2.36)
, , ,ˆ , 1,...,in i in i in id D d i m= + = (2.37)
, ,,
, ,
ˆ , 1ˆ , 2,..., .
out j in jout j
out j out j
D d jd
D d j n
− == + =
(2.38)
In response to these inputs, the average inductor current iL, the average capacitor voltages vC, j ( j =
1,…, n), the average input powers pin,i (i = 1,…, m), and the average output voltages vout, j (j = 1,…,
n), can be expressed as equilibrium points plus small-signal perturbations as follows
ˆL L Li I i= + (2.39)
, , ,ˆ , 1,...,C j C j C jv V v j n= + = (2.40)
, , ,ˆ , 1,...,in i in i in ip P p i m= + = (2.41)
, , ,ˆ , 1,..., .out j out j out jv V v j n= + = (2.42)
17
2.4 Power Management and Control Strategy
2.4.1 Power Budgeting
For fixed input voltages, there could be an infinite number of combinations of duty ratios to yield
the same output voltages. Accordingly, different power flow can be realized. That means it is
feasible to change the ratio of the amount of power supplied by each input without changing the
total power delivered to the loads while keeping the output voltages at desired levels.
In a practical system, the generated power from each input can be managed by regulating the
current, voltage or power based on applicable specifications. However, the total power consumed
by the outputs must be equal to the total power supplied by the inputs. In order to maintain the
power balance, one of the inputs should behave as a slake source. For instance, the power coming
from the first input Pin,1 is relaxed while the others Pin,i (i = 2,…,m) are regulated; that is,
,1 , ,1 2
n m
in out j in ij i
P P P= =
= −∑ ∑ (2.43)
where
, , , , 2,...,in i in i L in iP V I D i m= = (2.44)
2
,, , 1,..., .out j
out jj
VP j n
R= = (2.45)
2.4.2 Controller Design
For an m-input n-output converter, it is possible to regulate the n outputs at near-constant voltages
and operate the m1 inputs at near-constant powers; that is, m1 input powers are selected as the
control objectives as well as the n output voltages, i.e. Din,i (i = 1,…, m) and Dout, j ( j = 2,…, n)
are the control variables for the controller.
Figure 2.5. Control block diagram of the MIMO non-inverting buck–boost converter.
+ PI
PI
PI
∆y1
∆y2
∆ym+n-1
H J
*
*
*
∆y1
∆y2
∆ym+n-1
_
+_
+_
18
Assuming the proposed converter is operating in a given region, the output voltages and input
powers can be alternatively expressed in terms of Din, i (i = 1,…, m) and Dout, j ( j = 1,…, n) as
follows
( )
( )
( )
, , 1 , ,1
12 2
, , 1 ,1
,
, , ,1
1 2 2, , 1 ,
1
, 1,..., 1
,
m
j out j out j in k in kk
n
out k out k k out n nk
out j m
j out j in k in kk
n
out k out k k out n nk
R D D D Vj n
D D R D R
V
R D D Vj n
D D R D R
+=
−
+=
=−
+=
− = − − +=
= − +
∑
∑
∑
∑
(2.46)
( )
, , , ,1
, 1 2 2, , 1 ,
1
, 2,..., .
m
in i in i in k in kk
in i n
out k out k k out n nk
V D D VP i m
D D R D R
=−
+=
= =− +
∑
∑ (2.47)
Replacing Dout,1 with 1 Din,1 and rewriting (2.46) and (2.47) in matrix form
( ) ( ) ( ) ( ) ( )( )T
,1 ,2 , ,2 ,( ) , ,..., , ,...,out in in n out out mV P P V V=Y D D D D D D (2.48)
where D = (Din,1,…, Din,m, Dout,2,…, Dout,n)T.
Vector-function Y represents the proposed nonlinear system, and is intended to be linearized
around an equilibrium point D* for a control-oriented model
( )* * * *( ) ( ) ( ) ( )ο= + − + −Y D Y DD DD D DJ (2.49)
where J is the Jacobian matrix of Y with respect to D
,1 ,1 ,1 ,1
,1 , ,2 ,
,2 ,2 ,2 ,2
,1 , ,2 ,
, , , ,
,1 , ,2 ,
,2 ,2
,1 ,
out out out out
in in m out out n
in in in in
in in m out out n
in m in m in m in m
in in m out out n
out out out
in in m
V V V V
D D D D
P P P P
D D D D
P P P P
D D D D
V V V
D D
∂ ∂ ∂ ∂∂ ∂ ∂ ∂∂ ∂ ∂ ∂∂ ∂ ∂ ∂
∂ ∂ ∂ ∂=
∂ ∂ ∂ ∂∂ ∂ ∂∂ ∂
J
⋯ ⋯
⋯ ⋯
⋮ ⋱ ⋮ ⋮ ⋱ ⋮
⋯ ⋯
⋯,2 ,2
,2 ,
, , , ,
,1 , ,2 ,
.
out
out out n
out n out n out n out n
in in m out out n
V
D D
V V V V
D D D D
∂ ∂ ∂ ∂ ∂ ∂ ∂ ∂ ∂ ∂ ∂
⋯
⋮ ⋱ ⋮ ⋮ ⋱ ⋮
⋯ ⋯
(2.50)
19
Therefore, the relationship between the controls and the outputs around equilibrium operating
point D* is
∆ = ∆Y J D (2.51)
where J represents the gain matrix of the proposed MIMO non-inverting buck–boost converter.
Figure 2.5 shows the control block diagram. The compensator matrix H can be described as
follows. With (2.51) written as ∆Y = J∆D*, the term ∆D* is defined as a modified vector, i.e. ∆D*
= H∆D. In this manner, the goal of the matrix H is to make JH a diagonal matrix. A
straightforward design is to choose H as the inverse of the gain matrix, namely J1 . Thereafter,
separate PI controllers can be implemented in the overall system to control the outputs.
2.5 Computer Studies
A triple-input triple-output non-inverting buck–boost converter is examined. The input voltage
are Vin,1 = 120 V, Vin,2 = 96 V and Vin,3 = 90 V. The output voltages are regulated at Vout,1 = 190 V,
Vout,2 = 24 V and Vout,3 = 12 V, whereas R1 = 5 Ω, R2 = 10 Ω and R3 = 20 Ω define the loads at the
corresponding outputs. Whenever the power demand is higher than the generation from Vin,2 and
Vin,3, the input Vin,1 supplies the deficit power. Whenever the loads require less power than the
generation from Vin,2 and Vin,3, surplus power is stored separately or the power reference should be
changed appropriately. Both Pin,2 and Pin,3 are regulated at 1 kW.
2.5.1 System Response to Input Voltage Variation
To investigate the dynamic performance of the proposed converter, a change in Vin,3 from 90 V to
60 V is performed. Figure 2.6 shows the simulation results of the DM and AVM. As it can be
observed, the output voltages are tightly controlled. As the reference value of Pin,3 does not
change and the total power fed to the loads remains constant, the deficit power due to a drop in
Vin,3 is compensated by increasing Iin,3. Thus, Pin,3 is regulated at the desired level. The output
voltages undergo a small transient when Vin,3 steps down. The ratio of the power drawn from
these three sources stays the same and the power is stably provided to all the loads. The
simulation results of DM and AVM closely match in both steady state and transient.
2.5.2 System Response to Output Load Variation
Figure 2.7 illustrates the transient response due to a change in load R1 from 5 Ω to 3 Ω. As can be
seen from Figure 2.7, the output voltages return to the desired levels after transient when R1 is
20
reduced to 3 Ω. The Pin,2 and Pin,3 are regulated to keep track of the command values, whereas the
increased power demand is automatically supplied by Vin,1. The output voltages are regulated by
receiving adequate power from Vin,1 even if R1 changes. It is clearly shown that the desired power
management is achieved, drawing constant powers from Pin,2 and Pin,3 while variation in the load
demand takes place. Figure 2.7 demonstrates the behaviors of the DM and AVM, which match
very well in both steady state and transient. This study confirms converter’s capability to
autonomously match the load variation while the Pin,2 and Pin,3 are kept around the reference values
and output voltages are held stable.
2.5.3 System Response to Input Power Variation
Figure 2.8 shows the response of the controlled MIMO non-inverting buck–boost converter to a
reference change in Pin,2 from 1 kW to 2 kW. As can be observed, the output voltages undergo a
transient and return to specified levels. The reference for Pin,3 is fixed at 1 kW to deliver constant
power. Therefore, Pin,3 returns to its specified level after transient. Since Pin,2 is taking a larger
part in power demand of the loads, Pin,1 automatically decreases to maintain the power balance.
The results of the DM and AVM are in good agreement, as expected, which verifies the
derivations presented in this chapter. Also, it validates the proposed MIMO converter can alter
the ratio of the amount of power supplied by each input in case of constant load.
21
Figure 2.6. Simulated system response of the MIMO non-inverting buck–boost converter to input
voltage change.
4.5
5
5.5
Pin
,1 (
kW)
0.9
1
1.1
Pin
,2 (
kW)
0.4
0.6
0.8
1
Pin
,3 (
kW)
170
180
190
200
Vou
t,1 (
V)
a) DMb) AVM
20
25
Vou
t,2 (
V)
10
12
14
Vou
t,3 (
V)
0.1 s
22
Figure 2.7. Simulated system response of the MIMO non-inverting buck–boost converter to load
change.
6
8
10
Pin
,1 (
kW)
a) DMb) AVM
0.8
1
1.2
1.4
1.6
Pin
,2 (
kW)
0.8
1
1.2
1.4
1.6
Pin
,3 (
kW)
140
160
180
200
Vou
t,1 (
V)
20
25
Vou
t,2 (
V)
0.1 s
6
8
10
12
14
Vou
t,3 (
V)
23
Figure 2.8. Simulated system response of the MIMO non-inverting buck–boost converter to input
power change.
3.5
4
4.5
5
5.5
Pin
,1 (
kW)
1
1.5
2
Pin
,2 (
kW)
a) DMb) AVM
0.9
1
1.1
Pin
,3 (
kW)
185
190
195
200
Vou
t,1 (
V)
222426
Vou
t,2 (
V)
10
12
14
16
18
Vou
t,3 (
V)
0.1 s
24
CHAPTER 3: MIMO FLYBACK CONVERTER WITH STACKED CAPACITORS
In this chapter, an isolated MIMO converter is investigated. The operation principle is given, and
a specific switching pattern is proposed. A multivariable control scheme is presented that enables
budgeting the input powers coming from different sources in addition to regulating several output
voltages. Both DM and AVM are provided to validate the operation of the proposed MIMO
converter.
3.1 Circuit Configuration and Operation Principle
Conventional flyback converter is a good topology to derive isolated MIMO converter. In fact,
there exist two methods to expand the flyback converter to its MIMO version. One is to use a
transformer with a separate winding for each input and output, as shown in Figure 3.1. In this case,
all the ports are galvanically isolated, though the MIMO converter is kind of paralleling flyback
converters on one core. The other is to connect the inputs on a single winding at the primary side
of the transformer and the outputs on the other single winding at the secondary side, as pictured in
Figure 3.2. The second topology is preferable due to its reduced parts count and compact structure.
Figure 3.2 shows the proposed MIMO flyback converter. The primary side sub-circuit consists
of m input legs in parallel, and the secondary side sub-circuit consists of n output legs in parallel.
Each input and output leg contains a forward-conducting bidirectional-blocking switch except for
the first output leg interfacing Vout,1. The forward-conducting bidirectional-blocking switch is
realized by a series pair of a MOSFET and a diode. The output capacitors are shared between
every two outputs. For instance, C1 is placed between Vout,1 and Vout,2. The transformer is modeled
as a magnetizing inductance LM in parallel with an ideal transformer and the turns ratio is defined
as 1/N.
The inputs and outputs can be arranged such that Vin,1 > Vin,2 > ··· > Vin,m and Vout,1 > Vout,2 > ··· >
Vout,n. The switching pattern is demonstrated in Figure 3.3. All the MOSFETs operate at the same
frequency. The input MOSFETs are synchronized with the same turn-on transition but different
turn-off moments, and the output MOSFETs are synchronized with the same turn-off transition but
different turn-on moments. The duty ratios of the input switches Sin,i and output switches Sout, j are
denoted by Din, i and Dout, j, respectively. Although Sout,1 is uncontrollable, abstract gating signal is
assigned on it to simplify the converter analysis, i.e. Dout,1 = 1 – maxDin,i. If two or more input
switches conduct at a time, only the one connected to the highest input voltage could be on.
Similarly, if two or more output switches conduct at a time, only the one connected to the lowest
25
output voltage could be on. Effective duty ratios Din, eff, i and Dout, eff, j are defined as the portion of
time when the corresponding switches conduct
, , 1
, ,, , 1 , , 1
0, 2,...,
, in i in i
in eff iin i in i in i in i
D Di m
D D D DD −
− −
≤= = − >
(3.1)
, , 1
, ,, , 1 , , 1
0 1,..., 1
, out j out j
out eff jout j out j out j out j
D Dj n
D D DD
D+
+ +
≤= = − − > (3.2)
where Din,eff,1 = Din,1 and Dout,eff, n = Dout, n.
3.2 Static Characteristics
3.2.1 Operational Analysis of the Circuit
The operation principle of the proposed MIMO flyback converter is to charge the transformer in
one period of a switching cycle Ts, and discharge it in the following period. The converter
operation can be divided into two stages. The equivalent circuits of the converter in these two
stages are shown in Figure 3.4.
Stage 1: The transformer is in charge-state, and one of the input switches is on. There are m
subintervals. The transformer is charged by the inputs from the lowest index to the highest. When
Sin,p is on and the others are off, voltage applied on the transformer’s primary winding is Vin,p.
Stage 2: The transformer is in discharge-state, all the input switches are off, and one of the
output switches is on. Similarly, there are n subintervals. The transformer is discharged to outputs
Figure 3.1. Example of MIMO flyback converter with a separate winding for each port.
Vin, 1
Vin, mS in, m
S in, 1 S out, 1
S out, n
C1
Cn
+−
Na
Nb
Nc
Nd+−
+
−
Vout , 1R1
Rn
+
−
Vout , n
26
in an increasing order of indices. When Sout,q is on and the rest are off, voltage applied on the
transformer’s secondary winding is Vout,q. Referring it to the primary side is Vout,q / N.
3.2.2 Steady-State Analysis
3.2.2.1 CCM
The volt-second balance principle implies the average voltage of the magnetizing inductance LM
is zero in steady state. Considering an ideal converter, one obtain
, , , , , ,1 1
10.
m n
L in eff i in i out eff j out ji j
V D V D VN= =
= − =∑ ∑ (3.3)
In addition, the capacitor charge balance implies
,, , ,
1 1
10, 1,..., .
j jout k
C j out eff k Lk k k
VI D I j n
N R= =
= − = =∑ ∑ (3.4)
Solving (3.3) and (3.4)
2, , ,
1
2, ,
1
m
in eff i in ii
L n
out eff j jj
N D VI
D R
=
=
=∑
∑ (3.5)
, , ,
1, , ,
2, ,
1
, 1,..., .
m
in eff i in ii
out j out eff j j n
out eff k kk
N D VV D R j n
D R
=
=
= =∑
∑ (3.6)
Figure 3.2. Proposed MIMO flyback converter that minimizes the number of windings.
vL
+
_
transformer model
1:N
Vin, 1+−
Vin, 2+−
Vin, m+−
S in, 1
S in, 2
S in, m
S out, 2
S out, 1
S out, n
C1
CnLM
iL
Vout , 1R1
Vout , 2R2
Vout , nRn
C2
27
Assuming the switching frequency is faster than the inductor dynamics, the shape of the
magnetizing current is a polygonal curve. Thus, the peak-to-peak magnetizing current ripple is
, , ,1
ms
L in eff i in iiM
Ti D V
L =∆ = ∑ (3.7)
or
, , ,1
.n
sL out eff j out j
jM
Ti D V
NL =∆ = ∑ (3.8)
The output voltage ripples are approximated with the same assumption as
, ,
1, ,
1
(1 ), 1,..., .
j
out eff k s jk
C j out kkj
D Tv I j n
C=
=
−∆ = =
∑∑ (3.9)
3.2.2.2 DCM
DCM occurs when the proposed MIMO flyback converter operates at light load. The converter is
defined to operate in the hth discontinuous mode if the energy stored in the magnetizing
inductance is released completely during the hth transformer-discharge subinterval. It is worth
noting that the switch Sout,h may not conduct for the whole duration Dout,eff,hTs if the converter is in
the hth discontinuous mode. The actual effective duty ratio Dout,eff,h of the hth output switch is then
Figure 3.3. Gating signals of the MOSFETs for the proposed MIMO flyback converter.
Sin,1
Sin,m−1
Sin,m
Sout,1
Sout,n−1
Sout,n
Din,eff,1Ts
Ts
Din,mTs
Dout,eff,n−1Ts
Dout,eff,nTs
28
Figure 3.4. Equivalent circuits of the MIMO flyback converter at two operating stages.
vL
+
_
1:N
Vin, 1
Vin, m
S in, 1
S in, m
S out, 1
S out, n CnLM
iL
Vout , 1R1
Vout , nRn
C1
vL
+
_
1:N
Vin, 1
Vin, m
S in, 1
S in, m
S out, 1
S out, n CnLM
iL
Vout , 1R1
Vout , nRn
C1
Stage 1
Stage 2
vL
+
_
1:N
Vin, 1
Vin, m
S in, 1
S in, m
S out, 1
S out, n CnLM
iL
Vout , 1R1
Vout , nRn
C1
vL
+
_
1:N
Vin, 1
Vin, m
S in, 1
S in, m
S out, 1
S out, n CnLM
iL
Vout , 1R1
Vout , nRn
C1
+−
+−
+−
+−
+−
+−
+−
+−
29
1
, , , , , ,1 1
, ,,
.
m h
in eff i in i out eff j out ji j
out eff hout h
N D V D V
DV
−
= =
−=∑ ∑
(3.10)
The effective duty ratios of the output switches before the hth transformer-discharge
subinterval stage the same and those after it become zero. In the following derivations of this
section, updated effective duty ratios of the output switches are used.
The magnetizing current ripples in each transformer-charge and -discharge subinterval are
, , , , , 1,...,s
L i in eff i in iM
Ti D V i m
L+∆ = = (3.11)
, , , , , 1,..., .s
L j out eff j out jM
Ti D V j n
NL−∆ = = (3.12)
Since in DCM the magnetizing current starts from zero each switching cycle, the magnitude of
the magnetizing current is
, , , , ,
1 1
m ms
L peak L i in eff i in ii iM
TI i D V
L+= =
= ∆ =∑ ∑ (3.13)
and the initial value of the magnetizing current in the jth transformer-discharge subinterval is
,
1, ,max
, ,1
, 1
, 2,..., .
L peak
jL j
L peak L kk
I j
II i j n
−−
−=
== − ∆ =
∑ (3.14)
The voltage ripple of the output capacitor can be expressed as
, ,
1, ,
1
(1 ), 1,..., .
j
out eff k s jk
C j out kkj
D Tv I j n
C=
=
−∆ = =
∑∑ (3.15)
Assuming the MIMO flyback converter is in the jth transformer-discharge subinterval, the
amount of energy stored in the transformer released to the capacitors and loads during this period
is
2 2, , ,max
,2 2
, 1,max , ,max
( ), 12
( ), 2,..., .2
ML peak L j
L jM
L j L j
LI I j
PL
I I j n
−
− − −
− =∆ = − =
(3.16)
All the energy passes to the capacitors and loads. The net energy transferred to the pth capacitor
Cp during the jth transformer-discharge subinterval is
30
2 2
, , ,max , , 1,max, ,
( ), 2
0,
pC p j C p j
C p j
CV V p j
P
p j
+ + −
− ≥∆ =
<
(3.17)
where VC+, p, j, max is the maximum value of the pth capacitor voltage in the jth transformer-
discharge subinterval
, , ,
, 1, , ,max ,
, ,1
.2
j
C p out eff kC p k
C p j C p p
out eff kk
v Dv
V V
D
=+
=
∆∆= − +
∑
∑ (3.18)
Meanwhile, the energy passing to the pth load Rp during the jth transformer-discharge subinterval
is
, , , ,, ,
,
0, .out eff j out p out p
R p j
D V I p jP
p j
≥∆ = <
(3.19)
This yields the energy balance equation for the jth transformer-discharge subinterval, which has
the following form
, , , , ,1
( ).n
L j C k j R k jk
P P P=
∆ = ∆ + ∆∑ (3.20)
Substituting (3.16), (3.17) and (3.19) into (3.20), the output voltages might be solved.
3.3 Average-Value Modeling
As explained in Section 3.2, the converter operation is divided into two stages: (1) the
transformer is in the charge-state; (2) the transformer is in the discharge-state. To facilitate the
explanation of the operation of the proposed MIMO flyback converter, the differential equations
for these two stages are derived.
Stage 1: When Sin, p is on, the differential equations describing the converter behavior are
,L
M in p
diL v
dt= (3.21)
,
,
, 1 ,1
, 1
, 2,...,
nC k
k j jC jj n
C j C kj
k j j
vj
RdvC
dv vdtC j n
dt R
=
−−
=
− == − =
∑
∑ (3.22)
, , , 1,...,n
out j C kk j
v v j n=
= =∑ (3.23)
31
,,
,
0, 1,..., 1, 1,..., .L
in iin i
i i pi
i i p p m
== = = − +
(3.24)
Stage 2: When Sout, q is on, the system are represented by
,
1 nL
M C kk q
diL v
dt N == − ∑ (3.25)
,
, 1 ,,1
, 1 ,1
, 1
, 2,..., 1, 1,...,
1,
nC k
k j j
nC j C kC j
jjk j j
nC j C k
L jk j j
vj
R
dv vdvC j q q nC
dt Rdt
dv vi C j q
N dt R
=
−−
=
−−
=
− = − = − += + − =
∑
∑
∑
(3.26)
, , , 1,...,
n
out j C kk j
v v j n=
= =∑ (3.27)
, 0, 1,..., .in ii i m= = (3.28)
Considering (3.21)–(3.28), the AVM of the MIMO converter is derived as follows
, , , , , ,
1 1
1m n nL
M in eff i in i out eff j C ki j k j
d ddi
L v vdt N= = =
= −∑ ∑∑ (3.29)
, ,
, ,1 1
1, 1,...,
j j nC j C k
j in eff k Lk s k s s
dv vC i j n
dtd
N R= = =
= − =∑ ∑∑ (3.30)
, , , 1,...,
n
out j C kk j
v v j n=
= =∑ (3.31)
, , , , 1,..., .in i in eff i Li i i md= = (3.32)
3.4 Power Management and Control Strategy
For an m-input n-output flyback converter, it has m+n MOSFETs, but only m+n1 of them can be
independently controlled. If the n output voltages are desired to keep at specific values, it is
unable to regulate the m input powers simultaneously. Assuming a lossless converter, the
following equation based on the power balance principle is obtained
, ,
1 1
m n
in i out ji j
P P= =
=∑ ∑ (3.33)
where Pin,i and Pout, j denote the input and output powers, respectively.
32
2, , ,
1, , , , , ,
2, ,
1
, 1,...,
m
in eff k in kk
in i in i in i in eff i in i n
k out eff kk
N D VP V I D V i m
R D
=
=
= = =∑
∑ (3.34)
2
,, , 1,..., .out j
out jj
VP j n
R= = (3.35)
According to the conservation of power principle, one of the inputs should not be directly
regulated. For instance, the first input is relaxed while the rest are regulated to deliver
commanded powers. The output formulas are composed of (3.6) and (3.34) except for the
equation of Pin,1. They can be alternatively expressed in terms of commanded duty ratios Din, i and
Dout, j instead of the effective duty ratios Din,eff,i and Dout,eff, j. In matrix form, one obtains
( )T
,1 ,2 , ,2 ,( ) ( ), ( ), , ( ), ( ), , ( )out in in m out out nV P P V V=Y D D D D D D… … (3.36)
where D = (Din,1, …, Din,m, Dout,2, …, Dout,n)T. The Taylor series of (3.36) around an equilibrium
point D* can be expressed using Jacobian matrix J of Y with respective to D
( ) ( ) ( )( )∗ ∗ ∗−= +Y D Y D J D D D (3.37)
where
,1 ,1 ,1 ,1
,1 , ,2 ,
,2 ,2 ,2 ,2
,1 , ,2 ,
, , , ,
,1 , ,2 ,
,2 ,2
,1 ,
out out out out
in in m out out n
in in in in
in in m out out n
in m in m in m in m
in in m out out n
out out out
in in m
V V V V
D D D DP P P P
D D D D
P P P P
D D D DV V V
D D
∂ ∂ ∂ ∂∂ ∂ ∂ ∂∂ ∂ ∂ ∂∂ ∂ ∂ ∂
∂ ∂ ∂ ∂=
∂ ∂ ∂ ∂∂ ∂ ∂∂ ∂
J
⋯ ⋯
⋯ ⋯
⋮ ⋱ ⋮ ⋮ ⋱ ⋮
⋯ ⋯
⋯,2 ,2
,2 ,
, , , ,
,1 , ,2 ,
.
out
out out n
out n out n out n out n
in in m out out n
V
D D
V V V V
D D D D
∂
∂ ∂ ∂ ∂ ∂ ∂ ∂ ∂ ∂ ∂
⋯
⋮ ⋱ ⋮ ⋮ ⋱ ⋮
⋯ ⋯
(3.38)
The control-to-output relationship can be derived using the linearization of the static
characteristic of the proposed MIMO flyback converter around an operating point. It can be
observed that interactions exist between different loops, which shall be mitigated by a
compensation network H. The product JH needs to be diagonal, enabling the required
decoupling. For simplicity, it can be chosen that JH = diag(1,…,1)T. Thus, multiple PI controllers
33
G1,…, Gm+n1 , as depicted in Figure 3.5, can be implemented to regulate the input powers and
output voltages. By tuning the coefficients of the PI controllers, one can obtain a desired dynamic
performance of the overall system.
3.5 Computer Studies
A double-input double-output flyback converter is examined here to verify the proposed concept.
Two input DC voltages are defined as Vin,1 = 120 V and Vin,2 = 50 V. A transformer with turns
ratio N = 1/2 is incorporated, and two resistive loads are assumed to be connected to the
converter, which are represented by R1 = 1 Ω and R2 = 1 Ω, respectively. The input power from
the second input Pin,2 is regulated at 1.5 kW, and the output voltages are adjusted to maintain at
Vout,1 = 48 V and Vout,2 = 24 V, respectively.
3.5.1 System Response to Input Voltage Variation
To demonstrate the converter performance under variability of input voltage, variation in Vin,2
from 50 V to 60 V is applied. As can be seen from Figure 3.6, the input power Pin,2, is regulated in
addition to the output voltages. As the preset point of the second input power does not move,
power supplied by the second source remains the same as before, which results in Pin,1 keeping
constant by adjusting the duty ratios through the controller. It also indicates the closed-loop
behavior matches in both steady state and transient between the DM and AVM.
Figure 3.5. Block diagram of the proposed control structure for the MIMO flyback converter.
J 11
J x1
J 1x
J xx
Σ
Σ
H11
Hx1
H1x
Hxx
Σ
Σ
∆Y1
∆Yx
G1
Gx
-+∆Y1
*
∆Yx*
-+
H J
x=m+n-1
34
3.5.2 System Response to Output Load Variation
To demonstrate the converter performance under variability of load, a step-change in R1 from 1 Ω
to 0.7 Ω is considered. The system response is depicted in Figure 3.7. As shown, the output
voltages undergo a transient as the controller regulates the output voltages to the specified
reference values. The power extracted from the first input increases to compensate for the deficit
power, while the second input is regulated to deliver constant power. Thus, Pin,2 has a transient
but returns to the same reference level of 1.5 kW.
3.5.3 System Response to Input Power Variation
To demonstrate the converter performance under variability of input power, the preset point of
the second input power Pin,2 is moved from 1.5 kW to 1 kW. The corresponding transient response
of the converter is pictured in Figure 3.8. Obtainable from the figure, the decreased amount of
power from the second source results in more power drawn from the first source; that is, the first
source supplies the power difference between the required power of the loads and readily
available power from the second source. Meanwhile, the output voltages undergo a transient and
return to their specified reference values.
35
Figure 3.6. Simulated system response of the MIMO flyback converter to input voltage variation.
1.2
1.3
1.4
1.5
1.6
1.4
1.6
1.8
2a) DMb) AVM
45
50
55
Vou
t,1 (
V)
22
24
26
28
Vou
t,2 (
V)
Pin
,1P
in,2
(kW
) (
kW)
0.1 s
36
Figure 3.7. Simulated system response of the MIMO flyback converter to load variation.
1
1.5
2
2.5
a) DMb) AVM
1.2
1.4
1.6
1.8
2
40
45
50
Vou
t,1 (
V)
20
25
30
Vou
t,2 (
V)
0.1 s
Pin
,1P
in,2
(kW
) (
kW)
37
Figure 3.8. Simulated system response of the MIMO flyback converter to input power variation.
1.2
1.4
1.6
1.8
2
0.8
1
1.2
1.4
1.6
46
48
50
Vou
t,1 (
V)
a) DMb) AVM
23
24
25
Vou
t,2 (
V)
0.1 s
Pin
,1P
in,2
(kW
) (
kW)
38
CHAPTER 4: DERIVATION OF MIMO CONVERTERS BASED ON DC LINK
This chapter provides a description of PSCs, FCs, DLI, and DLC that are used to make up non-
isolated MIMO converters. Connection rules of PSCs and FCs are introduced. A uniform
structure is put forward for generating MIMO converters based on DLI and DLC. The synthesis
procedures are presented.
4.1 Basic Ideas for Deriving DLI- or DLC-Coupled MIMO Converters
As can be seen from the MIMO non-inverting buck–boost and flyback converters, the converter
is a cascade connection of multiple inputs, inductor/transformer, and multiple outputs. Within an
appropriate switch network, the inductor or transformer accumulates energy from the inputs in
one period, and releases energy to the outputs in the subsequent period. The inductor and
transformer function as central energy buffer element, and multiple inputs and outputs are
interconnected through them. Based on this concept, the non-isolated MIMO converters can be
realized by coupling multiple PSCs and FCs to an intermediate DC link with necessary switches
(Figure 4.1). The DC-link quantity can be expressed by an inductor or a capacitor.
The PSCs and FCs can be categorized into two types. One is voltage type, which includes
pulsating voltage source cells (PVSCs) [76] and capacitor filter cells (C-FCs) [77]. These type
cells either source or sink voltage. The other is current type, which includes pulsating current
source cells (PCSCs) [76] and inductor-capacitor filter cells (LC-FCs) [77]. These type cells
either source or sink current. The voltage-type cells shall be interconnected through DLI and the
current-type cells shall be interconnected through DLC.
4.2 Non-Isolated PSCs and Their Connection Rules
4.2.1 Basic PSCs
The concept of non-isolated PSCs, including PVSCs and PCSCs, are presented here. Three
PVSCs extracted from buck, Ćuk, and Zeta converters are presented in Figure 4.2, and three
PCSCs extracted from boost, buck–boost, and SEPIC converters are demonstrated in Figure 4.3.
The PVSC is composed of a DC voltage source and a switch network. It provides a high-
frequency pulse-wave voltage. When the active switch is on, the terminal voltage of the PVSC
has a nonzero value. When the active switch is off, the terminal voltage is zero. The supplied
power can also be properly controlled through the active switch.
39
The PCSC consists of a DC current source and a switch network. It generates a pulsating
current. When the active switch is on, the outgoing current is zero. When the active switch is off,
the outgoing current has a nonzero value. Independent power flow control is also achieved by
closing and opening the active switch. It should be mentioned the DC current source in PCSC is
not ideal, but realized by a DC voltage source associated with an inductor in practice. Thus, if a
PCSC is disconnected from the circuit for a long time to stop providing power and the active
switch in the PCSC is kept on, the inductor would get overcharged resulting in destruction of
devices.
Figure 4.1. Basic structure of MIMO converters based on DLI or DLC.
Figure 4.2. Non-isolated basic PVSCs: (a) buck; (b) Ćuk; and (c) Zeta.
Figure 4.3. Non-isolated basic PCSCs: (a) boost; (b) buck-boost; and (c) SEPIC.
Combination of Multple PSCs
DLI/DLCwith Switches
Combination of Multple FCs
PSC 1
PSC 2
PSC m
FC 1
FC 2
FC n
Vout , 1
Vout , n
+−
+−
+−
+
−
+−+
−
(a) (b) (c)+
− +−
Vin Vin Vin
+−
+−
+−
(a) (b) (c)
−+
Vin Vin Vin
40
4.2.2 Hybrid PSCs
In non-isolated topologies, the inductor and capacitor play the role of energy buffer. Auxiliary
PSCs can be inserted to provide additional energy to the inductor or/and capacitor of a primary
PSC besides the original source. In fact, auxiliary PVSC can be placed in series with an inductor of
a primary PSC to obtain hybrid PVSC. Auxiliary PCSC can be placed in parallel with a capacitor
of a primary PSC to obtain hybrid PCSC.
Figure 4.4 shows some hybrid PVSCs, where auxiliary PVSCs—buck, Ćuk, and Zeta are
inserted in series with an inductor of Zeta primary PVSC, respectively, and Figure 4.5 shows some
hybrid PVSCs, where auxiliary PCSCs—boost, buck–boost, and SEPIC, are placed in parallel with
a capacitor of Ćuk primary PVSC, respectively. Similarly, hybrid PCSCs can be obtained by
inserting auxiliary PVSC to the inductor branch and/or paralleling auxiliary PCSC with the
capacitor. Figures 4.5 and 4.6 show some hybrid PCSCs based on buck–boost and SEPIC primary
PCSCs. Although the above developed and discussed hybrid PSCs are limited to two inputs,
hybrid PSCs with more than two inputs can also be synthesized by the same principle.
Figure 4.4. Non-isolated hybrid PVSCs: (a) buck-Zeta; (b) Ćuk-Zeta; and (c) Zeta-Zeta.
Figure 4.5. Non-isolated hybrid PVSCs: (a) boost-Ćuk; (b) buck–boost-Zeta; and (c) SEPIC-
Ćuk.
+−
+
−
(a)
+−
Vin,1
+−Vin,2
+−
+
−
(b)
+−
Vin,1
+−
+ −
Vin,2
+−
+
−
(c)
+−
Vin,1
+−
+−
Vin,2
+−
+−
(a)+
−
Vin,1
+−
Vin,2
+−
+−
(b)+
−
Vin,1
+−Vin,2
+−
+−
(c)+
−
Vin,1
+−
−+
Vin,2
41
4.2.3 Connection Rules of PSCs
4.2.3.1 Connection Rules of PVSCs
Multiple PVSCs can be connected in series or parallel, as demonstrated in Figure 4.8(a) and (b). In
series configurations, multiple PVSCs supply power individually or simultaneously. In parallel
configurations, since PVSCs may have different terminal voltages, appropriate switch arrangement
is required to prevent them from being directly connected together. The apparent limitation of
parallel configurations is that only one source is allowed to supply power at a time.
4.2.3.2 Connection Rules of PCSCs
Multiple PCSCs can be connected in series or parallel, as shown in Figure 4.8(c) and (d). In series
configurations, multiple PCSCs can be connected in a manner without violating Kirchhoff’s
current law provided that only one PCSC delivers power at a time. Additional switches are
Figure 4.6. Non-isolated hybrid PCSCs: (a) buck-buck–boost; (b) Ćuk-Buck–boost; and (c) Zeta-
buck–boost.
Figure 4.7. Non-isolated hybrid PCSCs: (a) boost-SEPIC; (b) buck-SEPIC; and (c) SEPIC-
SEPIC.
+−
(a)
Vin,1
+−Vin,2
+−
(b)
Vin,1
+−
+ −
Vin,2
+−
(c)
Vin,1
+−
+−
Vin,2
+−
(a)
−+
Vin,1
+−
Vin,2
+−
(b)
−+
Vin,1
+−Vin,2
+−
(c)
−+
Vin,1
+−
−+
Vin,2
42
required to prevent direct series connection; that is, when a PSCS supplies power, it is essential to
insulate other PCSCs. As the DC current source of PCSC is not ideal, series configurations may
only work under some constraints. In parallel configurations, the multiple PCSCs supply power
individually or simultaneously.
4.3 Central Energy Buffer Element—DLI and DLC
4.3.1 DLI Cell
Figure 4.9(a) shows the DLI within a switch network. It is used to interconnect voltage-type cells.
The active switch is on when power is deposited, and it is off when power is withdrawn. When
the active switch is in on-state, DLI is connected to the PVSCs. Energy is stored temporarily in a
magnetic field. When the active switch is off, the diode conducts to provide a bypass path for the
inductor current and the DLI is connected to the C-FCs. Energy is transferred from the magnetic
field through the C-FCs to the loads.
4.3.2 DLC Cell
Figure 4.9(b) shows the DLC within a switch network. It is used to interconnect current-type
cells. The active switch is off as long as the DLC accumulates energy, and it is off when the DLC
Figure 4.8. Combination of PSCs: (a) PVSCs in series; (b) PVSCs in parallel; (c) PCSCs in series;
and (d) PCSCs in parallel.
Figure 4.9. DC-link configurations: (a) DLI cell; and (b) DLC cell.
−
+
−
+
(a) (b) (c) (d)
PVSC 1
PVSC m PVSC 1 PVSC m
PCSC 1
PCSC 1PCSC n PCSC n
−
(a)
++
−
(b)
−
+
43
releases energy. When the active switch is in off-state, the DLC is connected to the PCSCs.
Energy is transferred from the PCSCs and stored electrostatically in an electric field. Voltage of
the DLC increases. When the PCSCs no longer supply energy to the DLC, the active switch
conducts and the diode blocks reverse current. The DLC is connected to the LC-FCs, and the
energy is released from the electric field through the LC-FCs to the loads. Also, voltage of the
DLC drops.
4.4 FCs and Their Connection Rules
4.4.1 C-FCs and Their Connection Rules
The C-FC, as shown in Figure 4.10(a), is a first-order low-pass filter or a voltage sink leaking
constant voltage. When constructing multiple-output structure using C-FCs, necessary switches
are needed to avoid shorting the capacitors. In other words, multiple C-FCs need to be placed
within a switch network. Similar to the combination of multiple PVSCs, the C-FCs can be
connected in series or parallel, as pictured in Figure 4.11(a) and (b). When multiple C-FCs are
connected in series, the C-FCs are capable to draw power simultaneously from the DLI. There
exist alternative ways to place the loads so that different output voltages can be obtained. Figure
4.12(a) and (b) show two examples. One is to place a load across each capacitor, and the other is
to place a load across several capacitors. The case in Figure 4.12(a) renders equal-output-voltage
Figure 4.10. FCs: (a) C-FC; and (b) LC-FC.
Figure 4.11. Combination of FCs: (a) C-FCs in series; (b) C-FCs in parallel; (c) LC-FCs in series;
and (d) LC-FCs in parallel.
(a) (b)
C-FC LC-FC
PCSC PVSC VoutVout
−
+
−
+
(a) (b) (c) (d)
C-FC 1
C-FC m
LC-FC 1
LC-FC n LC-FC 1 LC-FC nC-FC 1 C-FC m
44
and the case in Figure 4.12(b) enables a common ground for the loads. When multiple C-FCs are
connected in parallel, a common ground is obtained, but energy flows through the C-FCs one-by-
one. Figure 4.12(c) depicts the circuit diagram including loads.
4.4.2 LC-FCs and Their Connection Rules
The LC-FC, as shown in Figure 4.10(b), is a second-order low-pass filter or a current sink leaking
constant current. Multiple LC-FCs can be connected in series or parallel, as shown in Figure
4.11(c) and (d). Similar to construct multiple-output using C-FCs, necessary switch arrangements
are required for putting multiple LC-FCs together. When LC-FCs are connected in series, an
Figure 4.12. Outputs taken from C-FCs: (a) series-connected C-FCs and series outputs; (b) series-
connected C-FCs and parallel outputs; and (c) parallel-connected C-FCs and parallel outputs.
Figure 4.13. Outputs taken from LC-FCs: (a) series-connected LC-FCs and outputs; and (b)
parallel-connected LC-FCs and outputs.
−
+
−
+
(a) (b) (c)
−
+
−
+
−
+
−
+
−
+
−
+
−
+
Series Connection of C-FCs Series Connection of C-FCs Parallel Connection of C-FCs
−
+
(a) (b)
−
+
−
+
−
+
Series Connection of LC-FCs Parallel Connection of LC-FCs
45
active switch is lumped together with each LC-FC. However, the LC-FCs can only be
individually charged from the DLC. The diagram with a load placed at each capacitor is depicted
in Figure 4.13(a). When multiple LC-FCs are connected in parallel, a diode is placed in parallel
with each LC-FC. The diode is used for circulating current when the designated LC-FC is
disconnected. An active switch is also used for insulating the LC-FC when it does not sink power.
Thus, independent power flow control can be achieved. In parallel configurations, the LC-FCs
can draw power individually or simultaneously, and a common ground is available for the loads.
The resulting circuit with loads is shown in Figure 4.13(b).
4.5 Synthesis of Non-Isolated MIMO Converters
As shown in Figure 4.1, the DLI or DLC is employed to create an interface between multiple PSCs
and FCs. DLI-coupled and DLC-coupled MIMO converters are then generated, respectively.
4.5.1 DLI-Coupled MIMO Converters
As the average current of the inductor shall not depend on the connected PSCs or FCs, DLI is used
to link the multiple PVSCs and multiple C-FCs. The synthesis of the DLI-coupled MIMO
converters is briefly described as follows:
Step 1: Choose appropriate PVSCs and combine them according to the connection rules
described in Section 4.2.3.1.
Step 2: Construct the multiple-output structure by combining the C-FCs based on the
connection rules described in Section 4.4.1.
Step 3: Link the multiple PVSCs and multiple C-FCs with DLI.
Figure 4.14 shows six DLI-coupled MIMO converter topologies generated by using buck
PVSCs and C-FCs. The subfigures in the first and second columns show topologies synthesized by
series-connected and parallel-connected multiple buck PVSCs, respectively. In series input
configurations, as the freewheeling diodes associated with the DLI is redundant, it can be
removed. Also, the PVSCs can supply power to the DLI either individually or simultaneously. In
parallel input configurations, a diode is inserted in series with MOSFET of each PVSC to avoid
direct parallel connection. Thus, only one PVSC is allowed to deliver power at a time. The
subfigures in the first two rows of Figure 4.13 depict MIMO converters with series-connected
multiple C-FCs, and the subfigures in the last row show topologies with parallel-connected C-FCs.
In the series output configurations, the loads draw power from the DLI through C-FCs
simultaneously. In parallel output configurations, the loads can only draw power individually.
46
4.5.2 DLC-Coupled MIMO Converters
As the average voltage of the capacitor shall not depend on the connected PSCs or FCs, DLC is
used to link the multiple PCSCs and multiple LC-FCs. The synthesis of DLC-coupled MIMO
converters is described as follows:
Figure 4.14. Buck-derived DLI-coupled MIMO Converters: (a) buck PVSCs in series and C-FCs
in series with series outputs; (b) buck PVSCs in parallel and C-FCs in series with series outputs;
(c) buck PVSCs in series and C-FCs in series with parallel outputs; (d) buck PVSCs in parallel
and C-FCs in series with parallel outputs; (e) buck PVSCs in series and C-FCs in parallel with
parallel outputs; and (f) buck PVSCs in parallel and C-FCs in parallel with parallel outputs.
+−Vin,1
+−Vin,m
+−Vin,1
+−Vin,m
+−Vin,1
+−Vin,m
(a)
(d)
(f)
+−Vin,1
+−Vin,m
(b)
(c)
+−Vin,1
+−Vin,m
(e)
+−Vin,1
+−Vin,m
+
−
Vout , 1
+
−
Vout , n
+
−
Vout , 1
+
−
Vout , n
+
−
Vout , 1
+
−
Vout , n
+
−
Vout , 1
+
−
Vout , n
+
−
Vout , 1
+
−
Vout , n
+
−
Vout , 1
+
−
Vout , n
47
Step 1: Choose appropriate PCSCs and combine them according to the connection rules
described in Section 4.2.3.2.
Step 2: Construct the multiple-output structure by combining the LC-FCs based on the
connection rules described in Section 4.4.2.
Step 3: Link the multiple PCSCs and multiple LC-FCs with DLC.
Following the synthesis procedure, four DLC-coupled MIMO converter topologies are
generated by using boost PCSCs and LC-FCs, as shown in Figure 4.15. The subfigures in the first
and second columns of Figure 4.15 show topologies synthesized by series-connected and parallel-
connected multiple boost PCSCs, respectively. In series input configurations, the MOSFET of
each PCSC also provides a freewheeling path for other PCSCs when it does not supply power
externally. In this case, only one PCSC is allowed to supply power to the DLC at a time. In
parallel input configurations, the diode associated with the DLC is removed due to redundancy.
Also, power can be supplied simultaneously from the PCSCs. The subfigures in the first and
second rows of Figure 4.15 depict MIMO converters with series-connected multiple LC-FCs and
loads, and parallel-connected multiple LC-FCs and loads, respectively. In the series output
Figure 4.15. Boost-derived DLC-coupled MIMO Converters: (a) boost PCSCs in series and LC-
FCs in series; (b) boost PCSCs in parallel and LC-FCs in series; (c) boost PCSCs in series and
LC-FCs in parallel; and (d) boost PCSCs in parallel and C-FCs in parallel.
+−
+−
Vin,1
Vin,m
+−
Vin,1
+−
Vin,m
(c)
(b)
(d)
+−
+−
Vin,1
Vin,m
+−
Vin,1
+−
Vin,m
(a)
+
−
Vout , 1
+
−
Vout , n
+
−
Vout , 1
+
−
Vout , n
+
−
Vout , 1
+
−
Vout , n
+
−
Vout , 1
+
−
Vout , n
48
configurations, only one load is allowed to draw power from the DLC through the LC-FC
because series connection of current sources should be avoided. In parallel output configurations,
the loads can draw power through the LC-FCs either individually or simultaneously.
4.6 Zeta-Derived DLI-Coupled MIMO Converter
The layout of a newly designed MIMO converter is shown in Figure 4.16, where m series-
connected Zeta PVSCs and n parallel-connected C-FCs are linked by DLI Lc. The PVSCs are
arranged in a descending order of the MOSFETs’ duty ratios din,1 > din,2 > ··· > din,m, and the C-
FCs are ordered such that vout,1 > vout,2 > ··· > vout,n.
The switching scheme is demonstrated in Figure 4.17 with switching cycle of Ts. The trailing
edges of the gating signals of the input MOSFETs coincide, so as the output MOSFETs. The
Figure 4.16. Zeta-derived DLI-coupled MIMO converter example.
Figure 4.17. Switching pattern for the Zeta-derived DLI-coupled MIMO converter.
Vout ,1
Vout,n
Sout, 1
Sout,n
S
Cout,n
Cout,1
Lc
Rout,n
+−
+−
Rout, 1
Vin, 1
Vin, m
S in, 1
S in, m
D in, 1
D in, m
L in, 1
C in, 1
L in, m
C in, m
Sin,1
Sin,2
Sin,m
Sout,n
Sout,2
Ts
Sout,1
Dout,eff,1Ts
Dout,eff,nTs
Din,olp,mTs
49
main switch S is on whenever there is any input switch Sin,i (i = 1,…, or m) on; it is off only when
all the input switches Sin,i (i = 1,…, m) are off. The following equality is satisfied
,1
.m
in ii
d d=
=∪ (4.1)
Here, din,i (i = 1,…, m) and dout, j (j = 1,…, n) denote the commanded input and output duty ratios,
and d denotes the duty ratio of S. As Sout,1 is simplified as a diode here, it does not need gating
signal. However, to simplify the model formulation, virtual gating signal dout,1 = 1 d is assigned
on it.
The concepts of the overlapping duty ratio of the input switch din,olp,i and effective duty ratio of
the output switch dout,eff, j are defined same as in Section 2.1
, , ,
1, ,
, , , , , ,1 1
0,
1,..., 1
,
m
in i in olp kk i
in olp i m m
in i in olp k in i in olp kk i k i
d d
d i m
d d d d
= +
= + = +
≤= = − − >
∑
∑ ∑ (4.2)
, , ,
1
, ,
, , , , , ,1 1
0,
1,..., 1
,
n
out j out eff kk j
out eff j n n
out j out eff k out j out eff kk j k j
d d
d j n
d d d d
= +
= + = +
<= = − − ≥
∑
∑ ∑ (4.3)
where din,olp,m = din,m and dout,eff,n = dout,n.
There are m+n switching subintervals. In each subinterval, either different combinations of
sources are utilized, or one load is powered. Thus, m+n states exist in the system.
4.6.1 State-Space Averaging
For an m-input n-output converter, the state-space description of the converter in each subinterval
can be expressed as
1,...,k k
k k
k m n= +
= + = +
Kx A x B u
y C x E u
ɺ (4.4)
where x is a state vector containing the inductor currents and capacitor voltages, y is an output
vector containing m input powers and n output voltages, u is an input vector containing the input
voltages. K is a matrix containing the inductances and capacitances. Matrices Ak, Bk, Ck, and Ek
contain constants of proportionality. Given these state equations, one obtains
50
= +
= +
Kx Ax Bu
y Cx Eu
ɺ (4.5)
where
, , , ,1 1
, , , ,1 1
, , , ,1 1
, , , ,1 1
.
m n
in olp i i out eff j m ji j
m n
in olp i i out eff j m ji j
m n
in olp i i out eff j m ji j
m n
in olp i i out eff j m ji j
d d
d d
d d
d d
+= =
+= =
+= =
+= =
= +
= + = + = +
∑ ∑
∑ ∑
∑ ∑
∑ ∑
A A A
B B B
C C C
E E E
(4.6)
It is worth to note the first output’s effective duty ratio dout,eff,1 is not controllable. Therefore, it has
to be expressed in terms of the other output effective duty ratios and input overlapping duty ratios
as
, ,1 , , , ,1 2
1 .m n
out eff in olp i out eff ji j
d d d= =
= − −∑ ∑ (4.7)
Considering (4.7), (4.6) can be modified as follows
, , 1 , , 1 11 2
, , 1 , , 1 11 2
, , 1 , , 1 11 2
, , 11
( ) ( )
( ) ( )
( ) ( )
( )
m n
in olp i i m out eff j m j m mi j
m n
in olp i i m out eff j m j m mi j
m n
in olp i i m out eff j m j m mi j
m
in olp i i m oui
d d
d d
d d
d d
+ + + += =
+ + + += =
+ + + += =
+=
= − + − +
= − + − +
= − + − +
= − +
∑ ∑
∑ ∑
∑ ∑
∑
A A A A A A
B B B B B B
C C C C C C
E E E , , 1 12
( ) .n
t eff j m j m mj
+ + +=
− +
∑ E E E
(4.8)
Alternatively, one can obtain the following form of the state equations
,
,
, ,
,
,
, , , , , ,
, , , , ,1 1
, , , , ,
(1 ) , 1,...,
( )
(1 ) , 1,.
in i
in i
c
in i out j
in i
c in i
m mL
in i in olp k in i in olp k ck i k i
m m nL
c in olp k in i c out eff j Ci k i j
m mC
in i in olp k L in olp k Lk i k i
diL d v d v i m
dt
diL d v v d v
dt
dvC d i d i i
dt
= =
= = =
= =
= − − =
= + −
= − + − =
∑ ∑
∑∑ ∑
∑ ∑
, ,
, , ,
..,
, 1,...,out i out i
c
C C
out j out eff j Lj
m
dv vC d i j n
dt R
= − =
(4.9)
51
,
,
, , , ,
,
( ), 1,...,
, 1,..., .
c in i
out j
m
in i in olp k in i L Lk i
out j c
p d v i i i m
v v j n=
= + = = =
∑ (4.10)
To obtain the steady-state input powers and output voltages, all time-derivative terms in (4.9)
and (4.10) are set to zero, which yields
, ,
, , , , ,, ,1
, ,2
, ,1
(1 )
, 1,...,1
out eff k
m m mm
in olp p in k in olp pin olp kk p k p kk i
in i in i m n
in olp k kk i k
D V DDP V i m
D D R
= = ==
= =
−= =
−
∑∑ ∑∑
∑ ∑ (4.11)
, ,
, , , , ,1
, , ,2
1
(1 )
, 1,..., .
out eff k
m m m
in olp p in k in olp pk p k p k
out j out eff j j n
kk
D V D
V D R j nD R
= = =
=
−= =
∑∑ ∑
∑ (4.12)
4.6.2 Design Considerations
The parameters of the proposed converter’s components need to be properly selected. These
include all the inductances and capacitances. Assuming time constants are relatively large with
respect to the switching cycle, the inductor current ripples and capacitor voltage ripples can be
calculated based on the linear-ripple approximation. The selection of input inductances Lin,i (i =
1,…, m) is similar as that in a conventional converter. When the input switch Sin,i is on, the
voltage across inductor Lin,i is Vin,i. Then
,
, ,
, ,
, 1,...,in iL
in i in im
in olp k sk i
IL V i m
D T=
∆= =
∑ (4.13)
where ,in iLI∆ is the desired peak-to-peak current ripple of the inductor Lin,i. Thus, if
,in iLI∆ needs to
be controlled within a certain value , (max)in iLI∆ , the following inequality should be satisfied
,
, , ,
,(max)
, 1,..., .in i
m
in olp k in i sk i
in iL
D V TL i m
I=≥ =
∆
∑ (4.14)
Similarly, if a maximum inductor current ripple (max)cLI∆ is required, the central inductance Lc
would be determined as follows
, , , , ,1(max)
(1 ).c
m m ms
c in olp k in i in olp ki k i k iL
TL D V D
I = = =≥ −
∆ ∑∑ ∑ (4.15)
52
In steady state, when the ith input switch Sin,i is off, the current flowing through the ith input
capacitor is the ith input inductor current
,
,,
, ,
, 1,..., .(1 )
in i
in i
C
in i Lm
in olp k sk i
VC I i m
D T=
∆= =
−∑ (4.16)
If the input capacitors’ voltage ripple is limited within a specific value , (max)in iCV∆ , the input
capacitance should satisfy the following conditions:
,
, ,
, , , , ,, , , ,1
,2(max)
, ,1
(1 )(1 ), 1,..., .
1in iout eff k
m m mm m
in olp p in k in olp pin olp k s in olp kk p k p kk i k i
in i m nC
in olp k kk i k
D V DD T D
C i mV
D D R
= = == =
= =
−−≥ =
∆ −
∑∑ ∑∑ ∑
∑ ∑ (4.17)
Also, if the output capacitance is selected to comply with the maximum allowable voltage ripples
, (max)out jCV∆
,
, , ,,
(max)
, 1,..., .out j
out eff j s out jout j
C j
D T VC j n
V R≥ =
∆ (4.18)
4.6.3 Power Flow Management
The MIMO converter should be capable of controlling several input powers synergistically and
coping with power mismatch among different inputs. As it is not possible to regulate all the input
powers and output voltages at the same time, one of the inputs is relaxed.
If power losses are neglected and a steady-state operating point is assumed, the energy
conservation principle implies that the total power supplied by the inputs must be equal to the
total power consumed by the outputs
, ,
1 1
.m n
in i out ji j
P P= =
=∑ ∑ (4.19)
where the output powers are calculated as
,
2
, , 1,..., .Cout j
out jj
VP j n
R= = (4.20)
4.6.4 Control Scheme
A multivariable controller is proposed to regulate the input powers and output voltages
simultaneously. For an m-input n-output converter, it has m+n1 degrees of freedoms. Here, the
53
last m1 input powers are regulated at command values in addition to the n output voltages. The
controller design and stability assessment often require the control-to-output transfer function
extracted from small-signal model using the state-space averaging technique. For this purpose,
the average model described in (4.5) is linearized around an equilibrium operating point. The
steady-state terms are removed from the perturbed equations, and only the small-signal linear
terms and nonlinear terms are considered. The higher-order perturbation terms are negligible
since they are very small. Also, the variations of the input voltages are neglected and the
commanded duty ratios are alternatively constructed from the input overlapping and output
effective duty ratios. In matrix form, the small-signal model of the open-loop system is
ˆˆ ˆ
ˆˆ ˆ
= +
= +
Kx Ax Bd
y Cx Ed
ɺ ɶ ɶ
ɶ ɶ (4.21)
where x, y , and dare perturbations around equilibrium points
,1 , ,1 , ,1 ,
T
T,1 ,2 , ,2 ,
T,1 ,2 , ,2 ,
ˆ ˆ ˆˆ ˆ ˆ ˆ ˆ( ,..., , , ,..., , ,..., )
ˆ ˆ ˆ ˆ ˆ ˆ( , ,..., , ,..., )
ˆ ˆ ˆ ˆ ˆˆ ( , ,..., , ,..., )
in in m c in in m out out nL L L C C C C
out in in m out out n
in in in m out out n
i i i v v v v
v p p v v
d d d d d
= =
=
x
y
d
(4.22)
and Aɶ , Bɶ , Cɶ , and Eɶ are coefficient matrices of open-loop system.
A multivariable controller, as shown in Figure 4.18, can be implemented to regulate the input
powers and output voltages, which can be described as
Figure 4.18. Block diagram of the closed-loop system.
-+ PI11
PI1c-+
sampling circuit
MIMOC
PIc1
PIcc
++
M
* c = m+n−1
y r v ˆ ˆ ˆ
ˆ ˆ ˆ
= +
= +
Kx Ax Bv
y Cx Ev
ɺ ɶ ɶ
ɶ ɶ
++
54
IP s
= + KM K (4.23)
where KP is the proportional gain matrix and KI is the integral gain matrix. The state-space
description of the closed-loop system is then derived as follows
ˆ ˆˆ
ˆˆ
ˆˆˆ
ˆ
= +
= +
xK 0 xA Br
0 I pp
xy C Er
p
ɺ
ɺ (4.24)
where r is the reference vector, p is the defined as ˆ ˆ ˆ= −p r yɺ , and A ,B,C, and E are the state,
input, output, and feedforward matrices of the closed-loop system
( )
11 12
21 22
1
2
1 2
1( )P P−
=
=
= = +
A AA
A A
BB
B
C C C
E I EK EKɶ ɶ
(4.25)
with
( )( )
11 1
11
12
121
11
122
1
( )
( )
P P
I P P
P I
I
P
−− −
−− −
−
−
= = = − +
=
− +
− +
− +
A
A
A I
K A K BK I EK C
K BK K BK I
K C
A I K
EK EK
E
EKE
ɶ ɶɶ ɶ
ɶ ɶ ɶ ɶ
ɶ
ɶ ɶ
ɶ
(4.26)
( )
( )1
2
11 1
1
P P P P
P P
−− −
−
− +
+
= = −
K BK K BK I EK EK
I I K
B
EB EK
ɶ ɶ ɶ ɶ
ɶ ɶ (4.27)
1
11
2
( )
( ) .P
P I
−
−
= +
= +
C I K C
C I
E
EK KEɶ ɶ
ɶɶ (4.28)
4.6.5 Case Studies
A double-input double-output Zeta-derived DLI-coupled converter is considered in this section.
Two input voltages Vin,1 = 120 V and Vin,2 = 50 V are assumed. The outputs are regulated at Vout,1 =
55
48 V and Vout,2 = 24 V, while two 1 Ω resistors define the loads. Pin,2 is kept at 1.5 kW while Pin,1 is
relaxed. To demonstrate the operation of the proposed MIMO converter, several transient studies
are described below, in which the converter is assumed to initially operate in steady state defined
by the nominal condition specified above.
In the first study, a step-change in Vin,2 from 50 V to 60 V is applied. The converter response is
depicted in Figure 4.19, which indicates the output voltages are regulated and return to their
desired values after the transient. Since the demanded power stays the same, the input powers
drained from both sources return to their preset values.
In the second study, the converter response to a load change is considered. Figure 4.20 shows
the system response to the first load R1 changing from 1 Ω to 0.7 Ω. The controller regulates the
outputs to track the specified voltage values, while the increased power demand from R1 is
compensated by the first input. The input power Pin,2 is regulated to remain constant at the
reference level of 1.5 kW.
In the final study, it is assumed that the second source Vin,2 is disconnected. Figure 4.21
illustrates the simulation result corresponding to this event. The power drop in the second input
automatically results in the first input supplying the deficit power. The output voltages undergo a
transient and return to their specified reference levels, as expected.
56
Figure 4.19. Simulated waveforms of the Zeta-derived DLI-coupled MIMO converter in response
to step change in input voltage.
1.3
1.4
1.5
1.6
1.4
1.6
1.8
2
46
48
50
52
54
22
24
26
28
0.2 s
Pin
,1 (
kW)
Pin
,2 (
kW)
Vou
t,1 (
V)
Vou
t,2 (
V)
57
Figure 4.20. Simulated waveforms of the Zeta-derived DLI-coupled MIMO converter in response
to step change in load.
1
1.5
2
2.5
1
1.5
2
35
40
45
50
55
20
25
30
35
0.2 s
Pin
,1 (
kW)
Pin
,2 (
kW)
Vou
t,1 (
V)
Vou
t,2 (
V)
58
Figure 4.21. Simulated waveforms of the Zeta-derived DLI-coupled MIMO converter in response
to one source missing.
0
1
2
3
0
0.5
1
1.5
10
20
30
40
50
5
10
15
20
25
30
0.2 s
Pin
,1 (
kW)
Pin
,2 (
kW)
Vou
t,1 (
V)
Vou
t,2 (
V)
59
CHAPTER 5: EXTENSION OF SISO CONVERTERS TO THEIR MIMO VERSIONS
This chapter proposes some general synthesis techniques for the generation of both non-isolated
and isolated MIMO converters. These techniques are simple in concept. Using PSCs and FCs,
feasible MIMO converters are constructed by replacing the original PSC or DC source of SISO
converters with combination of multiple PSCs, and the original FC or simply the C-FC with
combination of multiple FCs or C-FCs.
5.1 Isolated PSCs and Their Connection Rules
Apart from the six aforementioned non-isolated PSCs, six isolated PSCs are presented here. Figure
5.1 shows three isolated PVSCs, including full-bridge isolated buck, push–pull isolated buck, and
forward. Figure 5.2 shows three isolated PCSCs, including full-bridge isolated boost, push–pull
isolated boost, and flyback.
Applying analog connection rules of non-isolated PVSCs, isolated PVSCs can be connected in
series or parallel. In series configurations, multiple isolated PVSCs deliver power individually or
simultaneously. In parallel configurations, only one PVSC is able to deliver power at a time.
Same as the non-isolated PCSCs, multiple isolated PCSCs can be connected in series or
parallel. In series configurations, direct connection of isolated PCSCs should be avoided as per
Kirchhoff’ current law and appropriate adjustment of duty ratios is needed. Thus, only one PCSC
delivers power at a time. In parallel configurations, multiple isolated PCSCs can deliver power
individually or simultaneously.
Therefore, the connection rules are uniform for both non-isolated and isolated PSCs. In the
following derivations, they will not be distinguished.
5.2 Basic Configuration of Conventional SISO Converters
For the SISO converters, they can be decomposed into PSC and FC (Figure 5.3). As can be seen,
the output capacitors are employed in these converters to balance the instantaneous power
difference between the input source and output load and minimize voltage variation. In other
words, the C-FC is always included at the load while it is possible to decompose the LC-FC into
an inductor and a C-FC.
Figure 5.4 shows the basic structure of non-isolated SISO converter. It comprises an input
source, an active switch, at least one intermediate storage element, a diode, and a filter (consisting
of an optional inductor and a C-FC). The input can be a stable DC voltage source or a stable DC
60
current source. The active switch operates to chop the voltage source or current source to a high-
frequency pulse-train voltage or current waveform. The intermediate storage element between the
input and filter alters the high-frequency pulse-train voltage or current waveform to high-
frequency pulse-train current or voltage waveform. The diode can be placed in two manners. The
series diode blocks possible voltage difference, while the parallel diode is supplemented for
circulating possible current. Finally, the high-frequency pulse-train voltage or current waveform
is filtered out by the combination of optional inductor and C-FC.
Figure 5.5 shows the basic structure of isolated SISO converter. It consists of a DC voltage
source or a DC current source, a switch network, a high-frequency transformer, an output
rectifier, and a filter (consisting of an optional inductor and a C-FC). The operational principle of
isolated SISO converter is to convert the DC source to an AC pulsating source through the
switching network, step-up or -down the AC source via the transformer, rectify the AC source to
DC, and filter it to smooth and stable DC voltage.
The SISO converters can be identified into two types. One is the voltage-source type,
including buck, buck–boost, Zeta, full-bridge isolated buck, push–pull isolated buck, forward,
and flyback converters, and the other is current-source type, including boost, Ćuk, SEPIC, full-
bridge isolated boost, and push–pull isolated boost converters.
Figure 5.1. Isolated PVSCs: (a) full-bridge isolated buck; (b) push–pull isolated buck; and (c)
forward.
Figure 5.2. Isolated PCSCs: (a) full-bridge isolated boost; (b) push–pull isolated boost; and (c)
flyback.
(c)
+−Vin
+
−
(b)
+−
Vin
+
−+−Vin
(a)
+
−
(c)
+−Vin
+−Vin
(a)
+−
Vin
(b)
61
5.3 Realization of Multiport Structure
5.3.1 Multiple-Input Structure
Multiple PSCs can be connected in series or parallel as shown in Figure 4.8, and then use them to
replace the original single PSC or DC source of the SISO converter. Specifically, the combination
of multiple PVSCs is used to replace the voltage-type blocks (including the original PVSC and
DC voltage source), and the combination of multiple PCSCs is used to replace the current-type
blocks (including the original PCSC and DC current source).
5.3.2 Multiple-Output Structure
Multiple FCs can be connected in series or parallel as shown in Figure 4.10, and then use them to
replace the original single FC of the SISO converter. In fact, original C-FC is replaced with
multiple series- or parallel-connected C-FCs and original LC-FC is replaced with multiple series-
or parallel-connected LC-FCs. In addition, as the LC-FC could be represented by an inductor
followed by a C-FC, it is possible to only replace the separated C-FC from LC-FC with the
combination of multiple C-FCs.
Figure 5.3. General configuration of a SISO converter.
Figure 5.4. Basic configuration of non-isolated SISO converter.
Figure 5.5. Basic configuration of isolated SISO converter.
PSC FC Vout
+− or
DC Voltage orCurrent Source
ActiveSwitch
Energy IntermediateStorage Element
PowerDiode
OpitionalInductor
OutputC-FC
Vout
+− or
DC Voltage orCurrent Source
SwitchNetwork
High-FrequencyTransformer
OutputRectifier
OpitionalInductor
OutputC-FC
Vout
62
5.4 Synthesis of MIMO Converters
Replacing different blocks, four combinatorial structures of MIMO converter can be derived from
the PVSC-source SISO converter and two combinatorial structures of MIMO converter can be
derived from the PCSC-source SISO converter. Table 5.1 shows the eligible blocks of a SISO
converter that can be replaced with multiport structure.
1) The original PSC and integrated FC of the SISO converter are replaced. This method is
applicable to extend both PVSC- and PCSC-source SISO converters to their MIMO versions.
Figure 5.6 shows the circuit topology of MIMO converter generated by replacing the original
PVSC of the buck converter with series-connected multiple buck PVSCs, and the original LC with
series-connected multiple LC-FCs. Similarly, using series or parallel connection of multiple Ćuk,
Zeta, full-bridge isolated buck, push–pull isolated buck, forward PVSCs, or their combination to
replace the original PVSC can lead to several other MIMO converters. Also, the original single
LC-FC can be replaced with alternative series or parallel connection of multiple LC-FCs.
Figure 5.7 shows the circuit topology of MIMO converter generated by replacing the original
PCSC of the flyback converter with parallel-connected multiple flyback PCSCs, and the original
C-FC with parallel-connected multiple C-FCs. Similarly, using series or parallel connection of
multiple boost, buck–boost, SEPIC, full-bridge isolated boost, push–pull isolated boost PCSCs,
or their combination to replace the original PCSC can lead to several other MIMO converters.
Table 5.1. Eligible blocks that can be replaced with multiport structure.
DC voltage source DC current source PVSC PCSC C-FC LC-FC
Buck
Ćuk
Zeta
Boost
Buck–boost
SEPIC
Full-bridge buck
Push–pull buck
Forward
Full-bridge boost
Push–pull boost
Flyback
63
Figure 5.6. Circuit configurations: (a) SISO buck converter; and (b) PVSC-source MIMO
converter generated by several buck PVSC in series and LC-FCs in series.
Figure 5.7. Circuit configurations: (a) SISO flyback converter; and (b) PCSC-source MIMO
converter generated by several flyback PCSCs in parallel and C-FCs in parallel.
+−Vin,1
+−Vin,m
+−Vin
Original Buck PVSC Original LC-FC
Series-Connected Buck PVSCs
Series-Connected LC-FCs
(a) (b)
Vout
+
−
+
−
Vout , 1
+
−
Vout , n
+−Vin,1
+−Vin,m
Parallel-Connected C-FCsParallel-Connected Flyback PCSCs
+−Vin
+
−
Vout
Original Flyback PCSC Original C-FC
(a)
(b)
+
−
Vout , 1
+
−
Vout , n
64
Series connection of multiple C-FCs can also be used to replace the original single C-FC, which
may give different configurations.
2) The original DC source and FC of the SISO converter are replaced. This method is
applicable to extend both PVSC- and PCSC-source SISO converters to their MIMO versions.
Figure 5.8 shows a voltage-source MIMO converter based on Zeta converter. The original DC
voltage source is replaced with parallel-connected multiple buck PVSCs and the original LC-FC
is replaced with parallel-connected multiple LC-FCs. In this topology, the PVSCs supply power
in interleaved mode, and the loads draw power individually.
Figure 5.9 depicts a current-source MIMO converter, which is generated by integrating
multiple boost PCSCs with the primary side sub-circuit of a push-pull isolated boost converter,
and multiple series-connected FCs with the secondary side sub-circuit while providing a common
ground for the loads. In this topology, all the PCSCs are allowed to deliver power either
individually or simultaneously, but the loads can only draw power simultaneously.
3) The original PSC and separated C-FC from LC-FC of the SISO converter are replaced. This
approach is only applicable for extension of PVSC-source SISO converter.
Figure 5.8. Circuit configurations: (a) SISO Zeta converter; and (b) MIMO Zeta converter with
parallel-connected buck PVSCs as inputs and parallel-connected LC-FCs as outputs.
Original LC-FC
Parallel-Connected Buck PVSCs
(a)
(b)
+−Vin
Original DC Voltage Source
Parallel-Connected LC-FCs
+
−
Vout , 1
+
−
Vout , n
+−Vin,1
+−Vin,m
+
−
Vout
65
Figure 5.10 presents a PVSC-source MIMO converter based on forward converter topology.
Derivation of this MIMO converter is achieved by putting multiple forward PVSCs in series to
replace the original PVSC, and putting multiple C-FCs in parallel to replace the separated C-FC.
Here, the PVSCs power the loads individually or simultaneously, but more than one load may be
allowed to draw power at a time.
4) The original DC source and separated C-FC from LC-FC of the SISO converter are
replaced. This method is only application for extension of PVSC-source SISO converter.
Figure 5.11 shows an example for the synthesis of PVSC-source MIMO converter. The
primary side sub-circuit is formed by replacing the original DC voltage source of the full-bridge
converter with series-connected multiple buck PVSCs, and the secondary side sub-circuit is
configured by using parallel-connected multiple C-FCs to replace the separated C-FC. In this
topology, simultaneous power transfer from the multiple PVSCs is available, while only one load
is allowed to draw power at a time.
Figure 5.9. Circuit configurations: (a) SISO push–pull isolated boost converter; and (b) MIMO
push–pull isolated boost converter with parallel-connected boost PCSCs as inputs and series-
connected C-FCs as outputs.
+−
Vin,1
+−
Vin,1
+−Vin
+
−
Vout
Original DC Current Source
+
−
Vout , 1
+
−
Vout , n
Original C-FC
Parallel-Connected Boost PCSCs Series-Connected C-FCs
(a)
(b)
66
5.5 Transformer-Coupled MIMO Converters
There are two categories of isolated MIMO converters. One category of converters uses multiple
transformers, and the other category of converters involves a single transformer with multiple
windings wound on a core. Using multiple isolated PSCs is one option to implement isolation via
multiple transformers, but isolated MIMO converters can also be derived from transformer-
coupled SISO converter topology in an inexpensive manner, by adding multiple primary windings
with primary side sub-circuits, or/and multiple secondary windings with secondary side sub-
circuits.
In general, the transformer-coupled MIMO converters can be divided into four categories: 1)
single-primary-single-secondary-winding-transformer-coupled (SPSSWTC) topologies; 2) single-
primary-multiple-secondary-winding-transformer-coupled (SPMSWTC) topologies; 3) multiple-
primary-single-secondary-winding-transformer-coupled (MPSSWTC) topologies; and 4) multiple-
primary-multiple-secondary-winding-transformer-coupled (MPMSWTC) topologies.
Figure 5.10. Circuit configurations: (a) SISO forward converter; and (b) PVSC-source MIMO
converter generated by several forward PVSCs in series and C-FCs in series.
(a)
+−Vin
Original Forward PVSC
Series-Connected Forward PVSCs
+
−
Vout
Separated C-FC
Series-Connected C-FCs
+
−
Vout , 1
+
−
Vout , n
(b)
+−Vin,1
+−Vin,m
67
1) SPSSWTC MIMO converters can be obtained by using the combinations of multiple non-
isolated PSCs to replace the original DC source of the conventional transformer-isolated SISO
converter and the combinations of multiple FCs to replace the original single FC. In these
topologies, galvanic isolation only occurs between the primary side and secondary side. Basic
topology structure is demonstrated in Figure 5.12.
2) SPMSWTC MIMO converters can be obtained replacing the original DC source of the
conventional isolated SISO converter with multiple non-isolated PSCs and paralleling the
secondary sub-circuits. This kind of converters provides isolation between multiple outputs, and
turns ratios can be chosen to acquire the desired output voltages. The general configuration of
SPMSWTC MIMO converter is shown in Figure 5.13.
3) MPSSWTC MIMO converters can be obtained by paralleling primary sub-circuits and
replacing the original single FC with its multiport version. Therefore, galvanic isolation is
provided between multiple inputs, and the voltage levels are adjustable through the transformer
Figure 5.11. Circuit configurations: (a) SISO full-bridge isolated buck converter; and (b) MIMO
full-bridge isolated buck converter with series-connected buck PVSCs as inputs and parallel-
connected C-FCs as outputs.
+−Vin,1
+−Vin,m
+−Vin
+
−
Vout
Series-Connected Buck PVSCs Parallel-Connected C-FCs
Original DC Voltage Source Separated C-FC
(a)
(b)
+
−
Vout , 1
+
−
Vout , n
68
Figure 5.12. Basic structure of SPSSWTC MIMO converter.
Figure 5.13. Basic structure of SPMSWTC MIMO converter.
Figure 5.14. Basic structure of MPSSWTC MIMO converter.
Figure 5.15. Basic structure of MPMSWTC MIMO converter.
SwitchNetwork
OutputRectifier
OpitionalInductor
PSC 1
PSC 2
PSC m
C-FC- Load 1
C-FC- Load n
Vout , 1
Vout , n
OutputRectifier 1
OpitionalInductor 1
OutputC-FC 1
OutputRectifier n
OpitionalInductor n
OutputC-FC n
SwitchNetwork
PSC 1
PSC 2
PSC m
Vout , 1
Vout , n
OutputRectifier
OpitionalInductor
SwitchNetwork 1
SwitchNetwork m
DCSource 1
DCSource m
OutputC-FC 1
Output C-FC n
Vout , 1
Vout , n
SwitchNetwork 1
DCSource 1
SwitchNetwork m
DCSource m
OutputRectifier 1
OpitionalInductor 1
OutputC-FC 1
OutputRectifier n
OpitionalIndcutor n
OutputC-FC n
Vout , 1
Vout , n
69
winding ratios, as each input provides power to the system through an individual winding.
Typical structure of MPSSWTC MIMO converter is depicted in Figure 5.14.
4) MPMSWTC MIMO converters can be simply obtained by paralleling both primary and
secondary sub-circuits. Therefore, all ports ate electrically isolated and voltage levels of each port
could be flexible. Structure illustration is shown in Figure 5.15.
70
CHAPTER 6: CONCLUSIONS
In this concluding chapter, the major contributions of this research project are summarized and
possible future work is discussed.
6.1 Contributions of the Thesis
This work introduces theoretical concepts and presents overall discussions to the field of MIMO
converters. Two major contributions are reported.
Firstly, two typical MIMO converters are introduced in detail, and a simple approach that can
be applied in analyzing these converters is presented. The proposed two MIMO converters
include a non-isolated topology and an isolated topology. Both topologies can be scaled to
arbitrary numbers of inputs and outputs, and the output voltages could be regulated individually
either greater than the maximum input voltage or less than the minimum. Closed-loop examples
consisting of decoupler and controller are shown to provide actions for power management,
voltage regulation and duty ratio adjustments. The DMs are presented to validate the operation of
the proposed MIMO converters, and the AVMs are developed and compared with the DMs.
AVMs and DMs are shown to be in good agreement.
Secondly, general approaches for deriving MIMO converters are proposed. With basic
building blocks (including PSCs and FCs), a basic structure based on DLI/DLC is proposed for
the synthesis of a family of non-isolated MIMO converters. Connection rules for building blocks
of PSCs and FCs are listed. Formalization of interface between multiple PSCs and FCs is realized
by DLI or DLC with necessary switches. Following a uniform method, two types of DC-linked
MIMO converters are obtained. In the end, a set of uniform rules for synthesizing general MIMO
converters based on basic SISO converters are proposed. MIMO converters can be derived by
replacing the PSC or original DC source of a conventional converter with series- or parallel-
connected PSCs, and the FC or original DC load with series- or parallel-connected FCs.
6.2 Future Work
6.2.1 Practical Implementation
Realization of the proposed MIMO converters in hardware is not considered in this thesis. The
theoretical derivation of the MIMO non-inverting buck–boost and flyback converters have been
validated by computer simulations, but it is still worthwhile to investigate if their practical
71
implementation would be effective for a specific application such as DC distribution system of a
smart home with multiple DC sources and loads at different voltage levels.
6.2.2 Controller Optimization
The controllers employed with the MIMO converters proposed in Chapter 2–4 of the thesis have
been demonstrated to be capable of regulating the input powers along with the output voltages.
However, since the proposed methodology is based on linearization, more development and
extensive analysis is required for controller tuning and optimal performance over wide range of
operating conditions.
6.2.3 Non-Ideal MIMO Converters
The AVMs in the Chapter 2 and 3 are built based on ideal MIMO converters, which neglect
parasitics or losses to simplify the derivations and modeling procedures, and the resulting models
may not be sufficiently accurate for practical converters. It would be helpful to model the MIMO
converters with parasitic elements.
6.2.4 Bidirectional Multiport Converters
The converters presented in this thesis allows for only unidirectional power flow. However, to
satisfy the application where an energy storage element is indispensable, bidirectional power flow
is required. Instead of using additional converter for feeding the energy back, it would be
desirable to analyze and synthesize bidirectional multiport converters.
72
REFERENCES
[1] D. Nilsson and A. Sannino, “Efficiency analysis of low- and medium-voltage DC
distribution systems,” in Proceedings of IEEE Power and Energy Society General Meeting,
2004, vol.2, pp. 2315-2321.
[2] P.-W. Lee, Y.-S. Lee, and B.-T. Lin, “Power distribution systems for future homes,” in
Proceedings of IEEE International Conference on Power Electronics and Drive Systems,
vol. 2, 1999, pp. 1140–1146.
[3] A. Sannino, G. Postiglione, and M. Bollen, “Feasibility of a DC network for commercial
facilities,” IEEE Transactions on Industry Applications, vol. 39, no. 5, pp. 1499–1507,
Sep./Oct. 2003.
[4] W. Jiang and B. Fahimi, “Multiport power electronic interface—Concept, modeling and
design,” IEEE Transactions on Power Electronics, vol. 26, no. 7, pp. 1890–1900, Jul. 2011.
[5] H. Behjati and A. Davoudi, “Single-stage multi-port DC–DC converter topology,” IET
Power Electronics, vol. 6, no. 2, pp. 392–403, Feb. 2013.
[6] H. Behjati and A. Davoudi, “A multiple-input multiple-output DC–DC converter,” IEEE
Transactions on Industry Applications, vol. 49, no. 3, pp. 1464–1479, May/Jun. 2013.
[7] H. Behjati and A. Davoudi, “Power budgeting between diversified energy sources and
loads using a multiple-input multiple-output DC–DC converter,” IEEE Transactions on
Industry Applications, vol. 49, no. 6, pp. 2761–2772, Nov/Dec. 2013.
[8] H. Keyhani and H. A. Toliyat, “A ZVS single-inductor multi-input multi-output DC-DC
converter with the step up/down capability,” in Proceedings of IEEE Energy Conversion
Congress and Exposition, 2013, pp. 5546–5552.
[9] H. Matsuo, W. Lin, F. Kurokawa, T. Shigemizu, and N. Watanabe, “Characteristics of the
multiple-input DC–DC converter,” IEEE Transactions on Industrial Electronics, vol. 51,
no. 3, pp. 625–631, Jun. 2004.
[10] K. Kobayashi, H. Matsuo, and Y. Sekine, “Novel solar-cell power supply system using a
multiple-input DC–DC converter,” IEEE Transactions on Industrial Electronics, vol. 53,
no. 1, pp. 281–286, Feb. 2006.
[11] Y.-M. Chen, Y.-C. Liu, and F.-Y. Wu, “Multiinput converter with power factor correction,
maximum power point tracking, and ripple-free input currents,” IEEE Transactions on
Power Electronics, vol. 19, no. 3, pp. 631–639, May 2004.
73
[12] N. D. Benavides and P. L. Chapman, “Power budgeting of a multiple input buck–boost
converter,” IEEE Transactions on Power Electronics, vol. 20, no. 6, pp. 1303–1309, Nov.
2005.
[13] F. Caricchi, F. Crescimbini, O. Honorati, A. D. Napoli, and E. Santini, “Testing of a new
DC/DC converter topology for integrated wind-photovoltaic generating systems,” in
Proceedings of European Conference on Power Electronics, 1993, pp. 83–88.
[14] L. Solero, F. Caricchi, F. Crescimbini, O. Honorati, and F. Mezzetti, “Performance of a 10
kW power electronic interface for combined wind/PV isolated generating systems,” in
Proceedings of IEEE Power Electronics Specialists Conference, 1996, pp. 1027 - 1032.
[15] Y.-M. Chen, Y.-C. Liu, and S.-H. Lin, “Double-input PWM DC/DC converter for high-
/low-voltage sources,” IEEE Transactions on Industrial Electronics, vol. 53, no. 5, pp.
1538–1545, Oct. 2006.
[16] J. Zeng, W. Qiao, L. Qu, and Y. Jiao, “An isolated multiport DC–DC converter for
simultaneous power management of multiple different renewable energy sources,” IEEE
Journal of Emerging and Selected Topics in Power Electronics, vol. 2, no. 1, pp. 70–78,
Mar. 2014.
[17] A. Hussam, F. Tian, and I. Batarseh, “Tri-modal half-bridge converter topology for three-
port interface,” IEEE Transactions on Power Electronics, vol. 22, no. 1, pp. 341–345, Jan.
2007.
[18] Z. Qian, O. Abdel-Rahman, H. Al-Atrash, and I. Batarseh, “Modeling and control of three-
port DC/DC converter interface for satellite applications,” IEEE Transactions on Power
Electronics, vol. 25, no. 3, pp. 637–649, Mar. 2010.
[19] Z. Qian, O. Abdel-Rahman, and I. Batarseh, “An integrated four-port DC/DC converter for
renewable energy applications,” IEEE Transactions on Power Electronics, vol. 25, no. 7,
pp. 1877–1887, Jul. 2010.
[20] S. Falcones, R. Ayyanar, and X. Mao, “A DC–DC multiport-converter-based solid-state
transformer integrating distributed generation and storage,” IEEE Transactions on Power
Electronics, vol. 28, no. 5, pp. 2192–2203, May 2013.
[21] Z. Wang and H. Li, “An integrated three-port bidirectional DC–DC converter for PV
application on a DC distribution system,” IEEE Transactions on Power Electronics, vol.
28, no. 10, pp. 4612–4624, Oct. 2013.
[22] H. Wu, P. Xu, Z. Zhou, and Y. Xin, “Multiport Converters Based on Integration of Full-
Bridge and Bidirectional DC–DC Topologies for Renewable Generation Systems,” IEEE
Transactions on Industrial Electronics, vol. 61, no. 2, pp. 856–869, Feb. 2014.
74
[23] A. Di Napoli, F. Crescimbini, S. Rodo, and L. Solero, “Multiple input DC–DC power
converter for fuel-cell powered hybrid vehicles,” in Proceedings of IEEE Power
Electronics Specialists Conference, 2002, pp. 1685 - 1690.
[24] L. Solero, A. Lidozzi, and J. A. Pomilio, “Design of multiple-input power converter for
hybrid vehicles,” IEEE Transactions on Power Electronics, vol. 20, no. 5, pp. 1007–1016,
Sep. 2005.
[25] H. Tao, A. Kotsopoulos, J. L. Duarte, and M. A. M. Hendrix, “Multi-input bidirectional
DC–DC converter combining DC-link and magnetic-coupling for fuel cell systems,” in
Proceedings of IEEE Industry Applications Society Annual Meeting, 2005, pp. 2021–2028.
[26] M. Marchesoni and C. Vacca, “New DC–DC converter for energy storage system
interfacing in fuel cell hybrid electric vehicles,” IEEE Transactions on Power Electronics,
vol. 22, no. 1, pp. 301–308, Jan. 2007.
[27] Z J. Duarte, M. Hendrix, and M. Simoes, “Three-port bidirectional converter for hybrid fuel
cell systems,” IEEE Transactions on Power Electronics, vol. 22, no. 2, pp. 480–487, Mar.
2007.
[28] G.-J. Su and L. Tang, “A reduced-part, ripple-voltage DC–DC converter for EV/HEV
power management,” IEEE Transactions on Power Electronics, vol. 24, no. 10, pp. 2406–
2410, Oct. 2009.
[29] L. K. Gummi and M. Ferdowsi, “Double-input DC–DC power electronic converters for
electric-drive vehicles—topology exploration and synthesis using a single-pole triple-throw
switch,” IEEE Transactions on Industry Applications, vol. 57, no. 2, pp. 617–623, Feb.
2010.
[30] Z. Zhang, Z. Ouyang, O. C. Thomsen, and M. A. E. Andersen, “Analysis and Design of a
Bidirectional Isolated DC–DC Converter for Fuel Cells and Supercapacitors Hybrid
System,” IEEE Transactions on Power Electronics, vol. 27, no. 2, pp. 848–859, Feb. 2012.
[31] H. Matsuo and K. Harada, “New energy-storage DC-DC converter with multiple outputs,”
IEEE Transactions on Magnetics, vol. mag-14, no. 5, pp. 1005–1007, Sept. 1978.
[32] F. Kurokawa, H. Matsuo, "A new multiple-output hybrid power supply", IEEE
Transactions on Power Electronics, vol. 3, no. 4, pp. 412 – 419, Oct. 1988.
[33] D. Ma, W.-H. Ki, C.-Y. Tsui, and P. K. T. Mok, “Single-inductor multiple-output switching
converters with time-multiplexing control in discontinuous conduction mode,” IEEE
Journal of Solid-State Circuits, vol. 38, no. 1, pp. 89–100, Jan. 2003.
75
[34] S. Chakraborty, A. K. Jain, and N. Mohan, “A novel converter topology for multiple
individually regulated outputs,” IEEE Transactions on Power Electronics, vol. 21, no. 2,
pp. 361–369, Mar. 2006.
[35] J.-J. Lee and B.-H. Kwon, “DC–DC converter using a multiple-coupled inductor for low
output voltages,” IEEE Transactions on Industrial Electronics, vol. 54, no. 1, pp. 467–478,
Feb. 2007.
[36] D. W. Kwon and G. A. Rincón-Mora, “Single-inductor-multiple-output switching DC-DC
converters,” IEEE Transactions on Circuits Systems–II, Express Briefs, vol. 56, no. 8, pp.
614–618, Aug. 2009.
[37] P. Patra, A. Patra, and N. Misra, “A single-inductor multiple-output switcher with
simultaneous buck boost and inverted outputs,” IEEE Transactions on Power Electronics,
vol. 27, no. 4, pp. 1936–1951, Apr. 2012.
[38] V.-L. Tran and W. Choi, “Novel time division multiple control method for multiple output
battery charger,” IEEE Transactions on Power Electronics, vol. 29, no. 10, pp. 5102–5105,
Oct. 2014.
[39] Y. Xi and P. K. Jain, “A forward converter topology with independently and precisely
regulated multiple outputs,” IEEE Transactions on Power Electronics, vol. 18, no. 2, pp.
648–658, Mar. 2003.
[40] Y. Gu, Y. Kong, S. Nie, and X. Pei, “A simple structure of LLC resonant DC–DC
converter for multi-output applications” in Proceedings of IEEE Applied Power Electronics
Conference and Exposition, 2005, pp. 1485–1490.
[41] H.-S. Kim, J.-H. Jung, J.-W. Baek, and H.-J. Kim, “Analysis and design of a multioutput
converter using asymmetrical PWM half-bridge flyback converter employing a parallel–
series transformer,” IEEE Transactions on Industrial Electronics, vol. 60, no. 8, pp. 3115–
3125, Aug. 2013.
[42] R.-J. Wai, and K.-H. Jheng, “High-efficiency single-input multiple-output DC–DC
converter,” IEEE Transactions on Power Electronics, vol. 28, no. 2, pp. 886–898, Feb.
2013.
[43] A. A. Boora, F. Zare, G. Ledwich, and A. Ghosh, “A new DC–DC converter with multi
output: topology and control strategies,” in Proceedings of Power Electronics and Motion
Control Conference, 2008, pp. 468–474.
[44] A. Nami, F. Zare, A. Ghosh, and F. Blaabjerg, “Multi-output DC–DC converters based on
diode-clamped converters configuration: topology and control strategy,” IET Power
Electronics, vol. 3, no. 2, pp. 197–208, Mar. 2010.
76
[45] A. Boora, F. Zare, and A. Ghosh, “Multi-output buck–boost converter with enhanced
dynamic response to load and input voltage changes,” IET Power Electronics, vol. 4, no. 2,
pp. 194–208, Feb. 2011.
[46] Y. Zhang and D. Xu, “Design and implementation of an accurately regulated multiple
output ZVS DC–DC converter,” IEEE Transactions on Power Electronics, vol. 22, no. 5,
pp. 1731–1742, Sep. 2007.
[47] Y. Chen, Y. Kang, S. Nie, and X. Pei, “The multiple-output DC–DC converter with shared
ZCS lagging leg,” IEEE Transactions on Power Electronics, vol. 26, no. 8, pp. 2278–2294,
Aug. 2011.
[48] L. K. Gummi and M. Ferdowsi, “Double-input DC–DC power electronic converters for
electric-drive vehicles—topology exploration and synthesis using a single-pole triple-throw
switch,” IEEE Transactions Industry Applications, vol. 57, no. 2, pp. 617–623, Feb. 2010.
[49] A. Di Napoli, F. Crescimbini, F. Guilii Capponi, and L. Solero, “Control strategy for
multiple input DC–DC power converters devoted to hybrid vehicle propulsion systems,” in
Proceedings of IEEE Power Electronics Specialists Conference, 2002, pp. 1685–1690.
[50] B. G. Dobbs and P. L. Chapman, “A multiple-input DC–DC converter topology,” IEEE
Power Electronics Letters, vol. 1, no. 1, pp. 6–9, Mar. 2003.
[51] O. C. Onar, O. H. A. Shirazi, and A. Khaligh, “Grid interaction operation of a
telecommunications power system with a novel topology for multiple-input buck–boost
converter,” IEEE Transactions on Power Delivery, vol. 25, no. 4, pp. 2633–2645, Oct.
2010.
[52] H. Wu, J. Zhang, and Y. Xing, “A family of multiport buck–boost converters based on DC-
link-inductors (DLIs),” IEEE Transactions on Power Electronics, vol. 30, no. 2, pp. 735–
746, Feb. 2015.
[53] S. Bae and A. Kwasinski, “Maximum power point tracker for a multiple-input Ćuk DC–DC
converter,” in Proceedings of International Telecommunications Energy Conference, 2009,
pp. 1–5.
[54] R. Zhao and A. Kwasinski, “Multiple-input single ended primary inductor converter
(SEPIC) converter for distributed generation applications,” in Proceedings of Energy
Conversion Congress and Exposition, Sep. 2009, pp. 1847–1854.
[55] S.-Y. Yu and A. Kwasinski, “Analysis of Soft-Switching Isolated Time-Sharing Multiple-
Input Converters for DC Distribution Systems,” IEEE Transactions on Power Electronics,
vol. 28, no. 4, pp. 1783–1794, Apr. 2013.
77
[56] M. Veerachary, “Two-loop controlled buck–SEPIC converter for input source power
management,” IEEE Transactions on Industrial Electronics, vol. 59, no. 11, pp. 4075–
4087, Nov. 2012.
[57] W. Ki and D. Ma, “Single-inductor multiple-output switching converters,” in Proceedings
of IEEE Power Electronics Specialists Conference, 2001, vol. 1, pp. 226–231.
[58] Y.-M. Chen, Y.-C. Liu, and F.-Y. Wu, “Multi-input DC/DC converter based on the
multiwinding transformer for renewable energy application,” IEEE Transactions on
Industry Applications, vol. 38, no. 4, pp. 1096–1104, Jul. 2002.
[59] H. Wu, R. Chen, J. Zhang, Y. Xing, H. Hu, and H. Ge, “A family of three-port half-bridge
converters for stand-alone renewable power system,” IEEE Transactions on Power
Electronics, vol. 26, no. 9, pp. 2697–2706, Sep. 2011.
[60] Z. Wang and H. Li, “An integrated three-port bidirectional DC–DC converter for PV
application on a DC distribution system,” IEEE Transactions on Power Electronics, vol.
28, no. 10, pp. 4612–4624, Oct. 2013.
[61] H. Wu, P. Xu, H. Hu, Z. Zhou, and Y. Xing, “Multiport converters based on integration of
full-bridge and bidirectional DC–DC topologies for renewable generation systems,” IEEE
Transactions on Industrial Electronics, vol. 61, no. 2, pp. 856–869, Feb. 2014.
[62] F. Liu, Z. Wang, Y. Mao, and X. Ruan, “Asymmetrical half-bridge double-input DC/DC
converters adopting pulsating voltage source cells for low power applications,” IEEE
Transactions on Power Electronics, vol. 29, no. 9, pp. 4741–4751, Sep. 2014.
[63] D. Maksimović and R. Erickson, “Modeling of cross-regulation in multiple-output flyback
converters,” in Proceedings of IEEE Applied Power Electronics Conference and
Exposition, 1999, pp. 1066–1072.
[64] M. Goldman, A. F. Witulski, “Analysis and prediction of regulation in a multiple-output
current-mode controlled DC-to-DC converter,” IEEE Transactions on Aerospace and
Electronic Systems, vol. 31, no. 2, pp.626–633, Apr. 1995.
[65] J. Sebastian, J. Uceda, M. Rico, M. A. Perez, and F. Aldana, “A complete study of the
double forward-flyback converter,” in Proceedings of IEEE Power Electronics Specialists
Conference, 1988, pp. 142–149.
[66] H. E. Tacca, “Single-switch two-output flyback-forward converter operation,” IEEE
Transactions on Power Electronics, vol. 13, no. 5, pp. 903–911, Sep. 1998.
[67] H.-J. Chiu, H.-M. Huang, L.-W. Lin, and M.-H. Tseng, “A multiple-input DC/DC
converter for renewable energy systems,” in Proceedings of IEEE International Conference
on Industry Technology, 2005, pp. 1304–1308.
78
[68] R. Ahmadi and M. Ferdowsi, “Double-input converters based on H-bridge cells:
Derivation, small-signal modeling, and power sharing analysis,” IEEE Transactions on
Circuits Systems–I, Regular Papers, vol. 59, no. 4, pp. 875–888, Apr. 2012.
[69] R. Ahmadi, H. Zargarzadeh, and M. Ferdowsi, “Nonlinear power sharing controller for a
double-input h-bridge-based buckboost–buckboost converter,” IEEE Transactions on
Power Electronics, vol. 28, no. 5, pp. 2402–2414, May 2013.
[70] H. Matsuo, “Comparison of multiple-output DC–DC converters using cross regulation,”
IEEE Transactions on Industrial Electronics and Control Instrumentation, vol. IECI-27,
no. 3, pp. 176–189, Aug. 1980.
[71] C. Ji, K. M. Smith, Jr., K. M. Smedley, and K. King, “Cross regulation in flyback
converters: analytic model and solution,” IEEE Transactions on Power Electronics, vol. 16,
no. 2, pp. 231–239, Mar. 2001.
[72] C.-C. Wen, C.-L. Chen, W. Chen, and J. Jiang, “Magamp post regulation for flyback
converter,” in Proceedings of IEEE Power Electronics Specialists Conference, 2001, pp.
333–338
[73] Y.-L. Lin and K. H. Liu, “A new synchronous-switch post regulator for multi-output
forward converters,” in Proceedings of IEEE Applied Power Electronics Conference and
Exposition, 1990, pp. 693–696.
[74] Q. Chen, F. C. Lee, and M. M. Jovanović, “Analysis and design of weighted voltage-mode
control for a multiple-output forward converter,” in Proceedings of IEEE Applied Power
Electronics Conference and Exposition, 1993, pp. 449–455.
[75] A. Ferreres, J. A. Carrasco, E. Sanchis, J.M. Espi, and E. Maset, “Application of a novel
parallel regulation technique in a two output forward converter,” in Proceedings of IEEE
Power Electronics Specialists Conference, 1999, pp. 914–919.
[76] Y.-C. Liu and Y.-M. Chen, “A systematic approach to synthesizing multi-input DC–DC
converters,” IEEE Transactions on Power Electronics, vol. 24, no. 1, pp. 116–127, Jan.
2009.
[77] Y. Li, X. Ruan, D. Yang, F. Liu, and C. K. Tse, “Synthesis of multiple input DC/DC
converters,” IEEE Transactions on Power Electronics, vol. 25, no. 9, pp. 2372–2385, Mar.
2010.