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Multi-limit-cycle operation of Sigma Delta modulators andefficient decimation, theory and applicationCitation for published version (APA):Ouzounov, S. F. (2008). Multi-limit-cycle operation of Sigma Delta modulators and efficient decimation, theoryand application. Eindhoven: Technische Universiteit Eindhoven. https://doi.org/10.6100/IR635719
DOI:10.6100/IR635719
Document status and date:Published: 01/01/2008
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Multi-limit-cycle operation of SD modulators and efficient decimation, theory and application
Sotir Filipov Ouzounov
The work described in this thesis has been supported in part by the Dutch Technology Foundation STW.
Front and back covers are based on artist's vision of white dwarf star spiral in the J0806 binary start system.
Image credit: NASA/Tod Strohmayer (GSFC)/Dana Berry (Chandra X-Ray Observatory). © Sotir F. Ouzounov 2008 All rights are reserved. Reproduction in whole or in part is prohibited without the written consent of the copyright owner. Printing: Eindhoven University Press
Multi-limit-cycle operation of SD modulators and efficient decimation, theory and application
PROEFSCHRIFT ter verkrijging van de graad van doctor aan de Technische Universiteit Eindhoven, op gezag van de Rector Magnificus, prof.dr.ir. C.J. van Duijn, voor een commissie aangewezen door het College voor Promoties in het openbaar te verdedigen op donderdag 26 juni 2008 om 14.00 uur door Sotir Filipov Ouzounov geboren te Pazardzhik, Bulgarije
Dit proefschrift is goedgekeurd door de promotor: prof.dr.ir. A.H.M. van Roermund Copromotor: dr.ir. J.A. Hegt CIP-DATA LIBRARY TECHNISCHE UNIVERSITEIT EINDHOVEN Ouzounov, Sotir Filipov Multi-limit-cycle operation of Σ∆ modulators and efficient decimation, theory and application / by Sotir Filipov Ouzounov. – Eindhoven : Technische Universiteit Eindhoven, 2008. – Proefschrift. ISBN 978-90-386-1324-6 NUR 959 Trefw.: elektronica / CMOS-schakelingen / analoog-digitaal conversie Subject headings: sigma-delta modulation / asynchronous circuits / CMOS analog integrated circuits / limit cycles / describing functions / linearisation techniques / decimation filters
Abstract
In this thesis, sigma-delta modulators are treated as non-linear closed-loop systems. Two types of sigma-delta modulators are studied: asynchronous (ASDMs) and synchronous (SDMs). The limit cycle oscillations in these systems are identified as the dominant phenomenon that determines their operation and the quality of the performed signal processing.
The ASDM operation, properties and hardware implementation are investigated. A Fourier expansion method and a describing function method are used for the determination of the ASDM limit cycle behavior in idle mode and for DC and harmonic inputs.
A new multi-limit-cycle model of the SDM operation is developed, analyzed and applied in circuit design. It demonstrates that the SDM operation is based on switching between two or more limit cycles, explains several phenomena in the SDM operation like tonal behavior, spectral peaks and dead zones, and gives a stability criterion. A deeper insight in the SDM properties is gained via a new quantization noise model. The model is used for the determination of the SDM limit cycle behavior that results in an optimal trade-off between performance, power consumption and chip area.
For the implementation of several high performance SDMs, a new highly linear transconductor circuit is analyzed. It implements harmonic compensation via a combination of resistive feedback and cross-coupling such that a significant suppression of the third and the fifth order harmonic components in the transconductor characteristic can be achieved.
In order to improve the power efficiency of the complete SD ADC, a decimator based on the recursive bitstream conversion algorithm is studied and extended. It is demonstrated that its algorithmic complexity pays off with a very simple, and area and power efficient implementation.
The IC designs, implementations and measurements of a separate transconductor stage, first and second order ASDMs and two SDMs are described.
vi Abstract
Contents Abstract............................................................................................................................ v
Abbreviations .............................................................................................................. xiii
Glossary........................................................................................................................xvii
1. Introduction ............................................................................................... 1
1.1. Motivation ...................................................................................................... 1
1.2. Goals .............................................................................................................. 2
1.3. Thesis outline .................................................................................................. 2
2. Oscillations in non-linear, closed-loop systems .............................................. 5
2.1. Scope and classification ................................................................................. 5
2.1.1. Non-linear systems........................................................................... 7
2.1.2. Closed-loop systems ........................................................................ 8
2.1.3 Externally and internally synchronized systems............................... 9
2.2. Construction of synchronous and asynchronous NLCL systems ................... 13
2.2.1 Non-linear elements and functions ................................................... 13
2.2.2 Linear elements and functions .......................................................... 14
2.2.3 Feedback transfer .............................................................................. 17
2.3. Conclusions..................................................................................................... 18
3. Methods for analysis of NLCL systems ............................................................. 19
3.1. Linearization of NLCL systems...................................................................... 19
3.1.1. White noise model ........................................................................... 19
3.1.2. Noise spectrum and SNR................................................................. 21
3.1.3. Limitations of the approach ............................................................. 21
3.2. Analysis of NLCL systems with Fourier series .............................................. 22
3.3. Application of Describing Functions for the study of NLCL systems ........... 24
3.3.1. Derivation and basic properties of DFs ........................................... 24
3.3.2. DF for DC input ............................................................................... 26
3.3.3. Sinusoidal input DF ......................................................................... 26
3.3.4. Multiple input DF ............................................................................ 29
3.4. Conclusions..................................................................................................... 30
viii Contents
4. Idle limit cycles in ASDMs ................................................................................... 31
4.1. Motivation and definitions.............................................................................. 31
4.2. Idle limit cycles evaluation: time waveforms ................................................. 32
4.2.1. System structure and description ..................................................... 32
4.2.2. Existence and frequency of idle limit cycles ................................... 33
4.2.2.1. Closed-form solutions for the loop filter expansions........ 38
4.2.2.2. Truncation of the summations .......................................... 38
4.2.3. Loop filter impact on the limit cycle behavior................................. 39
4.2.3.1. First order systems ............................................................ 39
4.2.3.2. Second order systems........................................................ 44
4.2.3.3. Extra loop delay ................................................................ 47
4.2.3.4. Third and higher order systems......................................... 48
4.3. Idle limit cycles evaluation: DF approach ...................................................... 48
4.3.1. Idle limit cycles in a DF-linearized NLCL system .......................... 48
4.3.2. Analytical solutions: examples ........................................................ 49
4.3.2.1. First-order systems............................................................ 50
4.3.2.2. Third-order systems .......................................................... 51
4.3.3. Graphical evaluation of idle limit cycles ......................................... 52
4.4. Comparison of DF and time-domain approaches ........................................... 54
4.5. Conclusions..................................................................................................... 54
5. Evaluation of input-driven ASDMs..................................................................... 55
5.1. Application of the Fourier expansion method ................................................ 55
5.1.1. ASDM analysis for a DC input........................................................ 56
5.1.1.1. Derivation of ASDM Characteristic Equations ................ 59
5.1.1.2. Example for a first order ASDM with BQh...................... 60
5.1.1.3. Generalization of the filter description ............................. 62
5.1.2. ASDMs analysis for sinusoidal inputs............................................. 65
5.2. Application of DFs for analysis of input driven ASDMs ............................... 69
5.3. Conclusions..................................................................................................... 72
6. Multi limit cycle behavior of synchronous SDMs........................................... 73
6.1. Motivation and Definitions ............................................................................. 73
6.1.1. Performance estimation and measurements..................................... 73
6.1.2. Definition of terms and scope .......................................................... 75
Contents ix
6.2. Limit cycle model of SDMs in idle mode....................................................... 76
6.2.1. Sampled DF ..................................................................................... 76
6.2.2. Potential idle sub-harmonic modes.................................................. 78
6.2.3. Clock introduced phase shift............................................................ 79
6.2.4. Graphical evaluation of idle limit cycle modes in SDMs ............... 80
6.2.5. Active idle limit cycle...................................................................... 82
6.3. Input driven time variant limit cycle behavior of SDM ................................. 85
6.3.1. SDM operation with DC input......................................................... 85
6.3.1.1. Conceptual description...................................................... 86
6.3.1.2. Analytical description for DC input.................................. 91
6.3.2. SDM operation with sinusoidal input .............................................. 93
6.4. System impact on the LC behavior: characteristic examples ......................... 96
6.4.1. Test bench definition........................................................................ 96
6.4.2. Limit cycle behavior of SDM with BQ0 ......................................... 98
6.4.2.1. First order systems ........................................................... 98
6.4.2.2. Second order systems........................................................ 100
6.4.2.3. Arbitrary order loop filters................................................ 103
6.4.3. Limit cycle behavior of SDM with BQh.......................................... 106
6.4.4. Impact of the extra loop delay ......................................................... 107
6.5. Conclusions..................................................................................................... 109
7. Performance Evaluation and Optimal Design of SDMs................................. 111
7.1. Quantization noise in SDMs ........................................................................... 111
7.1.1. Quantization noise models............................................................... 111
7.1.2. LC behavior and SDM output spectrum .......................................... 113
7.1.3. Modified quantization noise model ................................................. 116
7.1.4. Quantization noise power ................................................................ 121
7.2. Optimal SDM parameterization...................................................................... 126
7.2.1. Design space definition.................................................................... 126
7.2.2. Choice of SDM LC behavior ........................................................... 127
7.2.3. Functional level optimization for maximum performance .............. 132
7.2.4. Optimization of the SDM power efficiency..................................... 134
7.3. Conclusions..................................................................................................... 135
x Contents
8. Analysis and design of high performance Transconductors.......................... 137
8.1. Problem definition .......................................................................................... 137
8.2. Linearization of the transconductor function.................................................. 138
8.2.1. Linearization via negative feedback ................................................ 140
8.2.2. Linearization via harmonic compensation ....................................... 141
8.3. Analysis and optimization of the V-I characteristics...................................... 142
8.3.1. Basic analytical description ............................................................. 142
8.3.2. Formalization of the analytical description...................................... 143
8.3.3. Optimization of the linearity performance....................................... 145
8.3.4. Analytical evaluation of the thermal noise ...................................... 150
8.3.5. Analytical evaluation of the achievable dynamic range .................. 152
8.4. Circuit level evaluation of DR, SNR and THD .............................................. 155
8.4.1. Non-idealities in the transconductor implementation ...................... 155
8.4.2. Evaluation of the static performance ............................................... 157
8.4.3. Evaluation of the dynamic performance .......................................... 160
8.4.4. Evaluation of robustness with ADAPT............................................ 161
8.5. Conclusions..................................................................................................... 164
9 Decimation via Recursive Bitstream Conversion ............................................. 165
9.1. Decimation in Sigma-Delta ADC ................................................................... 165
9.2. Decimation cost factors................................................................................... 167
9.3. Theoretic fundaments of REBIC .................................................................... 169
9.3.1. Spectral equivalence of multi-rate signals ....................................... 172
9.3.2. Spectral properties of the REBIC decimation filter ......................... 175
9.3.3. System filter characteristics ............................................................. 178
9.4. Design example............................................................................................... 180
9.5. Evaluation of the decimator characteristics .................................................... 183
9.5.1. Evaluation of stability ...................................................................... 183
9.5.2. Ideal system evaluation.................................................................... 185
9.6. Hardware implementation............................................................................... 187
9.7. Conclusions..................................................................................................... 190
10. Design examples .................................................................................................... 191
10.1. V-I converter design ..................................................................................... 191
10.1.1. Circuit description and layout........................................................ 191
Contents xi
10.1.2. Measurement set-up ....................................................................... 193
10.1.3. Experimental results....................................................................... 193
10.1.3.1. Static measurements........................................................ 193
10.1.3.2. Dynamic measurements .................................................. 194
10.1.4. Conclusions.................................................................................... 195
10.2. High performance ASDMs ........................................................................... 196
10.2.1. Implementation of first and second order ASDMs........................ 196
10.2.1.1. Design of loop filter and gain stages............................... 199
10.2.1.2. Design of feedback ......................................................... 200
10.2.1.3. Design of asynchronous BQh ......................................... 200
10.2.1.4. Performance limitations and tradeoffs ............................ 201
10.2.2. Experimental results....................................................................... 202
10.2.3. Conclusions.................................................................................... 206
10.3. Second order SDM design ............................................................................ 206
10.3.1. Block diagram and parameterization ............................................. 207
10.3.2. Evaluation and measurements........................................................ 209
10.3.3. Conclusions.................................................................................... 211
10.4. Fifth order SDM design ................................................................................ 212
10.4.1. Modulator architecture and programmability ................................ 212
10.4.2. Loop timing and phase control ...................................................... 213
10.4.2.1. Phase correction with zeroes........................................... 215
10.4.2.2. Phase loss compensation with extra current ................... 216
10.4.3. Measurement example: low power Bluetooth mode ..................... 217
10.4.4. Conclusions fifth order SDM......................................................... 223
10.5. Conclusions................................................................................................... 223
11. Main Conclusions .................................................................................................. 225
A. Analytical evaluation of ASDMs ........................................................................ 227
A.1. Characteristics equation for BQ0 and DC input ............................................ 227
A.2. Generalization of the filter representation ..................................................... 228
A.3. Evaluation of ASDM output spectrum with DFs........................................... 233
B. Application of DF forms in SDM analysis ....................................................... 235
B.1. Magnitude relations in sampled TSIDFs for BQ0 ......................................... 235
B.2. Derivation of DIDF for BQ0.......................................................................... 237
xii Contents
B.3. Derivation of sampled TSIDFs for BQ0 ........................................................ 238
C. V-I normalization and Taylor series expansion............................................... 241
D. Incorporation of the system filter function in REBIC .................................. 243
References........................................................................................................................ 247
Original Contributions .................................................................................................. 253
List of publications ........................................................................................................ 255
Future Work..................................................................................................................... 257
Summary .......................................................................................................................... 259
Samenvatting................................................................................................................... 261
Acknowledgements ....................................................................................................... 263
Biography......................................................................................................................... 265
Abbreviations
AC Alternating current
ADC Analog-to-digital converter
ASDM Asynchronous sigma delta modulator
BT Bluetooth
BW Bandwidth
CCP Cross-coupled differential pair
CCS Continuous-time and continuous-amplitude signal
CDS Continuous-time and discrete-amplitude signal
CMFB Common mode feedback
CMOS Complementary metal oxide semiconductor
CMRR Common mode rejection ratio
CT Continuous-time
DAC Digital-to-analog converter
dB Decibel
DC Direct current
DCS Discrete-time and continuous-amplitude signal
DDS Discrete-time and discrete-amplitude signal
DE (DIF) Differential
DF Describing function
DIDF Dual-input describing function
DLL Delay locked loop
DR Dynamic range
DSP Digital signal processing
DT Discrete-time
EF Equalization filter
ENOB Effective number of bits
FB Feedback
FF Feed forward
FIR Finite impulse response
xiv Abbreviations
FOM Figure of merit
FPGA Field programmable gate array
FS Full scale
FTC Fourier transform for continuous signals
GSM Global system for mobile communication
HDSL High bit-rate digital subscriber line
HOT High-order terms
IC Integrated circuit
IFTC Inverse Fourier transform for continuous signals
IIR Infinite impulse response
INL Integral non-linearity
LC Limit cycle
LCM Limit cycle model
LCQM Limit cycle model for quantization noise
LHS Left hand side
LMS Least mean-squared
LPF Lowpass filter
LSB Least significant bit
LTI Linear time invariant
LUT Look-up table
MASH Multi-stage noise shaping
MD Modulation Depth
MOS Metal oxide semiconductor
MSB Most significant bit
NL Non-linear
NLCL Non-linear closed-loop
NRZ Non-return-to-zero
NTF Noise transfer function
OPAMP Operational amplifier
OSR Oversampling ratio
OTA Operational transconductance amplifier
PCM Pulse-code modulation
PID Proportional integral differential (regulator)
PLL Phase locked loop
PVT Process, voltage and temperature
Abbreviations xv
RCCP Resistor degenerated cross-coupled differential pair
RDP Resistor degenerated differential pair
REBIC Recursive bitstream conversion
RHS Right hand side
rms Root mean squared
ROM Read only memory
SA Spectrum analyser
SC Switched capacitor
SD Sigma-delta
SDM Sigma-delta modulator
SE Single ended
SG Signal generator
SIDF Sinusoidal input describing function
SINAD (SNDR) Signal-to-noise-and-distortion ratio
SNQR (SNRq) Signal-to-quantization noise ratio
SNR Signal-to-noise ratio
SP Simple differential pair
SPC Serial-to-parallel converter
Specs. Specifications
STF Signal transfer function
THD Total harmonic distortion
TSIDF Two-sinusoidal input describing function
UMTS Universal mobile telecommunication system
V-I converter Voltage-to-current converter
WLAN Wireless local area network
WNM White noise model
ZOH Zero order hold
xvi Abbreviations
Glossary
Symbol Description Unit1
cA Amplitude of the idle oscillations in front of the quantizer V
iLCA Limit cycle amplitude in front of the quantizer V
[ ]sb nqT Decimated signal
0BQ Binary quantizer
BQh Binary quantizer with hysteresis
oxC Oxide capacitance per unit area F/m2
miC Binomial coefficient
gc Optimal quantizer gain
d Duty cycle parameter
d One-sided size of the middle level of the three level quantizer
D Quantizer output level
h One sided hysteresis level
( )h t Continuous-time impulse response of a filter
( )sh jT Sampled impulse response of a filter
mg transconductance µA/V
( )2e t Mean-squared error
( )qe t White noise source that represents the quantization error
( )E k Complete elliptic integrals of first kind
clockf Clock frequency Hz
Bf Signal frequency band Hz
ugf Unity gain frequency Hz
sf Sampling frequency Hz
ifb Feedback coefficient
iff Feed-forward coefficient
1 Several symbols listed here are used in normalized expressions and variables and as a result are dimensionless.
xviii Glossary
Symbol Description Unit
( -1) Fourier transform (inverse Fourier transform)
( )i t Quantizer input signal
( ) tailI I Tail current of a differential pair A 2
, ,n out totI Total noise current referred to the output node pA Hz
2RI Noise current of a resistor pA Hz
k Bolzmann’s constant equal to 231.38 10−× J K
k Amplitude ratio
( )K k Complete elliptic integrals of second kind
oil Optimal weighting function for input i
vl Optimal weighting function for DC input
L Order of the loop filter in a Σ∆ ADC
L Transistor length µm
( )L jω Frequency transfer function of the loop filter
iLC Sub-harmonic limit cycle of order i
m Current modulation depth
( )N A Sinusoidal input DF: general DF representation of a quantizer with respect to sinusoidal input with amplitude A
( ), sN A ϕ Sampled sinusoidal input DF: general DF representation of a sampled quantizer with respect to sinusoidal input with amplitude A
( )0BQN A Sinusoidal input DF of a binary quantizer
( )BQhN A Sinusoidal input DF of a binary quantizer with hysteresis
( )3QN A Sinusoidal input DF of a three-level quantizer
( )N V DC input DF: general DF representation of a quantizer with respect to DC input V
( ),AN A B Dual input DF: general DF representation of a quantizer to input signal with amplitude A when another signal with amplitude B is simultaneously applied as its input
( ),i in iDC Q LCN V A
Dual input DF representation of a quantizer to DC input signal with amplitude VQin when limit cycle i with amplitude ALCi is active, signal DF.
( ),i i inLC LC QN A V
Dual input DF representation of a quantizer to the limit cycle i with amplitude ALCi when driven with a DC input signal, limit cycle DF.
( ),, ,in iDC Q LC s iN V A ϕ Sampled signal DIDF for DC input
( ), ,, ,LC in iiA Q n LC s iN V A ϕ Sampled limit cycle DF
Glossary xix
Symbol Description Unit
( ), , ,,QinV AC Qin AC LC iN V A Sampled TSIDFs of the quantizer for the signal component
q Quantization step
q Ratio between two transistor dimensions
q Decimation factor
3Q Three level quantizer (1.5 bit quantizer) p Tail currents ratio
P Power consumption W
qP Quantization noise power W
NLCP Quantization noise power according to LCQM W
ir Local feedback coefficient
zct Time moment of a zero crossing of a signal
( )T jω Tsypkin locus
( )it
T jω Truncated Tsypkin locus to order ti
( )u k Unit step function, Heaviside function
ddV Positive supply voltage V
gsV Gate-to-source voltage V
gtv Effective gate-to-source overdrive voltage V
inV Voltage at the input of the SDM V
,in ppV Peak-to-peak input voltage V
,eq nV Total input referred noise voltage nV Hz
outV DC voltage at the output of the SDM V
inQV Signal DC component in front of the quantizer V
,inQ nV Instantaneous DC component at the quantizer input at each sampling moment n V
ssV Negative supply voltage V
TV Transistor threshold voltage V
w Input voltage ratio W Transistor width µm ( )y t Quantizer output signal
[ ]sy nT SDM output bitstream in idle operation
[ ]* sy nT SDM output bitstream in busy operation
x Degeneration coefficient
xx Glossary
Symbol Description Unit
α Duration of the positive part of the period of a square wave
iα Coefficients in the Taylor series expansion of the transconductor characteristics
β Transconductance parameter A/V2
( )LC t∆ Time-domain representation of the difference between the asynchronous quantizer output signal and the output bitstream.
( )tε Quantization error signal
( )LC tε Quantization error signal according to the LCQM of SDM
iλ Phase margin for iLC : the phase shift that is required to make iLC a possible mode of operation in an SDM rad
µ Frequency of the SDM input signal Hz
nµ Carrier mobility cm2/V-s
iς Phase rotation in the SDM loop at the frequency of the limit cycle i due to the loop filter rad
iρ Phase boundary for iLC : the phase angle, measured from a steady state oscillation conditions, which has to be surpassed in order to render limit cycle i unstable
rad
,i optρ Optimal phase boundary for iLC rad
τ Extra loop time delay sec
( )iiϕ τ Autocorrelation function
sϕ Clock added loop phase shift rad
,i nχ Signal dependent phase shift for limit cycle i and sampling moment n
cω Idle limit cycle frequency (centre frequency) rad/s
iω Instantaneous frequency of the limit cycle oscillations rad/s
iLCω Sub-harmonic limit cycle frequency rad/s
pω Frequency position of pole p in the loop filter frequency transfer characteristics rad/s
zω Frequency position of zero z in the loop filter frequency transfer characteristics rad/s
( )LC fϖ Quantization noise power spectrum density V2/Hz
1. Chapter 1
Introduction The rapid technological development and the introduction of sub-micron processes
decrease the cost of implementation of complex digital functions. That opens new mass markets for many new products ranging from mobile and personal to automotive, entertainment and medical. At the same time, analog electronics is driven to perform even better when implemented in the advanced digital processes and with low supply voltages. Those tendencies motivate a constant research effort not only in the adaptation of analog and mixed-signal functionalities in the new digital processes, but also in significantly improving their performance characteristics.
Sigma-delta modulation (SDM) enables an analog to digital conversion technology with a long-term advantage in the new processes. An inherent property of SDM is the transformation of the amplitude information at its input into time information at its output and in this way trading-off resolution in amplitude for resolution in time. That is why, in contrast with most of the other types of converters, it can benefit from the increased speed and better time resolution of the new processes, without a significant increase of the design complexity and the cost of implementation.
However, high speed signal processing is associated with significant power consumption. That puts special emphasis on the establishment of the fundamental power limits that are required to fulfill the desired functionality and performance. The power efficiency is especially relevant for mobile products, where it directly translates to cost, competitiveness and market success.
1.1. Motivation
Currently, multiple communication applications begin to utilize SDMs with large bandwidths: 20MHz and above, and with high accuracy: better than 14bit. Despite the technological advances, those requirements pose a significant design challenge. At the same time, the room for architectural and conceptual improvements of SDMs seems to be exhausted and the implementations are striving to achieve high performance mainly through an increase of cost and complexity. The performance is often improved via the introduction of multi-bit quantizers or multi-stage (MASH) implementations. Those architectural alternatives increase quite significantly the complexity of the design and lead to an increase of area and power consumption. Alternatively, the performance is improved by the application of higher clock speeds. However, an increase in the sampling frequency requires an increase of the gain-bandwidth product of the building blocks, faster settling times and power hungry decimation filters and ultimately requires an increase of the power consumption and the cost. The power efficiency of the SDM implementation has a high technological and market relevance.
In parallel to the increased specifications, the intensive research work in the field is driven by the lack of complete understanding of the SDM operation. Several important phenomena in SDM operation, like limit cycles and spurious tones remain without solid theoretical
2 Chapter 1: Introduction
explanation. In that respect, the SDM design is still put on a rather heuristic background that relies on simulations. Despite their evident importance, simulations may not include all important design parameters and may not always bring new insights in the SDM operation and behavior. That motivates the investigation of new theoretical approaches for the analysis of the SDM operation and attracts interdisciplinary knowledge. A step further in the conceptual understanding and theoretical description of the SDMs can be done if the non-linear nature of the modulators is recognized and exploited in their analysis and design.
1.2. Goals
The main goal of this thesis is to introduce and investigate a new perspective in the theory and in the design of SD ADCs. In contrast with the general line of theoretical studies in the subject, here, the SD ADCs are treated as non-linear closed-loop systems. The thesis aims to illustrate the new insights that this approach gives in the SD operation and to translate the new knowledge into new design concepts and new system implementations.
A particular goal of the thesis is to investigate the possibilities to reduce the high speed processing in the SD ADC conversion path, either by employing a special mode of SDM operation and/or by employing advanced decimation algorithms.
In parallel with the theoretical advances, the work described in this thesis aims to confirm the developed theories with scientific experiments via integrated circuits implementations and measurements.
1.3. Thesis outline
The thesis consists of an introductory part that is presented in Chapters 2 and 3 and builds a framework composed of non-linear, closed-loop, asynchronously and synchronously oscillating systems and identifies the SD ADC inside such a framework. Chapters 4 and 5 treat the modeling and the analysis of asynchronous SDMs (ASDMs). Their non-linear properties and limit cycle behavior is analyzed in detail. In Chapters 6 and 7 the introduced non-linear analysis is used and further developed for the study of synchronous SDM. Chapter 8 identifies high performance transconductors as key building blocks in the SDM system and treats their analysis and design. Chapter 9 investigates the requirements towards the decimator in the SD ADCs and studies in detail the Recursive Bitstream Conversion (REBIC) as a decimation algorithm. Chapter 10 gives design examples and measurement results from the implementations of a high performance transconductor circuit, two ASDMs and two SDMs that operate in special sub-harmonic, limit cycle modes. In Chapter 11 conclusions are drawn and some directions for future work are pointed out. The outline of all the chapters is illustrated in Fig. 1.1 and is described next in more detail.
Chapter 2 introduces the basic concepts that are used further on in the thesis. It summarizes the general knowledge of closed-loop, non-linear, asynchronously and synchronously oscillating systems. Sigma-delta modulation is identified as a principle that combines all of the above features in order to achieve a specific new operation and functionality. It is shown that the SDM properties depend on the particular choice of non-linear and linear components incorporated in its closed loop system. Asynchronous and synchronous oscillations are pointed out as the mechanisms that enable the transformation of amplitude information into time information. In Chapter 2 the non-linear functions used in the thesis are described. A general form of the loopfilter description is given and the construction of different noise and signal transfer functions is illustrated with examples.
1.3. Thesis outline 3
Chapter 3 treats the methods for analysis of non-linear systems that are used in the scope of this thesis. The commonly used linearized model of the SDM operation is compared with the time-domain non-linear analysis method that employs Fourier series and with the Describing Function (DF) method. The representation of the studied quantizers with their sinusoidal input describing functions is illustrated. The properties of dual input DFs are also discussed.
Fig. 1.1. Thesis outline
In Chapter 4 the idle operation of ASDMs is studied. The idle limit cycle behavior of the ASDMs is described and related to the particular system construction and parameterization. Graphical application of the Fourier expansion method and the DF methods is used for the determination of the idle limit cycles in ASDMs.
In Chapter 5 the ASDM analysis is extended to describe firstly, the impact of the input signal on the limit cycle behavior and secondly, the impact of the limit cycle properties on the quality of the signal processing. General design rules are derived with respect to the required idle limit cycle frequency and the required performance of the building blocks for certain quality of the conversion.
In Chapter 6 the theoretical framework established in the previous chapters is extended for the investigation of the well known synchronous SDMs. With the help of the DF representation of the quantizer, a new limit cycle model (LCM) of the SDM operation is created. A graphical application of the method is introduced that allows a quick evaluation of the SDM system with respect to the main system parameters: loop filter transfer function,
Limit cycle behavior
Multi-limit-cycle operation of SD modulators and efficient decimation, theory and application
Synchronous
SD Modulation
Decimation (REBIC)
Asynchronous
SD Modulation
Time-domain non-linear analysis and DF methods (Chapter 3)
High performance Transconductors
Design examples
Synchronicity in non-linear, closed-loop systems (Chapter 2)
}
}
Chapter 4: Idle limit cycles in ASDMs
Chapter 5: Impact of the input signal in ASDMs
Chapter 6: Limit cycles in synchronous SDMs
Chapter 7: Optimal parameterization of SDM
} Chapter 9{Chapter 8
Chapter 10}
Syst
em T
heor
ySy
stem
Impl
emen
tatio
n
Conclusions Chapter 11}
4 Chapter 1: Introduction
quantizer properties and clock frequency. The LCM is extensively used in the identification of sub-harmonic limit cycle modes in the SDM operation. The multi-limit-cycle operation of SDM is described and illustrated with simulation examples. The advantages and disadvantages of the SDM operation at particular sub-harmonic modes are elaborated with an analytical study and confirmed with simulations.
With the help of the LCM of SDM operation, in Chapter 7, a new approach is introduced for the evaluation of the quantization noise that is introduced by the SDM operation. A new limit cycle model for the quantization noise (LCQM) is proposed that incorporates the switching between the possible LCs in the evaluation of the quantization noise power in the SDM signal band. In the same chapter, several SDM design optimization procedures are described that identify the realization of a particular SDM LC behavior as a trade-off between the required performance and power consumption. The choice of SDM loopfilter characteristics, clock frequency and extra loop delay is elaborated in this specific context.
In Chapter 8 the transconductance amplifiers are identified as a critical building block in the SDM loop. The trade-offs in their implementation are analyzed. The harmonic balancing method for the linearization of the transconductor characteristics is introduced. The method is implemented in a new highly linear transconductor that uses a combination of local resistive feedback and cross-coupling in order to achieve high linearity for minimal power consumption.
Chapter 9 treats a decimation filter implementation based on the Recursive Bitstream Conversion algorithm. The theoretical fundaments of the algorithm are investigated in detail and conceptualized. Design examples are given for the decimator synthesis. Different decimation factors and filter orders are evaluated via high level and FPGA implementations. The stability of the REBIC decimator is analyzed.
In Chapter 10, the designs that are implemented and evaluated in the context of this thesis are presented. Firstly, this chapter discusses the IC implementation and the measurement of the stand alone transconductor stage from Chapter 8. Secondly, two implementations of respectively first and second order ASDMs are described and compared. Measurement results that add extra insight and confirm the theoretical studies in Chapters 4 and 5 are given. Finally, Chapter 10 describes also two implementations of SDMs that utilize a particular LC behavior for the implementation of an optimal trade-off between performance and power consumption. The first SDM uses a second order feedback implementation for the loop filter and a binary quantizer with hysteresis. The second SDM is an extensively programmable multimode SDM that uses a fifth order feed forward implementation of the loop filter and a simple binary quantizer. In this chapter, several design techniques for the modification of the SDM LC behavior are elaborated and their practical implementation is illustrated. Again extensive measurement examples are given and analyzed.
In Chapter 11 conclusions are drawn and the results obtained in this thesis are put in perspective. Based on the developed theory and the obtained results in this thesis, several topics with high industrial and scientific relevance are pointed out for further research.
2. Chapter 2
Oscillations in non-linear, closed-loop systems The goal of this chapter is to identify SDMs as a particular class of non-linear closed-loop
(NLCL) systems. Such an identification allows the study that is presented in this thesis to be put in a much broader perspective than the SDM alone. It also gives awareness of the various aspects of the SDM as a system and establishes the theoretical apparatus that can be employed in the study of its properties. This chapter also introduces the notions for asynchronous oscillations and synchronous (or clock synchronized) operation. The construction of asynchronously and synchronously oscillating NLCL systems is also treated. Special attention is given to the non-linear element (or the quantizer) in SDM systems and the loop filter. Some possible loop filter topologies are discussed.
2.1. Scope and classification
Modern electronics is used in the implementation of an extremely broad range of systems. Those systems can be classified, for example, with respect to their properties, functionalities, application areas and/or time and frequency behavior. Here, special attention is given to some classes of non-linear closed-loop asynchronously and synchronously oscillating systems. Sigma-delta modulation is identified as an example for a system that combines a non-linear closed-loop structure with asynchronous or synchronous operation in order to achieve new behavior and functionality. However, this combination of features is not always recognized in the analysis and design of SDMs. For example, historically, the non-linear nature of the SDMs received little attention and a great majority of SDM implementations is based on linear models. As practice has shown, the linearized approach gives good results when the designer has an excess of resources in terms of power and clock speed or can afford higher complexity of the implementation. However, the linear models cannot give a complete insight in the system behavior and consequently cannot result in maximal design efficiency.
In Fig. 2.1 the coexistence of non-linear, closed-loop, asynchronously or synchronously oscillating systems is plotted as area overlaps. In order to identify the possible combinations, each overlap is numbered and extracted in Table 2.1. The table gives examples for electronic circuits and systems with structure or behavior predominantly described with one or more of the properties under consideration. In practice, very often, a separation has to be made between the primary property of the electronic circuit and the possible secondary properties. For example, the primary property of a closed-loop asynchronous quantizer is the amplitude quantization of the input signal. At lower level, the quantizer can be implemented with a closed or open-loop structure and at even lower level are the non-idealities that are introduced from the particular implementation.
6 Chapter 2: Oscillations in non-linear, closed-loop systems
Fig. 2.1. Identification of the overlaps in system functionalities.
Table 2.1. Examples of characteristic system functionalities
1 The system engineer has to resolve the trade-off between complexity of the system
identification and the mathematical description, and the robustness of the found solution. When more secondary properties of the particular circuit or system are included in the 1 Ring oscillators give another example of a non-linear system that is usually analyzed with linear theory.
Non-linear
Synchronous
Closed loop
Asynchronous
III
III
IV
VVI
VII
IX
X
VIII
Linear,
Open loop
0
XI
ASDM+++XI
Tunnel diode oscillator [4]++IX
0
X
VIIIVII
VI
V
IV
III
II
I
Graph area
Multiple examples
SDM
ring oscillator1
DLL , PLL
sampled quantizer
closed-loop asynchronous quantizer
quartz oscillator
D-latch
PID regulator
open loop asynchronous quantizer
System functionality (examples)
++
+++
+
++
+
Asynchronous (oscillating)
++++
Linear, open loop systems
+
Non-linear
Synchronous (clocked)
Closed-Loop
+
ASDM+++XI
Tunnel diode oscillator [4]++IX
0
X
VIIIVII
VI
V
IV
III
II
I
Graph area
Multiple examples
SDM
ring oscillator1
DLL , PLL
sampled quantizer
closed-loop asynchronous quantizer
quartz oscillator
D-latch
PID regulator
open loop asynchronous quantizer
System functionality (examples)
++
+++
+
++
+
Asynchronous (oscillating)
++++
Linear, open loop systems
+
Non-linear
Synchronous (clocked)
Closed-Loop
+
2.1.1. Non-linear systems 7
description and the analysis, the actual behavior of the system can be modeled with a better accuracy. However, that leads to complexity of the evaluation and increases the design time. The trade-off is then determined by the specifics of the particular design task.
For many years the linear models of sigma-delta operation have given sufficiently good results and because of their extreme simplicity have become a standard approach. Here, SDMs are treated as closed-loop non-linear systems. Moreover, it will be shown that such an approach in their analysis can reveal an internal asynchronous timing mechanism in the SDMs operation. This mechanism takes the form of asynchronous self-oscillations and is evident in the operation of Asynchronous SDMs (ASDMs) that are studied in Chapters 4 and 5. The synchronous SDMs operate with an external sampling clock signal. In such a case, the interaction between the internal timing mechanism and the clock is important. A better understanding of the properties of the SDM is gained from the study of that interaction.
2.1.1. Non-linear systems
The simplest way to define a system as non-linear is to postulate that any system that does not obey the principle of superposition is non-linear. The non-linear system requires a special evaluation of the system response for each type of input signal.
The non-linearity can be found in many levels in the circuit and system design. For example, distinct definitions of the non-linear behavior are possible in the context of a single transistor, operational amplifier, and signal converter or in a complete product such as a portable radio. From engineering perspective the non-linearity can be seen from two different perspectives. Most often it is an unwanted effect because it introduces harmonic components and changes the shape of the signals and deteriorates the direct mapping of linear mathematical functions into real hardware. One of the most important qualitative measures for many electronic circuits and systems is their non-linearity. In practice most systems are approximately linear only in a limited range on their operation. For different systems and applications the linearity usually translates to quality measures as Signal-to-Distortion Ratio (SDR), linear dynamic range and others. When the non-linearity is an unwanted phenomenon it is treated as a non-ideality of the practical implementation. The minimization of this non-ideality takes a permanent research effort. For example, in this thesis, the subject is treated in Chapter 8, in the context of the linearization of the transfer characteristics of voltage-to-current converters.
A second, equally important perception of the non-linear behavior is as a desired property. In such a case, it is the particular non-linear function or behavior that is used in the design in order to obtain the desired system properties. Such a non-linearity is inherently needed for the operation of the system and as such is a wanted phenomenon. A typical example for an intrinsic non-linearity is the sign function performed by a binary quantizer. The systems that convert continuous in amplitude signals into discrete in amplitude signals, by definition are performing a non-linear operation, and thus contain a wanted non-linearity. Those systems and the associated non-linear elements fall in the scope of this thesis. Our study, however, is limited to binary quantizers as those are primarily used in SDM design.
A general classification of non-linear elements that can also be valid for quantizers, defines the non-linear elements as dynamic or static, such that the transfer characteristics of a general dynamic non-linear element depends on the input signal and at least on the first time derivative of the input signal:
( ), ( )y y x t x t• =
(2.1)
8 Chapter 2: Oscillations in non-linear, closed-loop systems
When the non-linear element is static, its output signal is dependent only on the
instantaneous value of the input signal, such that:
( )y y x= (2.2) Static non-linear elements can be single or multiple valued. For the single valued non-
linear elements the output is uniquely determined by the current value of the input. For multi-valued non-linear elements, more than one output value is possible for a given input value and the non-linear element’s response to the input depends on the previous input states. In that respect, the multi-valued non-linear elements possess memory.
The non-linear elements that fall in the scope of this thesis are static and display time invariant behavior.
2.1.2. Closed-loop systems
The general structure of a closed-loop (or feedback) system is shown in Fig. 2.2. It has a signal path that takes the information from the output of the system and feeds it back to the input. In the most general case, the feedback system processes external information as well as the systems response itself, thus a feedback for the performed function is used again for the modification of the system response. Two variations of the structure are common. A feedback system that operates without an input signal is shown in (Fig. 2.2a). In such a case, the system generates a signal that is a function its internal structure, the properties of its building blocks and of its initial state.
A much more common feedback system implementation is shown in (Fig. 2.2b). It processes an input signal and provides a separate feed forward path (FF) path for the input signal and a feedback path (FB) for the output signal. For the moment, those transfer paths are assumed to have linear transfer functions. That allows the application of linear theory for their analysis.
Closed-loop systems are often used in control applications, where some process is monitored and regulated. The function of the feedback is to provide a measurement for the process parameters and compare them with a reference value. The result from that comparison is normally treated as an error in the measured parameter and is further processed by the system in a way that tries to minimize that error.
a) b)
Fig. 2.2. Basic structures of closed-loop systems: a) without an input signal, b) with an input signal.
feed-forwardOut
feed-forwardOut Feed-forward
FF
Feedback
FB
InOutFeed-forward
FF
Feedback
FB
InOut
2.1.2. Closed-loop systems 9
The feedback can take many different forms and implementations. Examples can be given with respect to the position of the feedback: local, global; or the type of the feedback signal: voltage, current, or the effect of the feedback: frequency compensation, linearization.
An attractive property of closed-loop systems is the different transfer function that can be implemented with respect to inputs introduced at different points in the closed-loop. In Fig. 2.3 the addition of the input signal sources ( ),In t ( )tη and ( )tϕ in the closed loop is shown and their transfer functions with respect to the output signal ( )Out t are given in (2.3) to (2.5).
Fig. 2.3. Evaluation of the transfer functions of a feedback system with respect to an input signal and error sources.
( ) 0( ) 0
( )( ) 1 .t
t
Out t FFIn t FF FBϕ
η==
=−
(2.3)
( ) 0( ) 0
( ) .( ) 1 .t
In t
Out t FF FBt FF FBϕη =
=
=−
(2.4)
( ) 0( ) 0
( ) 1( ) 1 .t
In t
Out tt FF FBηϕ =
=
=−
(2.5)
The transfer function of the system with respect to the input signal is referred to as the
Signal Transfer Function (STF). In the case that the signals ( ) and ( )t tη ϕ describe unwanted influences or noise sources, their corresponding systems transfer functions are defined as Noise Transfer Functions (NTFs). The response of the closed-loop system to the signal and to noise sources can be controlled via the feedback and feed forward transfer functions. They can be chosen such that the desired STF is implemented and the impact of the noise sources is minimized. Due to the linearity of the system, equivalent loop transformations can be performed and the transfer function with respect to different points inside the loop can be easily evaluated. The equations (2.3) to (2.5) are going to be used in several occasions further on for the evaluation of SDMs.
2.1.3. Externally and internally synchronized systems
Another notion that is important for the understanding and the determination of the properties of a system is its behavior in time or with respect to a reference source of timing signals. Several scenarios are common practice:
FF
FB
( )e t+ +
+
( )In t( )Out t
( )tϕ
( )tη
FF
FB
( )e t++ ++
++
( )In t( )Out t
( )tϕ
( )tη
10 Chapter 2: Oscillations in non-linear, closed-loop systems
• In many cases an external time reference is required for the implementation of the system functionality. In such a case, the total system or a part of it processes data at discrete moments in time that are synchronous to the time reference. Such a requirement is valid for many digital systems and for most of the data converters that interface analog and digital signals.
• Secondly, there are systems that generate a time reference or have an internal mechanism that positions the information at deterministic moments in time that, in the ideal situation, are not dependent on external data. Oscillators, clock generators and synthesizers, and asynchronous oscillating systems fall into this category. Their primary use is to provide the generated time reference to other systems or to synchronize the input data to the internally generated timing.
In many practical situations, there is a single time reference that synchronizes all blocks in
a given system. The separate blocks may generate time references of their own or use other external timing signals in their operation. In many cases the operation and the performance of the system is dependent on the accuracy of the time reference. An example of such a system is the Delay Locked Loop (DLL) that generates delayed versions of the applied input timing reference. The DLL is a typical externally synchronized closed loop system. In contrast to DLLs, ring oscillators are examples of asynchronously oscillating closed loop systems.
The process of taking samples of analog data, usually at equidistant time moments, is called sampling. When the amplitude domain of the signal remains continuous, a discrete-time analog2 signal is produced. When the sampling is also combined with quantization of the amplitude of the signal, the analog data is converted into a quantized analog sampled-data signal that can be represented by a digital code. A possibility also exists to perform an amplitude quantization of the signal and preserve its continuous-time nature. An example, for such a system is the asynchronous binary quantizer. The output signal of this quantizer, when driven with a time-varying signal with amplitude that fits in the signal space of the quantizer, is a signal with discrete amplitude levels that correspond to the output levels of the quantizer. When the input of the quantizer is periodic, the periodicity of the quantizer output signal is preserved.
In Fig. 2.4, the possible transitions from analog to digital representations of the signals and vice versa are plotted. Several different types of conversions are indicated:
a) From analog signals that can be described as continuous-time and continuous-amplitude signals (CCS) to digital signals that can be described as discrete-time and discrete-amplitude signals (DDS). In this type of conversion the sampling and the amplitude quantization are performed simultaneously.
b) In the left branch of the diagram in Fig. 2.4 the conversion of analog to digital signals is done with an intermediate step: conversion to continuous-time discrete-amplitude signals (CDS), such that firstly quantization in amplitude is performed (non-linear operation indicated as 1NL ). The conversion to a digital signal requires subsequent sampling (indicated as 2S ).
c) In the right branch of the diagram in Fig. 2.4, an intermediate conversion to discrete-time continuous-amplitude signals (DCS) is shown. In this case the, the signals are first sampled (indicated as 1S ) and then quantized in amplitude ( 2NL ).
d) The conversion from digital to analog signal takes the reverse paths and includes DA conversion, preceded or succeeded by interpolation in time, denoted as 1I and 2I .
2 Alternatively, the term analog sampled-data signal, is largely used.
2.1.3. Externally and internally synchronized systems 11
For the sampling operation 1S , the conditions of the sampling theorem should be fulfilled, namely, the bandwidth of the sampled signal should be limited to at most half of the sampling frequency via anti-aliasing filtering.
Fig. 2.4. Possible transitions from analog to digital representation of signals. NL indicates non-linear operation, S indicates sampling, I interpolation in time, and DA digital to analog
conversion.
The sampling process produces a weighted (by a factor 1 T ) version of the continuous-time signal and weighted harmonic sidebands located at integer multiples of the sampling frequency and running to infinity. In frequency domain the ideal sampling operation can be represented by the expression:
( ) 1 2k
kY XT T
πω ω∞
=−∞
= −
∑ (2.6)
where ( )X ω is the frequency spectrum of the analog signal and ( )Y ω is the frequency
spectrum of the sampled signal. The reverse conversion from discrete to analog is called interpolation, which is a form of low-pass or band-pass filtering and, for the case of a zero-order interpolation, can be given by the following formula:
( ) ( ) ( )( )( )
sin
n
t nT Tx t x nT
t nT Tπ
π
∞
=−∞
−= − ∑ (2.7)
A subsequent removal of the distortion can be done, for example for the case of zero-order
interpolation, with sinα α correction. Thus the conversion CCS to DCS representation of the signal can be done without loss of information when the analog signal is band limited.
The conversions CCS to CDS and DCS to DDS employ amplitude quantization. Through this non-linear operation, an infinite number of analog values is mapped to a limited number
Analog
Continuous time Continuous amplitude
Continuous time Discrete amplitude
Discrete time Continuous amplitude
Digital
Discrete time Discrete amplitude
NL1 S1
S2NL2
NLS
I1DA
I2
DA
I
DA
12 Chapter 2: Oscillations in non-linear, closed-loop systems
of quantization levels. In Fig. 2.4 the non-linear transition is denoted as NL . In the general case this is an irreversible operation because there is no mechanism that can extract back the exact amplitude of the original signal. The error that is made depends on the quantization step size referenced to the dynamic range of the quantized signals.
The loss of information resulting from amplitude quantization can be decreased or totally circumvented if during the quantization process the amplitude information of the original continuous signal is placed in time without loss of its original timing information. Intuitively, the placement in time requires a time reference. If the system that converts CCS to CDS has an internal timing mechanism, the continuous-time nature of the system is preserved and the resolution in amplitude can be traded for resolution in time. The timing mechanism can take the form of asynchronous self-oscillations. Following [1], an active electrical system can sustain self-oscillations if it contains a feedback path. Thus the non-linear element (quantizer) should be incorporated in a closed loop in order to create conditions for asynchronous self-oscillations. The non-linear element, together with the linear part of the loop determines the properties of the timing mechanism. The asynchronous SDM that will be discussed in Chapters 4 and 5 can be given as an example for a system that performs the conversion CCS to CDS using an internal timing mechanism and thus minimizes the error of the amplitude quantization.
As will be discussed, the non-linear continuous-time discrete-amplitude systems have merits of their own. However, when the application requires a digital representation of the signals, a sampling operation still has to be performed. In Fig. 2.4, the transition CDS to DDS requires sampling (S2). However, quantized-in-amplitude signals can have a very broad spectrum. For example, the ideal square wave with 50% duty cycle has an infinite spectrum containing the fundamental frequency of the square wave and its odd order harmonics. When such a signal is sampled, the conditions of the sampling theorem cannot be approximated and an error is introduced. The energy of the sidebands that result from the sampling operation causes aliasing. In this situation, it can be taken into account that the information of the amplitude of the signal is already positioned in time via the asynchronous self-synchronization. In such a case, the error that is made by the sampling operation [2], [3], results in a quantization noise spectrum ( )E f , given by:
2
8( )3
c
s
f E ff
= (2.8)
From (2.8), the noise spectrum is proportional to the ratio between the frequency cf of the
sampled square wave signal and the external sampling signal with period sT and inversely proportional to the square of the sampling frequency sf .
The error from the conversion CDS to DDS can be further decreased if the sampling operation is also incorporated inside the closed loop, so that the error it introduces can be subjected to the suppression properties of the loop. Such an incorporation of the sampling into the asynchronously oscillating non-linear closed loop results in realization of a principle known as sigma-delta modulation. A question that has to be answered is whether the introduction of an external clock completely overrules the internal timing mechanisms in the non-linear closed-loop or modifies its properties. This subject is treated in detail in Chapter 6.
2.2. Construction of synchronous and asynchronous NLCL systems 13
2.2. Construction of synchronous and asynchronous NLCL systems
As elaborated in the previous section, a system that transforms amplitude information into continuous-time information can be constructed if a quantizer is incorporated in a feedback loop. The non-linear transfer function of the quantizer is denoted as ( )NL A , where A is the amplitude of the quantizer input. For example, ( )NL A can be incorporated in the linear closed-loop system from Fig. 2.3 with a substitution of the summation point for ( )tϕ . The new system can be described by the block diagram shown in Fig. 2.5. The output of the quantizer is taken as the system output, as a signal that is quantized in amplitude. The system from Fig. 2.5a is assumed to be an asynchronously oscillating non-linear loop. Its function is to convert analog signals into discrete-amplitude continuous-time signals. The conditions under which such a system can sustain asynchronous self-oscillations are investigated in Chapter 4. Its synchronous counterpart is shown in Fig. 2.5b, where the application of a sampling clock is indicated by a switch positioned after the non-linear element and controlled with frequency sf . The second system is implemented as an externally-synchronized non-linear loop that converts an analog input signal into a digital output.
Fig. 2.5. Block diagrams of: a) asynchronously oscillating NLCL system, b) clock synchronized NLCL system.
The properties of the system can be understood when the properties of their building blocks are described and taken into account into the system identification. Next, general descriptions of the linear and non-linear building blocks of the studied systems are given.
2.2.1. Non-linear elements and functions
Because of the extremely large variety of non-linear functions, here, without loss of generality, the attention is concentrated on the non-linear blocks that are of particular interest in analog-to-digital conversion. That includes the very common3 quantizers: the simple two- 3 Most of the theoretical developments can also be applied for multi-bit quantizers.
( )X sFF(s) NL(A)
FB(s)
+
FF(s) NL(A)
FB(s)
+
( )R s ( )I s ( )Y s
( )G s
( )*K s
( )K s
sf( )I s( )R s( )X s
( )G s
a)
b)
14 Chapter 2: Oscillations in non-linear, closed-loop systems
level binary quantizer (BQ0), the three-level quantizer (Q3) and the binary quantizer with hysteresis (BQh). In Fig. 2.6, the signals ( )i t and ( )y t that represent respectively, the input and the output signals of the non-linear elements in time domain, are identified. The static input-output transfer characteristics of these non-linear elements are shown in the middle column of Fig. 2.6, where h is the one-sided hysteresis level, d is the one-sided size of the middle level of the three level quantizer and D± are the output levels. It is important to point out that from the three studied quantizers, only the quantizer with hysteresis is introducing a phase shift in the signal. This phase shift results in a time delay at the quantizers’ output that is linearly and inversely dependent on the applied input frequency. The non-linear function of the BQh is independent from the derivative of ( )i t and consequently is static; however, the BQh is a non-linear element that possesses memory.
Fig. 2.6. Output waveforms for BQ0, BQh and Q3 when a sinusoidal input signal is applied at their inputs (1st column: input signal; 2nd column: non-linear input-output transfer
characteristics; 3rd column: output waveforms).
The three output waveforms are shown to commence at the same time moment. In this way, normalization with respect to the output signal is introduced that takes a common time origin for the output signals and later on allows a common form of the Fourier series expansion to be used for the three waveforms. The phase delay that the BQh is introducing into the signal and the impact of the dead zone in Q3 are taken into account by shifting the input waveform at time 0t = .
2.2.2. Linear elements and functions
The study of the linear part is confined to continuous-time (CT) filters with arbitrary low-pass characteristics, such that the possible gain factors in the system are also included in the
y
i
y
i
y
i
t
i
t
y
t
i
t
i
T
y
tT
tT
2bT
2T
h
d
y
i
t
y
D
D−
D
D
D
D
D
D−
D−
D−
D−
d−
h−
D−
1sin dbπ
−
=
h
d
2.2.2. Linear elements and functions 15
filter function. When the system is asynchronously oscillating, the filters in the NLCL system are in the most typical case continuous. When the system is clock synchronized, a continuous-time implementation is not a functional requirement anymore and discrete-time filters can be implemented as well. However, later in this thesis, an argumentation is presented that gives an advantage of continuous-time filters also for sampled NLCL systems. The advantage is seen as arriving purely from an implementation point of view and does not have an influence on the system analysis.
In addition, the analysis treats only filters with low-pass characteristics. Those filters are of primary interest due to the range of applications that fall in the scope of this thesis. However, the presented analysis can be applied without restrictions to systems that incorporate band-pass or high-pass filters.
A basic CT filter description is given by the filter transfer function defined in the s-domain (2.9). The polynomials ( ) ( ) and P s Q s are of order n and m respectively, such that n<m. For convenience, the polynomials can be represented as a product of their factors, for example ( ) 1 2
1 2 ( ) ( ) ...( ) krr rkQ s s p s p s p= − − − , where each jp is a root of degree jr and k is
the number of distinct roots of ( )Q s . In mathematical terms, the root ip is single when 1ir = .
( ) ( )( )
1 11 1 0
1 11 1 0
......
n nn n
m mm m
P s a s a s a s aL sQ s b s b s b s b
−−
−−
+ + + += =
+ + + + (2.9)
The transfer function can be used for the derivation of other filter representations wherever
they are more convenient for the particular evaluation. For example, gain-phase, polar or root locus representations can be derived from the transfer function. A convenient representation of an arbitrary filter transfer function as shown in (2.10), is its partial fractional expansion. The expansion significantly simplifies the mathematical manipulation of the filter transfer function and for higher order filters can be an important step in the evaluation. A general form of the partial fractional expansion of an arbitrary transfer characteristic that accommodates multiple roots of higher order is defined as:
( ) ,
1 1 ( )
jrkj l
lj l j
AL s
s p= =
= − ∑ ∑ (2.10)
where ( ) ( )( ),1 ( )lim !
jj
jj
r lr
j l jr ls p j
dA s p L sr l ds
−
−→
= −−
and j
j
r l
r ldds
−
− denotes the jr l− derivative
with respect to s . Representation (2.10) for the linear part simplifies the evaluation of ( )L s in the complex plane and/or in the magnitude-phase plane as the calculations can be performed on simple components that participate in the summation.
One and the same filter function can be implemented with different architectures. For example, a second order filter defined with a transfer function:
( ) ( )1
1 2( )( )A s z
L ss p s p
+=
+ + (2.11)
where A is gain and 1,2 1,p z are respectively the poles and the zero in the transfer function.
For example, (2.11) can be implemented in a SDM with two quite different structures as
16 Chapter 2: Oscillations in non-linear, closed-loop systems
shown in Fig. 2.7 and Fig. 2.8. The filter implemented in Fig. 2.7 uses a cascade of integrators with unity gain frequencies iA . The outputs of the integrators are multiplied by feed forward coefficients iff and summed in front of the quantizer. The topology uses only one feedback path from the output of the quantizer to the input and is usually denoted as a feed forward loopfilter implementation. In Fig. 2.7 and Fig. 2.8, the quantizer is given with its amplitude transfer function ( )NL A . The impact of ( )NL A on the operation of the studied systems is discussed in detail in the following Chapter.
Fig. 2.7. Block diagram of a second order feed forward loop filter implementation.
The impact of the linear part in Fig. 2.7 on the system behavior is studied without input signal ( )X s via evaluation of the closed loop transfer function. The transfer function of the loopfilter shown in Fig. 2.7, with ( )Y s taken as an input signal is given in (2.12). It can be further modified if an additional local feedback is applied via 1r− . The feedback coefficient
1r− leads to complex poles in (2.12).
( )( )
( )1 1 2 2 12
1 2 1
I s A ff s A ff fbY s s A A r
+= −
+ (2.12)
Fig. 2.8. Block diagram of a second order feedback loop filter implementation.
( )X s1A
s1A
s2A
s2A
s++ ++ 1ff
( )I s
1r−
( )NL A( )Y s
2fb−1fb−
( )X s
1ff
1As
1As
2As
2As
++ ++2ff( )I s
1r−
( )NL A( )Y s
1fb−
2.2.2. Linear elements and functions 17
In Fig. 2.8, a feedback implementation of the general second order filter in (2.11) is shown. The implementation is characterized by separate feedback paths that are provided to the input of each integrator via weighting factors ifb− . Only the output of the last integrator is fed to the input of the quantizer. The corresponding transfer function for ( )Y s is then given as:
( )( )
( )2 1 2 1 12
1 2 1
I s A ff fb s A fbY s s A A r
+= −
+ (2.13)
Expressions (2.12) and (2.13) show that with respect to the closed loop behavior without
input signal ( )X s , there is no functional difference between the two topologies. These expressions also identify the sensitive points in the architectures that allow the designer to modify the loop filter characteristics. For example, the position of the zero in (2.13) can be modified by either feedback coefficients or by the unity gain frequency of the first integrator.
It is also interesting to compare the two topologies with respect to the transfer characteristics for the input signal ( )X s . For simplicity we can choose ( ) 1NL A = because in a certain frequency band of interest the output signal ( )Y s should represent very accurately the input signal. That is possible only if the non-linear function incorporated in the closed-loop system is not influencing the accuracy with which ( )X s is processed by the loop. Such a simplification will be justified in the following sections. For the moment it is important to point out that it is made for both topologies. Then the signal transfer function as defined in (2.3) can be calculated for both topologies as follows:
( )( )
( )( )
1 1 2 22
1 1 1 1 2 1 2 1FF
Y s A ff s A ffSTF
X s s A ff fb s A A r ff fb+
= =+ + +
(2.14)
( )( ) ( )
1 2 12
2 1 2 1 2 1 1 1FB
Y s A A ffSTFX s s A ff fb s A A r ff fb
= =+ + +
(2.15)
Expressions (2.14) and (2.15), show the possibility to implement quite different signal
transfer functions with the two topologies. For example, the FFSTF in (2.14) can lead to frequency dependent signal peaks, while the FBSTF in (2.15) has a low-pass character.
2.2.3. Feedback transfer
The above examples show the degrees of freedom the designer may have in the implementation of a desired filter function. The coefficients that modify the feedback transfer were included in the signal and in the closed-loop transfer functions. However, the feedback coefficients are also responsible for the scaling of the linear dynamic range of the ideal system to the linear dynamic range of the actual circuits. In most practical situations the dynamic range of the implementation is determined by the linear range of operation of its input stage. Then, the feedback coefficients are responsible for mapping the two-level quantizer output to the dynamic range of the input.
18 Chapter 2: Oscillations in non-linear, closed-loop systems
2.3. Conclusions
In this chapter the systems and functionalities that fall in the scope of the thesis were outlined. Sigma-delta modulators were identified as closed-loop non-linear systems which operation is controlled by an asynchronous or synchronous timing mechanism. Special attention was given to the binary quantizers as non-linear elements, predominantly used in SDMs. A generalized description of the linear part of the loop was given. Several loop filter topologies were discussed in order to demonstrate the possible methods for analysis and several important design choices.
3. Chapter 3
Methods for the analysis of NLCL systems This chapter discusses some methods that can be used for the analysis of non-linear
closed-loop (NLCL) systems and in particular for analysis of sigma-delta modulators. The study of NLCL systems is complicated, because of the specific, signal dependent function that is performed by every non-linear block. In practice, there is no universal analysis method that can give consistent results for every non-linear element. However, for the quantizing non-linear functions that are used in analog-to-digital conversion, and are applied for many industrial applications, several different theoretical approaches have been developed. Next, the most commonly used linearized system model is compared with the Fourier expansion method and with the describing function (DF) method. These three approaches are briefly presented and the scope, the accuracy and the ease of application of each method is discussed. Special attention is given to the DF approach as the most universal method for the investigation of NLCL systems.
The advantages and the disadvantages of the three methods are evaluated with respect to: • the accuracy of the model that is used for the description of the non-linear element
incorporated in the NLCL system; • the possibility to evaluate the internal timing mechanisms and the impact of the
external time reference.
3.1. Linearization of NLCL systems
Linearization of the non-linear operation that is performed inside the sigma-delta loop is by far the most used approach for analysis. For different quantizing functions several linearization techniques have been described and used in practice. An extensive summary is given in [5]. The most common approach treats the error that is introduced from the quantization process as an additive white noise source such that the spectrum of the quantization error is assumed equally distributed up to half of the sampling frequency. The distribution is assumed to be independent of (thus uncorrelated to) the quantizer’s input signal.
3.1.1. White noise model
The white noise model represents the quantization process as an additive white noise source ( )qe t . In Fig. 3.1 its s-domain representation ( )qE s is shown. The noise is assumed to be independent of the quantizer input signal and has a uniform distribution in the quantization interval [ 2, 2]q q− , where q is the quantization step. The system has a loop filter defined by the transfer function ( )L s and a normalized signal space of 1± that corresponds to the maximum and minimum output value of a symmetric quantizer. The parameter gc represents
20 Chapter3: Methods for the analysis of NLCL systems
the gain of the quantizer. For a uniformly distributed quantization noise and N quantization steps, the power of the error signal can be evaluated as:
2
1 2 1 3 21 13 3
2
2 2 2 2 2N
N
N N N NqP e de
−
−
− − − −
−
= = ⋅ ⋅ ⋅ = ⋅∫ (3.1)
The quantization noise power is:
2
12qqP = (3.2)
Fig. 3.1. Linearized model of the NLCL system.
The properties of the linearized system from Fig. 3.1 can be investigated with linear transfer functions for the signal and for the noise as defined in Chapter 2. The noise transfer function is given in the form:
( ) 1( )( ) 1 ( )q g
Y sNTF sE s c L s
= =+
(3.3)
The quantizer gain gc aims to incorporate into the model some dependency on the input
signal ( )X s . In [6], the quantizer gain is calculated such that the quantization noise power is minimized. For that purpose a rather general definition of the optimal gain is given as:
( )( )g
cov i, yc
var i= (3.4)
The calculation of (3.4) requires a priori knowledge of the signal statistics and has to be
redone for each new input. A very similar approach is taken in [7], where gc is derived under the condition that for very small input signals the output power of the quantizer is equal to the noise power. Because the quantizer output in the normalized signal space is a square wave that switches between -1 and 1, the total amount of noise power under such conditions is equal to 1:
( )2
0
1 1 13 1 ( )q j T
g
P d Tc L e
π
ω ωπ
= =+∫ (3.5)
( )X s( )L s++ ++gc ( )Y s
( )qE s
( )I s
3.1.1. White noise model 21
The gain gc is then established for a given spectral shape of the loop filter. Again, however, this approach does not provide the possibility for an a priori calculation of the gain for arbitrary signal levels.
A major advantage, however, of the approximation of the non-linear closed-loop behavior with a linear system is that this approach allows application of the well established linear theory and simplifies the evaluation significantly.
3.1.2. Noise spectrum and SNR
When an external signal ( ) 0X s ≠ is applied to the system given in Fig. 3.1, the quantization noise power spreads in the frequency band up to 2sf , where sf is the applied sampling frequency. Thus, the power spectral density of the quantization noise is expressed from (3.2) as:
( )2
6es
qS ff
= (3.6)
The parameter oversampling ratio (OSR) where 2s BOSR f f= is normally introduced to
indicate the relative clock speed that is used for the conversion of a certain signal band Bf . The oversampling is used as a mechanism that decreases the amount of quantization noise in the desired signal band by spreading the noise energy into a much larger frequency band and in this way decreasing the noise in the signal band of interest. For the closed-loop system the impact of the OSR on the quantization noise should be evaluated with respect to the applied filter function. The noise power at the output that remains in the pass band of the low-pass loop filter ( )L s is then expressed as:
( ) ( )
22
0
1( )1
Bf T
n e j Tg
S f S d Tc L e
π
ωω=
+∫ (3.7)
From (3.7), the maximal SNR is established with respect to the maximal signal in the
normalized space. The filter function ( )L s is dependent on the application. In the predominant number of
implementations it is realized via a low pass (LP) or band pass (BP) filter. Though most of the theoretical studies given in this thesis are applicable for any type of filter, of a primary interest for the applications under consideration are low pass continuous time filters.
3.1.3. Limitations of the approach
The linear approximation is giving good results for higher resolution quantizers. However, for low resolution quantization the results show significant deviation from the experimental results obtained with simulations or from measured hardware systems.
An observation should be made that the developments up to now are independent from the existence of an external or internal timing mechanism. They are valid even for static NLCL systems driven with an input signal. The linearized approach does not take into account the shape of the time waveforms at any point in the system or the particular quantizer implementation. The phase and gain relation in the closed-loop is also not taken into account.
22 Chapter3: Methods for the analysis of NLCL systems
Thus the design of the system is confined to the establishment of a filter function that gives maximum suppression of the quantization noise in a chosen band of interest. For higher order filters the main research effort following that approach is concentrated in finding filter functions that results in a stable SDM.
The linear approach fails to explain or predict several phenomena in the operation of SDM systems like limit cycles or idle tones.
3.2. Analysis of NLCL systems with Fourier series
In several cases, Fourier analysis can be used in the investigation of the properties of the signal waveforms that appear in the SDMs’ loop as a result of the non-linear operation and the internal timing mechanism. The approach uses the fact that the time waveforms of the signals in the non-linear, closed-loop, asynchronous systems can be explicitly determined or, as will be shown later, can be approximated with sufficient accuracy. The time waveforms can be studied with Fourier theory and conclusions for the properties of the NLCL can be drawn. The Fourier analysis method can give exact solutions for the system properties of asynchronous SDMs. When the system is clock-synchronized the application of this approach is complicated due to the time uncertainty that is introduced by the interaction of the sampling clock with the internal asynchronous timing mechanism and the resulting aperiodicity of the signals. For such systems the approach results in an approximation of the system behavior that is valid for certain system parameterizations. A drawback of the approach is that the evaluation becomes laborious for higher order systems and complex non-linear elements.
The power of the Fourier analysis is in the possibility to investigate the frequency properties of signals described with an arbitrary time function. The non-linear operation that is performed inside the loop is taken into account in the establishment of the correct time function and in the conditions for transition from one state of the non-linear loop to another. For the asynchronous NLCL systems, the analysis gives exact solutions in terms of oscillation frequency and amplitude and therefore can directly be used for the establishment of circuit design parameters.
The application of this method can be demonstrated in the analysis of the internally synchronized NLCL system, Fig. 3.2. The non-linear element is a quantizer with hysteresis defined as 2h and output levels defined as D± .
The properties of the system are studied under the condition that no sampling operation is performed inside the NLCL. However, it will be assumed that the loop possesses a periodic asynchronous oscillation mechanism that is active without the presence of an input signal. This oscillation is characterized by the frequency cω . The loop filter ( )L s has low-pass characteristics.
Fig. 3.2. Asynchronously oscillating NLCL system.
( )X s( )L s++
( )Y s( )I s( )NL A
3.2. Analysis of NLCL systems with Fourier series 23
The output signal of the studied binary quantizers that appears when the system operates in idle mode ( ( ) 0x t = ) is represented with its Fourier series expansion:
( ) 01 1
1 cos sin2 k c k c
k ky t a a k t b k tω ω
∞ ∞
= =
= + +∑ ∑ (3.8)
where 0 , ka a and kb are the Fourier coefficients and cω is the frequency of the quantizer
output. For the symmetric quantizers studied in Chapter 2, the input/output functions are odd and as a result 0ia = . Then expression (3.8) is significantly simplified to:
( )1,3,5... 1,3,5...
sin4 4 Im( )cjk tc kk
k k
k t CD Dy t C ek k
ωωπ π
∞ ∞
= =
= =∑ ∑ (3.9)
where kC is a frequency independent factor that characterizes the square wave properties
such that kC is equal to 1 for BQ0 and BQh and to cos kc , with 2(1 2 )c b Tπ= − for Q3. The Fourier series expansions of the output waveforms of the three quantizers from Chapter 2 are summarized in Table 3.1. For BQh and Q3, the amplitudes of the input signals are assumed large enough, such that the quantizers are producing an output signal.
Table 3.1. Fourier expansions of the quantizers’ output waveforms for sine input signal
The above evaluation procedure can be applied for different binary quantizers or other non-linear elements as far as their output waveforms are known and can be expressed in Fourier series.
However, in order to qualify the system properties, an analysis of its behavior is required when an external data signal is applied. The application of the Fourier method in this case is elaborated in Chapter 5.
Theoretically, any periodic waveform can be described with Fourier series. However, the mathematical description of complex multi-valued signals requires significant computation. The elaborated derivation of a closed-form mathematical representation burdens significantly the application of the method.
BQh
wc is the frequency of the limit cycle oscillation and D is the quantizer output level. (Note that the two quantizers have equal output waveforms).
BQ
Q3
ParametersFourier series expansion of the output waveforms
BQh
wc is the frequency of the limit cycle oscillation and D is the quantizer output level. (Note that the two quantizers have equal output waveforms).
BQ
Q3
ParametersFourier series expansion of the output waveforms
( )1,3,5... 1,3,5...
sin4 4 1 Im( )cjk tc
k k
k tD Dy t ek k
ωωπ π
∞ ∞
= =
= =∑ ∑
( )1,3,5... 1,3,5...
sin4 4 1 Im( )cjk tc
k k
k tD Dy t ek k
ωωπ π
∞ ∞
= =
= =∑ ∑
( )1,3,5... 1,3,5...
sin4 4 coscos Im( )cjk tc
k k
k tD D kcy t kc ek k
ωωπ π
∞ ∞
= =
= =∑ ∑ 1 22
bcT
π = −
24 Chapter3: Methods for the analysis of NLCL systems
3.3. Application of DFs for the study of NLCL systems
The Describing Function (DF) method allows a formalized description of the NLCL systems of interest. It replaces the non-linear element with a set of quasi-linear1 functions that are defined for an input of a particular form or combination of forms like DC, sinusoids or signals with Gaussian distribution.
In this section, firstly the derivation and the basics of the DF approach are summarized. Secondly, the application of the approach for non-linear elements driven with DC and one or more sinusoidal inputs is demonstrated. Thirdly, the application of several DF forms is demonstrated in the description of a practical non-linear function that describes the operation of a single bit quantizer with hysteresis. Finally, the applicability of the theory for the study of asynchronous and synchronous SDMs is discussed.
3.3.1. Derivation and basic properties of DFs
The goal of the DF approach is to build a linear approximation of non-linear elements according to a certain linearization rule and with respect to preliminary defined input signals, for example DC or sinusoidal signals. The quasi-linear approximating functions, which describe approximately the transfer characteristics of the non-linear element, are named describing functions. The linearization rule implements a criterion for the evaluation of the approximation. The most common criterion that is used in practice is the minimum mean-squared difference between the approximated output and the actual output of the non-linear element.
Fig. 3.3. Representation of a non-linear function with a set of approximating linear weighting functions.
For generality, the minimization of the mean-squared error is treated as a statistical task. All processes are assumed stationary2 and as such not dependent on the absolute time of observation but only on the difference between two moments of observation. As shown in Fig. 3.3 the input signal ( )ix t is decomposed into an arbitrary number n of constants,
1 The term quasi-linear linearization is used to indicate that the linear approximating functions that are created are different for the different types of inputs or for different magnitudes of the input signal. The dependence on the magnitude is typically non-linear, thus the linearization is quasi linear. 2 A stationary process is a random process for which none of its statistical properties varies with time.
non-linear element N
1( )l t
2 ( )l t
( )nl t
1( )x t
2 ( )x t
( )nx t
( )x t ( )y t
( )ay t
Approximation of N
+
+
non-linear element N
1( )l t1( )l t
2 ( )l t2 ( )l t
( )nl t( )nl t
1( )x t
2 ( )x t
( )nx t
( )x t ( )y t
( )ay t
Approximation of N
+
+
3.3.1. Derivation and basic properties of DFs 25
sinusoids or signals with Gaussian distribution. The terms ( )il t represent a parallel set of linear operators, one to pass each component of the input, for example sinusoidal signal with a certain frequency and amplitude. The goal of the DF methods is to establish a set of linear approximators ( )il t such that the mean-squared difference between the output of this approximation set and the output of the non-linearity is minimal. That implies that the mean-squared error is treated as the expectation of the squared approximation error at any time over all members of the set of possible inputs. The error of the approximation is:
( ) ( )( ) ae t y t y t= − (3.10)
The mean-squared error is then:
( ) ( ) ( ) ( )2 22( ) 2a ae t y t y t y t y t= − + (3.11) where the bars in (3.11) refer to the expectations of the variables. The approximated output ( )ay t is a random variable that can take values over a continuous range, given by the integral
in (3.12), and is defined for any arbitrary time interval t.
( ) ( ) ( )1 0
n
a i ii
y t l x t dτ τ τ∞
=
= −∑∫ (3.12)
The goal of the mathematical evaluation is to find an optimal set of functions ( )il t that
leads to a minimal mean-squared error as defined by (3.11). This poses an optimization task that has been investigated by [8] for the construction of optimal linear filters and in [9] for the construction of general DFs. A solution of the optimization task defined by (3.11) and (3.12) is given for the input i as:
( ) ( ) ( )2 1 2 2 10
( )oi ii il d y t x tτ ϕ τ τ τ τ∞
− = −∫ (3.13)
with ( ) ( )( )ii i ix t x tϕ τ τ= + (3.14)
and oil defined as an optimal linear filter. Equation (3.13) states that the mean-squared
approximation error is minimal when for all non-negative arguments, the input-output cross-correlation function (RHS of (3.13)) for the actual nonlinearity output and input-output cross-correlation function of the approximated output (LHS of (3.13)) are equal for every input component.
Expression (3.14) gives the set of auto correlation functions for the defined set of input signals. An extensive mathematical elaboration on the properties of (3.13) can be found in [9]. Here, only the assumptions that are relevant for the studied system are cited:
• The error 2( )e t is defined as stationary with respect to the variations of ( )il t from the optimum set. Thus the statistical properties of the error are assumed invariant with time.
• The error is uncorrelated with the input signal. This assumption resembles the basic assumption of the linearization model discussed earlier. The main difference,
26 Chapter3: Methods for the analysis of NLCL systems
however, is that the approximated output preserves the correlation between the input and the output that exist in the real system.
The calculation of the optimal approximating functions ( )oil t can be done with (3.14) for specific input signals. The application of the method for DC and sinusoidal signals is discussed next.
3.3.2. DC input DF
The signal that is applied to the input of the non-linear element has a DC value V:
( )i t V= (3.15) Then the autocorrelation function defined in (3.13)3 for an input signal ( )x t V= is:
( ) ( ) 2 2( )x t x t V Vϕ τ τ= + = = (3.16)
Using expressions (3.13) and (3.15) the equation for the optimal weighting function Vl for
a DC voltage V, is:
( ) 22 2
0
( )Vl V d V y tτ τ∞
=∫ (3.17)
Since the statistics of the process are assumed stationary, the mean output of the non-linear
component is a constant and the solution of the integral in (3.17) is given by ( ) ( )2 2( )Vl y t u Vτ τ= , where 2( )u τ is the unit impulse function. The mean-squared
approximation error for a bias input is minimized when the filtering function is a static gain that equates the mean output of the approximation function with the output of the non-linear element. This gain is the describing function for DC input and is denoted as VN . For invariant non-linear elements, the output statistics are stationary and independent from the moment of observation; then, ( ) (0)y t y→ and the DF is given as:
1( ) (0)N V yV
= (3.18)
3.3.3. Sinusoidal input DF
The frequency response of non-linear systems driven with sinusoidal input signals has been of particular interest for several scientific branches. The DFs that describe this particular situation are named sinusoidal input describing functions (SIDF). For sinusoidal input signals, the describing function can be found in a similar way, as described above for DC. The quantizer input signal is defined as:
( ) sin( )i t A tω θ= + (3.19)
3 A we have a single (DC) input, we can leave out the index i.
3.3.3. Sinusoidal input DF 27
where the amplitude A and the frequency ω of the sine wave are deterministic variables
and θ is a random variable with uniform distribution over 2π radians. Then the autocorrelation function for the input signal is defined as:
( )2
2 2
0
1 1sin sin( ) cos2 2
A d Aπ
ϕ τ θ ωτ θ θ ωτπ
= + =∫ (3.20)
The optimum quasi-linearization for a non-linear element driven by a single sinusoidal
input is given [9] by:
2 2( ) (0)sin (0)cosN A y j yA A
θ θ= + (3.21)
With the representation [ ] sinsin ( ) x Ay A y x θθ == , the output of a static non-linear element at
an arbitrary time moment 0 leads to:
[ ](0) siny y A θ= (3.22)
The expectation is a single integral over the range of θ. From (3.21) and (3.22), the DF is then:
[ ] [ ]2 2
0 0
1 1( ) sin sin sin cosN A y A d j y A dA A
π π
θ θ θ θ θ θπ π
= +∫ ∫ (3.23)
The DF can be defined as the complex gain for the fundamental component at the output
of the non-linear element when a sinusoid is applied at its input:
1 ( )1( ) ( ) j AA Aphasor of output component atN A ephasor of input component at A
ϕωω
= = (3.24)
The general form of the sinusoidal input DF is then given by the expression:
[ ]2
0
( ) sin jjN A y A e dA
πθθ θ
π−= ∫ (3.25)
If the non-linear element is static, odd and without memory, (3.25) is given as:
[ ]2
0
4( ) sin sinN A y A dA
π
θ θ θπ
= ∫ (3.26)
The general mathematical apparatus presented up to now can be used for the calculation of
the DFs for the non-linear elements described in Chapter 2. For example, the binary quantizer (BQ0) is a static, odd and memoryless non-linear element, consequently, (3.26) can be used for the establishment of its DF. Taking into account that the output of the quantizer is
28 Chapter3: Methods for the analysis of NLCL systems
( )[ sin ] D ( )y A sign i tθ = where D is the output level of the quantizer and ( )i t is defined in (3.19), then
2
00
4 4( ) sgn( )sinBQDN A D x d
A A
π
θ θπ π
= =∫ (3.27)
Expression (3.27) shows that the sinusoidal input DF for a binary quantizer is a variable
gain that is inversely proportional to the amplitude of the input single tone signal. In a similar way, from (3.26) and with 1sin ( )b Aϕ −= , the DF for Q3 is given in the form:
22
30
4 4( ) 0sin sin 1 A bQD bN A d D d with
A A A
πϕ
ϕ
θ θ θ θπ π
= + = − ≥
∫ ∫
(3.28) The BQh possesses a memory and expression (3.23) should be used for the calculation of
its DF in the form:
( )
( )1
0
2sin /
2
2, sin sin
4 4 41
BQh
j h A
jN A D d D d =A
D h Dh D= j e , with A hA A A A
ϕ π
ϕ
ϕ θ θ θ θπ
π π π−−
= − +
− − = ≥
∫ ∫ (3.29)
The DF method is going to be used extensively further in this thesis and the applicability
of expression (3.27) to (3.29) in the analysis of asynchronous and synchronous sigma- delta modulators will be confirmed with simulations. Here, it has to be pointed out that due to the fact that each DF is defined for a specific type of input signal, the application of the method is much dependent on the possibility to represent or approximate the quantizer input with one of the predetermined forms. In the SDM systems that use a low pass loop filter, the approximation of the quantizer input in an idle mode of operation, with a sinusoid, is straight forward. When the square wave output signal is fed back to the SDM input and consequently filtered by the loop filter, all high frequency components are removed and only the fundamental component of the square wave is provided to the quantizer. Thus, the sinusoidal input DF can be applied for the evaluation of the SDM properties in an idle mode of operation.
The power of the DF methods is in the ease with which higher order systems and complex non-linear functions can be treated. However, the accuracy of the solution is dependent on the linear portion of the closed-loop and on the particular non-linear function. The obtained results need an experimental verification for each particular case.
3.3.4. Multiple input DF
In many cases, it is suitable to use a DF linearization of the non-linear element that takes into account two harmonic inputs or a harmonic input and a DC component. Those
3.3.4. Multiple input DF 29
combinations are particularly relevant for SDM systems driven with DC or harmonic inputs. Let the signal driving the non-linear element be defined as:
( ) sin sin ci t A t B tµ ω= + (3.30) where the frequencies and cµ ω are in the general case not related harmonically. The dual
input DF determines the response of the non-linear element to a signal of a specific form when a second input signal of the same or different form is also present at the its input. Using the same optimal quasi-linear approximation (3.13), but with respect to the two signals given in (3.30), the dual input DF is given in the form:
( ) [ ]( )1 2 1 1 22
1, sin sin sin2AN A B y A B d d
A
π π
π π
ϕ ϕ ϕ ϕ ϕπ − −
= +∫ ∫
(3.31) where 1 tϕ µ= and 2 ctϕ ω= . The dual input DF in (3.31) can be evaluated for BQ0 (static
memoryless non-linear element) by taking into account the following conditions:
[ ] when sin sin 0
sin sin when sin sin 0
{ cc
c
D t k ty A t B t
D t k tµ ω
µ ωµ ω± ≥
+ =− ± <
(3.32) where k B A= . The angle that satisfies the switching condition sin sin 0ct k tµ ω± = is
( )-1sin sin 0ck tµ ω= = . Therefore, (3.31) can be written as:
( ) ( ) ( ) ( )( )
( )1
1
sin sin2 2 2
20 0 0 sin sin
4, sin sin sin c
c
k t
A ck t
DN A B t d t t d t t d t d tA
ωπ π π
ω
µ µ µ µ µ µ ωπ
−
−
= − − ∫ ∫ ∫ ∫
(3.33)
with ( )2
2 2
0
1 sin c cE k k td tπ
ω ω= −∫ , expression (3.33) is given in a closed form [9], by the
expression:
( ) ( )2
8,ADN A B E kAπ
= (3.34)
Following the same procedure as described in (3.32) to (3.34), the dual input describing
function with respect to the second input signal is given as:
( ) ( ) ( ) ( )22 2
8, 1BDN A B E k k K kk Aπ
= − − (3.35)
30 Chapter3: Methods for the analysis of NLCL systems
where ( )E k and ( )K k are complete elliptic integrals of first and second kind respectively. Each DIDF given in (3.34) and (3.35) is real and depends on the amplitudes of the input components. Both functions, however, are frequency independent.
Several applications of the DFs theory are demonstrated in this thesis. In Chapter 4, the
sinusoidal input DF is used for an alternative evaluation of idle LCs in an ASDM. In Chapter 5, dual input DFs are applied for the evaluation of the LC behavior of ASDMs driven with DC or sinusoidal input signal. In Chapter 6, the DF theory presented here is extended with the introduction of the sampled DFs that are use in the study of LC behavior synchronous SDMs.
3.4. Conclusions
Three methods for the analysis of SDMs were presented. The first creates a linear model of the SDM operation that is very suitable for the evaluation of the performance specifications in terms of SNR. The approach can also be used for the evaluation of the required loop filter order and parameterization. The linear approach, however, tends to give incorrect results for single bit quantizers and fails to predict and analyze the magnitude - phase relation of the closed-loop. The Fourier expansion method can allow an exact evaluation of the system properties. However, it is extremely computational intensive and for sampled SDMs only approximate. The DF method uses a relatively simple mathematical apparatus for the establishment of a quasi linear description of the quantizer. A limitation of the method is the requirement for a specific form of the quantizer input signal that in turn requires sufficient filtering from the loop filter.
4. Chapter 4
Idle limit cycles in ASDMs The goal of this chapter is to investigate the limit cycle (LC) phenomenon in
asynchronously oscillating NLCL systems and in ASDMs in particular. The non-linear nature of the studied systems and the magnitude - phase relations in the closed-loop are identified as the main causes for the LC phenomenon. The LC properties of the ASDMs are evaluated with the help of the Fourier expansion method and the describing function method that were studied in the previous chapter. Graphical applications of the methods are proposed and extensively used in the ASDM evaluation. The results of the two methods are compared through examples for different binary quantizers and loop filter orders. Conclusions for the design requirements that the desired LC behavior is posing on the system are drawn. Practical rules for the design of ASDM systems are derived.
4.1. Motivation and definitions
The term limit cycle is used for the description of unforced periodic oscillations in non-conservative NLCL systems. The frequency and the amplitude of these periodic oscillations are independent of the initial conditions and appear for certain system architectures, namely for a certain combination of the non-linear element and the linear part with particular magnitude-phase characteristics. The LC oscillations are possible only for a subset of system parameters that assure the oscillation conditions. Following the above definition, several electronic systems can be identified that display one or more LCs. In Chapter 2, the systems that use an internal synchronization mechanism in their operation were discussed. In most cases, this self-oscillation mechanism is in fact a LC mode that can be chosen in such a way that the desired functionality can be most effectively implemented.
Here, special attention is given to the LC modes in Asynchronous Sigma-Delta Modulation (ASDM). In Chapter 6, those modes are investigated for Synchronous Sigma-Delta Modulation (SDM) systems. The ASDM is identified as an asynchronously oscillating system that transforms the information in the amplitude of its input signal into time information in the output signal. This amplitude-time transformation in the ASDM is done using an inherent periodic self-oscillation: a limit cycle. In this chapter, several important aspects of the LCs modes in the context of sigma-delta modulation are pointed out:
• Limit cycles are the dominant phenomenon in sigma-delta systems. That is evident for the ASDMs where the LCs are inherent and desired system property. The existence of a LC is a functional requirement for the ASDM.
• The possibility for more than one LC mode in the studied systems deserves special attention. Especially in higher order systems, multiple LC modes can exist. In such a case, the conditions that cause operation in one mode or another have to be established. The impact of the particular LC mode on the achievable performance has to be evaluated. The operation in a particular LC mode is associated with a particular combination of the operational or environmental conditions for the system. A change in those conditions can lead to a change of the LC properties and possibly to a deterioration of the desired system performance.
• The impact of the LCs is becoming more evident when high performance is desired
32 Chapter 4: Idle limit cycles in ASDMs
with respect to signal bandwidth and SNDR for limited design resources in terms of power and complexity. In this respect, the insight in the actual LC behavior can result in a robust and cost-effective implementation.
In this chapter, the existence, the determination and the properties of the idle LCs in ASDMs are investigated using the different analysis methods described in Chapter 3. The first approach is based on an investigation of the time domain waveforms that appear in a system operating in a LC mode and uses Fourier series expansion for the determination of the system properties. The application of this method is elaborated in Section 4.2. The second method uses the describing function theory and is investigated in Section 4.3. These two methods are applied for an analytical and a graphical evaluation of the LCs in several ASDMs that incorporate binary quantizers.
4.2. Idle limit cycles evaluation: time waveforms
The task of LC evaluation comprises several aspects: firstly, each NLCL system needs to be evaluated for the presence of idle LCs or for the conditions (range of system parameters) for which idle or input driven LCs can appear or respectively can be avoided. Secondly, the properties of the possible LCs have to be established. Most often, each LC is defined with its frequency and amplitude.
4.2.1. System structure and description
The NLCL system in Fig. 4.1 is investigated for LCs. In order to facilitate the evaluation, the signals in the system are referred to in time domain while the transfer functions of the building blocks are defined in s-domain. The system is constructed by a linear part ( )L s and a non-linear element ( )NL A that are incorporated in a closed loop. An external input signal
( )x t is processed after subtraction of the output signal ( )y t that is fed back to the input. The signal ( )r t that results from the subtraction is applied to the input of ( )L s . For the following analysis it is assumed that ( )L s incorporates all linear, frequency dependent components in the closed loop. The non-linear element is assumed static and frequency independent. That implies that the output of the non-linear element depends only on the signal ( )i t and not on its derivatives.
Fig. 4.1. Asynchronous NLCL system.
For consistency, the amplitude of the LC is defined and observed at a fixed position in the system, for example, for the signal ( )i t in front of the non-linear element (see Fig. 4.1). This observation point is chosen because this is the point in the signal propagation path that exhibits continuous variations in amplitude with respect to system properties and consequently can carry information in the amplitude. In several self-sustained systems, that
( )x t( )L s++
( )y t( )i t( )NL A
( )r t
−
4.2. Idle limit cycles evaluation: time waveforms 33
do not process external data, like for example ring oscillators, the determination of the amplitude and the frequency of the LCs already results in a determination of the most important system parameters.
However, in sigma-delta modulators, a very important third aspect is the evaluation of the LC behavior when the system processes external data. On the one hand the impact of the data signal on LC properties needs to be evaluated. That supposes an indication whether the input signal changes the LC properties and how. From a practical point of view, it is far more important to evaluate the impact of the LC properties on the quality of the data processing that is performed by the system.
In this chapter, only the first two aspects, the amplitude and the frequency of the idle LC oscillations, are extensively elaborated. The impact of the input signal is evaluated in the next chapter, after the complete introduction of the mathematical apparatus and the investigation of the idle LC modes in ASDM.
4.2.2. Existence and frequency of idle limit cycles
Idle limit cycles, by definition, are the LCs that exist when no input signal is applied to the system, thus when ( ) 0x t = and as such are an inherent property of the studied systems. For the sake of completeness, the situation when the system could enter a LC due to external disturbances is not ruled out. Such an option can be investigated after the introduction of the possible evaluation methods. Again, we limit our studies to NLCL systems that incorporate quantizers.
The different properties of the LC can be observed at several points in the systems. The output signal ( )y t is a quantized-in-amplitude signal and for the BQ0 and the BQh it is a binary waveform that switches between upper and lower levels defined as D± . The quantizers’ characteristics are assumed fully symmetric. When the quantizer is driven with a sinusoidal signal, it produces a waveform that is symmetric with respect to the time axes. As the output signal of the quantizers is binary, the LC amplitude and frequency can be observed in front of the non-linear element where the LC amplitude can vary continuously. From now on, the terms “limit cycle frequency” and “limit cycle amplitude” will be used to characterize the signal in front of the non-linear element and are denoted respectively as cA and cω . Of course, when the system operates in a LC, all other signals in the closed loop have frequency
cω as well. For asynchronously oscillating systems with binary quantizers, the conditions for a
possible existence of LC oscillations can be evaluated [2], [10], [11] and [12] via inspection of the time domain waveforms that appear in the NLCL systems under the assumption that the system actually exhibits an idle LC. Then taking into account the properties of the LC and the structure of the system, conditions are derived for the system parameters that assure that those waveforms can indeed be generated.
The time waveforms that can be observed at the outputs of BQ0, BQh and Q3 were shown in Chapter 3. With a mathematical description of the output signal at hand, the evaluation of the possible existence of LCs can be done as in the following steps.
The Fourier series expansions of the output waveforms of the three quantizers were given in Chapter 3 (see Table 3.1). As a second step in the evaluation, the input signal ( )i t of the non-linear element is expressed as a time-domain convolution of the impulse response ( )l t of the linear portion of the loop and the residue signal ( ) ( ) ( )r t x t y t= − . With ( ) 0x t = , that is expressed as:
34 Chapter 4: Idle limit cycles in ASDMs
( ) ( )* ( )i t l t y t= − (4.1) The Fourier transform for continuous (FTC) signals can be used to replace the convolution
in time domain with a multiplication in frequency domain and respectively the inverse Fourier transform for continuous signals (IFTC) can be used to go back to the desired time representation. The transformations are described with the expression:
( )i t = − -1{ ( )* ( ){ }l t y t } = − -1 ( ) ( ){ }L j Y jω ω (4.2)
Using Table 3.1 from Chapter 3, the signal ( )i t can be calculated for BQ0, BQh ad Q3, as:
( )1,3,5...
4 1 Im ( ) cjk tk c
k
Di t C L jk ek
ωωπ
∞
=
= − ∑ (4.3)
where in (4.3) kC is one for BQ0 and BQh and coskC kc= for Q3. From (4.3), the
response of the linear portion of the loop to the feedback signal that is generated by the non-linear element can be described completely. However, for the complete system description, an evaluation should be done for the conditions under which the signals as described actually exist. Those conditions need to be related to the system parameters.
Fig. 4.2. Periodic waveforms for BQ0.
The conditions for the existence of a periodic waveform can be derived by posing a requirement for periodicity on the output signal ( )y t [9]. From the observation of the waveforms in Fig. 4.2, that appear for the simple binary quantizer, it can be concluded that the switching of the quantizer coincides with the zero crossings of ( )i t . At time moment 1S , ( )i t crosses the zero axis from minus to plus and ( )y t switches from D− to D+ ,
consequently for the first derivative of the function ( )i t can be concluded that 0di dt > . If the system is fully symmetric, the periodic oscillation will have period cT and 50% duty cycle. Then at the time moment 2S that corresponds to the half of the oscillation period, thus to
2cT , is valid that 0di dt < . The sufficient conditions for periodic oscillation can be summarized, as follows:
The value of the signal ( )i t at time moments 2cT corresponds to zero crossings. After each zero crossing the quantizer output changes state and the slope of the waveform is reversed. Those two requirements can be described as:
S1 S2 S3 t
i,y
i(t)
y(t)
4.2.2. Existence and frequency of idle limit cycles 35
02cTi−
=
and 02cTdi
dt
− <
(4.4)
where the notation 2cT − indicates that the zero crossing at half a period had occurred due
to transition from plus to minus. For non-zero initial conditions similar to (4.4) relations can be given for 2cT + .
Expressions similar to (4.4) can be constructed for the waveforms that are generated from BQh and Q3. The conditions for oscillation when the NLCL contains a BQh are derived as:
2cTi h−
= −
and 02cTdi
dt
− <
(4.5)
A characteristic property of the three-level quantizer is that its output waveform switches 4
times per one period of the signal ( )y t , (see Fig. 4.3). If 1S is the starting point of the periodic waveform, the first switching occurs at 2S where 2ct bT −= and is from +D to zero. A second switching from zero to –D occurs at half period 2cT − . Because of the doubled number of switching moments the conditions for periodicity are also doubled:
2
2
c
c
bTi d
Ti d
−
−
=
= −
and 0
2
02
c
c
bTdidt
Tdidt
−
−
<
<
(4.6)
Fig. 4.3. Periodic waveforms for Q3.
The periodicity conditions (4.4) to (4.6) for the three quantizers include the first derivative of the signal ( )i t . Using expression (4.3) the derivative is calculated as:
1,3,5...
4 Re ( ) cjk tck c
k
Ddi C L jk edt
ωωω
π
∞
=
= − ∑ (4.7)
t
i,y
2cbT
2cT
S1
S2 S3
t
i,y
2cbT
2cT
S1
S2 S3
36 Chapter 4: Idle limit cycles in ASDMs
The signals ( )i t and di dt are not per definition continuous. A check for discontinuities has to be performed. Using the Mean Value Convergence Theorem 1 for di dtλ = , discontinuities will appear if lim ( )
ssL s
→∞ is non-zero. The magnitude of the discontinuity is
defined as:
( )2 lim2 2c c
s
T Tdi di D sL sdt dt
+ −
→∞
− = −
(4.8)
The Fourier series of a piecewise-continuous function converges to the midpoint of each
discontinuity:
[ ] ( )1,3,5...
4 Re ( ) lim2c c
k c sk
di T D C L jk D sL sdt
ω ωπ
− ∞
→∞=
= −
∑ (4.9)
If the right hand side of (4.9) will remain negative, the convergence of the Fourier series is
assured, thus:
[ ] ( )1,3,5...
Re ( ) lim4k c sk c
C L jk sL sπωω
∞
→∞=
<∑ (4.10)
If condition (4.10) is satisfied, the Fourier series that describe the input signal of each of
the treated quantizers are convergent and consequently the combination of the chosen filter transfer characteristics and non-linear element (represented in this treatment via the specific waveform of its output signal) lead to a system that can sustain periodic oscillations. When condition (4.10) is not satisfied LC oscillations cannot exist in the system.
[ ]
[ ] ( )
11,3,5...
1,3,5...
Im ( ) ( )
Re ( ) lim4
kc
k
k c sk c
C L jk f NLk
C L jk sL s
ω
πωω
∞
=
∞
→∞=
=
<
∑
∑ (4.11)
The left hand sides of expressions (4.4), (4.5) and (4.6) relate the signal in front of the
non-linear element (4.3) with the properties of the particular quantizer. The relation is written in a general form in the first row of (4.11) where 1( )f NL represents a function that has a specific form for each non-linear element. The equation in the first line of (4.11) is the characteristic equation for the idle limit cycles in ASDMs. The results in the form given in (4.11) are summarized in Table 4.1 for the three studied quantizers.
1 Mean Value Convergence Theorem: If a periodic function λ with period 2π is piecewise continuous over the interval [ ]π π− , , then the Fourier
Series of the function converges to the mean value ( ) ( )( )2 2 2c cT Tλ λ− ++ at point ( )2cT where both the left-
hand and right-hand first derivatives of ( )2cTλ exist.
4.2.2. Existence and frequency of idle limit cycles 37
Table 4.1. Conditions for existence and characteristic equations for the limit cycle in ASDMs with BQ0, BQh and Q3.
(4.12) (4.13) (4.14) In the last row of Table 4.1 the portion of the output period in which Q3 is in zero state is
indicated with parameter γ ( 0 1γ< < ). Table 4.1 summarizes the mathematical evaluation of the conditions for existence of an
idle limit cycle in an ASDM that is built with one of the three studied quantizers. It also gives an expression for the calculation of the limit cycle frequency in each case. Examples for the actual calculation of cω are given further in this chapter. A closer look at the table reveals that in all cases the limit cycle frequency cω is determined by a weighted infinite summation of the values of the imaginary part of ( )L jω calculated at odd integer multiples of cω . The condition for oscillation is established with the help of the real part of ( )L jω that is also represented as an infinite summation for odd integer multiples of cω . Those observations can be generalized with an introduction of a new function ( )T jω [11] that is derived from ( )L jω and is defined as:
[ ] [ ]1,3,5... 1,3,5...
( ) Re ( ) Im ( )k
k k
CT j L jk j L jkk
ω ω ω∞ ∞
= =
= +∑ ∑ (4.15)
Expression (4.15) is denoted as Tsypkin’s locus [13]. Thus, the linear part of the loop is
represented as two infinite series in ω , respectively, for the real and for the imaginary part of ( )L jω . From Table 4.1 and (4.15), it can be concluded that for the studied quantizer functions,
the evaluation of the idle limit cycles, in terms of conditions for existence and LC frequency, is confined to the evaluation of the series representation of the loop filter in the form given in (4.15). Table 4.1 can be used for the calculation of the loop filter parameterization for ASDMs with different filter orders and quantizer functions. Next several approaches for the practical implementation of (4.15) are discussed.
BQh
BQ
Q3
Calculation of wcConditions for limit cycle
BQh
BQ
Q3
Calculation of wcConditions for limit cycle
[ ] ( )1,3,5...
Re ( ) lim4c sk c
L jk sL sπωω
∞
→∞=
< ∑
[ ] ( )1,3,5...
Re ( ) lim4c sk c
L jk sL sπωω
∞
→∞=
< ∑
[ ] ( )
( )
1,3,5...
1,3,5...
Re ( ) lim4
Re ( ) lim4
c sk c
c
sk c
L jk sL s
L jk sL s
πωω
ω πγ ω
∞
→∞=
∞
→∞=
<
<
∑
∑
[ ]1,3,5...
1 Im ( ) 0ck
L jkk
ω∞
=
=∑
[ ]1,3,5...
1 Im ( )4c
k
hL jkk D
πω∞
=
= −∑
[ ]
[ ]
1,3,5...
1,3,5...
Im ( )4
Im ( )4
kc
k
kc
k
C dL jkk D
C dL jkk D
πω
πω
∞
=
∞
=
=
= −
∑
∑
38 Chapter 4: Idle limit cycles in ASDMs
4.2.2.1. Closed-form solutions for the loop filter expansions The infinite summations for the real and the imaginary parts of the loop filter as defined in
(4.15) can be solved in a closed form for certain transfer characteristics. In Table 4.2, the closed form solutions for the infinite series of the first, second and third order linear transfer characteristics are shown. For their derivation, the method proposed in [14] has been used.
Table 4.2. Closed-form summations for 1st, 2nd and 3rd order loop filters (from [14]]).
Table 4.2 can be used for the evaluation of transfer characteristics, containing one, two or
three equal poles. An arbitrary transfer characteristic ( )L jω that contains different poles with different orders can be represented with the help of the table. In that case, the function ( )L jω has to be decomposed in partial fractions as suggested in Chapter 3. Each term of the fractional expansion can be substituted with the corresponding term from Table 4.2 and then the final transfer characteristic is established after a summation of the individual fractions.
4.2.2.2. Truncation of the summations The derivation of a closed form solution requires significant mathematical manipulation. A
straightforward alternative approach is to evaluate the sums in (4.15) after truncation of the infinite summations to some manageable order k . In this way, the need to find a closed form solution can be avoided. The evaluation of the truncated summations is done in the following section with a particular example. The results from the truncated summations are compared with the exact closed-form solutions.
( )L s
1
ps ω+
( )2z
p
s
s
ω
ω
+
+
( )( )( )
1 23
z z
p
s s
s
ω ω
ω
+ +
+
( )1,3,5,...
Re ck
L jkω∞
=
∑ ( )1,3,5,...
1 Im ck
L jkk
ω∞
=
∑
tanh4 2
p
c c
πωπω ω tanh
4 2p
p c
πωπω ω
−
( )
( )
28 cosh 2
sinh
c p c
pz p
c c
πω πω ω
πω π ω ωω ω
− −
( )
2 28 cosh2
sinh
pp
c
p pz z p
c c
ππω
ωω
πω πωω ω ω
ω ω
−
− −
( )
( ) ( )
2
2
12
2 1 2
16 cosh2
2sinh
2tanh 22
pc
c
pp z
c c
pp z p z z
c c
ππω
ωω
πω π ω ωω ω
πω πω ω ω ω ωω ω
− −
− + − −
( )
( ) ( )
2 2
21 2 1
22 1 2
16 cosh2
2 sinh
tanh 22
pp
c
pz z p z
c
p pp z p z z
c c
ππω
ωω
πωω ω π ω ω
ω
πω ωω ω π ω ω ω
ω ω
−
− −
− + −
4.2.3. Loop filter impact on the limit cycle behavior 39
4.2.3. Loop filter impact on the limit cycle behavior
In the previous sections, the methodology for the treatment of the linear part in the establishment of limit cycles was built up. Next, this methodology is used for a further evaluation of idle LCs in ASDMs with first and second order loop filters. Such a choice is not limiting the generality of the approach, because as already discussed, any filter transfer characteristic can be decomposed via partial fractional expansion into simple first and second order sections. That makes the evaluation of higher order filters a trivial task. However, later in this section, the approach is extended to accommodate extra loop delay in the ASDM loop. It is demonstrated that the extra loop delay can have a significant impact on the idle LC behavior of the studied systems.
4.2.3.1. First order systems A first order linear transfer characteristic with DC gain pG ω and pole at pω is described
as:
( )p
GL jj
ωω ω
=+
(4.16)
In order to facilitate the required mathematical manipulation, expression (4.16) is
represented with separated real and imaginary parts as:
2 2 2 2( ) p
p p
G GL j jω ωω
ω ω ω ω= −
+ + (4.17)
The ( )T jω locus, based on the ( )L jω representation in (4.17), is:
( ) ( )2 22 2
1,3,5... 1,3,5...( ) p k
k kp p
G C GkT j jkk k
ω ωωω ω ω ω
∞ ∞
= =
= −+ +
∑ ∑ (4.18)
The closed-form solutions for these summations corresponding to the real and imaginary
parts of (4.18) can be found in Table 4.2. Next, the expression for a first order filter, as given in Table 4.2, are used for an analytical evaluation of the LC properties in systems incorporating each one of the three studied quantizers. For the BQh, using the characteristic expression for the LC from Table 4.1 and the corresponding entry for the linear part from Table 4.2, the limit cycle frequency is evaluated from the expression:
tanh4 2 4
p
p c
G hD
πωπ πω ω
− = − (4.19)
and after simple mathematical manipulation is found to be:
22arctanh
pc
p
GDh hGD
πω πω ω= ≈ (4.20)
40 Chapter 4: Idle limit cycles in ASDMs
Expression (4.20) shows that for a first order ASDM with BQh, the LC frequency is proportional to the loop gain and inversely proportional to the hysteresis level. The simplification ( )p parctanh h GD h GDω ω≈ that is used in expression (4.20) is valid for small values of ph GDω . It is valid for any practical ASDM implementation that uses high gain, small hysteresis value and relatively low frequency pole in order to increase the limit cycle frequency. As it is discussed further, in practice, it can be very beneficial to increase the limit cycle frequency to the possible limit for the used technology. That is why the mechanisms that can be used for that purpose are of a primary importance.
A result identical to (4.20) is obtained directly from the imaginary part of (4.18), under the assumption of p cω ω :
( )2 2
1,3,5...
14
c
k c p
Gk hk Dk
ω πω ω
∞
=
− ≈ −+
∑ (4.21)
The standard sum of series ( )
2
20
182 1n
n
π∞
=
=+
∑ can be used for the evaluation of (4.21) to:
2
8 4 2cc
G h GD D h
π π πωω
= ⇒ = (4.22)
The LC amplitude cA can also be established. For example, for the first order system with
BQh, the signal ( )i t results from a single integration (for simplicity ( )L s G s= is taken) of the output square wave and has a triangular shape (Fig. 4.4). The peak amplitude of ( )i t can be established via integration of ( )y t over one quarter cycle, for example, from a zero crossing point to the peak value of ( )i t as shown in Fig. 4.4. That results in the expression:
4
0
44
cT
chA G Ddt GD h
GD= = =∫ (4.23)
where 2 4c cT h GDπ ω= = is the period of the periodic oscillations and cω was established
using expression (4.22). The two approaches for the analytical determination of the LC frequency, illustrated with
(4.19) and (4.21) can also be applied for ASDMs with BQ0 and Q3. For the first order systems, from Table 4.1 and Table 4.2, the following expression, valid for BQ0 and Q3, is constructed:
tanh 04 2
p
p c
G πωπω ω
− = (4.24)
Equation (4.24) has a single solution: cω = ∞ , because the hyperbolic tangent is equal to
zero only if its argument is zero: tanh 0 0= . Thus for BQ0 and Q3, LC oscillations are not possible for a first order system.
4.2.3. Loop filter impact on the limit cycle behavior 41
Fig. 4.4. Time domain waveform of the output signal ( )y t and the signal in front of the quantizer ( )i t , 1st order system for BQh with 0.2h = .
The methodology that was described up to now can be used for the analytical evaluation of the properties of the idle LC in terms of its frequency and amplitude. However, from a practical point of view the trends in the system behavior with respect to a particular parameterization might be more important than the actual LC parameters. Those trends can be very easily visualized with a graphical application of the method. Next, the LC oscillations are evaluated graphically for the treated first order system.
For the study of the LCs in the ASDMs, built with one of the three studied quantizers, it is convenient to represent the linear portion ( )L jω of the loop with a particular series expansion
( )T jω given for the first-order system in (4.18). The plotted trajectories of expressions (4.17) and (4.18) with respect to frequency ω in polar or phase-magnitude coordinates are going to be referred to as Nyquist and Tsypkin’s loci, respectively. These loci for the first order system are compared in Fig. 4.5. The closed form solutions of the summations (4.18) from Table 4.1 are used for the plot of the ( )T jω locus. However, as stated previously, finding a closed-form solution for the infinite series that constitute ( )T jω might be a laborious task and that is why a truncation of the summations deserves to be investigated. For comparison, two truncated summations 1 2( ) ( )t tT j and T jω ω with respectively, k = 11 and k = 31 are also plotted. Several conclusions can be drawn from an observation of Fig. 4.5:
• Firstly, with respect to the Tsypkin’s loci ( )iT jω , the truncation of the summations has a noticeable impact only for low frequencies. For higher frequencies, the three loci overlap completely. The reason for this behavior can be deduced by a closer observation of expression (4.18). Namely, that while each point in the Nyquist locus corresponds to a single frequency, a point in the Tsypkin’s locus is established after a weighted summation of the main frequency component with all its odd multiples. Intuitively, for high frequencies the impact of those multiples decreases and the loci overlap. The same argumentation explains the difference between the truncated and the complete Tsypkin’s loci. That observation justifies the usage of truncated summations in the evaluation when the high frequency range is of a primary importance.
42 Chapter 4: Idle limit cycles in ASDMs
Fig. 4.5. Evaluation of the LC in first order ASDM with BQh (h = 0.4 and 0.04), with the help of Nyquist locus ( )L jω , Tsypkin locus ( )T jω , and truncated loci 1( )tT jω with k = 11,
and 2 ( )iT jω with k = 31.
• Secondly, the Nyquist locus can be regarded as a first order truncation of the Tsypkin’s locus and has the highest deviation from the Tsypkin’s locus for low frequencies.
• In Fig. 4.5, three points in each locus that correspond to the same frequencies: p, 2p and 10p are indicated. All the loci exhibit a relatively fast change for low frequencies and a tendency to saturate towards zero for high frequencies.
The discussion up to now shows that for the higher frequency range only the low order harmonics in ( )jT jω are determining the frequency transfer of the NLCL system and respectively participate in the determination of the idle LC properties. This phenomenon is more pronounced for higher order systems. Its impact is going to be further discussed in the context of DF application for LC evaluation.
From (4.13), the presence of hysteresis in the ASDM can be taken into account by drawing a line in parallel to the real axes and with an offset of 4h Dπ− . The intersection of this line with the transfer loci of the linear part indicates the existence of a LC and can be used for the calculation of its amplitude. In Fig. 4.5, two limit cycles are determined for h = 0.4 and h=0.04. The estimated LC frequency is virtually the same for all four studied representations of the linear portion of the loop. This observation suggests that for the establishment of high frequency limit cycles truncated summations can be used.
The first order linear transfer characteristics can provide maximally 90 deg. phase shift. In the cases when the non-linear element is not providing any phase shift, the phase delay that is accumulated in the loop is not enough to cause self-oscillations, at least in the ideal theoretical situation. In practice, due to the limited bandwidth of the possible implementation, high frequency parasitic poles and zeroes may add the delay required for self-oscillations. In such a case, the system should be treated as higher order already in the initial evaluation.
4.2.3. Loop filter impact on the limit cycle behavior 43
When there is no phase shift in the quantizer of the first order ASDM, idle LC oscillations cannot occur. This conclusion can be drawn from Fig. 4.5 where the BQ0 is represented as a line over the real axes (zero imaginary part). In this case, a crossing with the plotted loci corresponds to an infinitely high frequency. The same conclusion was already drawn from the analytical evaluation.
It is straightforward to plot the trajectories in the complex plane because the chosen mathematical approach uses a separation of the loop filter transfer characteristics into real and imaginary parts in order to construct the Tsypkin’s locus. However, in order to facilitate the comparison with the DF approach that is investigated further in this chapter, and to improve the visualization, the graphical evaluation of the LC properties is demonstrated also in the phase- magnitude plane.
The transition from the complex notations as given in Table 4.2 to a phase-magnitude representation is done by a calculation of the magnitude and the phase for each ω . When it is possible to use a truncated version of the summations in (4.18), firstly the truncated summations are evaluated for each frequency and then the magnitude and the phase for each frequency are established.
The presence of a BQh in the ASDM can be incorporated in the phase-magnitude notation by a transformation of the inequalities given in Table 4.1, as follows:
• An auxiliary complex boundary function Re[ ] Im[ ]aux aux auxN N N= + is defined with Re[ ] 4 lim[ ( )]aux c s
N sL sπ ω→∞
< and Im[ ] 4auxN h Dπ= − ;
• auxN is subsequently represented as: arctan(Im[ ] / Re[ ])2 2Re[ ] Im[ ] i N Naux auxaux aux auxN N N e= + ;
• For a particular filter, the inequality Re[ ] 4 lim[ ( )]aux c sN sL sπ ω
→∞< can now be
determined, and auxN can now be plotted as a directed curve in the phase-magnitude plane, parameterized for ω and for each hysteresis value h.
Fig. 4.6. Evaluation in phase-magnitude plane of the possible LCs in first order ASDM with BQh for different pω and h.
44 Chapter 4: Idle limit cycles in ASDMs
The directed curves originate from points 4h cS Gπ ω≈ and reach asymptotically -180deg. as indicated in Fig. 4.6. Several curves are plotted for different hysteresis values h.
In Fig. 4.6 magnitude-phase plots of several Tsypkin’s loci ( )iT jω for a first order linear element are compared. The loci are drawn after a transformation of the exact summations for the real and the imaginary parts of the loop filter (from Table 4.2) into a phase and magnitude representation. Due to the first order characteristics the phase reaches asymptotically -90deg. The loci display the impact of the pole frequency pω normalized to a fixed DC gain pG ω . A shift of the pole to a higher frequency results in a lower DC gain in the loop and in a decrease of the phase for high frequency. This can be observed for the points in each locus correspondingly. For example, when 10ω π= as indicated in the picture, for a system with a pole at low frequency, the phase shift already approaches the -90deg. line, while for the system with a high frequency pole the phase shift is around -45deg.
An intersection of the ( )iT jω loci with the h-vectors indicates a LC point. The LC frequency can be increased via a decrease of the hysteresis value. The hysteresis has a higher impact on the LC properties in terms of adding more phase shift into the loop when the DC gain in the loop decreases or when pω is shifted to higher frequencies.
Due to the negative feedback in the loop, the impact of BQ0 and Q3 can be visualized with a vertical line at –180deg. Again, it is clear that for an ideal first-order system built with such quantizers LC oscillations are not possible.
4.2.3.2. Second order systems A second order linear transfer characteristic with DC gain 2
z pGω ω , equal poles at pω and a zero at zω is described as:
( )( )2( ) z
p
G jL j
j
ω ωω
ω ω
+=
+ (4.25)
In order to establish the impact of the poles and the zero in (4.25) on the LC behavior, the
DC gain is normalized as 2 1z pGω ω = . Applying the same procedure as described for the first order linear transfer characteristics, (4.25) can be used for the analytical determination of the idle LC frequency. For example, with the simplifications p cω ω , z cω ω and by using Table 4.1 and Table 4.2, the LC frequency is established as:
2
2p
cz
Dh
ω πωω
≈ (4.26)
Expression (4.26) is quite similar to expression (4.22) derived for the first order system.
The only difference is in the formation of the DC gain that arises by taking into account the transmission zero. Intuitively, such a result can be understood from the fact that for the assumptions made, the ASDM loop behavior at higher frequencies, where the active LC is determined, the loop filter approaches first order and the loop operas as first order with DC gain of 2
z pω ω . However, for the second order ASDM, the assumption that the transmission zero is always far from the LC frequency is an oversimplification. That is why its impact is going to be investigated in more detail via a graphical evaluation. In Fig. 4.7 the Bode plots of the transfer characteristics given by (4.25) are plotted for different positions of the
4.2.3. Loop filter impact on the limit cycle behavior 45
transmission zero zω with respect to the double pole pω . Due to the zero, all four transfer characteristics exhibit first order behavior for high frequencies. However, as can be seen from the lower part of Fig. 4.7, the zero position influences the phase characteristic in the transition from second to first order behavior and as a result can be used for the control of the LC behavior. The impact is illustrated in detail in Fig. 4.8.
Fig. 4.7. Bode plots for second order loop filter transfer charac teristic for various frequency positions zω of the zero in (4.25).
In Fig. 4.8 the phase-magnitude plot is shown. The loci ( )iT jω are drawn using the exact summations for the second order system given in Table 4.2. The impact of the pole and the zero frequencies on the LC behavior is visualized for four typical situations:
• z pω ω≈ ; When the pole and the zero are close in frequency, they cancel each other. The systems behavior tends towards a first order one. The conclusions made for the first order system apply in this situation.
• when in (4.25) ( ) 0zjω ω+ = ; If there is no zero in the transfer characteristic, the locus asymptotically reaches -180deg., that is the maximally achievable phase shift for a second order system. Though, ideally the -180deg. line is never crossed, in a practical situation, the system will be very susceptible to parasitics and disturbances. In fact, even some small propagation delay in the loop will result in a total phase delay that exceeds 180 deg .− In such a situation, it is possible to construct a system that can enter a LC mode using any of the three studied quantizers. However, in the strictly ideal situation when there is no phase delay in the linear portion of the loop that is not included in the description of ( )L jω , only a system constructed with a BQh can exhibit LC oscillations.
1 10 100 1000−180
−150
−120
−90
−60
−30
0
Frequency [MHz]
Pha
se [D
eg.]
1 10 100 1000−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
Frequency [MHz]
Mag
nitu
de [d
B]
z pω ω=
without zero
z pω ω>
z pω ω
46 Chapter 4: Idle limit cycles in ASDMs
Fig. 4.8. Evaluation in phase-magnitude plane of the possible LCs in second order ASDM with BQh for different zω and h.
• z pω ω> , If the pole is positioned at lower frequency than the zero, the phase shift exceeds -90deg. for some frequency range, for which the impact of the zero is weak. As the impact of the zero increases for high frequencies, the locus asymptotically reaches -90deg. and the system tends to first order. This situation can have a twofold application. On the one hand, the zero can be used for the creation of a phase margin in the loop in order to decrease the impact of the parasitics and avoid the appearance of a LC for low frequencies. On the other hand, the zero can deliberately be introduced in order to push the LC to higher frequencies. The second situation is valid under the assumption that the parasitics have a strong impact already in a relatively low frequency range and the achievable LC frequency is not sufficiently high. If the gain and the hysteresis can not be further modified in order to increase cω , the transmission zero can be used for this purpose. Evidently, when the system is ideal, those considerations are valid only for ASDMs containing a BQh.
• z pω ω , This situation is treated for completeness though it can be deduced from the argumentation up to now. It shows that if the zero is positioned at frequencies much higher than the poles, it creates significantly less phase margin in the loop for low frequencies. This margin might be insufficient to prevent oscillations due to parasitics.
The introduction of a zero in the second order transfer characteristics gives an additional degree of freedom in the control of the desired LC properties. Thus a zero in the loop filter can be used in ASDM design for the realization and control of the desired frequency and amplitude of the LC oscillations.
z pω ω=
0zω =
z pω ω>
z pω ω
0.5h =
0.1h =
0.02h =
Phase [Deg.]
Mag
nitu
de [d
B]
Phase-magnitude plot: Exact solution for 2nd order linear element and BQh
without zero
4.2.3. Loop filter impact on the limit cycle behavior 47
4.2.3.3. Extra loop delay In the ideal, theoretical situation, the first and the second order systems that were treated
up to now can enter a LC mode only if the quantizer is contributing to the phase delay in the closed loop. For the second order ASDM this argumentation is already superfluous as even some small propagation delay can add the required phase delay and cause LC oscillations. As this delay is unavoidable in any practical situation and thus creates conditions for a LC mode into a second order system that is built with any of the three studied quantizers, this propagation delay needs to be taken into account in the analysis. The delay is modeled as a factor of the type je ωτ− , where τ represents the total delay that is accumulated in the loop irregardless of its exact position. Thus τ unifies all the propagation and parasitic delays whether they are generated in the linear part or in the quantizer itself. If the system is built with a second order integrator and the delay is taken into account, the loop filter is modeled as
( )( )2
j
p
GeL jj
ωτ
ωω ω
−
=+
(4.27)
where G again is the gain. With the assumption that p cω ω , expression (4.27) can be represented with a Tsypkin’s locus as:
( )( ) ( )2 2
1,3,5...
cos sin1c c
k
k kT j G jkk k
ω τ ω τωω ω
∞
=
= − −
∑ (4.28)
By using Table 4.1, the LC frequency of ASDM with BQh can be established from the
expression:
2 31,3,5...
sin4
c
kc
kG hk Dω τ π
ω
∞
=
− = −∑ (4.29)
and respectively for BQ0 as:
2 31,3,5...
sin 0c
kc
kGkω τ
ω
∞
=
=∑ (4.30)
If the closed-form of the summation: ( )31,3,5...
sin8k
kx x xk
π π∞
=
= −∑ is used, the LC frequency
for the BQh is established as:
( )2 28 4 2c
c cc
G h GD D GD h
πω τ π π τπ ω τ ωω τ
− = ⇒ =+
(4.31)
As expected, the delay in the loop decreases the LC frequency. In the limit, when 0τ → ,
expression (4.31) simplifies to (4.26)2.
2 With a different DC gain, as (4.27) does not have a zero.
48 Chapter 4: Idle limit cycles in ASDMs
For an ASDM with BQ0 or Q3, and with loop filter as defined in (4.27), applying the closed-form solution for (4.30), the LC frequency is found as:
( )2
2 02 2
ccc
c
G ω τπω τ πω
ω τ
− = ⇒ =
(4.32)
Thus for a second order ASDM with BQ0 and Q3, for which the loop filter provides
almost -180deg., the LC frequency is inversely proportional to the delay in the loop.
4.2.3.4. Third and higher order systems A characteristic feature of the third and higher order systems is the possibility for LC
modes for any of the three studied quantizers. In all cases, the linear portion of the loop can provide the phase shift required for self-oscillations. New issues that arise for those systems are the stability of the LC oscillations and the number of possible LC modes.
Higher order systems can be treated without restrictions with the Fourier expansion method as developed in this section. However, the complexity of the evaluation increases significantly and the construction of the ( )T jω loci might be a laborious task. Next, an alternative approach that uses DFs is elaborated and is shown that it can significantly simplify the analysis of ASDMs with higher order loop filters.
4.3. Idle limit cycles evaluation: DF approach
The study of the limit cycle oscillations in a non-linear feedback system can be formalized with the help of the Describing Function (DF) representation of the non-linear element. Again, the goal of the study is a system description in terms of existence, frequency and amplitude of the idle LC oscillations in ASDMs.
As was explained in section 3.3, the DF approach builds a linear approximation of the non-linear element according to a certain linearization rule and with respect to a preliminary defined input signal, for example bias, sinusoid or signals with Gaussian distribution. Hereafter, the derivation of the system description based on sinusoidal input describing functions is given. Analytical and graphical applications of the DF method for the quantizers that were treated in the preceding section 4.2 are illustrated with examples. Conclusions for the accuracy of the method and its applicability for the ASDM study are pointed out.
4.3.1. Idle limit cycles in a DF-linearized NLCL system
In this section, the DF theory is first applied to the system description. The non-linear element is replaced by its describing function ( , )N A ϕ that depends on the amplitude of the signal ( )i t in front of the non-linear element and ϕ accounts for a possible phase rotation that is due to the non-linear function. For example, it was shown that the binary quantizer with hysteresis introduces such a phase rotation in the corresponding DF. The linear part ( )L jω of the loop is described as before. When the non-linear element in a NLCL system is represented with a DF, the resulting system can be treated as linear and is shown in Fig. 4.9. The structure of the system and the building blocks are equivalent to those treated in section 4.2 with the exception of the non-linear element, which is replaced with a linear equivalent:
4.3.1. Idle limit cycles in a DF-linearized NLCL system 49
its DF. A major advantage that comes from this representation is the possibility to use a well-established linear theory for the study of the system.
Fig. 4.9. Quasi-linearized ASDM system.
Standard linear theory can be applied also for the evaluation of possible periodic oscillations. Undamped oscillations that are found in the linearized systems are then interpreted as LC oscillations in the non-linear system.
Again, the existence and the properties of the LC oscillation are established for a zero input signal, ( ) 0x t = . The system in Fig. 4.9 is described with the following set of equations:
( ) ( ) ( )( ) ( ) ( ),
I j L j Y j
Y j N A I jω ω ωω ϕ ω
= −=
(4.33)
The solution of which is given by the equation:
( ) ( )1 , 0N A L jϕ ω+ = (4.34) This equation can be interpreted in analogy to the Barkhausen criteria. Namely, that a
closed-loop system is prone to self-oscillation at a frequency for which an integer multiple of 360 degrees of phase shift occurs and the gain is 1.
The DF approach results in a set of equations that can be used for the establishment of an an idle LC and the evaluation of its properties. Equation (4.34) can be used in several ways in the study of limit cycles’ properties. Firstly, it can be solved analytically for the determination of the LC amplitude and frequency. In the general case when ( )L jω and
( , )N A ϕ are complex functions, (4.34) can be written in the form:
( ) ( ) ( ) ( )( ) ( ) ( ) ( )
, , 1
, , 0c c c c
c c c c
Real: Re N A Re L j Im N A Im L j
Imaginery: Re N A Im L j Im N A Re L j
ϕ ω ϕ ω
ϕ ω ϕ ω
− = − + =
(4.35) The system (4.35) of two equations with two unknowns: c cA and ω can then be solved for
an arbitrary linear transfer characteristics and DF representation of the non-linear element.
4.3.2. Analytical solutions: examples
The three studied quantizers have sinusoidal input DFs 0 ( )BQN A , 3 ( )QN A and ( , )BQhN A ϕ , that for output level 1D = are given from (3.27), (3.28) and (3.29) as:
( )L ω ( ),N A ϕ
-
x(t) y(t)i(t)+ ( )L ω ( ),N A ϕ
-
x(t) y(t)i(t)+
( )L s( )X s ( )I s ( )Y s
50 Chapter 4: Idle limit cycles in ASDMs
( )04
BQN AAπ
= (4.36)
( ) ( )2
34 1 ,Q
bN A with A bAAπ= − ≥ (4.37)
( ) ( )12
sin /2
4 4 4, 1 j h ABQh
h hN A j e , with A hA A A A
ϕπ π π
−− = − − = ≥
(4.38)
4.3.2.1. First-order systems Firstly, the LC behavior is evaluated for the first-order filter from (4.16). The first order
loop filter gives the worst approximation of a sine wave in front of the quantizer. In that respect the application of the DF theory for low order systems is still questionable.
From the discussion in the previous section it was clear that a first order ASDM can sustain self-oscillations only if a binary quantizer is incorporated in the loop. This statement can be easily checked with the DF approach, as follows.
The DF of the binary quantizer is dependent only on the amplitude and not on the phase of the applied input signal, thus ( )Im[ ] 0cN A = . The parameters of the LC oscillation follow from the solution (see (4.35))of the system:
( ) ( )( ) ( )
1
0c c
c c
Re N A Re L j
Re N A Im L j
ω
ω
= − =
(4.39)
From (4.16) with p cω ω and (4.36), for the BQ0 case, the following characteristic
equations can be constructed:
2
4 1
4 0
p
c c
c c
GA
G
A
ωπ ω
π ω
=
= (4.40)
The second equation in (4.40) indicates a LC at cω →∞ which confirms the exact analysis,
that LC oscillations cannot exist in a first order system with BQ0. When the same approach is applied for a BQh, the characteristic equations are given as:
2
2 2
2
4 1
4 0
c c
c
c c c
h GA
A h G
A A
π ω
π ω
=
−=
(4.41)
The solution of (4.41) is cA h= , that confirms the evaluation done with the exact approach.
The LC frequency is evaluated as 4c G hω π= (the exact solution gave as result 4 2c G hω = )
4.3.2. Analytical solutions: examples 51
and thus deviates with 36% from the exact solution. As already mentioned this is the worst case deviation from the exact solution, because higher order filters better represent the conditions for the application of the sinusoidal DF.
As the maximum phase shift of the second order filter is not sufficient to cause limit cycle oscillations, the application of second order filters is not much different from that of the first order and will not be separately discussed.
4.3.2.2. Third-order systems Similar examples can be given for a third order loop filter. The third order system
introduces enough phase rotation in the loop and the system can oscillate even if the transfer of the non-linear element does not modify the phase characteristics of the loop. When, for example, the linear part is chosen as a third order integrator with one pole at the origin and two equal real poles:
( )( )2
p
GL jj j
ωω ω ω
=+
(4.42)
where G is the DC gain of the filter, and pω is the frequency of the double pole.
Expression (4.42) can be rewritten as the sum of a real and an imaginary part as:
( )( )
( )( )
22 2
2 22 2 2 2
2 pp
p p
GGL j j
ω ωωω
ω ω ω ω ω
−= − +
+ + (4.43)
With a filter characteristic decomposed in a real and an imaginary part, the possible limit
cycle oscillations can be established with (4.35) and the DF representation of the quantizers given in (4.36), (4.37) and (4.38).
The DF of the binary quantizer is dependent only on the amplitude and not on the phase of the applied input signal, thus ( )Im[ ] 0cN A = . The parameters of the LC oscillation follow from the solution of the system:
( )( )( )
22 2
22 2
22 2
24 1
4 0
p
c c p
p c
c c c p
GA
G
A
ωπ ω ω
ω ω
π ω ω ω
=+
−=
+
(4.44)
34
2 24 14
pc
pc p
c pc p
G GAA
ωπωπ ω
ω ωω ω
==⇒
==
(4.45)
According to (4.45), for the chosen filter function only one LC exists in the studied system
that has a frequency equal to the frequency of the double pole in the filter transfer characteristics.
52 Chapter 4: Idle limit cycles in ASDMs
The DF of Q3 quantizer again has ( )Im[ ] 0cN A = . Then, using (4.37) the system is evaluated as:
( )( )( )
2
22 2
22 22
22 2
24 1 1
4 1 0
p
cc c p
p c
cc c c p
GbAA
Gb
AA
ωπ ω ω
ω ω
π ω ω ω
− = +
− − = +
(4.46)
2 3
4 3
24 21 1 1 14p p
ccc p p
c p c p
G bGb AA p A G
ω π ωπ ω πωω ω ω ω
− = = + −⇒
= =
(4.47)
The system with the three level quantizer also exhibits one LC with frequency pω .
However, the amplitude of this LC is also dependent on the length of the middle level b in the quantizer. For the limit 0b → , at which the quantizer becomes a simple binary quantizer the LC amplitude equates (4.45).
The binary quantizer with hysteresis has a transfer characteristic that is also dependent on the phase of the applied input signal such that ( )Im[ , ] 0cN A ϕ ≠ . That complicates significantly the mathematical evaluation and encourages the application of simpler alternative approaches. Such an alternative approach can be found in the graphical evaluation of the LCs that is described next.
4.3.3. Graphical evaluation of idle limit cycles
A solution of (4.34) can be found if the transfer characteristics of ( )L jω , parameterized with respect to frequency and of 1/ ( , )N A ϕ− , parameterized with respect to amplitude A and phase rotation ϕ , are plotted in the same co-ordinate system. Then the crossing points of the two characteristics determine the solutions of equation (4.34) and consequently the LC points, and, respectively, cω and cA
This approach allows a simple and quick estimate of the LC oscillation. Its main advantage can be seen not only in the establishment of the LC parameters, but also in the visualization of the trends and dependences in the system. The evaluation of the LCs is confined to plotting the two complex functions ( )L jω and 1/ ( , )N A ϕ− in a way that can give most insight in the system. For the purpose, magnitude-phase plots, polar, or root-locus representations can be employed. The method allows a full control on the system behavior and shows the trends in the operation and with respect to the system parameterization. Next the method is illustrated with examples.
An evaluation of the LC behavior is done for a first order system with an ideal integrator and BQh and is shown in Fig. 4.10. On the horizontal axis, the phase shift that the linear part of the loop (the loop filter) and the quantizer are introducing in the loop is shown. On the vertical axis, the magnitude of the loop filter transfer characteristics calculated from (4.17) and the magnitude of 1/ ( , )N A ϕ− , calculated from (4.38), are plotted in dB such that the 0dB reference level corresponds to the output level of the quantizer that is normalized to 1 (D=1).
4.3.3. Graphical evaluation of idle limit cycles 53
Fig. 4.10. Limit Cycle for first order ASDM with BQ0 with hysteresis value h=0.02.
The magnitude of ( )L jω decreases with the increase of frequency while the magnitude of 1/ ( , )N A ϕ− increases with the increase of the amplitude. The integrator provides -90deg. of
phase shift in the loop while the phase shift of the quantizer depends on the hysteresis level. The LC magnitude and frequency can be determined from the crossing point as shown in the picture.
Fig. 4.11. Limit cycle for second order ASDM with BQh with hysteresis value h=0.02.
A w
( )L jω
( )1
,N A ϕ−
Limit Cycle Point
A w
( )L jω
( )1
,N A ϕ−
Limit Cycle Point
Phase [Deg.]
Mag
nitu
de [d
B.]
( )A h=
( ),1 -
N A ϕ
( )L jω
Limit Cycle Point
A
w
( ),1 -
N A ϕ
( )L jω
Limit Cycle Point
A
( ),1 -
N A ϕ
( )L jω
Limit Cycle Point
( ),1 -
N A ϕ
( )L jω
Limit Cycle Point
( ),1 -
N A ϕ
( )L jω
Limit Cycle Point
A
w
Phase [Deg.]
Mag
nitu
de [d
B.]
10
54 Chapter 4: Idle limit cycles in ASDMs
For example, an increase of the hysteresis value leads to a shift of the curve 1/ ( , )N A ϕ− upwards and results in a decrease of the LC frequency and an increase of the amplitude A of the signal in front of the non-linear element.
The graphical evaluation for the second order system with BQh is shown in Fig. 4.11. The crossing point between the filter locus and the 1/ ( , )N A ϕ− line gives the solution of (4.34) and describes a LC.
If there is no hysteresis in the quantizer, 1/ ( , )N A ϕ− is a straight line at -180°. On the other hand, for high frequencies, the filter characteristic is reaching the -180° phase shift with a very small tangent and ideally is not crossing the -180° line. In a practical implementation that would mean that the LC frequency is determined by parasitic phase delays in the loop. Much better control on the desired LC parameters can be achieved via an introduction of a hysteresis.
For non-linear elements that do not introduce phase shift in the loop, the LC oscillations are determined solely by the poles and zeros of the linear part. An increase of the gain in the loop only increases the amplitude of the LC oscillations and does not influence the LC frequency.
4.4. Comparison of DF and time-domain approaches
Because any periodic in time waveform can be described with Fourier series, the Fourier expansion method can always be applied for the study of idle LC oscillations. However, the mathematical description of multivalued signals requires significant computation. Although in many cases a simplification via the application of truncated expressions can be applied, the computational cost of the method encourages its application only in the case when exact knowledge of the LC parameters is required.
On the other hand, the DF approach is giving only an approximation for the LC frequency and amplitude. This approximation is better for higher order loop filters and high LC frequencies. However, the DF can be very easily applied. It gives the designer a simple but efficient tool for the evaluation of the system properties with respect to the particular loop filter function, the possible additional loop delays, and the chosen quantizer implementation.
4.5. Conclusions
In this chapter the properties of the idle LCs in ASDMs were studied with the Fourier expansion method and the DF method. Analytical and graphical applications of both methods were demonstrated with examples. A methodology for the application of the methods for systems with an arbitrary order of the loop filter was suggested. It was demonstrated that the Fourier expansion method can be used for the exact calculation of the amplitude and the frequency of the idle LC oscillations in NLCL systems with binary quantizers. The application of the DF method for a first order system shows a deviation of 36% from the exact results. This deviation is due to the initial construction of the DF with respect to a sinusoidal signal. For first order systems, however, the signal in front of the quantizer has a triangular shape. That explains the deviation from the exact solution. The deviation for third and higher order loop filters can be considered negligible.
The graphical applications of both methods showed to be very useful for the evaluation of the trends in the system behavior with respect to the properties and the parameterization of the building blocks. The graphical implementation of the DF method is going to be extensively used further on in the thesis.
5. Chapter 5
Evaluation of input-driven ASDMs In this chapter, the impact of the input signal on the operation of ASDMs with binary
quantizers is studied. The Fourier expansion method and the DF methods are used for the analysis of ASDM behavior for DC and harmonic inputs. The evaluation is done in several directions. Firstly, the impact of the amplitude and the frequency of the input signal on the LC behavior is studied in terms of frequency and magnitude modulation caused by the input signal. The output spectrum is described analytically. Secondly, an investigation is done on the impact of the idle LC properties on the quality with which the input signal is processed. The performance of the system as a function of the idle LC frequency and the order of the loop filter is evaluated. Both evaluation methods are illustrated with examples and compared.
5.1. Application of the Fourier expansion method
Up to now, the properties of the LC modes that appear in ASDMs were evaluated with respect to the properties of the asynchronous system: the filter order and parameterization, and with respect to the particular type of non-linear element. The study established the possible idle LC oscillations, in terms of amplitude and frequency as a function of the system parameters. This knowledge gives a sufficient insight for systems that do not process external data (for example ring oscillators).
Fig. 5.1. Impact of the input signal: evaluation steps for Fourier expansion method.
However, for sigma-delta modulators, it is very important to evaluate the behavior of the system when an input signal is applied. The evaluation steps used by the Fourier expansion method are shown in the block diagram in Fig. 5.1 and are applied in the analysis presented in this section.
The evaluation is done under the assumption that an idle LC with 50% duty cycle exists in the system. This assumption was quantified in the previous chapters to several general
1. Description of the output waveform with Fourier series
2. Subtraction from the input
3. Time-domain convolution with the loop filter impulse response
4. Evaluation of the zero crossings (impact of the non-linear element)
56 Chapter 5: Evaluation of input-driven ASDMs
requirements for the construction of the ASDM loop and for the parameterization of its building blocks. Next, the behavior of the ASDM shown at the left hand side of Fig. 5.2 is evaluated for DC and harmonic input signals.
5.1.1. ASDM analysis for a DC input
The evaluation for a DC input value is decoupled from that of harmonic signals, firstly because a DC input signal can be treated as a simpler intermediate case in the investigation that gives insight in the methodology and secondly, because a DC input often appears in practice when the hardware implementation introduces a DC offset. The analysis here continues with an investigation of the impact of the applied DC input signal on the amplitude and the frequency of the idle LC oscillation. From Fig. 5.1, a starting point for the evaluation is the analytical description of the ASDM output signal (an example of the output waveform is shown at the right hand side of Fig. 5.2). An examination of the output waveform shows that duty cycle of the ASDM output signal is modulated by the DC input.
In the previous chapter, the conditions for existence, the frequency and the amplitude of the LC oscillations were established for ASDMs operating in idle mode. The Fourier expansion method that was presented there can be further extended for the study of the system behavior when a DC input signal ( )x t V= is applied. Next, this modulation is related to the idle LC frequency and quantified.
Fig. 5.2. ASDM driven with DC signal: input and output waveforms.
The average value of the ASDM output signal corresponds to the DC value applied at the input. Such a statement is based on the assumption that the loop gain for DC signals is very high. The behavior of the system can be established taking into account that the idle LC frequency and amplitude are changed to accommodate the input signal. In order to distinguish from the idle mode of operation, the terms DC modulated amplitude and DC modulated frequency are introduced for the LC oscillations in the presence of a DC input signal. The DC modulated frequency is defined as 2i Tω π= where T is the period of the output signal that appears for input signal V . Again, as in the idle case, the frequency iω can be observed at any point in the closed-loop, while the DC modulated amplitude iA is defined only for the signal in front of the non-linear element. The frequency iω can be seen as a variable that departs from the center frequency cω of the idle LC oscillations by an amount that depends
( ) ( ),x t y t( ) ( ),x t y t
-
( )X sL(s) NL(A)+
( )R s ( )I s ( )Y s
5.1.1. ASDM analysis for a DC input 57
on the applied DC value of the modulating signal. Further in this chapter, the exact relation between the applied DC value and iω is derived.
In Fig. 5.3, the output waveform of a binary quantizer (BQh or BQ0) is shown, where the period of oscillation is normalized to 2π . The variable α indicates the duration of the positive part of one period of the output signal. The variations of the duty cycle are characterized by the duty cycle parameter d defined in (5.1) such that 0 1d≤ ≤ . The situation 1d = (or 0d = ) indicates that the output of the modulator is constantly at a high (low) level. That means that the applied input signal has an amplitude that causes an overload and cannot be processed by the loop. Because in overload the loop is in fact not operational, the analysis is always done under the assumption that 0 1d< < . If the output level D of the modulator is normalized to 1± it follows that 1V < . These initial requirements are summarized in (5.1) as follows:
1 and 2Vd d
Tα +
= = (5.1)
Fig. 5.3. The output square wave modulated with a DC.
As an indication for the magnitude of the applied input signal the term Modulation Depth (MD) is used. The MD is the ratio between the amplitude of the input signal and the maximum dynamic range or the Full Scale (FS) input signal that can be applied to the system without causing an overload. The MD is normally given as a percentage of the full scale (FS) signal. As already stated, 1V < is the only situation with a practical meaning in the normalized case. That is why the parameter MD remains always less than 100%. Later in this section, the MD is related to the behavior and the performance of the system. Next, the properties of the output signal are investigated. The modulated square wave that appears at the output of the system is shown in Fig. 5.3. When the period of the repetitions is normalized to 2π for some arbitrary input DC value V , the output waveform is described with Fourier series by the following expression:
Tα
D
D
t
( )y t Tα
D
D
t
( )y t
2π 4π0
iαiT T
α
D
D
t
( )y t Tα
D
D
t
( )y t
2π 4π0
iαiT
58 Chapter 5: Evaluation of input-driven ASDMs
( )( )
1
sin cos4
4
i
k
k k tD Ty t
k
απ ωα π
π
∞
=
− = +
∑ (5.2)
where as before, the output level of the quantizer can be normalized as 1D = . The above
expression can be represented in terms of the modulation variable d as:
( ) ( ) ( ) ( )1
sin cos2 1 4 i
k
k d k ty t d
kπ ω
π
∞
=
= − + ∑ (5.3)
In expressions (5.2) and (5.3) the impact of the input signal is seen firstly as a DC
component that appears in the Fourier series and is equal to ( ) ( )DCy t α π π= − . Using the relations given in (5.1) the DC component in the output is easily evaluated to ( )DCy t V= . Secondly, the harmonic content in the output signal is also modified with respect to idle mode. It consists of both even and odd weighted multiples of iω . According to (5.3), in order to establish the impact of the DC input on the output harmonic content it is sufficient to establish an analytical relation between iω and V .
The task of the subsequent evaluation is to establish the relation between the idle LC frequency cω and the DC modulated frequency iω for each input voltage V . According to the second and third steps of the evaluation procedure in Fig. 5.1, the output signal is subtracted from the input signal and the resulting signal ( )r t is convolved in time domain with the impulse response ( )l t of the linear part of the loop. After the representation of the convolution in time as a multiplication in frequency domain, and the application of inverse Fourier transform, the signal ( )i t in front of the non-linear element is derived. Those steps are indicated in (5.4).
( )i t = -1{ ( ) ( ) ( )1
sin sin(2 1) 4{ }i
k
k d k tV d L j
kπ ω
ωπ
∞
=
− − − ∑ } (5.4)
The frequency response of the filter ( )L jω results in non-zero components in (5.4) only
for DC, where (0)L G= and G is the DC gain of the filter, and for integer multiples of the instantaneous frequency iω . Thus, the filter frequency transfer in (5.4) could be represented as ( )iL jkω . This notation is used in Appendix A.1 in the manipulation of (5.4) to:
( ) ( ) ( ) ( ) ( ) ( ) ( )( )1
sin(2 1) 4 Re cos Im sini i i i
k
k di t V d G L k t k t L k t k t
kπ
ω ω ω ωπ
∞
=
= − − − − ∑
(5.5) Expression (5.5) describes exactly the signal in front of the non-linear element. It is valid
for an arbitrary filter function (that assures LC oscillations) and for a periodic binary output signal (bit-stream) that can be described with an expression similar to (5.2).
Up to now, the impact of the non-linear function performed by the quantizer is taken into account only in the mathematical description of the time-domain waveform at its output (5.2).
5.1.1.1. Derivation of ASDM Characteristic Equations 59
This description, however, is not complete because it does not contain any information about the phase relation between the output signal ( )y t and the signal ( )i t applied at the input of the quantizer. This phase relation is determined by the specific properties of the non-linear element in the loop. The establishment of a general relation for an arbitrary non-linear function is an impossible task, due to the very large variety of non-linear functions. However, a general system description can be sought for each particular non-linear element. Again, as in the idle case, the following analysis is limited to quantizers with highest industrial relevance like BQh and BQ0. However, the application for more specific cases like Q3 is straightforward.
5.1.1.1. Derivation of ASDM Characteristic Equations The capability of the Fourier expansion method to describe the response of ASDMs to DC
input signals can be easily demonstrated for a simple first order filter function. Later on in this section, the results of the method are generalized for several basic filter transfer characteristics.
The waveforms shown in Fig. 5.4 correspond to a first order ASDM built with an ideal integrator as a loop filter and a BQh. Similar waveforms can be identified for an arbitrary filter and, as a result, the mathematical elaboration that follows can be applied.
For the example in Fig. 5.4, the time duration of α and thus of the positive part of the output bitstream is 3 1t - t . The zero crossings, at time moments event , of the signal ( )i t (given by (5.5)) are exactly in the middle between two crossings of the hysteresis levels h± (see Fig. 5.4).
Fig. 5.4. Waveforms in a first order ASDM with BQh: a) signal ( )i t in front of the non-linear element, b) DC input signal and output square wave ( )y t .
At time moment 2t the signal ( )i t crosses the zero axis and in time moments 2 2t α± , ( )i t crosses the hysteresis levels. These two crossings define two equations, respectively as:
( ) ( ) ( ) ( ) ( ) ( )( )1
sin 2(2 1) 4 Re cos Im sini i i i
k
k dV d G L k k d L k k d h
kπ
ω π ω ω π ωπ
∞
=
− − − − = ∑
(5.6)
( )i t ( ) ( ),x t y t( )i t ( ) ( ),x t y t
t1 t2 t3 t4 t5 t1 t2 t3 t4 t5
60 Chapter 5: Evaluation of input-driven ASDMs
( ) ( ) ( ) ( ) ( ) ( )( )1
sin 2(2 1) 4 Re cos Im sini i i i
k
k dV d G L k k d L k k d h
kπ
ω π ω ω π ωπ
∞
=
− − − − = − ∑
(5.7) Expressions (5.6) and (5.7) build a system of two equations with two unknowns α and iω .
The above system of equations can be significantly simplified via a summation and a subtraction of (5.6) and (5.7). With the relations 2i iTω π= and i idTα = , the following expressions are derived:
( ) ( ) ( )1
sin 22 1 2 Re i
k
k dV d L k
k Gπ
ωπ
∞
=
− − = ∑ (5.8)
( ) ( )2
1
sinIm
4 ik
k dh L kkππ ω
∞
=
= − ∑ (5.9)
Expressions (5.8) and (5.9) allow investigation of the behavior of the system with respect
to the properties of the loop filter. They can be defined as characteristic equations for an ASDM with BQh for a DC input signal. These equations give an important analytical base for the establishment of the DC modulated frequency and the duty cycle parameters as a function of the filter characteristics. Those equations can also be applied easily for the specific case of BQ0 with 0h = .
5.1.1.2. Example for a first order ASDM with BQh Next, the solution of the characteristic equations (5.8) and (5.9) is illustrated for an ideal
first order integrator as a loop filter. The ideal integrator is described with ( )Re[ ] 0iL kω = and ( )Im[ ] 1iL k kω ω= . When this integrator description is used in (5.8) and (5.9) the following
expressions are derived:
( )2 1 0V d− − = (5.10)
( )2
21
sin14 ki
k dhkππ
ω
∞
=
= − ∑ (5.11)
From (5.10) follows that 2 1i id V− = and then the duty cycle parameter is finally simplified
to:
12V d +
= (5.12)
The infinite sinusoidal series from (5.11) can be represented in a closed-form by the
following mathematical manipulations [16]:
( ) ( ) ( )2
2 2 2 21 1 1 1
sin 1 cos 2 cos 212 2 2k k k k
k d k d k dk k k kπ π π∞ ∞ ∞ ∞
= = = =
−= = −∑ ∑ ∑ ∑ (5.13)
5.1.1.2. Example for a first order ASDM with BQh 61
Expression (5.13) simplifies further, when the following tabulated infinite summations are
used:
( ) ( )22 2
2 21 1
cos 2 216 4 12k k
k d d and
k kπ π ππ π∞ ∞
= =
−= = −∑ ∑ (5.14)
For an ideal integrator, the LC frequency in idle mode was derived in Chapter 4 to be
2c hω π= . The idle LC frequency and expressions (5.14) are substituted in (5.11) to arrive to the following representation:
( )( )2 21 2 1 1i i
c c
d Vω ωω ω
− − = ⇒ = − (5.15)
Expression (5.15) gives an important relation between the LC frequency in idle mode and
the instantaneous frequency of the LC when the system is driven with a DC input signal. From (5.15), it follows that 0 i cω ω≤ ≤ .
Fig. 5.5. Instantaneous frequency with respect to the applied DC input amplitude and idle limit cycle frequencies of 0.8, 1 and 1.2 MHz for a first order ASDM with BQh.
In Fig. 5.5, the DC modulated frequency iω , as defined in (5.15), is plotted with respect to the amplitude of the applied input voltage and for several idle LC frequencies.
From (5.15) and Fig. 5.5, it can be seen that for input DC signal levels that correspond to 50% MD, the DC modulated frequency decreases with 25% with respect to the idle LC frequency. Respectively, for 80% MD, the decrease is 64%. Of course, the instantaneous frequency for a fixed DC input value (and consequently, for a fixed modulation depth) is highest for the system that operates with the highest LC frequency in idle mode. In each case, however, the overload condition is accompanied by a significant degradation of the instantaneous frequency. In fact, an overload condition can be described as a situation where the input signal is so high that the closed-loop cannot maintain LC oscillations any more.
0 0.2 0.4 0.6 0.8 10
2
4
6
8
10
12x 10
5
Input amplitude, V
Inst
anta
neou
s fr
eque
ncy,
Hz
1MHz idle limit cycle;0.8MHz idle limit cycle;1.2MHz idle limit cycle;
Input DC value [V]
DC
mod
ulat
ed fr
eque
ncy
[Hz]
Input DC value [V]
DC
mod
ulat
ed fr
eque
ncy
[Hz]
62 Chapter 5: Evaluation of input-driven ASDMs
5.1.1.3. Generalization of the filter description With expressions (5.8) and (5.9) a general description of ASDMs with BQh and an
arbitrary loop filter is given. Very similar characteristic equations can be established for BQ0 and Q3. Though the example for a first order ideal integrator, described in Section 5.1.1.2, showed the possibility to evaluate the ASDM operation for a DC input via (5.12) and (5.15), it did not elaborate on a generally applicable procedure for the evaluation of ASDM properties with an arbitrary loop filter.
Next such an evaluation procedure is developed. An extensive elaboration of several examples is given in Appendix A.2. The results that are summarized in this section can serve in the ASDM design process as a reference. For the evaluation of the ASDM characteristic equations (of types (5.8) and (5.9)), the same approach as described in Chapter 4 for the idle mode of operation can be used. There, the system properties were defined with the help of an expansion of the filter characteristics into infinite series of weighted odd multiples of the LC frequency. Here, the ASDM characteristic equations (5.8) and (5.9) also contain series expansions of the filter function. The main difference, with respect to the idle mode is in the type of series representation for the loop filter. Namely, in (5.8) and (5.9) the real and the imaginary parts of the filter characteristics are expanded into series containing not only odd, as in idle operation, but odd and even integer multiples of the DC modulated frequency and are weighted by harmonic terms that depend on the type of the quantizer.
The solution of the characteristic system with respect to d and iω constitutes a mathematical problem of finding a close form solution for the series expansion of the specifically weighted filter function. In the most general case of arbitrary filter functions and non-linear elements, such an evaluation requires a mathematical elaboration that goes beyond the scope of this thesis. Here, we continue the bottom-up approach that studies typical filter characteristics that in combination with the partial fraction representation of the filter function enable the description for a large variety of filter functions. For consistency, the same basic filter characteristics as described in Table 3.2 of Chapter 4 are studied. Namely, a first order integrator, a second order integrator with a double pole with or without a zero and a third order integrator with a triple pole and up to two zeroes. An extensive mathematical elaboration for these filter functions is given Appendix A.2. There, the mathematical algorithm for the calculation of the closed-form solutions of the real (5.8) and the imaginary part (5.9) of the characteristic equations is developed. The results for the studied filter functions are summarized in Table 5.1 and Table 5.2.
The analytical forms of the studied filter characteristics are shown the first column of Table 5.1 and Table 5.2. In the second columns of the respective tables, the corresponding real or imaginary parts of the filter function are given as those are used in the intermediate steps of the evaluation. The third columns of Table 5.1 and Table 5.2 give the closed-form representation of the infinite summations that define the right hand side of the characteristic equations (5.8) and (5.9). The closed-form solution in terms of the duty cycle parameter d is calculated Appendix A.2. In Table 5.1 and Table 5.2 the following notations are used:
p ix ω ω= and 2 dα π= , and the
5.1.1.3. Generalization of the filter description 63
Table 5.1. Summary of the evaluation of characteristic equation in (5.8). expression E in Table 5.1 is calculated in Appendix A.2 and is given as follows:
5 4 3 2 4
...240 48 36 90a a a aE π π π
= − + − (5.16)
From Table 5.1 it can be seen that the terms given in (5.15) appear in common for an
arbitrary filter characteristic. Moreover, those terms have a dominant impact on the behavior of the characteristic equations.
The entries in the last column of Table 5.1 can be substituted directly in the ASDM characteristics equation of type (5.8) in order to establish the relation between the applied DC voltage and the resulting duty cycle at that ASDM output. It enables the exact control of the duty cycle and respectively of the bitstream representation of the applied DC input.
From Table 5.1, it can be concluded that the right hand side of (5.8) decreases with the increase of the instantaneous frequency of the ASDM loop. Thus the impact of the poles and zeros in the loop filter on the duty cycle of the output bitstream decreases for high LC frequencies and the behavior of the system with respect to the applied input levels can be approximated with (5.10). Then the duty cycle parameter d can be represented by expression (5.12). From Table 5.1 it can be seen that higher orders loop filters assure an even better approximation of (5.10).
1
Filter function
( )L jkω
Filter function: real part
( )Re pi
i
L k x=ω
ωω
Closed-form representation of the characteristic summation:
( )
1
1 sin 2 Re ik
k d L kG k
π ωπ
∞
=
∑
2 1
pjkω ω+ ( )2 2
1
i k xω + ( ) ( ) ( )
23 51 1 2
3 i i
d d d Ex x O xG G
πω π ω
− −− − +
3 ( )21
pjkω ω+
( )2 2 2
1
i k xω−
+ ( ) ( ) ( )
22 4
2 2
1 1 2 23 i i
d d d E x O xG G
πω π ω
− −− − −
4 ( )2z
p
jk
jk
ω ω
ω ω
+
+ ( )
( )
2 2
22 2 2
2
i
p z zk x
k x
ω ω ω
ω
− +
+ ( )( ) ( ) ( )
22 4
2 2
1 1 23
zz p
i i
d d d E x O xG G
π ωω ωω π ω
− −− − +
5 ( )31
pjkω ω+ ( )
( )
2 2
33 2 2
3
i
x k x
k xω
−−
+ ( )3
3
3
i
E x O xGπ ω
+
6 ( )3z
p
jk
jk
ω ω
ω ω
+
+ ( )
( )
4 2 3
33 2 2
3i p z z
i
k k x x
k x
ω ω ω ω
ω
− + − +
+ ( ) ( ) ( ) ( )
23
2 3
1 1 2 14 33 p z
i i
d d d E x O xG G
πω ω
ω π ω− − −
+ − + +
7 ( ) ( )
( )3z t
p
jk jk
jk
ω ω ω ω
ω ω
+ +
+
( )( )
( )( )( )
4 3
33 2 2
2 2
33 2 2
3
3 3
i p t z t z
i
p t z p t z
i
k x
k x
k x
k x
ω ω ω ω ωω
ω
ω ωω ω ω ω
ω
− − +−
+
+ − +−
+
( )( ) ( )
( ) ( )
2
4
23
3
1 1 23 3
3
7 5 5 3 1
p t zi
p p t p z t z
i
d d dG
Ex O x
G
πω ω ω
ω
ω ω ω ω ω ωω
π ω
− −− − −
− + + −− +
64 Chapter 5: Evaluation of input-driven ASDMs
Table 5.2. Summary of the evaluation of characteristic equation in (5.9). where, the coefficients A , B in Table 5.1 are calculated in Appendix A.2 and a given by
expressions:
( )2
2 14 2a aA d dπ π= − + = − (5.17)
( )4 3 2 2 4
22 148 12 12 3a a aB d dπ π π
= − + − = − − (5.18)
In combination with Table 5.1, the closed-form expressions in the last column of Table 5.2
can be used for the establishment of the exact DC modulated LC frequency iω as a function of the loop filter and the quantizer that are used in the particular ASDM implementation.
This section proposed and elaborated on a possible method for analysis and synthesis of ASDMs. It demonstrated the possibility for an exact calculation of the duty cycle of the output bitstream and its frequency, for DC input.
1
Filter function
( )L jkω
Filter function: imaginary part
( )Im , x= p
i
kω
ωω
,
Closed-form representation of the characteristic summation:
( )
2
1
sin Im ik
k d L kkπ ω
∞
=
− ∑
2 1
pjkω ω+ ( )2 2
c
kk xω +
( ) ( )2
212 i
d dO x
πω−
− +
3 ( )21
pjkω ω+
( )22 2 2
2
i
kx
k xω−
+ ( ) ( )
22 43
2
13 i
d dx O x
πω
− −+
4 ( )2z
p
jk
jk
ω ω
ω ω
+
+
( )
2 2
22 2 2
2
i
z
i
k k x x
k x
ωω
ω
− +
−+
( ) ( ) ( )
23
2
3 212 2
p z
i i
Bd dx O x
ω ωπω ω
−−− +
5 ( )31
pjkω ω+ ( )
( )
2 2
33 2 2
3
i
k k x
k xω
−
+ ( )2 22 4
3 5
16
p
i i
d dO
ωπω ω
−+
6 ( )3z
p
jk
jk
ω ω
ω ω
+
+ ( ) ( )
( )
2 3
33 2 2
3 3p z p z
i
kx k
k x
ω ω ω ω
ω
− − −
+ ( ) ( ) ( ) ( )
22 42 4
3 3
1 3 '6
z p p z
i i
d d Dx O x
π ω ω ω ω
ω ω
− − ++ +
7 ( ) ( )
( )3z t
p
jk jk
jk
ω ω ω ω
ω ω
+ +
+ ( )
( )( )( )
5 3 2 3 32
32 2
2
33 2 2
3 3
3
t z t z
i i
i
t z i t z
i
k k x k k x
k x
kx x
k x
ωω ω ωω ω
ω
ωω ω ω ω
ω
+− + + −
++
− + ++
+
( ) ( )2
2 44 4
12 2i i
d d B x O xπ
ω ω−
+ +
5.1.2. ASDMs analysis for sinusoidal inputs 65
5.1.2. ASDMs analysis for sinusoidal inputs
The ASDM systems are primarily used for the conversion of analog input signals into discrete-amplitude, continuous-time output signals. The information in the amplitude of the input signal is transformed into time information at the output by the ASDM LC oscillations.
In this section, the ASDM operation with sinusoidal input signals is studied. As before, for the analytical evaluation of the system properties, the same general description of an ASDM (see Fig. 5.6), is used. An initial assumption for the following study is that the system exhibits an idle LC.
The input and output waveforms shown at the right hand side of Fig. 5.6 appear when the ASDM is driven with a sinusoidal input signal defined as:
( ) cosmx t v tµ= (5.19)
In the previous section, the ASDM operation with DC input was studied. Here, the
mathematical evaluation follows the same algorithm (see Fig. 5.1). The main difference with respect to the DC case comes from the fact that not only the amplitude of the input signal modulates the ASDM duty cycle but also the frequency of the input signal interacts with the LC mechanism.
Fig. 5.6, ASDM driven with sinusoidal signal; a) system description, b) input and output waveforms
In Fig. 5.7, an example for the spectrum of the ASDM output signal ( )y t , is given. The plot shows the measured output spectrum of a first order ASDM with BQh that sustains idle LC oscillation at 140MHz and is driven with a sinusoidal signal with a frequency of 1MHz. The amplitude of the applied signals corresponds to approximately 10% modulation depth. From Fig. 5.7, two distinct regions in the ASDM output spectrum can be determined. The first region corresponds to the low frequency signal band that replicates the spectral content of the applied input signal. The second frequency region is defined by the LC oscillations.
The demodulation of the output signal can be performed without errors with a low-pass filter if the spectral content due to the limit cycle is not deteriorating the signal band. That is why the limit cycle frequency has to exceed significantly the signal frequency band. In order to quantify the required limit cycle frequency for an error-free demodulation, the impact of the input signal on the LC oscillations has to be evaluated.
-
( )X sL(s) NL(A)+
( )R s ( )I s ( )Y s
66 Chapter 5: Evaluation of input-driven ASDMs
Fig. 5.7. Measured output spectrum of a first order ASDM with 140c MHzω = , for a 1MHz test signal and a modulation depth of 10%.
In analogy to the DC case studied in Section 5.1.1, the system behavior can be characterized by the evaluation of the duty cycle and the instantaneous frequency of the output bitstream and their dependence on the ASDM loop filter. For sinusoidal input signals, these parameters vary in time and are denote, respectively, as ( )d t and ( )tω . The duty cycle is also related to the period of the limit cycle oscillations by:
( ) ( )( )t
d tT tα
= (5.20)
The instantaneous frequency is dependent on the time moment of observation and can be
described as the first derivative with respect to time of the instantaneous phase ( )tλ of the signal.
( ) ( ) ( ) ( )d tt t t dt
dtλ
ω λ ω= ⇒ = ∫ (5.21)
When (5.20) and (5.21) are substituted in (5.3), the output of the modulator for a
sinusoidal input, is described as:
( ) ( ) ( ) ( )1
sin cos2 1 4
k
k d t k ty t d t
kπ λ
π
∞
=
= − − ∑ (5.22)
Expression (5.22) describes the output of the ASDM as a square wave that is pulse-width
and pulse-frequency modulated by a sinusoidal signal. However, the behavior of ( )d t and ( )tω in time is dependent on the ASDM loop filter characteristics and the properties of the
binary quantizer. The impact of this filter function can be evaluated with step 3 from Fig. 5.1. In analogy to (5.4) the signal ( )i t is established as a time-domain convolution of the filter
5.1.2. ASDMs analysis for sinusoidal inputs 67
impulse response ( )l t and the signal given in (5.22). The convolution in time domain is mapped to a multiplication in the frequency domain, and the quantizer input signal is expressed as:
( )i t = -1{ ( ) ( ) ( ) ( )1
sin cos2 1 4
k
k d t k td t L j
kπ λ
ωπ
∞
=
− −
∑ } (5.23)
The analytical evaluation of (5.23) is significantly complicated, due to the presence of
nested sinusoidal functions (see Appendix A.3). The evaluation can be simplified [15], if the modulated output square wave, for the length of one period of the input signal, is decomposed into k instantaneous periods k iT , with a time varying length, as shown in Fig. 5.8.
Fig. 5.8. Signal waveforms for a first order ASDM with BQh, driven with sinusoidal input signal: a) input and output waveforms, b) waveform in front of the quantizer.
Such a decomposition presupposes that the ASDM input signal is slowly varying in respect to the period of the limit cycle oscillations, such that the phase behavior is monotonic within each period of the non-stationary periodic output signal [15]. Then for each instance i , the state of the output signal can be described in the same way as for a DC input signal with instantaneous amplitude iV . The analysis that was presented for a DC input signal in (5.1) to (5.9) can be applied for each instantaneous period k iT , .
The impact of the quantizer’ properties is incorporated by taking into account its decision moments. For example, for the BQh, described in Fig. 5.8, it can be seen that the moments when the signal ( )i t crosses the hysteresis levels correspond to the zero crossings of the
,n iT
iα
2iα t
t
h
-h
68 Chapter 5: Evaluation of input-driven ASDMs
output square wave signal. If the duty cycle of each instantaneous period is denoted as i n iTα , , then for the signal in front of the quantizer, it can be written that ,( 2)n n ii t hα± = ∓ .
In analogy to the DC case described in (5.6) and (5.7), with the help of Appendix A.1, expression (5.23) can be used for the determination of two crossings of the signal ( )i t with the hysteresis values. After recombination, similarly to (5.8) and (5.9), a characteristics system of equations that describes the behavior of the ASDM with BQh is defined as:
( )( ) ( ) ( ) ( )1
sin 2( ) 2 1 2 Rei
i ik
k dx t d L L k
kπ
µ ωπ
∞
=
− − = ∑ (5.24)
( ) ( )2
1
sinIm
4i
ik
k dh L kkππ ω
∞
=
= − ∑ (5.25)
From (5.24) and (5.25), it can be seen that the system of characteristics equations for
sinusoidal input resembles very closely the system that was derived for DC input. The difference is in a factor ( )L µ ( (0)L was participating in the equations for DC input). From (5.24), it can be seen that the higher the gain of the loop filter for the input signal frequency, the better is the ASDM representation of the ideal duty cycle modulation in (5.1). For example for a first order ideal integrator equations (5.24) and (5.25) are simplified to:
( )
( )2
21
( ) 2 1 0
sin4
i
i
k i
x t d
k dhk
ππω
∞
=
− − =
= −∑ (5.26)
From (5.26) the instantaneous limit cycle frequency and duty cycle, for ( )x t given in
(5.19), are described, as
( )2
1 cos2
1 cos
mi
im
c
v td
v t
µ
ω µω
+=
= − (5.27)
The output spectrum of the ASDM with BQh and the chosen filter paramenterization can
be described analytically when expressions (5.27) are substituted in (5.22). Then the low frequency band in which the modulating input signal is positioned and the fundamental harmonic band of the instantaneous frequency can be established analytically. The mathematical elaboration is given in Appendix A.3. The baseband and the fundamental harmonic band are given by a common expression as:
5.2. Application of DFs for analysis of input driven ASDMs 69
( )
( )
( ) ( )
0,1
2
0 2 11
22
2 1 21 1
cos
8 sin 2 14 2
216 sin 2 1 cos 42 4 2
m
c m ml
l
m cm c mn m
l m
y t v t
v vJ J l t
vv vJ J l t t m t
µ
ω π µπ µ
ωπ ω µ µπ µ
∞
−=
∞ ∞
−= =
= −
± − ±
− − ± − +
∑
∑ ∑
(5.28) From (5.28), it can be seen that the baseband equals the modulation signal without
distortion and that the first harmonic band contains spectral components around the idle limit cycle frequency and with amplitudes that, in the case of harmonic modulation, are Bessel functions. For a good design, the center frequency must be high enough to separate the Bessel components from the baseband.
5.2. Application of DFs for analysis of input driven ASDMs
In Chapter 3, several basic describing functions were treated that created a quasi-linear approximation of the non-linear element for specific types of input signals. In Chapter 4, a sinusoidal input DF was used for the analysis of the ASMD operation in idle mode. Here, it is shown that the analysis of ASDMs with the help of DFs can be extended with a description of the ASDM operation when DC or sinusoidal inputs are applied.
The application of DF theory for the description of input driven ASDM operation is governed by the same general rules as for the idle situation.
• Several DFs for the quantizer function can be defined that make a quasilinear representation of the quantizer but not with respect to a single sinusoid, as in the idle case, but with respect to two (or more) different input signals. In the most general case, those input signals can be an arbitrary combination of DC or harmonic signals. Here, we treat the combination of a sinusoid and DC and the combination of two sinusoids.
• In the case of two input signals, the quantizer is represented by two DFs. In the context of ASDM operation, one of the quantizers’ input signals represents the fundamental harmonic of the limit cycle. This implies that the ASDM still displays limit cycle oscillations for the applied input signal. The DF is then defined as the DF of the quantizer for the limit cycle oscillations in the presence of a second input. A second DF can be defined for the signal transfer to the output when the system operates with a limit cycle.
• In case that more LCs are possible, separate pairs of DFs can be defined with respect to each possible limit cycle.
Depending on the type of input signal, the quantizer can be represented with a Dual Input Describing Function (DIDF), when the second input signals is DC or by TSIDF when the second input signal is also sinusoidal. Next the application of DIDF for the description of the ASDM operation is demonstated.
Let the input signal ( )x t of an ASDM have a DC value V . Due to the high DC loop gain, the average value of the output is also V . The quantizer input signal, with respect to which the DIDF is calculated, is described as:
,( ) sinQin LC i ii t V A tω= + (5.29)
70 Chapter 5: Evaluation of input-driven ASDMs
where in (5.29) QinV is the DC component at the quantizer input that is due to V, and the
limit cycle fundamental component is described as , sinLC i iA tω . The index i suggests that the amplitude and the frequency of the LC change with the change of the input DC value. Then the quantizer can be represented by two DFs: ,( , )DC Qin LC iN V A for the DC signal, and
,( , )LC Qin LC iN V A for the limit cycle component. For example, for a BQ0, those two DFs are given [9] by the expressions:
( ) 1, ,
,
2, sin QinDC Qin LC i Qin LC i
Qin LC i
VDN V A V AV Aπ
−= < (5.30)
( )2
, ,, ,
4, 1 QinLC Qin LC i Qin LC i
LC i LC i
VDN V A V AA Aπ
= − <
(5.31)
The DF in (5.30), in fact defines the quantizer gain with respect to the DC value QinV at its
input, when a second sinusoidal signal, due to the limit cycle, is also present at its input. Because, due to the very high DC loop gain, the average value of the output bitstream is equal to the applied DC voltage at the ASDM input, the ASDM input/output transfer, with D = 1, is described by the expression:
( ),
1,
,
2sin sin
2
out Qin DC Qin LC i
Qin QinQin LC i
Qin LC i
V V V N V A
V V VV V AV A
ππ
−
= = ⇒
⇒ = ⇒ = (5.32)
On the other hand, in order to maintain the limit cycle oscillations in the presence of a DC
input, as described in (4.35), the following system of equations should have at least one solution:
( ) [ ]
( ) [ ],
,
Re Re ( ) 1
Re Im ( ) 0
LC Qin LC i i
LC Qin LC i i
N V A L j
N V A L j
ω
ω
= − =
(5.33)
The DIDF for BQ0 is a real number given in (5.31) and directly can be substituted in
(5.33). If we use as an example the third order filter given in (4.43), the operation of the ASDM with BQ0 is described from (5.31), (5.32) and (5.33), as:
5.2. Application of DFs for analysis of input driven ASDMs 71
( )( )( )
,
2
22 2, ,
22 2 2
22 2, ,
sin2
24 1 1
4 1 0
Qin LC i
Qin p
LC i LC i i p
p iQin
LC i LC i i i p
VV A
V GA A
GVA A
π
ωπ ω ω
ω ω
π ω ω ω
=
− = +
− − = +
(5.34)
When the system of equations in (5.34) is applied for the description of a third order
ASDM with BQ0, the following set of parameters is established:
( )
,
1 sin
2 cos2
Qin
LC i
i p
V V
VA
ππ
ππ
ω ω
=
=
=
(5.35)
where the third line in (5.35) gives the solution of the third equation in (5.34), which is
substituted in the second equation in (5.34), from which the limit cycle amplitude ,LC iA in (5.35) is established. Finally, QinV was established when ,LC iA was substituted in the first equation from (5.34).
The ASDM evaluation with DIDF representation of the binary quantizer in a third order ASDM driven with DC input, predicts that the frequency of the limit cycle oscillation is
i pω ω= . However, in Chapter 4, it was established that the for this ASDM the frequency of the idle limit cycle oscillations is also c pω ω= . Thus the DIDF is not predicting a change in the limit cycle frequency as a results of the applied DC input voltage.
In Fig. 5.9 the output spectrum of the studied third order ASDM is evaluated after transient simulations for small and large DC inputs and compared with the idle output spectrum. For DC input of -20dBFS and lower, the studied ASDM indeed oscillates with a frequency very close to the idle limit cycle frequency. However, for large signal with amplitude of -3dBFS, the simulated limit cycle frequency is significantly lower than the DF prediction.
This failure of the standard DIDF to describe the actual ASDM behavior comes from the starting point of the DIDF analysis that in a steady state the frequency of the limit cycle oscillations is fixed and not varying with the variations of the input signal amplitude.
72 Chapter 5: Evaluation of input-driven ASDMs
Fig. 5.9. Output power spectrum for a third order ASDM driven with DC input signal: a) small signal -20dBFS, b) large signal -3dBFS.
5.3. Conclusions
The impact of the loop filter characteristic on the ASDM behavior for DC and sinusoidal inputs was studied in detail with the help of the Fourier expansion method. A system of characteristic equations that describes the ASDMs operation with an arbitrary loop filter was derived. A mathematical procedure for the incorporation of various basic loop filter function in the ASDM analysis is proposed and elaborated in Appendix A.2. The procedure can be used for the exact calculation of the ASDM propertied for DC and harmonic inputs.
In this chapter it was demonstrated that the standard DF analysis is not capable of describing correctly the input driven ASDM behavior in terms of input modulated limit cycle frequency and amplitude, for large input signals.
6. Chapter 6
Multi limit cycle behavior of synchronous SDMs
This chapter treats the limit cycle phenomena in clock-synchronized sigma-delta modulators. A limit cycle model of the SDM operation is created. The limit cycle behavior of the SDM is seen as a result of the interaction of the internal asynchronous limit cycle mechanism with the external sampling clock. For the evaluation, a graphical application of the DF method is extensively used. The SDM behavior is studied for idle mode and for busy (input driven) operation. The properties of the limit cycle are shown to have a major impact on the system behavior and performance. SDMs that can operate in low sub-harmonic modes with respect to the applied sampling frequency are introduced and studied. Their performance is evaluated analytically and via simulations. The advantages and disadvantages that appear from operation in different sub-harmonic limit cycle modes are discussed and several implications for the overall system performance are derived. Conclusions for the design requirements that the desired limit cycle behavior is posing on the system are drawn and practical design rules are derived. The limit cycle behavior is illustrated with multiple examples for different system orders, non-linear elements and clock speeds.
6.1. Motivation and Definitions
Currently, multiple communication applications begin to utilize SDMs with large bandwidths (above 10MHz) and with high accuracy (better than 14 bit). Despite the technology advances, those requirements pose a significant challenge for SDM. At the same time, the room for architectural and conceptual improvements of SDMs seams to be exhausted and the implementations are striving to achieve high performance mainly through an increase of cost and complexity. One of the main cost factors is the clock speed. An increase in the sampling frequency requires an increase of the gain-bandwidth product of the building blocks, faster settling times and power hungry decimation filters. That requires from the SDM designs to utilize optimally the available clock speed and power budget. Alternatively, the performance can be improved via introduction of multi-bit quantizers or multi-stage (MASH) implementations. Those alternatives increase quite significantly the complexity of the design and again may lead to an increase of area and power consumption.
Here, we discuss in particular, high-order single-bit SDM designs and aim to establish the fundamental limits of their performance.
6.1.1. Performance estimation and measurements
In Table 6.1, several state of the art implementations are selected that realize single-loop single-bit SDMs. The designs are ordered in an increasing order L of the loop filter and an increasing signal bandwidth. The table illustrates ADCs that are designed for different frequency ranges, application areas and in different CMOS processes.
74 Chapter 6: Multi limit cycle behavior of synchronous SDMs
One of the goals of the table is to illustrate the difference in the ADC performance as evaluated analytically or simulated and the actual measurement results from some of the best-reported implementations. The analytical prediction for the achievable dynamic range (DR) is made with the help of the white noise model (WNM) of the quantizer in the SDM loop [6], [26], [27] and many others. As discussed in Chapter 3, the WNM treats the quantizer as a source of noise with a white spectral distribution independent on the input signal. The WNM takes into account the loop filter characteristics, the applied OSR and the resolution of the quantizer. For higher order loop filters the zeros of the NTF are often optimized in order to assure maximum quantization noise suppression in a certain bandwidth.
Table 6.1. Comparison of single loop single bit SDMs: evaluation vs. measurements
With the help of the WNM, the achievable dynamic range is evaluated with respect to the oversampling ratio (OSR) and the filter order. For full scale input signal the achievable DR that is predicted by the WNM is given in expression (3.3) and repeated here for convenience:
( ) 2 1
2
6 2 1 ++=
L
WNM L
L OSRDR
π (6.1)
The difference between the WNM prediction of the dynamic range and the measurements is given in column 8 (as Diff. I) of Table 6.1. The SDM implementations (with respect to L and OSR) from Table 6.1 are also evaluated with high-level simulations. A generally available tool [28] is used for the evaluation. The results are summarized in column 9 and the difference with the measurements is given in column 10 (as Diff. II). Several observations from the data in Table 6.1 have to be pointed out:
1413121110987654321
105
70.7
84
63
58
37
100
>100
38.4
49.4
Diff. I, dB
58
22
47
15
9
5
67.7
68
18.7
28.7
Diff. II, dB
120
96
120
105
85
85
153.7
173
106.7
106.7
DR, dB Sim.
audio0.35 µ m CMOS8588126.41002M25k13[18]
UMTS0.6 µm CMOS566216764400M3.1M15[24]
0.18 µmCMOS
0.18 µmCMOS
0.35 µmCMOS
90 nm CMOS
0.6 µmCMOS
0.5µm CMOS
Process
Bluetooth86186210256M600k14[20]
audio6277126.41001.538M16k13[17]
AM/FM radio77801343221.07M300k15[21]
UMTS74144.740153.6M3.84M
CDMA831676476.8M1.228M
GSM901534826M200k
15[23]
Bluetooth receiver75.5761343264M1M15[22]
Measure-ment105>205320256k40014[19]
Q bits OSR DR, dB
WNM
DR, dB, Meas.
SNDR, dB, Meas.
fS, Hz Applica-tion
Signal BW, HzLRef.
1413121110987654321
105
70.7
84
63
58
37
100
>100
38.4
49.4
Diff. I, dB
58
22
47
15
9
5
67.7
68
18.7
28.7
Diff. II, dB
120
96
120
105
85
85
153.7
173
106.7
106.7
DR, dB Sim.
audio0.35 µ m CMOS8588126.41002M25k13[18]
UMTS0.6 µm CMOS566216764400M3.1M15[24]
0.18 µmCMOS
0.18 µmCMOS
0.35 µmCMOS
90 nm CMOS
0.6 µmCMOS
0.5µm CMOS
Process
Bluetooth86186210256M600k14[20]
audio6277126.41001.538M16k13[17]
AM/FM radio77801343221.07M300k15[21]
UMTS74144.740153.6M3.84M
CDMA831676476.8M1.228M
GSM901534826M200k
15[23]
Bluetooth receiver75.5761343264M1M15[22]
Measure-ment105>205320256k40014[19]
Q bits OSR DR, dB
WNM
DR, dB, Meas.
SNDR, dB, Meas.
fS, Hz Applica-tion
Signal BW, HzLRef.
6.1.1. Performance estimation and measurements 75
• The reported measurement results show a significant deviation from the estimation that can be made with the WNM. Moreover, the deviation increases with the increase of the order of the loop filter and the applied OSR.
• In some cases, the ideal high-level simulations predict performance much closer to that of the implemented ADCs, than the WNM analysis. However, the difference with the measurements varies a lot between the designs and is worse for high-speed applications.
• The measured signal to noise and distortion ratio (SNDR), when given in the reference, is also included in the table in column 12. It shows that in practice there are implementation issues that further decrease the performance of the ADC with respect to the simulations.
• It has to be pointed out that the provided measurement results do not separate the contributions of the thermal and quantization noise in the measured DR. That is why all designs, for which the deviation in the DR (Diff. II from Table 6.1) exceeds 20dB, are assumed thermal noise limited.
Based on the above observations, the following conclusions can be drawn:
• The comparison: analytical model – simulation – measurement brings questions about the applicability of the WNM in modern SD design and respectively, about the level of understanding of the SDM operation.
• The SDM design is based on a rather heuristic background that relies on simulations. Despite their evident importance, the simulations may not include all important design parameters and may not always bring new insights in the SDM operation and behavior.
A step further in the conceptual understanding and theoretical description of the SDMs can be done if the modulators are treated as non-linear, closed-loop, sampled systems. Undoubtfully, such an approach is supported by a known phenomenon in the SDM operation, defined generally as limit cycle behavior. It is well known that those modes can cause appearance of spurious tones in the signal band and can lead to a significant deterioration of the performance of the modulator in terms of SNDR and DR. Here an analytical model on the SDM operation is constructed that is capable of describing the limit cycle behavior.
6.1.2. Definition of terms and scope
In this chapter the notion “limit cycle” is investigated in the context of the well-known clock-synchronized SDMs. Again, the limit cycle is defined as a periodic mode that exists or appears in the system for some combination of the system parameters or due to the input signal. The periodic modes that appear for zero input signal are denoted as idle limit cycles. As is going to be demonstrated in this chapter, when driven with an input signal, in most situations of practical importance, the SDMs operate at least at two limit cycles.
For the asynchronous modulators that were treated up to now, the limit cycle behavior appeared to be an important phenomenon that determines the operation and the performance of the system. Historically, in the context of SDM, the limit cycle behavior has been treated in a quite different perspective. In the great majority of studies on SDM, the limit cycle phenomena are perceived as unwanted and performance degrading effects in the operation of the modulator. This perception is partially due to the fact that the existence and thus the properties of the limit cycles in SDM cannot be studied with the traditional linear theory. The
76 Chapter 6: Multi limit cycle behavior of synchronous SDMs
description of the limit cycle behavior appears to be far more complex than the generally used linear model of a simplified linear loop that is excited by an extra, uncorrelated noise source. Thus, the great majority of studies and respectively the designs that rely on the implications of the white noise model of the SDM leave the limit cycles untreated and unforeseen. Though some recent studies [25] undertake a deep look in the limit cycle behavior of SDM, the phenomenon is mainly studied heuristically via extensive simulations. This has resulted in SDMs parameterization that follows simple “rules of thumb” but without solid analytical background. In practice, most SDM designs follow an experience-based approach that gives general rules of how to eliminate or significantly decrease certain phenomena in the SDM operation like the appearance of tones in the signal band or the deterioration of the noise shaping. Here, we demonstrate that those effects originate from a specific limit cycle behavior and can be treated analytically with the theory that is developed.
In analogy to ASDMs, here the limit cycle mechanisms in SDMs are studied and described analytically as a function of the parameters of the system architecture: the loop filter frequency transfer characteristic and the quantizer properties. Again the limit cycle behavior is evaluated with respect to the properties of the input signal in terms of frequency and amplitude modulation. The impact of the limit cycle modes on the performance of the system is established and several implications for the design parameterization are pointed out.
As a starting point for the following analysis, the knowledge of the limit cycle behavior in ASDMs is used. The similarities between the two types of modulators are sought at different levels including system description, functionality and implementation of their building blocks.
In analogy with the evaluation of the ASDM described in Chapters 4 and 5, the limit cycle behavior [68], [72], [73] in SDM is evaluated with respect to:
• Conditions for existence;
• Properties of the limit cycle mode in terms of frequency and amplitude and with respect to the parameters of the system;
• The impact of the external data signal on the limit cycle behavior;
• The impact of the limit cycle behavior on the quality of the data processing. The main difference with respect to the ASDM comes from the fact that the limit cycles in
SDM originate from the interaction of the sampling clock with the phase rotation that is introduced in the loop by its linear and non-linear components. Moreover, as demonstrated in the following section, the frequencies of the idle limit cycles modes in SDMs cannot vary continuously as in ASDMs but are always related to the frequency of the applied clock.
6.2. Limit cycle model of SDMs in idle mode
A limit cycle model (LCM) of the SDM operation can be established with the help of the systems shown in Fig. 6.1. In Fig. 6.1a, the SDM loop is built with a continuous time linear filtering block ( )L jω , a binary quantizer, a sampling switch and a zero-order hold (ZOH). As a first step of the development of the SDM LCM, a sampled DF is introduced.
6.2.1. Sampled DF
The ideal quantizer is memoryless and its position with respect to the sampling operation is of no consequence for the loop operation. Here, to decouple the amplitude quantization from the sampling, the sampling is performed after the quantizer. However, it is important to point out that by placing the sampler after the quantizer, the model gives a better
6.2.1. Sampled DF 77
representation for CT time loop filters. For DT loop filters, where the sampling is performed before the quantizer, special attention has to be paid to the possibility for the introduction of aliased components in front of the quantizer.
The limit cycle model of the SDM operation is constructed for idle mode ( ) 0x t = by an incorporation of the impact of the sampling into the underlying asynchronous mechanism, discussed in earlier chapters.
As before, it is assumed that in idle mode the SDM sustains a steady state oscillation denoted as limit cycle. The quantizer input signal is approximated with a sinusoid so that the DF theory can be applied. In Fig. 6.1b the quantizer is modeled with its describing function
( )N A , where A denotes the amplitude of the quantizers’ sinusoidal input signal. In Fig. 6.2, the time-waveforms of the quantizer input and output signals and of the ZOH
output are shown. From the picture, it can be concluded that the sampling switch and the ZOH introduce a phase delay sϕ between the quantizer output signal and the SDM output bitstream. This phase delay can take a value between zero and a clock period (if the limit cycle has frequency of 2sf ). As in idle mode the SDM is in a steady state, the clock introduced phase delay is fixed and depends on the parameterization of the loop filter. The exact relation is treated in Section 6.2.3.
The block diagram of the limit cycle model of the SDM is summarized in Fig. 6.1c, where the quantizer, the sampling switch and the ZOH are represented by the sampled DF given in (6.2).
a) b) c)
Fig. 6.1. SDM block diagrams: a) Basic SDM diagram; b) DF linearized SDM; c) SDM with sampled DF.
The separation of the quantization in amplitude from the quantization in time allows the introduction of a modified DF that can be denoted as sampled describing function and is defined, as follows:
( )( , ) −= s
sN A N A e ϕϕ (6.2)
( )L jω ZOH-
( )r tsf
( )i t [ ]sy* nT( )x t ( )y t( )L jω ZOH-
( )L jω ZOH-
( )r tsf
( )i t [ ]sy* nT( )x t ( )y t
( )L jω ZOH-
( )r tsf
( )i t [ ]sy* nT( )x t ( )y t( )N A( )L jω ZOH-
( )r tsf
( )i t [ ]sy* nT( )x t ( )y t( )N A( )N A
( )L jω-
( )r t ( )i t [ ]sy* nT( )x t ( ), sN A ϕ( )L jω-
( )r t ( )i t [ ]sy* nT( )x t ( ), sN A ϕ( ), sN A ϕ
78 Chapter 6: Multi limit cycle behavior of synchronous SDMs
Fig. 6.2. Introduction of phase delay sϕ in the SDM loop by the sampling operation.
From (6.2), it can be concluded that the magnitude of the sampled DF is in fact the magnitude of the usual DF studied earlier, while the sampling is incorporated as a phase component in the overall describing function. In this chapter, sampled DFs of the binary quantizer are introduced for different combinations of DC or harmonics inputs.
6.2.2. Potential idle sub-harmonic modes
For the construction of the limit cycle model (LCM) of SDM, firstly, the properties of the output bitstream in idle operation are considered. In idle mode and for an unbiased system, the average value of the output signal should also be zero. Thus, for idle mode, due to the full symmetry of the loop and the presence of an integrator, the output digital bitstream can consist only of N ones followed by N zeros [29]. This requirement presupposes that the only idle oscillations that can exist in the SDM loop are even integer multiples 2N of the sampling period sT ( N k= , period of oscillations is 2k and k=1, 2, 3...). Note that in many practical systems the condition for N ones followed by N zeros cannot be directly observed as it requires full symmetry in the loop that is very difficult to achieve. For example, even a small offset in the transistor implementation of the quantizer or the integrators disturbs this ideal periodicity in idle mode. However, those offsets can easily be incorporated in the analytical description if treated as input signals.
In Fig. 6.3 the signal ( )i t in front of the quantizer is shown as a sinusoidal waveform. For low order filters the signal ( )i t is not purely sinusoidal. However, the following interpretation of the clock introduced phase delay is fully applicable for an arbitrary waveform in front of the quantizer that fulfills the stated periodicity conditions. In that respect, the accuracy of the DF approximation for low order SDM systems is of less concern than in ASDMs, because the phase delay due to the clock is modeled in the same way for filters of an arbitrary order.
Clock
sϕy*[nTs]
Clock
sϕ
Clock
sϕy*[nTs]
6.2.3. Clock introduced phase shift 79
6.2.3. Clock introduced phase shift
From the asynchronous loop we know that the appearance of a limit cycle is determined by the phase/magnitude relation in the closed loop. If the same reasoning is applied here, the impact of a sampling operation in the loop on the phase/magnitude relation should be established and modeled. In the general SDM treatment, the sampling operation is incorporated in the white noise model of the quantizer.
Fig. 6.3. Evaluation of phase uncertainty due to sampling for different sub-harmonic limit cycle modes, *( ), [ ]si t y nT represent respectively the quantizer input
and the SDM output waveforms.
Such an approach models only the fact that the quantization noise is spread in a frequency band up to 2sf . The impact of sampling on the loop behavior can be incorporated in the limit cycle model with the help of Fig. 6.3. In Fig. 6.3, three possible idle limit cycle modes that fulfill the requirement for a zero average value are illustrated. Respectively, those modes have frequencies 2sf , 4sf and 8sf . All of them can be defined as sub-harmonic modes because they have a frequency that is an even integer fraction of the applied sampling frequency. The sampling signal with frequency sf is also indicated. In order to establish a clear notation those modes are denoted, respectively as first (with limit cycle frequency
2c sf f= ), second ( 4c sf f= ) and fourth ( 8c sf f= ) sub-harmonic limit cycle modes. Such a definition shows the direct coupling of the idle limit cycles to the applied clock frequency, and the deceasing speed of the signals in SDM loop for low frequency limit cycles.
The signals ( )i t and *[ ]sy nT represent respectively the input of the quantizer and the SDM output signal. For CT loop filters, the zero crossings of ( )i t occur asynchronously to the sampling moments. At the same time the output bitstream is clock synchronized. As a result, at each sampling instant a delay is introduced between the zero crossings of ( )i t and the zero crossing (or the change in the digital state) of *[ ]sy nT . From Fig. 6.3, it can be concluded that the signal phase shift due to the sampling can vary between zero (in case that the sampling moment coincides with the zero crossing of ( )i t ) and half a period of ( )i t . In idle mode of operation this phase shift is fixed and depends on the total phase rotation in the loop. The
sf
sf 2
sf 4
sf 8
π
2π
2π
sϕ
4π
( ) *si t ,y (nT )
sf
sf 2
sf 4
sf 8
π
2π
2π
sϕ
4π
( ) *si t ,y (nT )( ) [ ]*, si t y nT
80 Chapter 6: Multi limit cycle behavior of synchronous SDMs
amount of phase delay depends on the frequency of the idle limit cycle, such that for an idle limit cycle with frequency 2sf , the clock can introduce in the SDM loop a maximum phase delay of 180deg. This comes from the fact that for the first sub-harmonic limit cycle the sampling period corresponds to the half of the period of the limit cycle.
As the frequency of the limit cycle scales down, the maximum phase delay that can be introduced by the clock also scales down with the same even integer factor because of the relative decrease of the clock added phase for the lower sub-harmonic limit cycles. In Fig. 6.3, it is illustrated that for sub-harmonic limit cycles of respectively 4sf and 8sf , the maximum phase delay that the clock can introduce is correspondingly 90deg. and 45deg. Thus for the idle limit cycle oscillations with a lower frequency the impact of sampling on the loop phase behavior decreases proportionally1.
For busy operation, the phase shift that is introduced by the clock depends on the frequency and the amplitude of the signal in front of the quantizer at the particular sampling instance. As this amplitude is continuously varying, the phase shift that is introduced is not fixed. That is why for busy operation the term phase uncertainty can be used for the clock added phase delays. However, this phase uncertainty remains bounded between the phase limits for each limit cycle mode as determined for idle operation.
6.2.4. Graphical evaluation of idle limit cycle modes in SDMs
According to the above definition, the idle limit cycle is a stable periodic mode that appears in the system for zero input. For example, let us implement the system of Fig. 6.1 with a BQ0 and a second order loop filter with a frequency transfer characteristic given in (6.3):
( )( )2( )
+=
+z
p
G jL j
j
ω ωω
ω ω (6.3)
For an SDM that can sustain at least one limit cycle, in analogy to the ASDM studies, the
relation between the linear part of the loop and the DF representation of the non-linear element is given by:
( ) ( ),, ,
1,
= −LC iLC i s i
L jN A
ωϕ
(6.4)
where , , and LC i LC iA ω are the thi sub-harmonic limit cycle amplitude and frequency and ,s iϕ is
the clock added loop phase delay for iLC .
The solutions of equation (6.4) give the frequency and amplitude of the possible limit cycle oscillations. In the studied clock-synchronized system this expression reveals the phase/magnitude relation in the closed-loop at each sampling instance. In fact it allows us to investigate the SDM loop for an inherent asynchronous mechanism. The clock operation is treated as superimposed to this internal mechanism and the analysis establishes the interaction of this mechanism with the applied clock frequency.
1 In that respect, it can be concluded that when the loop operates at lower frequency sub-harmonic modes, it better approximates the
operation of the ASDM.
6.2.4. Graphical evaluation of idle limit cycle modes in SDMs 81
From the discussion up to now it became clear that a finite set of limit cycles can exist in the studied systems, such that in each case the limit cycle frequency is a fraction of the applied clock frequency. For each specific idle limit cycle the clock introduces some fixed delay in the loop. The limit cycle modes can be identified if this delay is taken into account for the evaluation done according to (6.4). The evaluation can easily be performed graphically as illustrated in Fig. 6.4. The clock introduced phase shift for each sf N frequency is shown as a line originating from the discrete frequency points of the locus
( )sL j Nω and with length equal to 2 Nπ as described in the previous section. In contrast to the asynchronous case where an indication for a limit cycle was given by an intersection between ( )L jω and -1 ( )N A , here the limit cycle modes correspond to those fractions of the clock frequency for which the sampling operation adds enough delay in the loop such that the delay lines starting from ( )sL j Nω can cross -1 ( )N A .
For the example plotted in Fig. 6.4, two limit cycle modes are possible with frequencies 2sf and 4sf . Limit cycles with lower frequencies are not possible because the total phase
delay in the loop for lower frequencies does not provide 360 degrees phase shift and thus cannot satisfy the oscillation conditions.
Fig. 6.4. Graphical description of the LCM of the SDM operation
The first sub-harmonic limit cycle mode with frequency 2sf is the only mode considered in practice for the design of SDMs. The reason for this choice is the maximum oversampling ratio that this mode offers and respectively the highest performance that can be achieved for high OSR according to the WNM. However, the LCM reveals the existence of at least a second sub-harmonic mode of operation with frequency 4sf . The conditions for operation in a particular limit cycle mode are studied in detail in Section 6.2.5.
From Fig. 6.4 several general observations have to be pointed out:
• The second sub-harmonic mode exists if the clock added phase shift for frequency of 4sf is such that -180deg. line is crossed (see Fig. 6.4). Such a condition is
( )L jω( )1
−N A
ϕs,2
2sf
4sf6
sfλ3
ρ1 ρ1
ρ 2 ρ 2
0
1ς
82 Chapter 6: Multi limit cycle behavior of synchronous SDMs
easily fulfilled even for a first order system built with an integrator that already provides 90deg. phase shift.
• The phase margin iλ for the prevention of lower sub-harmonic modes (see Fig. 6.4) (where i is an index for the particular sub-harmonic mode) in the loop, is the distance between the maximum phase delay that can be introduced for the particular sub-harmonic mode, and the -180deg. line.
• A parameter iρ for the phase boundary for each sub-harmonic mode can be introduced that gives a measure for the amount of phase with which the maximum added clock phase delay may exceed the -180deg. phase line.
• Here, we state that, in contradiction with the general perception of the SDM operation, the limit cycle with frequency 2sf is not always the only possible one. Moreover, it may not result in the best performance for the system. In fact, as will be shown in Section 6.4 the designer can choose the sub-harmonic modes to be implemented and the frequencies of operation of the SDM loop such that the best trade-off for the system performance can be made.
Several notions are stated here and are going to be elaborated on further:
• Every SDM operates at one or more limit cycles. In fact, the situation when only one limit cycle is possible in the system can be considered as a rare case. In most practical situations, at least two limit cycles should be introduced. As elaborated extensively in Section 6.3, the SDM limit cycle state depends entirely on the instantaneous amplitude of the input signal.
• The increase of the loop filter order introduces new degrees of freedom in the design. However, from the LCM in Fig. 6.4, it can be concluded that in order to avoid the possibility for multiple low frequency limit cycles, enough phase margin
iλ should be introduced in the loop via a proper parameterization of the loop filter.
• The SDM should be considered stable when it is able to produce a bitstream representation of an arbitrary (for example, zero, DC or sinusoidal) input signal with magnitude within its dynamic range. This somewhat broad definition of stability is required in order to distinguish from instable modes that lead to a permanent clipping of the output to either +1 or –1, such that the SDM is not able to process the input signal. The above definition of stability identifies as stable also the SDMs that operate at a very low limit cycle frequency. This definition is needed because quite often those modes are described as instable, only because their behavior drastically deviates from the predictions of the WNM.
6.2.5. Active idle limit cycle
As pointed out previously in this chapter, in an SDM with BQ0 or BQh, typically at least both the first and the second idle sub-harmonic limit cycles 1LC and 2LC appear to be possible modes of operation. However, in practice in idle mode the SDM loop oscillates at only one. From Fig. 6.12, Fig. 6.13, Fig. 6.14 and Fig. 6.17, it can be seen that for zero input the limit cycle 2LC with the lower (or the lowest if more limit cycles are possible) frequency is active. Intuitively, that is due to the fact that at steady state operation the loop gain is highest for the limit cycle mode with lowest frequency. In order to relate the loop gain to the SDM parameterization and to introduce the application of DF theory in the analysis, a more
6.2.5. Active idle limit cycle 83
formal evaluation is done, next. The two idle limit cycles are characterized with their amplitude and frequency respectively:
1LC with 1 1,LC LC A ω and 2LC with 2 2,LC LC A ω observed in front of the quantizer. For example, for a first order loop filter with a roll-off of -6dB/oct. , the amplitude of the lower frequency limit cycle is twice higher. Then, from the graphical representation of the limit cycle behavior of SDMs that was discussed earlier, the following relations between the respective amplitudes and frequencies can be pointed out:
1 2
21
2
= 2
LC LC
LCLC
AA
ω ω= (6.5)
The frequency relation is a direct result from the integer relation of both limit cycle
frequencies to the frequency of the applied clock. The amplitude relation depends on the characteristics of the loop filter. Moreover, as illustrated in Section 6.2, for a stable operation the loop filter characteristics at sf 2 and sf 4 has to approach first order behavior. That is why the amplitude relation in (6.5) is valid for many practical SDM implementations.
If the two idle limit cycles 1LC and 2LC are assumed to be active simultaneously in idle mode, according to the DF theory, the input signal in front of the quantizer is described with the expression:
( ) ( ) ( )1 1 2 2sin + sinLC LC LC LCi t A t A tω ω= (6.6)
The phase/gain relation in the SDM loop that exhibits two possible idle limit cycle modes
can be described with the following set2 of equations:
( ) ( )( ) ( )
,1 ,1
1
,2 ,2
2
1 2 1
2 1 2
, 1
, 1
s
LC
s
LC
j jA LC LC LC
j jA LC LC LC
N A A e L j e
N A A e L j e
τ
τ
ϕ ξ
ϕ ξ
ω
ω
− −
− −
= −
= − (6.7)
where in (6.7) 1 2( , )A LC LCLCi
N A A , 1,2i = are the two sinusoidal input describing functions (TSIDF) as derived in Chapter 3. The quantizer can be represented by two TSIDF (one for each sinusoid in (6.6)) that are formulated as:
1) The quantizer DF 1 21( , )A LC LCLC
N A A for sinusoidal input 1 1( ) sin1 LC LCi t A t= ω with another sinusoid 2 2( ) sin2 LC LC i t A t= ω present at the quantizer input with lower frequency but higher amplitude, is given (see Appendix B.3) for BQ0 as:
( ) ( ) ( ) ( )1
21 2 2 2
1
8, 1 , 1 = − − > LCA LC LCLC
N A A E k k K k kk Aπ
(6.8)
where in (6.8) 1 2LC LCk A A= .
2 The vertical line on the left of the system of equation indicates that only the roots that satisfy both of them are sought.
84 Chapter 6: Multi limit cycle behavior of synchronous SDMs
2) Respectively, the quantizer DF 2 12( , )A LC LCLC
N A A for sinusoidal input 2 2( ) sin2 LC LC i t A t= ω with another sinusoid ( )1 i t present at the quantizer input with higher frequency but lower amplitude than ( )2 i t , is given for BQ0 as:
( ) ( )1 1 2 2
1
8, , 1= <LCA LC LC
LC
N A A E k kAπ
(6.9)
where in (6.8) and (6.9), the ( )E k and ( )K k are respectively the complete elliptic integrals
of first and second kind, shown in Appendix B.1. The function ( )1 2,A LC LCLCi
N A A is in fact determining the magnitude of the sampled TSIDF
given as ( )1 2 ,, ,A LC LC s iLCi N A A ϕ . The clock added phase delays for sf 2 and sf 4 are
incorporated in ,s iϕ . The loop filter magnitude and phase for LCiω are given as ( )LCiL jω and
iξ , where the phase of the linear part iξ has two components due to the loop filter phase ( iς ) and to the extra loop delay ( iρ ), such that i i iξ ρ ς= + .
In SDM, the sampling results in fixed relations (6.5) between the amplitudes and the frequencies of the two idle limit cycles. The limit cycle conditions defined by (6.7) lead to the following magnitude relation:
( ) ( )( ) ( )
1 1
2 2
1 2 1
2 1 2
, , 1
, , 1
LC LC
LC LC
A LC LC s A
A LC LC s A
N A A L j
N A A L j
ϕ ω
ϕ ω
=
= (6.10)
Let us assume that 1LC is active and treat 2LC as a perturbation3 signal. From Appendix
B.1, the magnitudes of the two sampled TSIDF in (6.10) are related by the inequality (6.11) when the loop filter has a second order behavior at the limit cycle frequencies. The second order behavior determines the stability boundary.
( )( )
1
2
1 2 1
2 1 2
, , 1, , 1.6
LC
LC
A LC LC s
A LC LC s
N A A
N A Aϕϕ
< (6.11)
Due to the requirement for the simultaneous validity of both equations in (6.10) and from
(6.11), for the magnitude of the loop filter frequency response at the limit cycle frequencies can be concluded that:
( )( )
1
2
1.6>LC
LC
A
A
L j
L j
ω
ω (6.12)
However, expression (6.12) is not true for a low pass filter that is usually used in the SDM
loop, as:
3 A disturbance of motion or of state of equilibrium.
6.2.5. Active idle limit cycle 85
( )( )
1
2
1<LC
LC
A
A
L j
L j
ω
ω (6.13)
Expressions (6.11) and (6.12) show that if 2LC is perturbed with 1LC it remains stable,
while if 1LC is perturbed with 2LC it becomes unstable and the loop enters 2LC . The conclusion that for idle mode of operation the 2LC is active is very important as it
gives a criterion for the establishment of the possible transitions between the limit cycles when an input signal is applied.
The perturbation analysis can be also directly applied if more than two idle limit cycles are possible in the system. In the most typical low-pass SDMs, the analysis shows that the lowest frequency LC is the active one for idle mode of operation.
The following discussions and analyses elaborate further on the SDM operation for different types of input signals.
6.3. Input driven time variant limit cycle behavior of SDM
The evaluation in the previous sections showed that SDMs can operate at more than one limit cycle. Here, the limit cycle behavior for DC and harmonic inputs is described.
Firstly, a conceptual description of the limit cycle behavior for DC input is elaborated. Then an analytical approach that uses the Dual Input DFs (DIDFs) discussed in Chapter 5 is used for the description of the LC behavior. Finally, the SDM behavior when driven with sinusoidal input signals is evaluated. For the analysis, again the sampled TSIDFs are employed. The discussion concentrates mainly on SDMs with BQ0; however, the presented approach can be used for the analysis of other types of binary quantizers.
6.3.1. SDM operation with DC input
The perturbation analysis from Section 6.2.5 cannot incorporate the impact of an SDM input signal ( ) 0x t ≠ . The SDM operation when a DC input is applied can be treated with the help of the dual input DF (DIDF) studied in Chapter 5 for ASDM input under the condition that the DC input signal ( ) inx t V= results in a signal component in the signal ( )i t that is slowly varying with respect to the frequencies of both 1LC and 2LC . The quantizer input signal is then described as:
( ) ( ), , ,= +LC i LC i Qin ni t A sin t Vω (6.14)
where in (6.14) ,Qin nV is the “instantaneous DC” component at the quantizer input at each
sampling moment n . Expression (6.14) gives the summation of a sinusoidal component due to the active limit cycle iLC and a ramp with an instantaneous value that depends on the applied DC input inV and the order of the loop filter in the SDM loop. A slowly varying ,Qin nV means that it can be taken as constant between two consecutive sampling moments. Such an assumption presupposes that the limit cycle itself is not disturbed by the input signal ( )x t and remains stable as far as the magnitude/phase conditions for limit cycle oscillations are still
86 Chapter 6: Multi limit cycle behavior of synchronous SDMs
valid at each sampling moment. The slope of the ramp that appears in front of the quantizer after the integration of the
applied DC input by the loop filter depends on the applied DC value and the order of the loop filter. For small input signals, the condition for a slowly varying ,Qin nV is fulfilled due to the very slow ramp. A conceptual description of the SDM operation under such conditions is given next.
6.3.1.1. Conceptual description
The most easy and straight forward description of the SDM operation for DC input can be done for a first order system built with an ideal integrator. In order to assure that both the first and the second sub-harmonic limit cycles are present in the studied system, for the following discussion, a very small time delay 80= sTτ is added in the loop. This time delay corresponds to 1.125 deg. phase shift for frequency 4sf and to 2.25 deg. phase shift for
2sf . The idle SDM behavior that results from such a parameterization was evaluated graphically in Fig. 6.4 with the help of the limit cycle model.
As described above, for such a configuration, the loop oscillates in idle mode at 2LC such that the loop filter and the clock are each providing 90deg. phase rotation in the loop. The phase boundary 2ρ , as defined in Section 6.2.4, is then equal to the phase delay added in the loop by the extra time delay, thus 2 1.125deg.=ρ (without this delay 2 0=ρ for the studied first order SDM). In Fig. 6.5 the time waveforms of the signal in front of the quantizer ( )i t , the output signal of the quantizer ( )y t and the sampled signal (the output bitstream) *[ ]y nT are shown. The phase delay due to τ is independent on the input signal and has a fixed value that depends only on the frequency at which this phase delay is observed. In Fig. 6.5 the phase shift of the output bitstream with respect to the zero crossings of ( )i t is illustrated. The phase shifts 2ρ and ,2sϕ (such that 2 ,2 2s+ =ρ ϕ π ) are due, respectively to the extra loop delay and to the sampling and are indicated in Fig. 6.5.
Due to the presence of an ideal first order integrator as a loop filter, the quantizer input signal ( )i t has a triangular waveform. The amplitude of ( )i t is determined by the gain in the loop and for the above example is chosen to be 0.1 for a better visualization. In practice, the idle limit cycle amplitude should be much smaller such that clipping is prevented for large input signals, at the output of the loop filter or at the output of the individual integrators inside the loop filter.
6.3. Input driven time variant limit cycle behavior of SDM 87
Fig. 6.5. Waveforms in a first order SDM with BQ0 and a small extra loop delay of 80sT for DC input
When a DC input signal inV is applied at the SDM input, the behavior of the system is dependent on the value of inV and respectively on the time constant of the resulting ramp at the input of the quantizer due to the integration of inV by the loop filter. In Fig. 6.6 the waveforms in the studied SDM loop are shown when a small constant input of ( ) 20= −x t dBFS is applied. Several observations for the system behavior can be made:
• The application of a DC input adds a ramp signal to the idle waveform. For higher DC inputs the slope of the ramp also increases.
• The frequency and the amplitude of the triangular wave in front of the quantizer remain unaltered by the small DC input such that (6.14) holds.
• The quantizer output signal '( )y t is shifted in phase with respect to idle mode signal. The phase shift depends on the slope of the ramp and thus on the applied DC value inV .
• The phase shift due to inV alters the total phase rotation in the loop and as a result alters the conditions for stable oscillations. Those conditions have to be reevaluated at each sampling moment.
• For the observed time interval, the SDM output signal *[ ]y nT remains the same for idle mode and operation with a small DC input. That means that the instantaneous (for the particular sampling instant) input-added phase rotation remains undetected at the output for the observed time interval.
sϕ
2ρ
[ ]*y nT
88 Chapter 6: Multi limit cycle behavior of synchronous SDMs
Fig. 6.6. Comparison: idle ( )i t , ( )y t and small (-20dBFS) DC signal ' ( )i t , ' ( )y t waveforms for a first order SDM with BQ0, where *[ ]sy nT is the output bitstream.
If we assume a positive DC input and zero initial conditions (such that 2LC is initially active), the ramp causes an increase of the positive part of '( )y t . If the limit cycle waveform is approximated4 with a sinusoid, the zero crossings of '( )y t with respect to ( )y t occur when
, ,sin 0Qin n LCi i nV A− =χ . As a result, for each second sampling moment n this leads to the introduction in the loop of a signal dependent phase shift that is given by the expression:
,1, sin−= Qin n
i nLCi
VA
χ (6.15)
where ,Qin nV is the DC value in '( )i i at the particular sampling moment n. As the 2LC has
frequency 4sf , only half of the sampling moments actually lead to a transition in the output bitstream. For the other half of the sampling instances a value that is established at the previous clock moment is propagated. From (6.15) it can be seen that the phase shift that is introduced in the SDM loop by the DC input signal is proportional to arcsin of the ratio of the DC component in front of the quantizer and the respective idle limit cycle amplitude. As the value of ,Qin nV varies in time, the signal dependent phase shift 2,nχ is different at each
sampling moment. For the time interval observed in Fig. 6.6, the phase 2,nχ increases with each consecutive sampling moment. However, when ,i nχ exceeds the phase boundary iρ for the active limit cycle, the limit cycles becomes instable as the phase condition for exactly 360deg. phase rotation in the loop is not fulfilled. For the example above, the active second
4 The actual limit cycle waveform in the first order SDM with an ideal integrator as a loop filter is triangular,
however, around the zero crossings where the impact of the input signal is seen, it can also be approximated with a sinusoid.
, 1+s nχ,s nχ [ ]*sy nT
6.3. Input driven time variant limit cycle behavior of SDM 89
sub-harmonic limit cycle 2LC becomes instable when 2,nχ exceeds the phase introduced by
the deliberately introduced extra loop delay and the resulting phase boundary 2 1.125deg.=ρ Evidently, for the studied first order SDM, the phase boundary of the 2LC can be easily exceeded even for small input signals.
Fig. 6.7. The transition from 2LC to 1LC in first order SDM with +180deg. phase shift (phase advance).
At the sampling moment at which 2, 2>nχ ρ , 2LC becomes instable and the SDM loop enters the first sub-harmonic limit cycle 1LC . That is accompanied by a phase jump of +180deg. in the loop.
As the frequency of 1LC is 2sf the bitstream is changing a clock period earlier (Fig. 6.7). At the transition from 2LC to 1LC , due to the 180deg. phase jump, the DC component in front of the quantizer had become negative and equal to the amplitude of the idle 1LC ,
1, ≈ −Qin n LCV A .
The phase boundary 1ρ for 1LC is 90deg. and the amplitude ,1LCA is twice smaller. Due to the smaller amplitude of 1LC , the phase delay (6.15) that is introduced by the input signal
( )x t at each sampling instance is twice larger than the delay that is introduced in operation at
2LC with the same input signal. However, as 1ρ is almost 90deg. (see Fig. 6.4), a much longer phase accumulation is taking place before 1LC would become instable. For 1LC , the phase accumulation reaches the phase boundary such that 1, 1≈nχ ρ when , 1≈Qin n LCV A .
At the sampling moment when 1, 1>nχ ρ , 1LC is rendered instable, the output *[ ]y nT does not change state for an extra clock period and a phase jump of -90deg. is introduced in the loop. That makes 2LC operational and introduces a small negative DC component in front of the quantizer. 2LC does not start from its equilibrium idle value. The transition cycle starts from a different initial value and because the phase in the loop is evaluated at the discrete sampling moments, a slightly different bitstream is produced.
π phase advance
[ ]*y nT
90 Chapter 6: Multi limit cycle behavior of synchronous SDMs
Fig. 6.8. The transition from 2LC to 1LC in first order SDM and negative -90deg. phase jump.
In Fig. 6.9, the input signal of the quantizer is plotted for different DC inputs. From the waveforms the following observations can be pointed out:
• With the increase of the applied DC inputs, the rate of the transitions between the limit cycles 1LC and 2LC also increases. That is due to the fact that the phase boundary for each limit cycle is crossed over faster, because of the faster accumulation of phase shift for larger input signal.
• The transitions between the limit cycles are deterministic and from given initial conditions the output bitstream can be determined.
• For large DC inputs the phase boundary for 2LC is surpassed for a single clock period, as illustrated in the last waveform in Fig. 6.9.
Fig. 6.9. Comparison of quantizer input waveforms for a first order SDM with BQ0 for idle, small and large DC input signals.
[ ]*sy nT
6.3.1.2. Analytical description for DC input 91
6.3.1.2. Analytical description for DC input
From (6.7), the conditions for limit cycle oscillations in SDM when the quantizer is linearized with its DF are given by the relations:
( )( )
,
,
Re Re ( , , ). 1
Im ( , , )Im
+ + = −
i i i in
i i ini
LC LC LC Q s i
LC LC Q s iLC
L j N A V
j N A Vj L j
ω ϕ
ϕω (6.16)
( ), ,, , =i in
in
outDC i LC Q s i
Q
VN A VV
ϕ (6.17)
where in (6.16) ,( , , )LC LC Q s ii i in
N A V ϕ is the sampled DIDF (see Appendix B.1) that has a
magnitude given by ( , )LC LC Qi i inN A V and the sampling is accounted for in ,s iϕ . Respectively, in
(6.17) , ,( , , )DC i LC Q s ii inN A V ϕ is the describing function given in (6.18) for the quantizer for DC
input in the presence of a sinusoidal component in ( )i t and after sampling. It defines the gain of the quantizer for the DC component at its input.
The function , ,( , , )DC i LC Q s ii inN A V ϕ is denoted as the signal DF, while ,( , , )LC LC Q s ii i in
N A V ϕ is the limit cycle DF of the quantizer. The signal DF is given as:
( ) , 1, ,
2, sin− −
= +
ins i
i in
in i
QjDC i LC Q s i
Q LC
VN A V e
V Aϕ ϕ
π (6.18)
For the studied first order SDM two idle limit cycles exist and equations (6.16) and (6.17)
have to be solved for each of them. Respectively, for 2LC , the system behavior is described by:
( ) ( )
( )
,2 2
2 22
,2
2,2
, 1
,
s
LC in
s
in
in
j jA LC Q LC
j outDC LC Q
Q
N A V e L j e
V N A V eV
ϕ ξ
ϕ
ω− −
−
= −
= (6.19)
where in (6.19) outV is the DC component in the SDM output signal. From Section 6.2, the boundaries of the clock added phase shift for 2LC are given as
,20 2s< ≤ϕ π , and the phase rotation 2ξ in the linear part results in a phase boundary 2ρ . The DF in the second equation in (6.19) defines the quantizer gain for a DC input in the presence of a limit cycle and is defined as the ratio between the DC component in the output bitstream and the DC component in front of the quantizer.
For an ideal first order integrator, the loop filter and the extra loop delay at 4sf can be
described as:
92 Chapter 6: Multi limit cycle behavior of synchronous SDMs
( ) ( ) ( )( )
( ) ( )
2
2
2
2 2
2 2
2 2
10 cos sin
sin cos
−
= − − =
= − −
jLC
LC
LC LC
L j e j j
j
ξω ρ ρω
ρ ρω ω
(6.20)
From (6.16) and (6.19), with the help of (6.20), the 2LC is characterized by the following
system of equations:
( ) ( ) ( ) ( )( )
( ) ( ) ( ) ( )( )
2 2 2
2 2 2
2
2
,2 2 ,2 2
2
,2 2 ,2 2
,2
4 1 cos sin sin cos 1
4 1 cos cos sin sin 0
sin2
− + =
− + =
= +
in
in
in
Qs s
LC LC LC
Qs s
LC LC LC
Qout s
LC
VA A
VA A
VV
A
ϕ ρ ϕ ρπω
ϕ ρ ϕ ρπω
π ϕ
(6.21)
Substituting the third equation from (6.21) in the first two and via trigonometric
transformations, the system is represented as:
( )
( )2 2
2 2
,2 ,2 2
,2 ,2 2
4 cos sin 12
4 cos cos 02
+ + =
+ − =
out s sLC LC
out s sLC LC
VA
VA
π ϕ ϕ ρπω
π ϕ ϕ ρπω
(6.22)
The second equation in (6.22) can be used for the establishment of the phase conditions for
the maintenance of limit cycle oscillations in the presence of a DC input. In (6.22) ,20 2< ≤sϕ π , 2ρ has a predetermined value and the phase component 4inVπ (with the
assumption that =out inV V ) varies with the input signal. The solution of the second equation in (6.22) is given by:
,2 2
,2
,2
2
2 2
02
− =
+ <
< ≤
s
in s
s
V
πϕ ρ
π πϕ
πϕ
(6.23)
The second inequality in (6.23) is dictated by the first equation in (6.22) and gives the
range of phases for which the magnitude condition for oscillations is fulfilled. Respectively,
6.3.1.2. Analytical description for DC input 93
2LC is preserved in the presence of a DC component if:
2 02
− ≤inVπ ρ (6.24)
Expression (6.24) states that in order to maintain the oscillation at 2LC the phase added by
the input signal should remain below the phase boundary for the particular limit cycle. The regions of operation for 1LC can be established with the same approach. Using the
evaluation procedure described in (6.19) to (6.22), the following system can be derived:
,1 1
,1
,1
2 20
− =
+ <
< ≤
s
in s
s
V
ϕ ρ π
π πϕ
ϕ π
(6.25)
From (6.25) ca be concluded that 1LC is preserved in the presence of a DC component if:.
12 2− <inVπ πρ (6.26)
Expression (6.24) and (6.26) confirm the conceptual reasoning discussed in Section 6.3.1.1.
6.3.2. SDM operation with sinusoidal input
The SDM limit cycle behavior with sinusoidal inputs is governed by the same mechanisms as discussed for DC input:
• The limit cycle behavior is determined by the possible limit cycles in idle mode.
• The stability region for each possible limit cycle is dependent on the phase boundary for each LC that is possible for the particular SDM parameterization.
• Transitions between the cycles are dependent on the total phase accumulation at each sampling moment due the loop filter, the delay due to the sampling, the input signal and the extra loop delay.
In this section, the sampled TSIDF is employed for the analysis of the limit cycle behavior and the conditions for switching between the cycles. The dependence of the limit cycle behavior from the amplitude and the frequency of the input signal is discussed and illustrated with examples.
As a starting point for the following analysis, the input signal in front of the quantizer is described by one of the expressions:
( ) ( ) ( )( ) ( ) ( )
1 1
2 1
1
2
sin + sin
sin + sin
=
=
in
in
Q LC LC
Q LC LC
i t V t A t
i t V t A t
µ ω
µ ω (6.27)
94 Chapter 6: Multi limit cycle behavior of synchronous SDMs
where sin( )QinV tµ in (6.27) is the signal in front of the quantizer due to the signal applied to the SDM input. At each sampling instant, operation at only one limit cycle mode is assumed such that the signal in front of the quantizer can be described by either 1 2( ) or ( )i t i t . It has to be pointed out that as far as the studied SDMs use a continuous time loop filter, the frequency content of the input signal component in ( )i t is not changed by the loop filter and arrives at the quantizer input after a possible attenuation and an added phase from the loop filter but with unaltered frequency.
From (6.27), when only two idle limit cycles are possible, the SDM operation for sinusoidal input can be described by four sampled TSIDFs defined as follows:
• Two TSIDFs describe the quantizer response to the limit cycle in the presence of an
input signal and are given as: ,1
,11( , ) j ts
A LC Q ACLC inN A V e ϕ− : sampled TSIDFs of the quantizer for the 1LC component in the
presence of a sinusoidal input signal that has an amplitude of ,Q ACinV in 1 ( )i t ;
,2
,22( , ) j ts
A LC Q ACLC inN A V e ϕ− : sampled TSIDFs of the quantizer for the 2LC component in the
presence of a sinusoidal input signal that has an amplitude of ,Q ACinV in 2 ( )i t ;
• Two TSIDF describe the quantizer response to the input signal in the presence of a
limit cycle, given as:
,1,, 1
( , ) j tsV Q AC LCQ AC inin
N V A e ϕ : sampled TSIDFs of the quantizer for the signal component in 1 ( )i t in
the presence of a sinusoidal 1LC ; ,2
,, 2 2( , ) j ts
V Q AC LCQ AC ininN V A e ϕ− : sampled TSIDFs of the quantizer for the signal component in 2 ( )i t
in the presence of a sinusoidal 2LC ; The system behavior at each sampling instant is described by a set of two DFs from the
above: one DF for the limit cycle and one for the input signal. Each of the above functions can have a different analytical form that depends on the
relative amplitudes ,i LC Q ACi ink A V= of the limit cycle component and the signal component
such that the magnitude component of the TSIDFs is defined (see Appendix B.3) as follows:
( ) ( ) ( ) ( )2, 2 2
8, 1 for 1 = − − > LC i inii
A LC Q AC i i i ii LC
N A V E k k K k kk Aπ
(6.28)
( ) ( ), , 2
,
8, for 1= <Q AC in iin
in
V Q AC LC i iQ AC
N V A E k kVπ
(6.29)
In Appendix B.3 the sampled TSIDFs for SDM with a BQ0 when driven with sinusoidal
inputs are derived. From (6.28), (6.29) and (B.18) three cases can be described that determine the SDM limit cycle state with respect to the instantaneous ratio between the limit cycle amplitudes and the input signal component in front of the quantizer.
6.3.2. SDM operation with sinusoidal input 95
1) Case 1: The instantaneous amplitude of the signal component is smaller than the amplitude of the high frequency limit cycle (the one with the smaller amplitude), such that:
1 2, , < <
inQ n AC LC LCV A A and 11
, ,
1= <LC
Qin n AC
Ak
V
Then the SDM state is described by:
( ) ( )
( ) ( )1
1
1 ,1 12, ,
1 ,1 12, ,
8 sin 1
8 cos 0
+ =
− =
in
in
sLC Q n AC
sLC Q n AC
E kV
E kV
ϕ ρπ ω
ϕ ρπ ω
(6.30)
2) Case 2:
1 2, ,< <
inLC Q n AC LCA V A and 11
, ,
1= >in
LC
Q n AC
Ak
V, Then the SDM state is described by:
( ) ( ) ( ) ( )
( ) ( ) ( ) ( )1
1
2,2 2
1
2,2 2
1
8 1 sin 1
8 1 cos 0
− − + =
− − − =
i i i s i iLC
i i i s i iLC
E k k K kk A
E k k K kk A
ϕ ρπ
ϕ ρπ
(6.31)
3) Case 3:
1 2 , ,< <
inLC LC Q n ACA A V and 21 2
, ,
1< = <in
LC
Q n AC
Ak k
V
( ) ( )
( ) ( )2
2
2 ,2 22, ,
2 ,2 22, ,
8 sin 1
8 cos 0
+ =
− =
in
in
sLC Q n AC
sLC Q n AC
E kV
E kV
ϕ ρπ ω
ϕ ρπ ω
(6.32)
In analogy to the DC situation described earlier, the phase condition for oscillation at a
particular limit cycle can be derived from the second equation in (6.30), (6.31) or (6.32). The main difference with respect to the DC input case can be summarized as follows:
• Due to the AC properties of the signal component in ( )i t the loop phase variation due to the input signal is not monotonous (phase accumulation or subtraction) but is sinusoidal, such that equal phase accumulation and subtraction occurs in the loop for one period of the input signal ( )x t .
• For sufficiently high input amplitudes the SDM loop can jump between several limit cycles within one period of the input signal.
96 Chapter 6: Multi limit cycle behavior of synchronous SDMs
• The transitions between the limit cycles are also dependent on the frequency of the input signal as it influences the instantaneous amplitude of the signal component. An example is given in Fig. 6.10, where two wave forms of the signal in front of the quantizer are shown, that appear in a first order SDM for an input signal amplitude of -20dBFS and two input frequencies.
Fig. 6.10. Comparison of quantizer input waveforms for 1 1= MHzµ and 1 5= MHzµ and a fixed input amplitude of 20− dBFS
In order to couple the analytical description of the LC behavior to practical considerations in the SDM design, next the impact of the characteristics of the non-linear element, the filter order and the frequency of the sampling clock are evaluated.
6.4. System impact on the LC behavior: characteristic examples
The limit cycle model of the SDM operation gives new insights in the operation of the modulator and can be used for the derivation of design criteria and for system optimization. In this sub-section the limit cycle mode is used for the evaluation of SDMs built with the basic quantizers (BQ0 and BQh) studied up to now and loop filters of different orders. Special attention is given to the incorporation of extra loop delay in the limit cycle model and the evaluation of its impact. The basic dependencies that exist in the SDM systems are seen from the perspective of the limit cycle model. The possible design trade-offs are pointed out and several general design rules are derived. It is demonstrated that the LCM can be employed for the qualitative evaluation of several known phenomena in SDM operation, such as dead zones for the input signal, in-band spurious components and conditions for overload.
6.4.1. Test bench definition
In order to verify the applicability of the SDM LC model for the design of practical systems, a test bench for AC and transient simulations is defined. Firstly, the expected idle limit cycle behavior is evaluated graphically in the phase/magnitude plane5. From the AC
5 In a real design procedure such an evaluation requires a straight forward AC analysis of the linear part of the loop.
0 0.5 1 1.5 2 2.5 3 3.5 4
0
0
Time [ns]
fin=5MHz
fin=1MHz
6.4.1. Test bench definition 97
evaluation the desired idle limit cycle behavior can be chosen. Secondly, the limit cycle behavior (for idle and busy operation) is observed with transient simulations that use the same parameterization for the loop filter. As in previous cases, the limit cycle behavior is observed at the input of the quantizer.
Most of the experiments performed in this sub-section use a test bench with the following rather arbitrary specifications:
• The loop filter that is used in the simulations has a low pass character and is of an arbitrary order. However, in order to simplify the evaluation and the interpretation of the results, most of the simulations are performed with first and second order loop filters. At the end of this chapter, the implications of the LCM are generalized for a loop filter of an arbitrary order.
• In the evaluation BQ0 and BQh are used.
• An arbitrary bandwidth of 5MHz is chosen for the evaluation of the SNRq and SINAD. The clock frequency is set to 1GHz. This clock frequency provides an OSR6 of 100.
• When applicable, an input signal with 1MHz frequency is applied to the system.
The above test bench has the following advantages:
• The absolute (non-normalized) choice for the frequency parameterization (clock frequency, signal bandwidth and input signal) facilitates the simulation setup and the interpretation of the results.
• The high OSR introduces a large design space because it assures a large dynamic range and facilitates the evaluation of the impact of multiple simultaneous limit cycles.
• The transient simulations allow the observation of the time waveforms in the loop and the evaluation of the performance in terms of SNRq and SINAD via spectral analysis.
For each system parameterization several evaluations are provided. Firstly, the idle limit cycle behavior is evaluated in the phase/magnitude plane. Secondly, the limit cycle behavior is evaluated for a busy signal. For this purpose, the zero crossings in front of the quantizer are counted for a fixed time period, for example one period of the input signal. The result from the count in busy operation is compared with the count in idle mode. From the comparison, conclusions are drawn for the limit cycle behavior in busy operation. Finally, the output spectrum is calculated from the results of the transient simulations and the achievable performance, in terms of SNRq and SINAD is evaluated.
6 In the context of the SDM limit cycle model, the OSR receives an additional meaning, because it only shows the ratio between the
highest sub-harmonic mode and the signal band. As shown in this chapter, it has different implication for the LCM than for the WNM.
98 Chapter 6: Multi limit cycle behavior of synchronous SDMs
6.4.2. Limit cycle behavior of SDM with BQ0
As already pointed out on several occasions, the DF of a BQ0 depends only on the amplitude of the driving signal and is a real function ( ( ) 4N A A= π ). It is plotted simply as a straight line in the phase/magnitude plane. That means that the DF for BQ0 (and the corresponding quantizer) is not contributing to the phase behavior of the SDM loop. However, the sampled DF is complex due to the representation of the sampling as a phase shift introduced in the SDM loop.
6.4.2.1. First order systems
The loop filter of the first order SDM is described as follows:
( ) =+ p
GL jj
ωω ω
(6.33)
From (6.33) can be seen that for the first order loop filter, with a DC gain pG ω only one
degree of freedom exists for the parameterization of the loop filter and that is the frequency pω of the pole in the denominator of (6.33). Two situations have to be treated: 1) The DC gain in the loop filter is smaller than one such that pG <ω . In this situation the
phase of the loop filter at 4sf can be chosen to be less than 90deg. such that an idle limit cycle with frequency 4sf (see Fig. 6.11a) is not possible.
The first observation to be pointed out is that in contrast with the asynchronous case, the first order SDM system can sustain oscillations for BQ0. While in the first order ASDM case, the system was not capable of sustaining self-oscillations due to the insufficient phase rotation in the closed loop, here the required additional delay is provided by the sampling operation. Other remarks that have to be pointed out:
In Fig. 6.11b, the zero crossings in front of the quantizer are counted for 1us. As the applied sampling frequency is 1GHz, for 1us, 500 zero crossings occur in front of the quantizer when the loop operates in the first idle sub-harmonic mode with frequency of 2sf . From Fig. 6.11b, it can be concluded that when only one limit cycle is possible, for a large range of input amplitudes the loop operates only at 2sf .
In Fig. 6.11c the simulated output spectrum for -3dBFS input signal is shown. The high level of harmonics indicate a strong correlation between the SDM input signal and the quantization noise that results in a high quantization noise power at discrete frequencies multiples of the input signal.
For input amplitudes higher than -15dBFS the number of zero crossings starts to decrease rapidly. However, as indicated on Fig. 6.11d, for input amplitudes lower than -15dBFS, the SDM loop is not shaping the quantization noise.
6.4.2. Limit cycle behavior of SDM with BQ0 99
а) b)
c) d)
Fig. 6.11. Evaluation of the limit cycle behavior of a first order SDM a) graphical evaluation of the idle limit cycle modes, b) zero crossings count in front of the quantizer for different input amplitudes, c) Spectrum of the output bitstream for -3dBFS signal,
d) achievable DR for the particular filter parameterization
Evidently, this SDM parameterization does not provide a useful operation. However, it reveals the relation between the idle limit cycle behavior and the SDM operation and the achievable performance. Firstly, the lack of noise shaping can be explained with the very low loop gain that provides very low suppression of the quantization noise in the desired signal band. Secondly, it can be concluded that if in the SDM loop conditions exist for only one idle limit cycle, there is a strong correlation between the SDM input signal and the quantization noise that results in a high quantization noise power at discrete frequencies multiples of the input signal.
2) A second possible parameterization for the first order system implements a high DC gain such that pG ω>> . The graphical evaluation in Fig. 6.12a, reveals that the phase margin for the second sub-harmonic limit cycle 2 0→λ and two idle limit cycles with frequencies 2sf and 4sf exists in the loop.
−270 −225 −180 −135 −90 −45 −50
−45
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B]
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350
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500
Input Amplitude [dBFS]
Tra
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for
1us
100 Chapter 6: Multi limit cycle behavior of synchronous SDMs
a) b)
b) d)
Fig. 6.12. First order SDM with two idle limit cycles: a) graphical evaluation of the idle modes, b) transitions for different input amplitudes, c) typical time domain waveform in
front of the quantizer for -15dBFS, d) dynamic range.
Fig. 6.12b shows that the loop operates with 2sf only for very small input amplitudes and with the increase of the input signal the number of transition per second is decreasing because the loop starts to make more and more transitions with frequency 4sf . In Fig. 6.12c, the waveform in front of the quantizer is given that shows transitions with lower frequency. The evaluation of the achievable DR that is shown in Fig. 6.12d reveals a significant improvement of the performance with respect to the first studied case for a first order loop filter. The existence of a second LC mode allows a higher de-correlation of the quantization noise and introduces noise shaping and, as a result, improves the SDM performance.
6.4.2.2. Second order systems
The introduction of a second order transfer (6.3) for the loop filter increases further the available degrees of freedom for the parameterization of the filter function. Here several characteristic cases are studied from the LCM perspective. Again the LCM evaluations are confirmed with transient simulations and coupled with the achievable performance.
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Input Amplitude [dBFS]
i(t)
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1us
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6.4.2. Limit cycle behavior of SDM with BQ0 101
a) b) c) d)
Fig. 6.13, Second order SDM with multiple idle limit cycles: a) graphical evaluation, b) number of transitions for different input amplitudes, c) output spectrum for -20dBFS input
amplitude, d) dynamic range.
In analogy to the first order system, several typical situations can be defined with respect to the parameterization of the filter.
Case 1: In Fig. 6.13a a second order loop filter is evaluated with phase characteristic that
approaches 180 degrees for 2sf . Such a phase characteristic can be realized if the zero in ( )L jω is put at a very high frequency and does not have an impact on the observed
frequency range or if the filter is a second order integrator without zero. However, if the integrator is ideal, such that the phase of the filter immediately reaches 180 deg. the SDM is instable and cannot sustain oscillation and process the input signal. A stable system can be designed if the pole frequencies pω are chosen sufficiently high, such that the phase response plotted in Fig. 6.13a can be realized. Fig. 6.13a indicates that multiple low frequency idle limit cycles with frequencies as low as 18sf are possible. The transient simulations Fig. 6.13b show that indeed for small input signal the SDM loop oscillates with frequency
−80 −70 −60 −50 −40 −30 −20 −10 030
35
40
45
50
55
60
65
Input Amplitude [dBFS]
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nsiti
ons
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1us
−360 −270 −180 −90
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0
Phase [degrees]
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102 Chapter 6: Multi limit cycle behavior of synchronous SDMs
16sf (62.5 transitions for 1GHz clock and 1 sµ observation time, and peak in the spectrum) and for higher input signal the frequency of oscillation decreases as the loop starts to operate also at lower frequency limit cycles. The SDM cannot enter higher frequency LCs due to their very small phase boundary. In Fig. 6.13c the output spectrum is plotted for an input signal with amplitude of -6dBFS and in Fig. 6.13d the achievable DR is plotted with respect to the applied input signal amplitude. From Fig. 6.13d can be concluded that if the input signal is smaller than approximately 52dB it cannot be processed by the SDM. Alternatively, we can state that the input signal is processed only if it has sufficient amplitude to cause SDM operation at at least two limit cycles.
Case 2: In Fig. 6.14, the existence of idle limit cycle is evaluated for a second order system with a
zero zω , as a function of the frequency position of the zero. As illustrated in Fig. 6.14a,b the position of zω can influence significantly the limit cycle behavior such that for a low frequency zero only the first two sub-harmonic limit cycles exist Fig. 6.14a and by pushing the zero to higher frequencies additional limit cycles with lower frequencies are made possible. In Fig. 6.14c, the zero crossing in front of the quantizer are counted for
100 , 500 and 1zf MHz MHz GHz= . From the experiment can be concluded that:
• For all three zω parameterizations, the SDM operates at 4sf for idle mode and small input signal;
• For a small phase boundary 2ρ of the second sub-harmonic limit cycle (Fig. 6.14a) with the increase of the input amplitude the number of transitions per second in the loop with frequency 2sf increases fast.
• For a larger 2ρ (Fig. 6.14b and 500zf MHz= ), it can be concluded that for a large range of input amplitudes the SDM operates at two limit cycles. The average number of transitions indicates that the SDM makes an approximately equal number of transitions at each of the two possible limit cycles.
• When 1zf GHz= , four limit cycles with frequency down to 8sf are possible. From Fig. 6.14c it can be seen that the average number of transitions corresponds to simultaneous operation at four limit cycles with a bigger number of transitions made with 4sf .
In Fig. 6.14d the achievable qSNR is evaluated for the studied loop filter parameterization and limit cycle behavior. It shows similar performance for loop filters with
500 , 1zf MHz GHz= and a significant degradation of qSNR for 100zf MHz= . Again this deterioration can be explained with the effective decrease of the order of the loop filter for this parameterization or with the resulting limit cycle behavior that decreases the phase boundary for 2LC and respectively the de-correlation properties of the SDM loop.
6.4.2. Limit cycle behavior of SDM with BQ0 103
a) b) c) d)
Fig. 6.14. Graphical determination of idle limit cycles in second order SDM with BQ0 with respect to the position of the zero а) <<z sω ω , b) and =z s z sω ω ω ω , c)
comparison for the number of transition, d) comparison dynamic range
Special attention for the optimal SDM parameterization with respect to the LCM is given in Chapter 7. Next, for completion of the experiment, the limit cycle behavior of higher order loop filters will be illustrated and discussed.
6.4.2.3. Arbitrary order loop filters
The achievable DR increases significantly when the order of the loop filter in the SDM is increased. However, a common issue for higher order loop filters is the stability of the modulator. In this section the LCM is applied for the evaluation of the trade-offs that the higher order loop filters are introducing in the parameterization of the SDM loop. The increased order of the loop filter increases the available degrees of freedom for the parameterization. A typical property of higher order loop filters is the increased phase delay due to the increased number of poles. This phase delay can easily exceed 180deg. In Fig. 6.15a an example is given for a third order filter defined as:
( )2( ) =
+ p
GL jj j
ωω ω ω
(6.34)
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de [d
B]
ωz=1e8
−270 −180 −90−70
−60
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Phase [degrees]
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de [d
B]
ωz=5e8
ωz=1e91 8zf e= 1 9zf e=
5 8zf e=
104 Chapter 6: Multi limit cycle behavior of synchronous SDMs
Evidently, according to the LCM, an SDM loop filter built with an ideal third order integrator ( 0→pω ) will not result in a crossing in the phase/magnitude plane and will not sustain stable oscillations. This statement can be directly confirmed with transient simulations.
In the example plotted in Fig. 6.15a, pω is chosen such that the phase shift of ( )L jω does not exceed 180deg. for frequencies corresponding to 2sf and lower. According to the LCM this loop filter parameterization guaranties an oscillating loop with two possible sub-harmonic limit cycles 2sf and 4sf . Again this filter parameterization is evaluated with transient simulation and the zero crossings in front of the quantizer are counted Fig. 6.15b.
a) b) c) d)
Fig. 6.15. Application of LCM for higher order loop filters a) graphical determination of idle limit cycles, b) simulated number of transition in busy operation, b) example of the output spectrum for small signal of -40dBFS, d) evaluation of the achievable DR.
The simulations show that the SDM operates at both 2sf and 4sf . In Fig. 6.15c an example is given of the output spectrum for a small input signal (-40dBFS). The spectral peaking at 4sf is an indication for an limit cycle for this frequency.
From Fig. 6.15a, it can also be concluded that if the clock speed is increased beyond a certain value at which the ( )L jω locus crosses the -180deg. line, the SDM is not capable of
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Normalized Frequency
Out
put S
pect
rum
[dB
]
6.4.2. Limit cycle behavior of SDM with BQ0 105
operation at maximum clock speed and operates at limit cycles with a frequency of 4sf and 6sf .
The loop can be forced to operate at full clock speed with proper phase compensation. Namely, the phase delay produced by the clock should be compensated with a proper modification of the linear part of the loop.
In Fig. 6.16a, a third order loop filter defined in (6.35) is studied. With the help of the zeroes in ( )L jω , a proper phase compensation is realized such that the loop filter behavior approaches first order for high frequencies.
( )( )( )
1 22( )
+ +=
+z z
p
G j jL j
j j
ω ω ω ωω
ω ω ω (6.35)
a) b)
Fig. 6.16. Application of LCM for higher order loop filters a) graphical determination of idle limit cycles in third order SDM b) Impact of higher clock
frequency on the limit cycle behavior.
Thus, an increase of the loop gain results in higher amplitude of the limit cycle; however, its frequency remains the same, because the phase characteristic of the filter remains the same.
The LCM offers an intuitive interpretation of the requirements for a stable high-order SDM. The high-order low-pass SDM will be stable if the loop filter is designed such that only the high frequency idle limit cycles are possible or the phase boundary for the low frequency limit cycles is minimal such that only a small number of transitions occur at low frequency. Such a parameterization, requires a loop filter phase characteristic that has enough phase margin iλ for the whole frequency range up to 2sf .
Moreover, as illustrated in Fig. 6.16b, the positions of the zeros in ( )L jω determine the achievable performance and together with the extra loop delay and the possible hysteresis in the quantizer build an optimization space that is studied in the following chapter for the determination of the optimal SDM parameterization.
−270 −180 −90−100
−90
−80
−70
−60
−50
−40
−30
Phase [degrees]
Mag
nitu
de [d
B]
106 Chapter 6: Multi limit cycle behavior of synchronous SDMs
6.4.3. Limit cycle behavior of SDM with BQh
In Fig. 6.17, the LCM is applied for the evaluation of a second order SDM and a BQh with hysteresis h = 0.002. Several interesting properties of this implementation can be observed in Fig. 6.17a:
• The hysteresis introduces an extra amplitude dependent phase rotation in the loop.
• The hysteresis effectively increases the phase boundary iρ for the high frequency sub-harmonic limit cycles due to the added phase rotation for low signal amplitudes.
• In this particular example, the hysteresis renders impossible the first sub-harmonic limit cycle with frequency 2sf .
a) b) c) d)
Fig. 6.17. Evaluation of second order SDM with BQh (h=0.002) а) Graphical evaluation of the impact of h on the idle limit cycle behavior; b) number of
transitions in front of the quantizer, c) Output spectrum for -60dBFS input signal d) comparison of the dynamic range between BQ0 and BQh.
From Fig. 6.17b, on the other hand can be seen that for busy operation and a small input signal of 60− dBFS and lower, the loop operates only at the second and third sub-harmonic limit cycles. For higher input amplitudes the average number of transitions decreases as more
−270 −180 −90−60
−55
−50
−45
−40
−35
−30
−25
−20
Phase [degrees]
Mag
nitu
de [d
B]
−80 −60 −40 −20 080
100
120
140
160
180
200
220
Input Amplitude [dBFS]
Tra
nsiti
ons
per
1us
0 0.1 0.2 0.3 0.4 0.5−180
−160
−140
−120
−100
−80
−60
−40
−20
0
Normalized Frequency
Out
put S
pect
rum
[dB
]
6.4.3. Limit cycle behavior of SDM with BQh 107
transitions occur at the third sub-harmonic limit cycle. In Fig. 6.17c, the output spectrum is plotted for a small input signal of 60− dBFS . From
this spectrum, it can also be concluded that the majority of transitions appear with frequency of 4sf .
In Fig. 6.17d, the achievable DR is compared with that of a SDM implementation that uses the same filter but does not have hysteresis. From the plot approximately 7dB deterioration of the DR for BQh can be measured.
6.4.4. Impact of the extra loop delay
An important design issue in high speed SDMs is the evaluation of the impact of extra loop delay on the performance. This delay can be functionally required or parasitically introduced by the implementation.
A time delay can be introduced deliberately in the design of the quantizer or the feedback DAC. A typical example is the introduction of a time delay between the sampling moments of the latch stage that is used in the quantizer (see Fig. 6.18) and the digital block (most often a flip-flop) that is used for the propagation of the well defined digital signal to the output and for the feedback. In most cases such a delay is functionally needed as it provides a decision time for the latch such that it can process correctly input signals with predetermined low amplitude and high frequency. As on the other hand the latch decision time strongly depends on the current consumption, a trade-off is introduced between the added extra time delay and the power consumption of the comparator.
Fig. 6.18. Example of an extra loop delay introduced in the quantizer A time delay is also introduced in the DAC, normally to assure the right sequence of data
and clock signals. A third component of the extra time delay is the propagation delay of the building blocks that process the signal from the sampling moment of the latch , 1sf φ to the summation point with this input signal (or the input of the loop filter). Those last two components, though unavoidable, are relatively small.
The extra loop delay also gives rise to an extra phase delay component. In most cases it is purely parasitic as it originates from the parasitic high frequency poles in the frequency transfer characteristic of the operational amplifiers and the whole loop filter. In a practical transistor simulation, those parasitics are included in the evaluation and their impact is accounted for in the phase/magnitude plots studied previously. However, this delay is usually not included in the high level system evaluations and its impact remains hidden.
The extra phase delay has also a component that is due to the parasitics introduced in the layout (cross coupling capacitances and capacitances to the power supply lines). Evidently
τ, 1sf φ
, 2sf φ
τ, 1sf φ
, 2sf φ, 1sf φ
FF( )L jω
Loop Filter
DAC
+-
, 2sf φ
[ ]*sy nTinV
, 1sf φ
FF( )L jω
Loop Filter
DAC
+-
, 2sf φ
[ ]*sy nTinV
τ, 1sf φ
, 2sf φ
τ, 1sf φ
, 2sf φ, 1sf φ
FF( )L jω
Loop Filter
DAC
+-
, 2sf φ
[ ]*sy nTinV
, 1sf φ
FF( )L jω
Loop Filter
DAC
+-
, 2sf φ
[ ]*sy nTinV
108 Chapter 6: Multi limit cycle behavior of synchronous SDMs
the evaluation of those parasitics is a laborious task as it requires layout extraction. However, for high clock speed the parasitics introduced by the layout may have a significant impact and should not be neglected.
Whatever the source of the extra loop delay is, as far as it can be assumed to be constant, all components of the extra loop delay can be united in a single time constant τ . Due to the linearity of this delay for the study of the system behavior τ can be placed at an arbitrary position in the loop. In Fig. 6.19 the total extra loop delay τ is introduced in the LCM of the SDM loop.
Fig. 6.19. Incorporation of the extra loop delay τ in the LCM Expression (6.36) shows the incorporation of the total delay t into a second order filter
transfer function:
( )( )2
jz
p
j L j ej
ωτω ωωω ω
−+=
+ (6.36)
In Fig. 6.20, the impact of the delay is evaluated with the help of the LCM. In the figure
two SDM implementation are compared: one without extra loop delay 0
0( ) ( )L j L j eτ ω ω= and a second one
1
1( ) ( ) jL j L j e ωττ ω ω −= with a total extra loop delay 25% sTτ = .
From Fig. 6.20, it can be concluded that:
• The delay decreases the phase margin of the low frequency sub-harmonic limit cycles.
• For the studied filter configuration and clock frequency, a total extra loop delay that corresponds to 25% of the clock frequency already leads to the appearance of the 6sf limit cycle.
• The impact of the delay for higher frequencies is higher and with the increase of the sampling speed gets an increasingly important impact. In practice the possibility to utilize the 2sf sub-harmonic mode for high sampling clocks is limited by the extra loop delay that is introduced by the implementation.
• A time delay in the loop that approaches the period of the sampling clock leads to operation at a very low frequency limit cycle and has a severe deteriorating effect on the performance of the modulator.
delay
τVin=0
sf
( )L jω ( )c s ,iN A ,ϕI
+-
[ ]*sy nTdelay
τdelay
τVin=0
sf
( )L jω ( )c s ,iN A ,ϕI
+-
[ ]*sy nT
6.4.4. Impact of the extra loop delay 109
Fig. 6.20. Impact of the extra loop delay on the limit cycle behavior, 0 10, 25% sTτ τ= = .
6.5. Conclusions
In this chapter, a new limit cycle model of SDM operation is proposed and elaborated. The model treats the SDM as a sampled, non-linear closed loop system. Via analysis and simulation it has been shown that the SDM can operate at various modes of operation that are determined by the loop filter properties, the sampling clock and the extra loop delay.
The model uses TSIDF for the analysis and is able to predict the possible idle limit cycles in the SDM and the conditions for transitions between the limit cycles when the SDM is driven with an input signal.
For a busy operation, fully periodic modes can appear in the system only for a very specific set of input amplitudes and frequencies. For the majority of input signals the SDMs operation is quasi-periodic such that for every period of the input signal a slightly different digital output is produced.
The graphical application of the limit cycle model of the SDM operation can serve as a tool for a quick evaluation of the available phase margin in the loop and the possible limit cycle modes.
From the limit cycle point of view, the most important practical constraints are introduced by the extra loop delay and the hysteresis in the quantizer. Those two are underlined among the numerous other practical problems that may appear during an implementation, because they have a dominant impact on the performance and are present in any implementation. The limit cycle model offers a better understanding of the mechanism through which those effects deteriorate the SDM performance.
( )0
L jτ ω
( )1
L jτ ωExtra loop delay induced LC
( )0
L jτ ω
( )1
L jτ ωExtra loop delay induced LC
110
7. Chapter 7
Performance Evaluation and Optimal Design of SDMs
This chapter uses the limit cycle model of SDM operation for an analytical estimation of the achievable performance of single bit SDMs in terms of DR and peak SNRq. A new model for the evaluation of the quantization noise is proposed and investigated. Based on the analysis, the SDM design space is redefined and the considerations for an optimal parameterization of SDMs are discussed and illustrated with simulation examples. Two possible procedures for design optimization are proposed and elaborated.
7.1. Quantization noise in SDMs
The evaluation of the quantization noise introduced in the SDM operation and the respective quantization noise power spectrum has been a dominant subject of the theoretical research in the SDM operation since the introduction of the SDMs in the 50ties of the 20th century.
The quantization noise originates from the strongly non-linear quantizer function and the sampling in the SDM loop. The analytical treatment of the noise is very much complicated due to the non-periodic nature of the SDM output bitstream that does not allow a direct application of the standard Fourier analysis for the description of the SDM output spectrum and its quantization noise component.
The limit cycle model of SDM operation and the established transitions between the limit cycles for busy input can be incorporated in the evaluation of quantization noise in the SDM operation.
In this section, firstly, the existing quantization noise models are briefly discussed. Secondly, a new quantization noise model is created based on the established SDM limit cycle behavior. An evaluation is made for the achievable SNRq that takes into account the switching between the limit cycles.
7.1.1. Quantization noise models
Major works on the analysis of SDM quantization noise [30], [32], [33], [34], [70] have developed several analytical models. Those models can be divided in three groups:
• The first model (discussed earlier as WNM) replaces the binary quantizer by a white uniformly distributed noise process. However, in [34] it has been shown that the mean and the power of the binary quantization noise are consistent with this common uniform distribution assumptions but the power spectrum is not. Despite the well known limitations, the WNM is still extensively used in the SDM design because it makes the noise evaluation a simple matter of linear systems spectral analysis.
• A second type of quantization noise model builds a Fourier series representation of the quantization error signal for specific sets of input signals from which the
112 Chapter 7: Performance Evaluation and Optimal Design of SDMs
systems properties are extracted. However, the SDM output in busy operation is aperiodic. That means that for the same harmonic input a slightly different bitstream is produced due to the different initial conditions for each loop cycle1. Fourier analysis can be applied only in some special cases when the input signal frequency is harmonically related to the sampling frequency and for some DC inputs, because for such inputs the SDM produces periodic outputs. Then the conclusions drawn for the special cases are extrapolated to cover all possible input signals. A drawback of the approach is the inability to describe directly the general situation for arbitrary input signals.
• A third approach, described in [34] overcomes the aperiodicity problem by treating the binary quantizer error sequence as almost periodic by using the analysis given in [37] and subsequently builds Fourier series description of the quantization error. The quantization noise is described as cyclostationary random processes whose statistical properties are periodically time-varying. The presented results proved to be a better description of the SDM behavior and the quantization error. Here with similar arguments but with the LC behavior in mind, a new quantization noise model is established.
A common feature of the existing models is the definition of the quantization error ( )tε as
a difference between the quantizer output and quantizer input signals (see Fig. 7.1). ( ) [ ] ( )*
st y nT i t= −ε (7.1) The quantizer in Fig. 7.1 is treated as a single functional block without taking into account
that it incorporates two functions: quantization in amplitude and quantization in time. In fact, none of the existing models distinguishes the two functions because none of them studies the gain/phase relations in the SDM loop and the conditions for limit cycle oscillations. In most cases the clock impact is studied via a single parameter: the OSR. However, from the LCM developed in Chapter 6, we concluded that the clock added phase rotation has a major impact on the SDM operation.
Fig. 7.1. Block diagram for the standard evaluation of the quantization noise.
1 Here the term “loop cycle” is used as an indicator of the time interval in which the SDM processes one period of the input signal with constant frequency and amplitude.
( )L jω-
( )r tsf
( )i t [ ]sy* nT( )x t
-( )ε t
Sampled binaryquantizer
( )L jω-
( )r tsf
( )i t [ ]sy* nT( )x t
-( )ε t
Sampled binaryquantizer
7.1.1. Quantization noise models 113
Next, several aspects of the SDM LC operation that display the shortcomings of the above models are discussed and illustrated with simulation examples. Then, in Section 7.1.3 a new quantization noise model is developed that incorporates the SDM LC properties in the analytical treatment of the quantization noise.
7.1.2. LC behavior and SDM output spectrum
The insight in the limit cycle behavior of SDMs allows for an improvement of the previously discussed quantization noise models.
As described in Chapter 6, the input signal adds in the loop signal-dependent phase shifts that are dependent on the amplitude of the quantizer input signal at each sampling moment. Within one LC state (from here on we will denote as string the variable time interval in which the SDM operates in one LC state), those phase shifts vary monotonously for a DC input signal and follow a sinusoidal law in case of sinusoidal inputs. As each LC is bounded by some phase boundary, the signal added phase shifts accumulate in the SDM loop for DC inputs and eventually render the active LC instable. For sinusoidal inputs the active LC is rendered instable if for the particular sampling instant the signal added phase shift exceeds the phase boundary of the LC. At the sampling moment at which the active LC becomes instable, a jump occurs to another LC. An example for this behavior is given in Fig. 7.2 for a first order SDM with two possible LCs ( 1LC and 2LC ) driven with a sinusoidal input signal with 20dBFS− amplitude. The output bitstream *[ ]sy nT also switches between two sequences with frequencies 2sf and 4sf , however, the instantaneous variation of the amplitude of ( )i t is not propagated in *[ ]sy nT .
Fig. 7.2. Switching between 1LC and 2LC for a sinusoidal input signal in a first order SDM with an extra loop delay 25% sTτ = ; loop filter output signal ( )i t and output bitstream *[ ]sy nT .
From the LC behavior illustrated in Fig. 7.2, it can be concluded that: • The properties of the input signal are encoded in the output bitstream2 via the
transitions between the possible LCs . Those transitions occur between the strings and lead to the low frequency content in the output bitstream.
2 The statement is valid, as far as the SDM is not in overload.
114 Chapter 7: Performance Evaluation and Optimal Design of SDMs
• Between two transitions the SDM output is in steady state and does not contain actual information about the instantaneous amplitude of the input signal.
• The SDM input signal and the particular SDM properties in terms of 'LCs phase boundaries determine the dynamics of the transitions between the LCs .
As a second example of the LC behavior, two first order SDMs with different LC phase boundaries3 are compared. In Fig. 7.3a the steady state is compared for two different4 extra loop delays: ' and τ τ with ' 2τ τ= .
a) b)
Fig. 7.3. Comparison of two first order SDMs with different extra loop delays ' 2τ τ= a) Evaluation of the possible LCs and their phase boundaries in steady state, b) Spectrum of
the output bitstream [ ]*sy nT for 20dBFS− input amplitude.
3 In Fig. 7.3a, for a better visualization, only the positive part ( 2ρ ) or the negative part ( 1ρ ) of the phase boundaries are shown (see for
example Fig. 7.8 for the complete picture) 4 With the prime sign, the operation with doubled extra loop delay is indicated.
7.1.2. LC behavior and SDM output spectrum 115
The doubling of the extra loop delay leads to a decrease of the phase margin '1 1ρ ρ> for
1LC and increases the phase margin of 2LC such that '2 2ρ ρ< . The extra loop delay has a
linear impact, and because 1 22LC LCf f= the change in the phase margins has the same
relation: ' '1 22ρ ρ= .
In Fig. 7.3 b), the spectrum of the output bitsteam of the two cases is evaluated after transient simulations. From the figure, it can be seen that for the same input signal the change in the phase boundaries of the two LCs results in different LC behavior, such that for the case with less extra loop delay the SDM operates with a dominant 1LC and with the increase of loop delay the 2LC becomes dominant. The dominant operation at one or another LC can be concluded from the spectral bumps at the limit cycle frequencies.
The LC behavior has an impact on the SNRq. In Fig. 7.4 the SNRq with respect to the amplitude of the input signal is compared for a second order SDM with three different extra loop delays. The decrease of the loop delay changes the SDM operation from dominant operation at 2LC to a balanced LC operation when /8, /16s st tτ = . The terms balanced and equilibrium LC operation will be used for the situation when none of the possible LC is dominant. The notation is further discussed in Section 7.1.4. From Fig. 7.4, it can be seen that the change of the LC behavior leads to different SNRq for the same input amplitude. Moreover, the peak SNRq in the balanced case is approximately 7dB better than in the case of dominant 2LC operation.
Fig. 7.4. Comparison of the achievable peak SNRq for a second order SDM for different extra loop delay τ .
The observed LC behavior and the difference in the resulting SNRq, inspire an investigation of the relation between the LC behavior and the quantization noise power that is generated in the signal band. The goal of the following analysis is to describe the actual process of quantization noise generation and to couple it with the particular LC behavior. Such an analysis will allow the definition of an optimal LC behavior and, as a result, the optimal SDM parameterization.
116 Chapter 7: Performance Evaluation and Optimal Design of SDMs
7.1.3. Modified quantization noise model
A starting point for the following analysis is the observation that in idle mode the SDM operates at a single limit cycle and its output is a periodic bitstream that has a discrete spectrum with peaks at the oscillation frequency and its multiples and without quantization noise in the signal band. Thus, in idle mode, the effect of the strong non-linear function and the sampling are incorporated in the limit cycle oscillations and in steady state the quantization error is compensated by the loop mechanism.
A quantization error is introduced in the SDM operation for a busy input. The origin of the quantization error from the limit cycle perspective is easily seen by a comparison with the quantization-error-free ASDMs studied in Chapter 5. In the ASDMs, the variations of the input signal are accommodated in a variation of the instantaneous frequency and the duty-cycle of the limit cycle oscillation. In the sampled SDM, such variations are not possible due to the external clock. As a result a quantization error is introduced.
An insight of the quantization error generation can be gained with the help of Fig. 7.5 where the operation of the binary quantizer is divided in two functions: quantization in amplitude and quantization in time.
In Chapter 6, it has been shown that the non-linear amplitude quantization is incorporated in the loop operation by a signal dependent phase shift (expression (6.15) is repeated here for convenience):
1
,1, sin Qin n
i nLC
VA
χ −= (7.2)
where in (7.2), , /Qin n LCi
V A is the ratio between the instantaneous amplitude of the quantizer
input signal and the amplitude of the active LC. Here has to be pointed out that the angle ,i nχ follows the 1sin− law only for high order filters when the LC steady state waveforms approach sinusoids. The impact of the filter order will be discussed again later in this section.
On the other hand, the sampling in the SDM loop occurs asynchronously to the internal oscillation mechanism and the quantizer amplitude decision is propagated to the output at regular sampling intervals. With the help of the above observations the process of quantization error generation is described next. The new quantization noise model is denoted as LCM for the quantization noise (LCQM).
The first step in the development of the LCQM is in the redefinition of the quantization error in time as sequence ( ).
LCtε This error is transformed into some quantization noise in the
signal band of interest by the loop operation. For an idle mode the difference between *[ ]sy nT and ( )y t (see Fig. 7.5) is a sequence of
pulses ( )LC t∆ with alternating polarity and equal areas of the positive and the negative part of the pulse train (Fig. 7.6). Consequently, the sum of two consecutive pulses in ( )LC t∆ is zero.
The LC oscillations at a particular iLC are characterized by some phase boundary iρ (see Fig. 7.8) that depends on the clock introduced phase delay: , ,s i iiϕ π ζ= − (where iζ is the loop filter phase at LCi
f ), with ,2 /i s i iρ ϕ π≤ ≤ . The ,s iϕ parameter shows the contribution of the clock to the total phase rotation in the SDM loop that is needed for oscillations. In idle mode, the area of the ( )LC t∆ pulses (see Fig. 7.6) is determined by ,s iϕ such that the larger the contribution of ,s iϕ , the bigger the area of the pulses in ( )LC t∆ . For the example illustrated in Fig. 7.8, the contribution ,2sϕ of the clock (in idle mode 2LC is active) to the total loop
7.1.3. Modified quantization noise model 117
delay is 22 −π ζ . For 1LC the clock added phase shift is almost 90 and in idle mode will result in an almost half clock period duration of the positive part of the pulses in ( )LC t∆ . However, in idle mode the sum of two consecutive pulses in ( )LC t∆ is zero.
Fig. 7.5. Block diagram of the modified quantization error model (LCQM).
In Fig. 7.5, the signal ( )LC tε is constructed from the difference signal ( )LC t∆ by a gated integration in time that starts from a zero crossing moment zct of the signal ( )i t and lasts for one period of the active iLC , such that the integration boundary is { , }zc zc i st t t N T∈ + . For idle SDM operation, the positive and the negative pulses in ( )LC t∆ are identical and as a result ( ) 0LC tε = (see Fig. 7.6).
Fig. 7.6. Idle mode signal waveforms in a first order SDM and the construction of the ( ) and ( )LC LCt tε∆ sequences.
( )L jω ZOH-
( )r tsf
( )i t [ ]sy* nT( )x t ( )y t
+( )LC t∆ ε ( )LC t
zc i s
zc
t N T
t
+
∫
Sampled binary quantizer
+-
( )L jω ZOH-
( )r tsf
( )i t [ ]sy* nT( )x t ( )y t
+( )LC t∆ ε ( )LC t
zc i s
zc
t N T
t
+
∫
Sampled binary quantizer
+-
118 Chapter 7: Performance Evaluation and Optimal Design of SDMs
Next, it is shown that the sequence ( )LC tε characterizes the quantization error that is introduced in the SDM operation for busy inputs.
When the SDM is driven with an input signal, the amplitude change of ( )i t results in a signal dependent phase shift (7.2) that is added to the quantizer output signal '( )y t (see Fig. 7.7). As a result of this phase shift, the area of the positive and the negative pulses in
( )LC t∆ changes with respect to the area in idle mode and accommodates the impact of the input signal. On the other hand, the output signal *[ ]sy nT does not change instantaneously but only when the string changes. The gated integration of ( )LC t∆ gives as a result a pulse train ( )LC tε that corresponds to the amount of signal change that is not seen by the output and consequently represents the quantization error that is introduced by the sampling mechanism. Two important observations have to be pointed out:
As long as the SDM limit cycle state is not changed, the signal change is not incorporated
in the output bitstream and a quantization error is introduced. The quantization error sequence ( )LC tε represents the part of '( )y t that is not seen by the
feedback loop and is thus responsible for the quantization noise in the band of interest.
Fig. 7.7. DC input driven signal waveforms in a first order SDM and the construction of the ( ) and ( )LC LCt tε∆ sequences.
The gated integrator that is used for the definition of ( )LC tε removes from the quantization error signal ( )LC tε the spectral content at the LC frequencies ,LC inf and their multiples. As a result only the signal dependent quantization noise component is evaluated.
The LCQM described in Fig. 7.5 is based on the new insights in SDM operation
(described in Chapter 6) and incorporates much better than all previous models the non-linear, sampled data nature of the SDMs. By describing the effect of the sampled binary quantizer with two functional blocks: amplitude and time quantization; the LCQM is able to determine the actual process of quantization error generation and to give a measure for the dependence
7.1.3. Modified quantization noise model 119
of the quantization noise on the properties of the SDM implementation. This measure is used further in this chapter for the definition of an optimal SDM parameterization. Firstly, however, several SDM properties that LCQM clarifies are elaborated.
When we further speak about the instantaneous magnitude of the quantization error, we
will refer to the area of the pulses in ( )LC tε . In contrast to ( )LC t∆ , the maximum area of the pulses in ( )LC tε does not depend on the clock added phase delay but on the phase boundary of the particular LC.
Fig. 7.8. Graphical description of the LCM of the SDM operation (from Chapter 6).
The phase boundary iρ is an indicator of the largest possible instantaneous deviation of the loop phase rotation from the steady state value (see Fig. 7.8), due to the input signal. The particular iLC is still stable and active until the input signal adds sufficient phase shift such that iρ is exceeded. When the phase boundary of the active iLC is exceeded, the system enters another LC with a jump shift in phase. The phase jump reverses the polarity of the quantization error pulses in ( )LC tε (see Fig. 7.7).
An immediate conclusion from the developed quantization model is that the maximum area of the quantization error pulses in ( )LC tε depends on the particular limit cycle state and in particular on its phase boundary iρ
5 . The phase boundary determines the maximum instantaneous input amplitude that the particular LC can handle, and as the quantization error increases with the increase of the amplitude of the input signal, iρ also determines the maximum quantization error that is generated for a particular limit cycle. For the same input signal, the larger the iρ , the longer is the possible duration of the LC strings.
5 Actually, we use here a frequency/time model, where the “frequency” in Fig. 7.8 is defined for each period between two phase changes.
For the following simulations, done completely in time domain, this has no impact.
( )L jω( )1
−N A
ϕs,2
2sf
4sf6
sfλ3
ρ1 ρ1
ρ 2 ρ 2
0
1ς
120 Chapter 7: Performance Evaluation and Optimal Design of SDMs
The maximal quantization error that the SDM can make per limit cycle i is than defined
as:
( ) [ ] ( )( )* ',max,
0 0
i s i sT T
LC i LC s t dt y nT y t dtκ κ
ε = ∆ = −∫ ∫ (7.3)
where in (7.3), '( )y t is the output of the quantizer in busy mode, i i iNκ ρ π= is a scaling
factor that normalizes the phase boundaries iρ to the maximally possible clock added phase rotation for the respective LC and as before 2, 4, 6...iN = The normalization factors iκ come from the observation that ( )LC tε is evaluated in at least one period of the 1LC (in 2 clock periods) and in more clock periods for lower LCs. According to this definition, 1 1=κ corresponds to the maximum possible error for 1LC . When lower sub-harmonic LCs are possible, they have some phase boundary iρ and a respective normalized area factor iκ .
With the underlying LC behavior in mind, the following observations about the
quantization error can be pointed out: • The quantization error is generated at each sampling moment and depends not only
on the amplitude and the frequency of the input signal but also on the instantaneous LC state of the SDM loop for this particular input signal and sampling instance.
• The quantization error is proportional to the phase boundary because the bigger the phase boundary, the larger the instantaneous error that can be introduced.
• The impact of the clock on the formation of the LC oscillations decreases with the decrease of the frequency of the LC. That means that the relative quantization error per limit cycle decreases with the decrease of the LC frequency.
• In the typical case evaluated in Fig. 7.8, the maximal quantization error that is introduced when the SDM operates at the lower frequency sub-harmonic LCs, due to its smaller phase boundary, is smaller than the maximal quantization error introduced by operation at 1LC .
The generation of the quantization error and the LC behavior are dependent on the amplitude of the input signal, the order of the loop filter and the extra loop delay. With the increase of the order of the loop filter the quantizer input waveform changes from triangular (in case of first order ideal integrator) to almost purely sinusoidal for higher order filters. In the extreme first order case, the input-signal dependent phase shift has a linear dependence on the ratio , /Qin n LCi
V A :
,, =
Qin ni n
LCi
VA
χ (7.4)
In Fig. 7.9 expressions (7.2) and (7.4) are compared with respect to the variations of the
instantaneous amplitude of the quantizer input signal for the first two sub-harmonic LCs.
7.1.3. Modified quantization noise model 121
Fig. 7.9. Comparison between the dependence of the signal added phase rotation for first order and higher order loop filters.
From Fig. 7.9, it can be concluded that higher order loop filters achieve a better phase resolution when the SDM operates at 1LC . Respectively, the application of higher order filters results in a higher resolution in time.
In Chapter 6 and Fig. 7.8, it is shown that the SDM operation at each particular sub-harmonic limit cycle is bounded by some phase boundary dependent on the modulator implementation. For lower frequency sub-harmonic limit cycles, the phase boundary is typically much smaller than that for the first sub-harmonic limit cycle. That means that for a fixed observation time of operation (for example 1 period of the low frequency input signal) the SDM operates predominantly on the LC with the largest phase boundary and thus typically on the first sub-harmonic LC.
With the variation of the input amplitude, the LC behavior also varies. However, the quantization noise power in the lower frequency signal band does not vary significantly, such that the higher signal amplitude typically6 leads to higher SNRq. In the next section, the relation between a particular LC behavior and the achievable performance is further investigated.
7.1.4. Quantization noise power
More insight in the consequences of working at a particular limit cycle can be acquired after the evaluation of the quantization noise power NP within frequency bandwidth B.
The quantization noise spectrum and its power are traditionally [36] evaluated with the help of the quantization noise models discussed in 7.1.1. Here, the evaluation is extended with the help of the new LCQM from Section 7.1.3. The quantization noise power spectrum density (noise spectrum) that is evaluated with the help of the LCQM is denoted as ( )LC fϖ .
The analytical evaluation of the SDM output bitstream is significantly complicated by the variable time duration of the strings from which it is composed. The LCQM led to the
6 The monotonic increase of the SNR is not the only possibility. A typical example for an “oscillatory” behavior is the first order SDM which is very sensitive for the instantaneous amplitude of the signal in front of the quantizer such that the SNR can drop for a higher input signal due to a jump change of the limit cycle behavior.
122 Chapter 7: Performance Evaluation and Optimal Design of SDMs
representation of the quantization error ( )LC tε as a sequence that changes its frequency at each change of the LC state of the modulator. The error ( )LC tε follows the changes in the SDM output signal and also has a variable frequency. The properties of ( )LC tε can be investigated if we make use of the fact [31] that time-limited periodic signals are Fourier transformable. Let us take as an example the error sequence ( )LC tε of an SDM with two possible LCs ( 2)j = and observe it for an arbitrary time interval 1 2T T T= + for which is defined:
1 1
1 2 2
2 1
t {0, T } operation at LCt {T , T } operation at LCt=T switching to LC
∈∈ (7.5)
Then for the time interval T, ( )LC t,Tε is expressed as a summation of two consecutive in
time sequences that correspond to the two possible LCs: ( ) ( ) ( )
1 2LC LC 1 LC 2 t,T t,T t,T= +ε ε ε (7.6) As each sequence in (7.6) is defined in a given time interval, it is Fourier transformable:
( ) ( )
( ) ( )
1
1 1
2
2 2
2
2
,
,
LC
LC
j f tLC 1 LC 1
j f tLC 2 LC 2
t,T E f T e df
t,T E f T e df
∞
−∞
∞
−∞
=
=
∫
∫
π
π
ε
ε (7.7)
The power spectral densities can be established from the Parceval’s theorem:
( ) ( ) ( )2
0 0
,, ,
T
T
E f T1 t T dt df f T df2T T
ε ϖ∞ ∞
−
= =∫ ∫ ∫ , as:
( )
( )
( )( )
1
1
2
2
2
11
12
22
2
,
,
LCLC
LCLC
E f Tf,T
T
E f Tf,T
T
=
=
ϖ
ϖ
(7.8)
In order to establish the spectral density ( )
LCfϖ of the complete output signal with infinite
duration, the duration of operation at each LC can be averaged in accordance with the probability of occurrence of each LC string. Let the probability for generation of
1( )
LC tε be p ,
and for 2( )
LC tε be 1-p [31]. Then from (7.6) and (7.8), ( )LC fϖ is represented as:
( ) ( ) ( )( )
1 21LC LC LCf f p f p= + −ϖ ϖ ϖ (7.9)
7.1.1. Quantization noise power 123
Expression (7.9) enables the estimation of the total output spectrum from known spectra of the individual strings. However, the variable time duration of the strings still prevents the exact calculation. The changes in the LC state and the time duration of the strings are governed by the amplitude and the frequency of the input signal and the phase boundaries of the possible LCs. The evaluation of the quantization noise power in the signal band requires a description of the switching between the LCs. Several important characteristics of the switching behavior have to be pointed out:
• The SDM operation within a certain string is deterministic and from some known initial conditions, loop filter characteristics and input signal properties, the SDM output bitstream can be established.
• The switching between the strings is strongly dependent on the amplitude of the input signal, such that for small7 input signals the variations of the time duration of the strings is also small. Then the SDM behavior can be described as almost periodic or very slowly varying. This situation, however, is of a less practical importance because it also means that the rate of switching between the strings is very low and the SDM cannot process the input signal. Examples of this behavior were given in Chapter 6 and further elaborated in Section 7.2.
• The increase of the amplitude of the input signal intensifies the switching between the LCs. As the switching is accompanied by time varying phase jumps, it leads to different initial conditions, in terms of phase and amplitude, for each consecutive string. The different initial conditions result in aperiodicity of the output bitstream and randomize the duration of the strings. Thus for the operational DR, the switching between the LCs can be approximated with a random process, despite the deterministic behavior within each LC.
The area of the pulses in ( )LC tε varies in time and corresponds to the magnitude of the
instantaneous quantization error and is determined by the instantaneous value of the input signal and the phase boundary of the active LC. The maximum area of the pulses in ( )LCi
tε is proportional to iρ . It is well known that the spectrum of a pulse sequence can be broken into a component that contains the information about the pulse shape and a component that contains information about the area of each pulse and the periodicity. The evaluation of
( )LC
E f is simplified by making the following assumptions: • The area ,n iA of the error pulses in ( )LC tε is a random quantity and is uniformly
divided between 0 and i sTκ , where as before i is the order of the limit cycle and n is the sampling moment. The area scaling factor iκ incorporates the dependence of the area ,n iA on the properties of the particular LC and respectively on the properties of the SDM loop.
• The assumption for randomness of ,n iA is not fulfilled for DC and input signals harmonically related with sf . However, those are special cases for which ( )
LC tε is
deterministic and the following analysis can be applied without restrictions. • The exact shape of the error pulses is irrelevant, only the area is relevant. This
simplification is justified as long as the bandwidth of interest is small relative to the average repetition rate of the error pulses. From the perspective of the LCM of the SDM operation the shape of the pulses can be ignored as for most practical cases the frequency of the lowest possible LC should exceed significantly the Nyquist frequency of the converted bandwidth.
7 The “small” signal can be quantified for a particular loop filter order.
124 Chapter 7: Performance Evaluation and Optimal Design of SDMs
With the above assumptions, the quantization noise sequence ( )
LC t,Tε , given in (7.6) is
represented as two sequences of pulses generated in different LCs.
( ) ( ) ( )1 2
1
,1 1 ,2 20
R R
LC n s n sn n R
t,T A t nN T A t nN T= =
= − + −∑ ∑ε δ δ (7.10)
where in (7.10) 1,2R is the number of pulses in each sequence. In turn, from (7.10) and in
analogy to [2] and [3]:
( ) ( ) ( )22 2
,
2, , 2
3i
i i i
LC i sLC i LC i LC n i
f Tf T E f T f A
κϖ = = = (7.11)
From (7.9) and (7.11) the single-sided quantization noise spectrum, when two limit cycles
are possible in the loop, is evaluated as:
( ) ( ) ( ) ( )2 2
1 2
1 2
2 21
3 3s s
LCs s
T Tf p p
N T N Tκ κ
ϖ = + − (7.12)
After simplification with 1 22, 4N N= = , expression (7.12) is evaluated as:
( ) ( )( )2 21 2
1 2 16LC
s
f p pf
ϖ κ κ= + − (7.13)
Expression (7.13) can be used for the establishment of the optimal LC behavior if we take
into account that the probabilities for occurrence of each LC are proportional to the respective normalized area factors iκ :
1 1
2 21 2p
p= =
−κ ρκ ρ
(7.14)
then expression (7.13) is given in the form:
( ) ( )3 3
1 22 2
1 2
44 43 2 3LC
s s
f ff f
ρ ρϖ ρπ ρ ρ π
+= = +
(7.15)
From (7.15) an optimal ratio between the phase boundaries can be established that leads to
a minimization of the generated quantization noise power in the output bitstream. The optimal values for 1 2 and ρ ρ are evaluated graphically in Fig. 7.10 for a different combined phase boundary 1 2comb = +ρ ρ ρ .
From Fig. 7.10 it can be concluded that the phase boundaries of the limit cycles can be chosen such that the generated quantization noise is minimized by finding the minimum of the function ( )f ρ . Different minima for ( )f ρ and respectively for ( )LC fϖ can be found for different numbers of limit cycles and loop filter parameterization.
7.1.1. Quantization noise power 125
Fig. 7.10. Evaluation of the optimal phase boundaries in the presence of two limit cycles.
The possibility for an optimal relation between iρ can be used for the parameterization of the loop filter, such that the optimal phase boundaries are implemented. For a filter
Re[ ] Im[ ]L(f) L(f) j L(f)= + , the required filter parameterization is determined from the required filter phase characteristics for the established optimal LC phase boundaries. From Fig. 7.10
1 3 8optρ π≈ , as:
11
12
Im[ ]3 52tan8 8Re[ ]
2
Im[ ]74tan
8 8Re[ ]4
s
s
s
s
fL
fL
fL
fL
ππ πς π
π
ππ πς π
π
−
−
= = − + = −
= = − + = −
(7.16)
For the above example when only two LCs are possible, the phase of the optimal linear
part (filter and loop delay) for 2sf and 4sf is given by (7.16). From (7.15) the quantization noise power is calculated for bandwidth B, for a particular
loop filter ( )L f , as follows:
( )( ) ( )
3 31 2
2 221 20 0
42 4 23 21 1
B B
NLC LCs
P f df dffL f L f
ρ ρϖπ ρ ρ
+= = ++ + ∫ ∫
(7.17)
126 Chapter 7: Performance Evaluation and Optimal Design of SDMs
The calculation of (7.17) has to be performed after the evaluation of the possible LCs and their respective phase boundaries.
The dependency of the quantization noise from the SDM limit cycle behavior is used next for the definition of the optimal parameterization of SDMs.
7.2. Optimal SDM parameterization
The insights in the SDM LC behavior and the new quantization noise model allow for a refinement of the SDM design space. For an optimal SDM operation, the trade-off: performance – cost of the implementation is resolved by implementing a specific LC behavior. In order to illustrate the possible alternatives for SDM design optimization, firstly the most important design choices are discussed, and then three typical design cases are compared.
Later in this section the LCM of the SDM operation is used for the definition of design procedures for optimal parameterization of single bit SDMs.
A SDM that achieves a target SNR for minimal power consumption is defined as optimal. This notation can be extended to a multi-mode SDM that has to cover several conversion
bandwidths with different resolutions such that a local optimal operation is achieved with the resources and control means that are defined on a multi-mode level.
The proposed design approaches can also be extended to multi-bit and cascaded converters.
7.2.1. Design space definition
The concept for an optimal parameterization is treated in a design space defined by: • The clock frequency sf ; • The loop filter order and coefficients ; • Intended and parasitic loop delays; • Robustness of the desired LC operation over the PVT corners.
Next, the basic trade-offs that have to be resolved for the above design space are discussed.
Choice of sampling clock speed
The choice of the speed of the sampling clock is determined by the following set of factors and trade-offs:
• A faster sampling clock allows for a higher SDM performance in terms of SNR and DR. However, the faster sampling clock does not directly improve the SNR because the SDM design is becoming much more prone to entering lower frequency sub-harmonic limit cycles due to the higher relative impact of the clock and the extra loop delays on the SDM operation.
• A faster clock increases the power consumption of the analog and the digital part of the ADC. The power consumption of the analog components increases because of the increase of the required bandwidth of operation of the operational amplifiers and the required faster decision time of the comparator.
• The power consumption of the decimator also increases for faster clocks. The main factors that determine the power increase in the decimator are the longer decimation chain that is required for the achievement of the same conversion
7.2. Optimal SDM parameterization 127
bandwidth and the larger digital word and number of operations that are required for the same function.
Here, it has to be pointed out that while the power consumption of the digital circuits tends to decrease with the technology scaling, for the analog circuits the trend is opposite. The power consumption of the analog portion of the ADCs increases with the downscaling of the technology due to the required lower circuit noise levels for the realization of the same SNR with the decreased signal range in the lower supply voltage technologies.
The above factors advocate for a sampling clock speed that is as low as possible for the particular application and desired SNR.
Choice of loop filter order
With a chosen clock speed, the achievable SDM performance remains a function of the loop filter order and parameterization. An inherent issue in the utilization of a higher order loop filter is the stability of the desired SDM mode of operation. From the LCM perspective such an issue is resolved by the evaluation of the possible sub-harmonic LCs.
The LCM can significantly facilitate the design of stable higher order SDMs because it offers a simple method for evaluation of the possible low frequency sub-harmonic LCs. However, a major challenge that remains in the implementation of SDMs with a higher order filters is their robustness in the PVT corners. The requirement for robustness of the implementation limits the practical increase of the SNR through realization of higher order filters to a boundary where sufficient immunity towards the changes in the environmental and operational conditions can be guaranteed. As a result, the realization of higher order loop filters increases the cost of the design and might be only possible with appropriate calibration algorithms.
The possibility to realize a specific LC behavior can be used as an additional degree of
freedom for the definition of the optimal SDM implementation for a particular application. Next, the impact of the particular limit cycle behavior is studied in more detail.
7.2.2. Choice of SDM LC behavior
In order to illustrate the notion, three typical design parameterization cases are compared next.
• Case 1: SDM operating with a low clock frequency and parameterized for optimal LC behavior and maximal performance.
• Case 2: SDM operating with a high clock frequency and parameterized to operate predominantly at lower frequency sub-harmonic LCs.
• Case 3: SDM operating with a high clock frequency and parameterized for optimal LC behavior and maximal performance.
The advantages and disadvantages of each type of operation are compared in Table 7.1. . The simulation results given in the table are based on the test bench described in Section 6.4.1.
Table 7.1. illustrates several important trade-offs in the SDM parameterization:
• The achievable SNRq strongly depends on the LC behavior of the SDM. The introduction of lower frequency sub-harmonic LCs, or the creation of a dominant LC leads to a decrease of the SNRq. That is why the achievable SNRq for a certain clock frequency and filter order can be seen as a range (Case2 from Table 7.1. ) such that the exact SNRq value depends on the implemented LC behavior. The
128 Chapter 7: Performance Evaluation and Optimal Design of SDMs
maximum SNRq is achieved when the SDM operates with an optimal LC behavior (in equilibrium) as evaluated in 7.1.4.
• The equilibrium operation results in the highest possible SNRq, however, it can lead to an expensive design in terms of area, power consumption or robustness. The total SDM area is to a large extent determined by the capacitors area and scales down with the increase of the clock frequency. However, as already discussed, the higher clock speed requires higher power consumption and decreases the robustness of the design to parasitics. In that respect, the realization of a specific LC behavior allows for the best trade-off for given application requirements. Those factors are further qualified in Chapter 10 with particular design examples.
Table 7.1. Comparison of three design cases of a second order SDM
• The possible increase of distortion is due to the larger signal swings that are accompanying the lower frequency sub-harmonic LC. The increased amplitude of the low frequency LCs may lead to clipping that in turn causes distortion. Together with the decrease of the SNRq, the possibility for clipping limits the introduction of lower LC to the first few. The exact number of LCs that is allowed without degradation of the distortion performance is determined by the OSR and the linear range of the building blocks.
In Fig. 7.11, the second order SDM as defined in the test case from Chapter 6, is evaluated
for three different frequency positions of the zero in the loop filter. From the figure, it can be concluded that the position of the zero changes the LC behavior from a dominant 1LC for low frequency zero, to multiple LCs for a high frequency zero. For 6 8zω e= rad/sec the system is close to the optimal behavior, estimated in Section 7.1.4.
8 In Case 2, the SNRq is shown as a range in order to indicate that in fact the SNRq varies with the choice of the dominant LC.
Case 1 Case 2 Case 3 Clock frequency, sf [MHz] 125 1000 1000 Possible limit cycles 2sf , 4sf 2sf , 4sf , 6sf 2sf , 4sf Dominant limit cycle equilibrium 4sf or 6sf equilibrium Signal bandwidth [MHz] 5 5 5 Simulated SNRq [dB] 47 65-818 81 Distortion Low Possible increase Low Robustness High High Low Power Consumption Low Low High Area Large Small Small
7.2. Optimal SDM parameterization 129
Fig. 7.11. Impact of the zero position on the LC behavior in second order SDM.
In Fig. 7.12, the same three loop filter parameterizations are evaluated with transient simulations. The number of transitions for a fixed time interval is established. Fig. 7.12 illustrates several important dependences that result from the particular LC behavior.
Fig. 7.12. Comparison of the number of transitions for a fixed time interval of 1µs in second order SDM with respect to the zero position in the loop filter.
From Fig. 7.12, it can be seen that the number of transition in the SDM loop depends on the implemented LC behavior. When the number of transitions is high, ( 1 8zω e= , see
3 8zω e= 6 8zω e= 1 9zω e=
130 Chapter 7: Performance Evaluation and Optimal Design of SDMs
Fig. 7.12), the SDM operates predominantly on 1LC and the achievable SNRq is very low. In the figure it can be seen that for 6 8zω e= and 1 9zω e= the number of transitions varies very little with the increase of the amplitude of the input signal. When 6 8zω e= the number of transitions is approximately 375 and indicates that almost equal number of transitions has been made on 1LC and 2LC . As discussed in Section 7.1.4 such an operation results in the highest SNRq. The corresponding output spectra are shown in Fig. 7.13.
a) b) c)
Fig. 7.13. SDM output spectrum for 20dBFS− input signal and: a) dominant 1LC with 3 8zω e= , b) equilibrium with 6 8zω e= , c) dominant 3LC with 1 9zω e= and additional
4sτ t /= .
The expected SNR for each zero position is confirmed with the evaluation of the output spectrum after transient simulations (see Fig. 7.14).
Fig. 7.14. Comparison of the achievable DR in second order SDM with respect to the zero position in the loop filter.
In Fig. 7.15 the number of transitions in the output signal of an SDM with equilibrium LC behavior is evaluated for DC, single tone and band limit white noise (BLWM) as input
7.2. Optimal SDM parameterization 131
signals. The amplitude or the noise power is varied to cover the whole dynamic range of the SDM. From the simulation, it can be seen that in the operational dynamic range, the SDM displays very similar LC behavior for different types of input signals.
Fig. 7.15. Comparison of the achievable DR in second order SDM with respect to the zero position in the loop filter.
In the next section two design procedures for an optimal SDM parameterization are discussed that are based the following approaches:
• The first design procedure strives to achieve the optimal utilization (maximal SNRq) of the available power budget. Such a design approach aims the realization of Cases 1 and 3 from Table 7.1. .
• The second design procedure aims the optimization of the power consumption for a minimally required SNR. This design approach aims the realization of Case 2 from Table 7.1. .
Both procedures use the LCM of the SDM operation and the analytical prediction for the achievable SNR discussed in Section 7.1.
132 Chapter 7: Performance Evaluation and Optimal Design of SDMs
7.2.3. Functional level optimization for maximum performance
With the help of the limit cycle model for the quantization noise, the maximum achievable SDM performance in terms of SNRq for a chosen order of the loop filter can be implemented via an optimization of the SDM limit cycle behavior. The optimization discussed in this section is on a functional level as it discusses only the SDM performance with respect to the quantization noise and not with respect to the limitations of the building blocks.
Fig. 7.16. Algorithm I for an optimal design parameterization based on the LC properties of the SDM.
Initial selection of filter
order
Initial filter
parameterization
1Eval. of LC beh. due
to SDM loop filter
Optimization of filter
coefficients
2Eval. of LC beh. due to the SDM
imple-mentation
Higher order loop filter
3Eval. of LC beh.
over PVT
Optimization of filter
coefficients
4Eval. of LC beh. after extraction
Optimization of filter
coefficients
Design implementation
Initial conditions:BW, SNRq,min, fs
Calibration
AC analysis
AC analysis
AC analysis
AC analysis
7.2.3. Functional level optimization for maximum performance 133
The optimization takes into account a given clock speed and signal bandwidth, known extra loop delays, a realistic parasitic evaluation, and the variations in the processing and the environmental conditions.
In Section 7.1.4, it was suggested that the loop filter parameterization that achieves a balanced limit cycle operation results in a maximal SDM performance. The balanced LC operation typically aims only two possible limit cycles: the first two sub-harmonic modes of operation. However, for high OSRs, the possibility to implement also lower frequency LCs has to be explored, because that adds an extra degree of freedom in the design process and can lead to a further improvement of the performance. The exact number of limit cycles that can be used in a particular design and in the optimization algorithm in Fig. 7.16, depends on the specific requirements of the application and on the available hardware resources.
It is very important to point out that the SDM limit cycle behavior has to be guaranteed over the PVT corners and after the introduction of the imperfections of the layout.
Here a design procedure is proposed and described with the block diagram in Fig. 7.16. The flowchart is explained next. The designer can make an initial choice for the loop filter order, for a given clock frequency with the help of the analytical prediction of the SNRq as described in Section 7.1.4. Then the filter coefficients are optimized for a maximal SNRq via an evaluation of the limit cycle behavior with AC simulations.
In decision 1, the simulated LC behavior is compared with the desired optimal LC behavior and the need for adjustment of the initial filter order and parameterization is determined.
In decision 2 from Fig. 7.16, the extra loop delay that is introduced from the particular SDM implementation has to be evaluated. In case that the extra loop delay changes unacceptably the LC behavior (lower sub-harmonic LC are introduced, or the phase boundaries for the high frequency LCs are too much decreased) an optimization of the loop filter coefficients is required. If the extra loop delay cannot be compensated with an adjustment of the coefficients and lower limit cycles are unavoidable, a modification of the loop filter characteristic is required. The modification can be done via an adjustment of the filter coefficients, phase corrections with zeros of the loop filter characteristic or an increase of the order of the loop filter. In most applications which require a high frequency sampling clock, the extra loop delays have to be carefully controlled in order to achieve the desired performance. As demonstrated in Chapter 10, the compensation of the impact of the extra loop delay on the LC behavior and on the SDM performance, requires an increase of the overall power consumption.
In decision 3 from Fig. 7.16, the LC behavior of the transistor implementation is evaluated in the PVT corners. Again, the evaluation is used for the determination of the required coefficient change for a balanced LC operation.
In decision 4 from Fig. 7.16, the need for a final coefficient change is established with evaluation of the SDM LC behavior after the introductions of the impact of parasitics, after their extraction from the layout.
In case that the variation of the LC behavior over the process corners is significant and the robustness of the design can be guaranteed only with an increase of the filter order or/and the circuit power consumption, it might be more efficient to calibrate the filter coefficients. The need for calibration and its properties in terms of range and resolution can be deduces from the evaluation of the LC behavior as discussed above.
134 Chapter 7: Performance Evaluation and Optimal Design of SDMs
7.2.4. Optimization of the SDM power efficiency
Here a possible extension of the optimization algorithm from Section 7.2.3 is described. The additional design steps that are suggested, aim the realization of a maximally power and area efficient SDM implementation.
An initial assumption is that the SDM design is already optimized with Algorithm I from Section 7.2.3 such that the SDM achieves the maximal performance for the chosen loop filter order (point 1 from Fig. 7.17). At the same time if the particular application has lower specifications, given as q,minSNR and indicated with point 2 from Fig. 7.17, the realization of the maximum performance might introduce overkill in the design and extra costs.
Fig. 7.17. Example for an optimization case, point 1 is a result of Algorithm I, point 2 indicates the desired q,minSNR
The key relation that is used here for power optimization is based on the observation that when the SDM operates with dominant lower frequency LCs, it requires less power. The decrease of the power consumption is due to the decreased power requirements for the building blocks and the higher immunity to loop delays.
Thus by decreasing the power consumption of the building blocks, the LC behavior can be changed. As the change from balanced situation also leads to a decrease of the performance, the allowed degradation can be qualified by a parameter SNRq∆ where:
q,min SNRq SNRq - SNR > ∆ (7.18)
A possible approach for the improvement of the SDM power efficiency is described with
the optimization procedure given in the block diagram in Fig. 7.18. The goal of the proposed optimization is to use the margin SNRq∆ in order to trade-off performance for power consumption via the realization of a specific LC behavior.
In the second optimization algorithm from Fig. 7.18, a decision (1) is introduced that compares the achievable qSNR with the desired q,minSNR , and in case of sufficient margin SNRq∆ , optimizes the power consumption by the introduction of a lower sub-harmonic LC in the
OSR
SNR
[dB]
6L =
5L = 4L = 3L =
2L =
1L =
7L =
8L =
} SNRq∆1
2
7.2.4. Optimization of the SDM power efficiency 135
SDM implementation. The application of Algorithm II is illustrated in Chapter 10 with a design example.
Fig. 7.18. Algorithm II for optimization of SDM power efficiency.
7.3. Conclusions
A new limit cycle model for the quantization error in the SDM operation was proposed. It identifies the quantization noise power as strongly dependent on the SDM LC behavior. Based on the new quantization noise model, the quantization noise power is analyzed and the optimal SDMs parameterization is defined and illustrated with examples. Two optimization procedures that aim respectively, a maximal SDM performance or maximal power efficiency, are described. The expected behavior and performance are confirmed with simulations.
136
8. Chapter 8
Analysis and design of high performance transconductors
This chapter studies the trade-offs in the design of high performance transconductors. The linearization of the transconductor input-output characteristic is treated in detail. The proposed harmonic compensation method is identified as a powerful approach for linearization. The basic analysis of the transconductor circuits is formalized via an introduction of a normalized analytical description of the transconductor operation. A novel circuit solution is described that uses a combination of local resistive feedback and cross-coupling. In this way, it achieves significant, simultaneous suppression of the third and the fifth harmonic components in the transconductor output current. The new circuit is compared with several well known topologies via static and dynamic simulations.
8.1. Problem definition
Transconductors or voltage-to-current converters (V-I converters) are basic building blocks in many analog transistor circuits that appear in a wide range of applications. They are extensively used in continuous time sigma-delta converters for the construction of continuous time (CT) Gm-C filters. Very often, low-noise and very low-distortion are required from the transconductor implementation. For the booming mobile applications, the low current consumption of the implementation has also become a major requirement. A typical example for a transconductor stage with very high specifications is the input stage of continuous time SDMs. There are several reasons for those high specifications:
• In Fig. 8.1 the position of the V-I converted in the SDM loop is illustrated. Typically it integrates the difference INTI between the feed forward current that is proportional to the applied input voltage (here outI is chosen as notation to identify the feed forward current as the output current of the V-I converter) and the feedback current that is produced by the DAC: DACI . The input V-I converter is outside the SD loop and its errors are not suppressed by the loop mechanism. That means that it has to achieve a better performance than the rest of the functional blocks of the SDM system. The simplest transconductor implementation is often just a resistor connected to the virtual ground node of an operational amplifier.
• The input V-I converter also determines to a major extent the achievable SNR of the SDM because all other noise sources in the system contribute after some amplification of the signal has taken place and as a result have a minor impact.
In the context of A/D conversion, a major requirement towards the V-I converter is a maximal linear input dynamic range for the predetermined converter accuracy. The transconductors show a linear relationship between a certain minimum and maximum
138 Chapter 8: Analysis and design of high performance transconductors
input voltage and a minimum and maximum output current. The transconductance is ideally constant between those limits. A first approximation to this characteristic is shown by a simple differential pair (SP) constructed with bipolar or MOS transistors Fig. 8.2a). Because of its differential character, even order harmonics are significantly suppressed, however, it is subject to severe harmonic distortion from odd harmonics in the output current. Numerous circuit implementations that battle that problem have been proposed in literature. The most popular techniques use source degeneration (done via resistors or transistors), multiple differential pairs (connected in series or cross-coupled), or adaptive biasing; some examples are presented in [39], [40], [41], [42], and [43]. With the technology scaling and the increased performance requirements, the proposed solutions also become more complex. Some of the recent state of the art implementations already use a combination of linearization techniques. For example, in [44] and [45] adaptive biasing is combined with source degeneration in order to achieve a Total Harmonic Distortion (THD) better than -75dB. In [46] and [47] comparable results are obtained via resistive degeneration and local negative feedback for the input signal. In order to understand the reasons for the improved performance of the combined techniques, the linearization mechanism is studied in detail.
Fig. 8.1. Input V-I converter position in the SDM loop.
8.2. Linearization of the transconductor function
The operation of the V-I converter is described by the function: ( )o ii f v= , where
iv and oi are, respectively, the applied differential input voltage and the differential output current. For a differential circuit in equilibrium, (symmetric biasing and no excitation signal) the function ( )if v reduces to a multiplication with a constant: the static transconductance value gm0. The transconductor circuit is approximately linear for a certain input voltage range iv∆ , if for that range, the dynamic transconductance gm remains very close to the equilibrium value gm0. The influence of the circuit parameters on the linearity of the transconductor can be investigated via a Taylor series expansion of the ( )o ii f v= function in the equilibrium point. For a fully symmetrical differential circuit, the expansion is given in the form:
3 5 71 3 5 7( ) ( ) ( ) ( ) ( )o i i i ii t v t v t v t v t HOTα α α α= + + + + (8.1)
-
DAC
V-I1 IntegrationoutIinV DACI
SDM loop
INTI-
DAC
V-I1 IntegrationoutIinV DACI
SDM loop
INTI
8.2. Linearization of the transconductor function 139
where the iα parameters are determined by the particular circuit implementation and HOT stands for the higher order terms in the equation. For an input signal ( ) cosi mv t v tµ= and after regrouping of the frequency terms, equation (8.1) is
rewritten as:
( )3 5 7
3 5 71
5 7 75 7 7
16 20 21( ) cos cos364
4 7 cos5 cos 764 64
m m mo m
m m m
v v vi t v HOT t HOT t
v v vHOT t HOT t HOT
α α αα µ µ
α α αµ µ
+ += + + + +
+
+ + + + +
(8.2)
Fig. 8.2. Basic transconductor topologies: a) Simple differential pair (SP), b) Resistor degenerated differential pair (RDP), c) Cross-coupled differential pairs, (CCP), d)
Resistor degenerated cross-coupled differential pairs (RCCP).
From (8.2), it becomes evident that every new term in the Taylor series expansion is refining the description of the harmonics in the input-output function. The linearity of the circuit can be very much improved when the harmonic content of (8.2) is
140 Chapter 8: Analysis and design of high performance transconductors
significantly suppressed. For example, a simultaneous minimization of the parameters 3α and 5α in (8.1) leads to a major suppression of the third harmonic and a
simultaneous minimization of the fifth. The simultaneous suppression of the harmonics requires a circuit with enough degrees of freedom. Then a combination of circuit parameters can be established that allows simultaneous cancellation of 3α and
5α . Such a circuit is designed in the following section. Two principles for suppression of the harmonics are well known: negative feedback and harmonic compensation (for example from control theory), and can be used in the context of V-I linearization. Next, both principles are discussed.
8.2.1. Linearization via negative feedback
The linearization properties of the feedback can be evaluated with the block diagram shown in Fig. 8.3, where the input-output relation without feedback is given in (8.2).
Fig. 8.3. Block diagram of a transconductor with a negative feedback.
The linearization properties of the feedback can be demonstrated if the ratio between the main and the thn order harmonic components in the system with and without feedback is compared:
( )
component 11
component
th
FBnth
m
n harmonicsignal
n harmonic g FBsignal
= +
(8.3)
Expression (8.3) demonstrates that the amplitude of the thn harmonic relative to
the signal component is reduces by a factor proportional to the thn power of the product mg FB , where FB gives the feedback transfer.
In circuit design, a known technique using this feedback linearization principle is the resistive source degeneration. In Fig. 8.2b a simple implementation of local feedback via a resistor is shown.
FB
( )iv t
mg( )oi t
-
8.2. Linearization of the transconductor function 141
8.2.2. Linearization via harmonic compensation
Another well-known principle for linearization uses several structures working in parallel in order to achieve compensation of the higher order harmonic content. For example, when two systems have identical structures but are parameterized differently, they process the same input signal in a similar but non-identical way. If the systems can be parameterized in such a way that after subtraction of their outputs the desired signal component is decreased less than the harmonics, the combined transfer has an improved linearity. An example of that operation is illustrated in Fig. 8.4. In Fig. 8.4a) a block diagram for the harmonic compensation principle is given and in Fig. 8.4b), the desired behavior is illustrated.
A circuit that utilized this principle is shown in Fig. 8.2c) and is denoted as cross-coupled pairs (CCP). It uses two simple differential pairs that operate in parallel for the input and are cross-coupled at the output. As shown in Section 8.4, the input transistors and the tail current sources in the CCP circuit can be parameterized such that the major contributor to the third order distortion in (8.2) is suppressed. From (8.2) and Fig. 8.4b), it can be seen that a better suppression of the harmonic content can be achieved if more degrees of freedom are available. These may be used to obtain a better match between the harmonic content in the two parallel branches and/or enable the simultaneous suppression of more harmonics. Extra degrees of freedom can be obtained by adding more structures that operate in parallel or by using a combination of linearization techniques.
Fig. 8.4. Harmonic compensation principle, a) block diagram, b) illustration of the suppression of the harmonics.
V-I1
V-I2
inV outI−
,1outI
,2outI
a)
wb)
,1 ,2out out outI I I= −
w
w
,1outI
,2outI
outIt
V-I1
V-I2
inV outI−
,1outI
,2outI
a)
wwb)
,1 ,2out out outI I I= −
w
w
,1outI
,2outI
outIt
,1 ,2out out outI I I= −
w
w
,1outI
,2outI
outIt
w
w
w
w
,1outI
,2outI
outIt
142 Chapter 8: Analysis and design of high performance transconductors
8.3. Analysis and optimization of the V-I characteristics
Important steps in the design of high performance transconductors are the analytical evaluation of their transfer function and the optimal parameterization of the circuit. Those tasks are further complicated when the transconductors use a combination of linearization mechanisms. In such a case, the parameterization of the circuit constitutes an optimization problem with multiple dimensions. Several important levels of analysis and optimization have to be pointed out:
• The transconductor transfer characteristics have to be described analytically in the form given in (8.1). This task can be solved practically only if a simple description of the characteristics can be made, and for some topologies, this might not be trivial. This step, however, is very important for the understanding of the properties and the behavior of a particular topology.
• The impact of the technology specific parameters can be evaluated only with actual transistor simulation. Modern sub-micron processes use sophisticated transistor models with parameters that can vary for the same process between the foundries and are rather dependent on the particular technological steps.
• The desired performance has to be verified with respect to the process corners and the technological spread of the parameters and the variations of the operating conditions, like voltage and temperature. This is a rigorous task that requires resources and experience. Recently, several tools [49], [50], [51] have been developed that strive to decrease the design time and facilitate the optimization of the circuit. Here, some simulation results from dedicated optimization software [52] are given in Section 8.4.
The majority of MOS transconductors are based on the simple differential pair shown in Fig. 8.1a. Here, in parallel with the SP, the resistor degenerated pair (RDP), Fig. 8.1b, the cross-coupled pairs circuit (CCP), Fig. 8.1c, and the newly proposed resistor degenerated cross-coupled pairs circuit (RCCP), Fig. 8.1d, are analyzed. The latter, in fact, uses a combination of cross-coupling (CCP) and local resistor feedback (RDP) in order to modify the V-I function. The parallel analysis of the four topologies allows a direct comparison of the linearization principles that are implemented in each of them. However, the presented analysis is generic and can be applied for an arbitrary transconductor circuit.
8.3.1. Basic analytical description
The analysis of the four circuits is done under the following initial assumptions: • The basic quadratic dependence [38] for a CMOS differential pair in saturation
(SP circuit as defined above), with tail current I and n oxC W Lβ µ= (where , , , Ln oxC Wµ are the mobility of the carriers, the gate oxide capacitance, the
width and the length of the gate of the transistor) is given as:
SP: 2
12 1
4i
o ivi v II
ββ= − (8.4)
• The channel length modulation is initially neglected. For submicron processes
this assumption might be an over-simplification and is discussed further in Section 8.4.
8.3. Analysis and optimization of the V-I characteristics 143
• The static and the dynamic linearity (the response of the system to DC and harmonic input excitations) are assumed equal for low frequencies. The actual bandwidth and the reactive effects are discussed in Section 8.4 in the context of a particular transistor sizing.
• The circuit implementation is regarded as fully balanced (differential). In such a case, the even order distortion can be neglected. In a practical situation, the device matching and the bandwidth of the common mode operation are limiting factors. Those are also discussed in Section 8.4.
From expression (8.4) the ( )o ii f v= functions are derived for the rest of the circuits under consideration. For the CCP case, cross-coupling at the drains corresponds to subtraction of the output currents:
CCP: 2 2
1 210 1 1 2 22
1 2
1 14 4
i ii
v vi v I II I
β ββ β
= − − −
(8.5)
In the case of resistive degeneration with resistor R, it is quite difficult to find a simple expression of the type ( )o ii f v= . In order to facilitate formula manipulation, in the initial mathematical treatment, the inverse relation is used:
RDP: 2 2o oi o
I i I iv i Rβ β+ −
= + − (8.6)
The RCCP can be described by two equations of type (8.6), where the index k=1,2 refers to pair one and pair two:
RCCP: , ,,1 ,2 ,
2 2k o k k o ki i i o k k
k k
I i I iv v v i R
β β+ −
= = = + − (8.7)
All of the above relations are nonlinear. As they utilize multiple pairs, tail current sources and local feedback resistors, their direct analysis and comparison is rather complicated. A possible simplification is introduced next.
8.3.2. Formalization of the analytical description
The analysis and especially the comparison of different transconductor topologies can be significantly facilitated if their description is formalized and made independent of the actual circuit dimensioning and of the particular technology used in the design. The last consideration is becoming more and more important with the technology scaling and the higher demand for portable analog designs.
A formalization of the analytical treatment can be done if the actual design parameters like currents and transistor ratios are expressed as coefficients that qualify the operation of the circuit. In the context of MOS transconductors, the following parameters can be used for that purpose:
The current modulation depth: m. This parameter shows to what extent the
available bias current is used for the generation of the output current and is defined as:
02m i I= (8.8)
144 Chapter 8: Analysis and design of high performance transconductors
The output differential current can not exceed the biasing, consequently 1m < .
Consequently, a higher m is an indication of a better power efficiency. The input voltage ratio: w . The effective gate-to-source overdrive voltage is defined as:
( )/gt GS Tv I v Vβ= = − (8.9) where ,GS Tv V are respectively, the applied gate-to-source voltage and the threshold
voltage of the transistors. The effective gate-to-source overdrive voltage gives an indication of the available voltage headroom and of the achievable dynamic range. In analogy to the current modulation depth, a parameter for the input voltage ratio can be introduced as:
i gtw v v= (8.10)
The parameter w , in fact, normalizes the input voltage to the overdrive voltage. A degeneration coefficient: x. The local feedbacks in the RDP and RCCP circuits
can be represented as:
/ gt mx IR v Rg= = (8.11) The coefficient x normalizes the value of the local feedback resistors to the
transconductance mg of the input transistors. Moreover, as already pointed out in Section 7.2.1, the linearity is determined not by the absolute value of the feedback resistor but from the product with the transconductance.
When the transconductor topology uses multiple structures that operate in parallel, the ratio between the parameters can be much more important than the nominal values.
A tail currents ratio: p can be defined for the CCP and RCCP circuits and is given
as:
1
2
I pI= (8.12)
where 1I and 2I are the respective tail currents in each differential pair.
A ratio between the transistor dimensions: q. The transistor transconductance
parameter β is giving an indication of the transistors’ W/L ratios and consequently about the effective gate-to-source overdrive voltage. For fixed transistor lengths
1 2L L L= = , the ratio between the dimensions of the input transistors can also be normalized as:
8.3. Analysis and optimization of the V-I characteristics 145
1 1
2 2
W qW
ββ
= = (8.13)
The detailed mathematical elaboration on formulae (8.4) to (8.7), according to
equation (8.2) and the described normalization, is shown in Appendix C. The ( )o ii f v= expressions are given as ( )m f w= . After the normalization, the input-
output characteristics of the four circuits are represented as a function of the tail currents’ ratios p, the transistor sizes ratios q and the degeneration coefficient x. (Note that after the Taylor series expansion, the analytical descriptions of RDP and RCCP circuits are also given as ( )o ii f v= ) The normalized representation of equations (8.4) to (8.7) for the four cases are:
SP: 3 5
...8 128w wm w= − − − (8.14)
CCP: [ ] [ ] [ ]3 5, , , ...m w p q w p q w p qτ χ σ= − − (8.15)
RDP: ( )
( )( )
53
4 7
2 72 2 ...2 2 2 2
w xw wmx x x
+= − −
+ + + (8.16)
RCCP: [ ] [ ] [ ] [ ]3 5 7
1 2 1 2 1 2 1 2, , , , , , , , , , , , ...m w p q x x w p q x x w p q x x w p q x xρ ψ ζ ω= − − − (8.17)
,where the functions [ ],p qτ , [ ],p qχ , [ ],p qσ , [ ]1 2, , ,p q x xρ , [ ]1 2, , ,p q x xψ ,
[ ]1 2, , ,p q x xζ and [ ]1 2, , ,p q x xω are also given in the appendix. The above equations can be used to determine the circuit parameterization that leads to an optimal suppression of the harmonic content in the characteristics and consequently results in a circuit with an improved linearity. For example, for the CCP circuit, the solution of equation [ ], 0p qχ = gives the values of p and q that lead to a suppression of the third harmonic in (8.2). With respect to equation (8.1) that corresponds to 3 0α = and to a significant but not full compensation of the third harmonic. A much better compensation can be achieved with the RCCP circuit because the coefficients 3α and
5α can simultaneously be made zero. The proper circuit parameterization is evaluated by solving the equations [ ]1 2, , , 0p q x xψ = and [ ]1 2, , , 0p q x xζ = .
8.3.3. Optimization of the linearity performance
The optimal parameterization of each circuit can be easily established via a graphical interpretation of the dependencies derived in the previous sub-section.
SP circuit: From equation (8.14), it is clear that there is no mechanism that allows
a modification of the harmonic content at the output. It is solely dependent on the ratio between the magnitude of the applied input signals and the effective gate-source overdrive voltage. The linearity of the circuit directly scales up with the increase of
146 Chapter 8: Analysis and design of high performance transconductors
the area and the current. However, the current modulation depth that can be achieved and consequently the efficiency of the circuit decrease with the upscaling of the parameters. That makes this circuit impractical when high linearity and SNR are required for reasonable area and power. The SP behavior is further discussed in Section 8.4 after the simulations of the actual transistor circuit. Here, however, the parameters I and β of the SP circuit can be taken as reference values with respect to which the effect of other linearization techniques is evaluated.
In the CCP circuit, the equation [ ] 1 (1 ), 1 08(1 ) (1 )
p qp q qq q p
χ +
= − = + + gives
the condition for the minimization of the third order distortion. This equation has a single solution for positive values of the parameters given by the relation:
3p q= (8.18)
The substitution of (8.18) in equation (8.15) ideally results in the elimination of the
main component of the HD3. The main signal component in the CCP circuit is given by the function [ ],p qτ . The effect of parameterization (8.18) on it is shown in
Fig. 8.5, and on the HD5 is given by the function [ ][ ]( )5
,
,
p q
p q
σ
τ as shown in Fig. 8.6.
Fig. 8.5. Influence of cross-coupling on the main signal component in the CCP circuit.
From (8.15) and (8.18) it follows that if q=1 then p=1. This corresponds to two
exactly equal cross-coupled pairs and consequently leads to a full cancellation of the signal.
1 2 3 4 5 6q value
−0.6
−0.4
−0.2
0.2
0.4
0.6
0.8
τ@p,qD [ ],p qτ
8.3.3. Optimization of the linearity performance 147
Fig. 8.6. Influence of cross-coupling on HD3 for the CCP circuit for 3p q= .
With the increase of the ratios, the difference between the two pairs increases and one becomes dominant i.e. [ ],p qτ reaches asymptotically one, while the second pair only serves for the compensation of the third harmonic. The HD3 is defined as the ratio between the third and the main harmonic. For equal pairs (p=q=1), the HD3 function goes to infinity as the signal component is zero. The function has a minimum close to q=2.5. This value of q together with expression (8.18) give the circuit parameterization in terms of ratios between the two parallel branches of the transconductor that lead ideally to a best cancellation of the third order distortion.
Fig. 8.7. Influence of the degeneration coefficient on the signal component in the RDP circuit.
2 3 4 5 6q value
0.5
1
1.5
2
2.5
3
σ@p,qDêHτ@p,qDL̂ 5
1
[ ] [ ]( )5
, ,p q p qσ τ
1 2 3 4 5x0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Signal Component
0
148 Chapter 8: Analysis and design of high performance transconductors
RDP circuit: From equation (8.16) can be seen that the harmonic content is suppressed by the degeneration coefficient x. However, the degeneration is also significantly decreasing the fundamental signal component. The impact of the degeneration on the signal component is illustrated in Fig. 8.7. For x=0 (no degeneration), the circuit is reduced to a simple SP case. However, for x=2, the signal component is reduced by half.
In Fig. 8.8 the linearization properties of the resistive degeneration are clearly illustrated. However, as mx Rg= it is evident that the price for the improved linearity is a higher current consumption and chip area.
Fig. 8.8. Suppression of the third harmonic in the RDP circuit.
RCCP circuit: The transfer characteristic of the RCCP circuit is given by equation (8.17). The circuit design increases the degrees of freedom for harmonic compensation, such that a simultaneous elimination of the dominant third harmonic contributions and a significant decrease of the fifth harmonic component can be achieved. An evaluation of the parametric choice that satisfies this requirement was done with the mathematical software package Mathematica. An optimization procedure was created that takes into account the physical boundaries of the transistor operation. The goal of this optimization was to find the global optimum: a choice of the current ratios p, the transistor sizes ratios q and the degeneration coefficients xi that results in a maximal signal component, ideally eliminates the 3v and 5v components and leads to a minimal 7v component. In the evaluation, the maximal ratios were also restricted. The reasons for this restriction are clear: very big ratios might lead in theory to an optimal solution but are rather difficult and costly to implement in a real design due to matching requirements, bandwidth reduction or noise considerations. The evaluation showed that the optimal relation between the degeneration coefficients is given by:
2 13
4x x
p q
=
= (8.19)
1 2 3 4 5x
0.005
0.01
0.015
0.02
0.025
0.03
Third Harmonic
0
8.3.3. Optimization of the linearity performance 149
An advantage of this parameterization is the relatively small reduction of 25% of the total transconductance with respect to the reference simple pair. It also gives easily implementable transistor and current ratios and a small reduction of the circuit bandwidth.
In order to avoid the drawbacks of strong degeneration, that were pointed out for the RDP circuit, here small resistors can be used as modifiers of the input-output characteristic. The parameterization x1=0.1 is used for the graphical evaluation of the linearization properties of the RCCP circuit. Such a parameterization corresponds to a resistance of one tenth of the reciprocal of the transconductance value. The behavior of the main signal component with respect to the p and q parameters is illustrated in Fig. 8.9. It increases monotonically with the increase of p and q. Such an increase corresponds to a larger difference between the two pairs.
Fig. 8.9. Main signal component with respect to p and q ratio for the RCCP circuit.
Fig. 8.10. Graphical evaluation of 3α and 5α coefficients for the RCCP circuit.
In Fig. 8.10, the dependence of the fifth and seventh order terms in the series expansion from the current and b ratios between the two pairs is studied. The plots show that for the specified region of the parameters, the two functions are rather flat.
23
45
6
q
2
4
6p
0.3
0.40.5
0.6
23
45 q
23
45
6
q
2
4
6p
0.3
0.40.5
0.6
23
45
6
q
2
4
6p
0.3
0.40.5
0.6
23
45 q
[ ],p qρ
23
45
6
q
2
4
6
8
p
00.00250.005
0.00750.01
23
45
6
q
00.00250.005
0.00750.01
-
23
45
6
q
2
4
6
8
p
00.00250.005
0.00750.01
23
45
6
q
00.00250.005
0.00750.01
23
45
6
q
2
4
6
8
p
00.00250.005
0.00750.01
23
45
6
q
00.00250.005
0.00750.01
23
45
6
q
2
4
6
8
p
00.00250.005
0.00750.01
23
45
6
q
00.00250.005
0.00750.01
-
23
45
6q
24
68
10p
-0.004-0.00200.002
23
45
6q
23
45
6q
24
68
10p
-0.004-0.00200.002
23
45
6q
23
45
6q
24
68
10p
-0.004-0.00200.002
23
45
6q
[ ],p qζ [ ],p qω
150 Chapter 8: Analysis and design of high performance transconductors
The flatness of the solution means that there is no need to find and implement the exact optimum and that the linearization technique is robust with respect to matching and process variations.
8.3.4. Analytical evaluation of the thermal noise
The thermal noise contributions of the input pairs, the tail current sources and the local resistive feedback are evaluated for the four studied circuits. All noise sources are referred to the output nodes as noise currents. Such a representation of the noise facilitates the evaluation of the SNR with respect to the chosen current settings [48]. The noise from the load transistors is not treated as it has the same contribution in all circuits.
Fig. 8.11. Dominant noise contributors in the studied MOS transconductors.
Noise contribution of the input pair(s):
From 2, 1
243n M mI kT g =
, it follows that the noise current of the input transistor can
be expressed as: 2
, ,283n out tot mI kT g =
(8.20)
Equation (8.20) gives the noise contribution of a single input pair. When more than one input pair is present (CCP, RCCP), the modification of mg should be taken into account. For example, for two input pairs the total noise current referred to the output is evaluated as:
2
, , 1 22 28 83 3n out tot m mI kT g kT g = +
(8.21)
For the RDP and RCCP circuits, the noise generated by the input pairs can also be
described, respectively as in (8.20) and (8.21).
8.3.4. Analytical evaluation of the thermal noise 151
Noise contribution of the degeneration resistor R:
The noise current of the degeneration resistor Fig. 8.11 is 2,n RI . The impedance
seen at the source of the input transistor is 1 mg . The output noise current 2xI flows in
both branches of the differential pair, where 2xI is determined by the parallel
connection of R and 2 mg , consequently the noise is given by the expression:
2
2 2, 2
mx n R
m
g RI Ig R
= +
(8.22)
From 2,
4n R
kTIR
= and m
xRg
= , the normalized output noise current due to the
degeneration resistor is given by:
( )
2, , 28
2n out R m
xI kTgx
=+
(8.23)
Noise contribution of the tail current sources: Each noise current source sees the parallel combination of 1 mR g+ and 1 mg . This
results in two different noise currents for the output given by:
( ), 1
12x n cs
mI I
g R=
+ and , 1
12
my n cs
m
g RI I
g R +
= + (8.24)
The other tail current source is producing also two output noise components:
( )
', 2
12x n cs
mI I
g R=
+ and '
, 212
my n cs
m
g RI I
g R +
= + (8.25)
Note that ,x yI I are correlated because they represent the same noise mechanism,
thus superposition should be used as if they are deterministic quantities. Then the output noise current due to , 1n csI is:
, 1 , 1 2m
n cs x y n csm
g RI I I I
g R
= − = + (8.26)
In the same way
' ', 2 , 2 2
mn cs x y n cs
m
g RI I I I
g R
= − = + (8.27)
That results in normalized expression that follows:
152 Chapter 8: Analysis and design of high performance transconductors
( ) ( ) ( )
2 22 2 2 2 2
, , , 1 , 2 , 1 , 2 22 2m
n out tot n cs n cs n cs n csm
g R xI I I I Ig R x
= + = + + +
(8.28)
8.3.5. Analytical evaluation of the achievable dynamic range
The formalized transconductor analysis can be further extended with a derivation of the analytical expressions for the third order harmonic distortion (HD3) and respectively the achievable dynamic range and SNR. The results from the evaluation, for all four circuits, are summarized in Table 8.1.
Table 8.1. Summary of the normalized representation for the compensation
conditions, HD3, and SNR for the four circuits.
In Table 8.1, the following terms are introduced: k, T and B are respectively, the
Boltzmann constant, the absolute temperature and the frequency bandwidth. In the second row of Table 8.1, the conditions that lead to harmonic compensation are given. It is clear that for the SP and RDP circuits such conditions are not available. In the table, the expression for the third harmonic is given after the application of the linearization conditions. One of the strengths of the normalization procedure is that we can easily reverse the representation of the V-I function. For example, the HD3 and the SNR are given as a function of the current modulation depth m. As is going to be shown, this representation gives a better estimate of the power required for a certain level of distortion and noise. The functions ( )xη , [ , ]p qθ and 1 2[ , , , ]p q x x∆ represent the normalized influence of the circuit parameters over the achievable SNR and are given in [53].
In the last two rows of Table 8.1, the normalized representations of the HD3 and the SNR are given for an optimal parametric choice. Those dependencies can be used for a comparison of the performance and the efficiency of the four circuits. The evaluation is done in the following order. Firstly, the current modulation depth m is expressed as a function of the SNR. Secondly, the resulting expression is substituted in the equation for the HD3. Then the quotient 2I gm is given as a function of the
8.3.5. Analytical evaluation of the achievable dynamic range 153
HD3, SNR, the frequency bandwidth B, the degeneration coefficients xi, and the transistor sizes and current ratios (q and p respectively). The resulting expressions for the four circuits are given as:
SP: 2 4
3 3m
I SNR kTBg HD
= (8.29)
CCP: [ ] [ ][ ]( )
2
5
,32 ,3 ,3
5m
p qI kTB SNR p qg HD p q
τθ
σ=
(8.30)
RDP: ( )( )
2
2 3m
kTB x SNRIg x HD
η=
+ (8.31)
RCCP: [ ]( )
[ ]
[ ]2
7
3
64 , , 1, 24096 3 , , 1, 2
21 , , 1, 2
m
I kTB SNR p q x xg HD p q x x
p q x xρ
ω
= ∆ (8.32)
Expressions (8.29) to (8.32) give design rules for the parameterization of the four
transistor circuits.
Fig. 8.12. Comparison for the required power consumption and dynamic range. For RDP1, x=2; for RDP2, x=10 and for RCCP x1=0.1, x2=0.4.
154 Chapter 8: Analysis and design of high performance transconductors
For example, the current consumption I and the transconductance value gm and the p and q ratios can be chosen with respect to the required SNR and HD3. In a practical situation, often, equal performance with respect to the noise and the harmonic distortion is required. That is why, next, the circuits are compared for
3LogSNR LogHD= . Note that in the above evaluation, the impact of the frequency bandwidth is taken
only with respect to the thermal noise. It is assumed that in this bandwidth the circuits show the predicted linear behavior. This assumption is evaluated in the next section via actual transistor simulations and in Chapter 10 with measurements. Next, for the purpose of the comparison, a bandwidth of 5MHz is taken. For the chosen technology, all four circuits exhibit linear behavior in this bandwidth.
Fig. 8.12 shows that the trade-off: linearity - noise performance is resolved with least power consumption and chip area by the RCCP circuit. In this figure, two cases RDP1 and RDP2 for the resistor degenerated circuit are given, respectively with two different degeneration coefficients x. With the increase of the degeneration, the RDP circuit shows improved power efficiency. However, the required degeneration resistor becomes impractical for implementation due to a significant increase of the required silicon area. Another negative effect is the decreased frequency bandwidth of linear operation. In the RCCP case, small degeneration coefficients are used. Also here, an improvement can be achieved with deeper degeneration (higher R), with the same penalties as for the RDP circuit.
The current consumption that is required for each circuit to achieve certain performance can be extracted from Fig. 8.12. For example, for an arbitrarily chosen
200mAg Vµ= , 70SNR dB= and 3 70HD dB= − , the required current is given in
Table 8.2.
Table 8.2. Example for the required current consumption for certain dynamic range
SP RDP1 CCP RCCP 2 , mWmI g , 0.87 0.3 0.168 0.028
, mg A Vµ 200 200 200 200 ,I mA 2 1.2 0.92 0.3
Up to now, the circuit behavior and performance is extensively studied analytically.
However, the evaluation remains largely approximative because some secondary order effects in the transistor implementation like matching precision, channel length modulation, body effect, carrier mobility dependence on the biasing point and the technology specific thermal noise parameters are not modeled. Those non-idealities are coupled with the technology, the available supply voltage and the transistor sizing. However, the non-idealities have, in general, an equal impact on all four circuits because of their similar structure. Moreover, the same analytical approach is used for their evaluation. The evaluation continues with simulations of the transistor circuits in which several of the aforementioned non-idealities are taken into account.
8.4. Circuit level evaluation of DR, SNR and THD 155
8.4. Circuit level evaluation of DR, SNR and THD
In the complex task of choosing a certain parameterization of every circuit, there always is a primary target performance determined by the application specifics. The analysis given so far was general and showed the basic trade-offs in the four circuits. In this section, firstly the non-idealities of the transistor implementation are discussed. Then the static and dynamic behavior and the robustness of the parameterization are evaluated with simulations. The actual circuit dimensioning is done in the context of a particular application that sets the requirements towards the current consumption, the SNDR and the bandwidth. The specifications are defined as: a SNDR of 75dB, a maximal differential input signal of 400mV peak-to-peak and a bandwidth of 5MHz. The complete transistor implementation of the RCCP circuit is given in Fig. 8.13. The core transconductor circuit is built with input transistors M1 to M4, tail current sources M5 to M8 and the degeneration resistors R1 and R2. The rest of the circuit provides biasing and common mode feedback and was also used in the evaluation of the other three circuits that were studied in the previous sections.
Fig. 8.13. Transistor implementation of the RCCP circuit.
8.4.1. Non-idealities in the transconductor implementation
Several important effects are introduced by the implementation of the transconductor function with particular MOS devices. In the design phase of the actual transistor circuit those effects can be significantly alleviated via a proper parameterization of the transistors. Next, the dominant effects are described and the proper circuit parameterization is elaborated.
156 Chapter 8: Analysis and design of high performance transconductors
Flicker noise In sub-micron processes, the flicker noise can have a significant impact on the
achievable SNR. It contributes to the SNR for low frequencies and especially when the corner frequency of the flicker noise falls within the operation band of the particular application. For the continuous time integrators that are used in low-pass SDMs the decrease of the flicker noise is a very important consideration. In many designs, a simple increase of the device sizes can be used to decrease the flicker noise below the acceptable levels. In practice, the required W L ratio is already determined from other considerations like linearity and noise. That is why an increase of the device sizes is associated with up scaling of all transistor dimensions. The minimal required transistor lengths can serve as an indication of the required parameterization. For the design case specified in Section 8.4 a gate length of min10 ,L L≈ ( min 0.18L mµ= ) is used for the transistors that determine the noise performance.
Channel length modulation The increased length also significantly decreases the impact of the channel length
modulation on the transconductor characteristics. For min10L L≈ the variation of
d DSI V∂ ∂ is decreased approximately 100 times. That means that the circuit operation is in very good correspondence with the basic quadratic equation that is used in the analysis given in the previous sections.
Matching Matching of the devices is of extra importance for the CCP and RCCP circuits
where the linearity of the circuits is dependent on transistor and current ratios. As already shown, the linearization mechanism in the RCCP case is rather insensitive to mismatch due to the flat optimal parameterization. A possible matching problem is additionally alleviated due to the increased size of the devices. However, during the layout phase special care should be taken for a very good symmetry between the two differential branches and an equal electrical and mechanical environment. The large transistors, however, introduce a penalty for the achievable bandwidth.
Reactive effects The design of high-speed circuit requires a careful consideration of the parasitic
impedances on the signal propagation path that limit the frequency range of operation of the circuit. A common advantage of all four studied designs is their direct structure that leads to high-speed operation. The degeneration is implemented via simple resistors and does not introduce a direct speed penalty as, for example, the more sophisticated source degeneration techniques. However, in the context of the studied transconductor implementations the following effects have to be pointed out:
• The common mode rejection ratio (CMRR) decreases at high frequencies due to the increased impact of the source capacitances. This effect decreases the symmetry of the circuit and may lead to a rapid degradation of the performance.
• The bandwidth of the common mode feedback (CMFB) is normally not a limiting factor for high-speed operation. However, for high-precision circuits a trade-off is introduced between the precision of the CMFB in terms of symmetry and transistor matching and its speed. The circuit that was used for the common mode feedback is shown in Fig. 8.13 as a part of the full
8.4. Circuit level evaluation of DR, SNR and THD 157
schematic of the RCCP circuit. The same common mode configuration is used for all four circuits. That assures equal impact on the bandwidth and noise.
• Two input pairs with different sizes have different frequency responses. With the increase of the frequency this leads to a deterioration of the efficiency of the harmonic compensation. This effect is illustrated in Section 8.4.3.
Temperature dependencies The strong temperature dependence of the mainstream resistor implementations
has to be pointed out. Due to cost factors, special resistors are in most cases considered impractical and are not treated here. The n+ Active and n+ Poly resistor implementations are evaluated in detail. The first is characterized with a higher sheet resistance, better matching properties but higher temperature dependence. As discussed in detail in Section 8.4.4, the temperature dependence can be alleviated if the circuit performance can be made less dependent on the absolute values of the used resistors.
8.4.2. Evaluation of the static performance
Firstly, the static behavior of the four circuits is treated. It can be considered an important step in the evaluation because it reveals the operation range of the circuit and qualifies the applied linearization techniques. For the purpose of the comparison, the total current consumption of the four circuits is normalized as I. In case of multiple differential pairs, the sum of all tail currents is kept constant:
1 2 ... nI I I I= + + . The static behavior and performance are illustrated with two examples, as described next. For both examples the total current consumption of each of the four circuits is equal and fixed as: 200I Aµ= .
Fig. 8.14. Transconductance variation with respect to the applied input voltage, SP circuit is taken as a reference.
mgA V
158 Chapter 8: Analysis and design of high performance transconductors
Example I: The four studied transconductor circuits are parameterized as follows: The input
transistors are chosen to have the same length: 1 2 .. nL L L L= = = and total width
1 2 .. nW W W W= + + . Furthermore, for the RDP and RCCP cases, the degeneration resistors are chosen such that the resulting transconductance after the linearization is approximately equal for both circuits. This parameterization makes the SP circuit a reference for the transconductance parameter β and for the achievable gain. The purpose of this parameterization is to show to what extent each linearization technique is decreasing the gain of the reference SP circuit.
In Fig. 8.14 the simulated variation of the transconductance value with respect to the applied input voltage is shown. The transconductance curve for the SP circuit has the maximum mg that can be achieved with the chosen current settings and transistor sizes. This mg is decreased by every linearization technique. The CCP circuit is parameterized for optimal linearity according to (8.18). From Fig. 8.14 it can be seen that the linear input dynamic range is significantly improved with respect to the SP circuit; however, the mg is decreased as predicted in Fig. 8.5.
For the RDP circuit, as all other settings are fixed, the degeneration coefficient x is directly determined by the resistor R. The choice of R depends on the allowed decrease of the transconductance and the available voltage headroom. Via R, the input dynamic range is increased. This can be evaluated quantitatively by solving equation (8.6) for the boundary condition 2 oi I= when only one of the input transistors carries
the entire tail current, ideally assuming the other is fully off. Then 4inSP
IVβ
= and
42inRDPIR IV
β= + , so that
2inIRV∆ = , where inV∆ is the difference between the input
voltages for which mg in the two circuits goes down to zero. This effect is not improving the level of the harmonic linearization. However, it determines the input range for which some linearization takes place. The linear range and the linearization level are increased when R is increased. As predicted, the cost is a significant decrease of the transconductance. The maximum applicable R is also determined by the saturation conditions of the tail current sources, effectively leaving less voltage room for the current sources for bigger R.
The same considerations for the resistor influence apply for the RCCP circuit. A major difference, however, is the different linearization mechanism that allows achieving the same mg and much better THD for significantly smaller resistor sizes. The simulations show that the resistor value in the main pair (the one with bigger input transistors and bigger tail current) is determining the current modulation depth and the voltage swings. The value of the second resistor is only modifying (linearizing) the top of the transconductor characteristic. The optimal ratios are the same as predicted from the mathematical evaluation (8.19).
Example II: A much more practical approach in the transistor sizing is used next. In order to
achieve a maximal linearity and an equal gain from the four circuits, only the current consumption is fixed, while the transistor dimensioning is not restricted. The four
8.4. Circuit level evaluation of DR, SNR and THD 159
circuits are parameterized for approximately equal transconductance value mg (see Fig. 8.15).
For the SP circuit, maximum linearity is achieved for large effective gate-to-source overdrive voltages. The overdrive voltage can be increased via a decrease of the W/L ratio of the input transistors. In practice, the length of the transistors is increased in order to fulfill the noise and matching requirements. The decreased ratio leads to a lower transconductance value, higher noise figure and to a decrease in bandwidth. The same considerations are valid the CCP circuit. However, there the linearity is improved with a minor increase of the transistor lengths.
For the RDP circuit, there is no need for adjustment of the transistor lengths as the linearity is determined by the degeneration coefficient x. On the contrary, a large W/L ratio allows a stronger degeneration and, consequently a better linearity. However, as already stated, large degeneration deteriorates the noise performance and the large sizes decrease the bandwidth.
For the RCCP circuit it is possible to increase the linearity via an increase of the effective gate-to-source overdrive voltage or via an increase of the degeneration resistors. In the circuit implementation, small resistors are used in order to minimize their impact on the noise and allow for larger bandwidth.
Fig. 8.15. Transconductance variation with respect to the applied input voltage, four circuits with approximately equal transconductance.
For the RDP and RCCP circuits the non-idealities of the resistors can be made negligible if larger resistor widths are used. Consequently, that leads to a significant additional area penalty for the RDP circuit due to the large resistors and to a small increase of the area required by the RCCP circuit. When the width is increased to 1mm, resistor implementations have a negligible impact on the circuit performance.
In Fig. 8.15 the four circuits are compared again with respect to the applied input DC voltage. The SP and RDP circuits have higher dynamic range within which some linearization is taking place. However, the linearity of those two circuits is much worse for the specified linearity limits. It can be improved only via an increase of the
160 Chapter 8: Analysis and design of high performance transconductors
transistor sizes. The RCCP circuit offers the best trade-off due to the applied linearization technique.
The static simulations are exact for the transconductance value, but give only a qualitative indication for the actual level of harmonic distortion. This level is evaluated in the next section via harmonic balancing simulation for the THD.
8.4.3. Evaluation of the dynamic performance
The THD and noise are frequency dependent. They are evaluated with dynamic simulations. In Fig. 8.16, the amplitude dependence of the THD is shown for an input signal frequency of 5MHz. In the performed simulations, THD showed to be flat with respect to frequency up to tens of MHz. After that range the reactive effects start to influence the operation. The RCCP circuit is showing a significant improvement in THD of 10dB on average.
Fig. 8.16. THD of the four circuits for input signal frequency of 5MHz. The vertical line at 200mV shows the targeted input range. In the RCCP curve: A-B region with maximal linearity, region B-C operation close to that of a single degenerated pair.
At point B of the RCCP curve (Fig. 8.16), the THD starts to increase faster. At this point the non-dominant input pair is overdriven and the effect of the linearization is decreased. The circuits start to operate as the stand alone RDP circuit but with a smaller tail current source. That leads to a faster increase of the THD.
In the simulations, the noise generated in the circuits is represented as an equivalent noise voltage source at the input. In
Table 8.3 the simulated total (thermal and flicker) input referred noise voltage in frequency band (100Hz, 5MHz) is given:
( )5
2,
100
( )MHz
Hz
eq n noiseV V f df= ∫ (8.33)
A
B
C
8.4.3. Evaluation of the dynamic performance 161
Then the SNR is calculated for two input differential peak-to-peak voltages: Vin,pp. The values for the THD are taken from Fig. 8.16.
Table 8.3. Simulated SNR and THD for input amplitudes of 200mVin,pp and
400mVin,pp.
Vinpp, mV SP CCP RDP RCCP , ,eq nV Vµ 55 65 94 86
THD, dB 200 -62 -70 -66 -89 SNR, dB 200 68 66.7 63.5 64.3 THD, dB 400 -60 -68 -64 -80 SNR, dB 400 74 72.7 69.5 70.3
The noise voltage generated in each circuit corresponds to the evaluation described
in 8.3.4. The split tail current sources (CCP and RCCP circuits) and the degeneration resistors (RDP and RCCP circuits) have the biggest impact on the generated noise. Every linearization technique is increasing the noise level. However, due to its superior linearity, the RCCP circuit has a much better overall performance.
8.4.4. Evaluation of robustness with ADAPT
The evaluation of the robustness of the circuit topology and its parameterization is a very important step in the design. Such an evaluation confirms the functionality and the performance of the circuit in worst case conditions: the combination of statistical, process and environmental parameters that constitutes the biggest deviation from the nominal. The worst case conditions may vary from circuit to circuit as the dominant deteriorating effects may be different. In the context of the studied transconductor topologies, the technology spread and the temperature dependence of the parameters can be identified as dominant deteriorating effects. The first one has an impact on the achievable matching accuracy, while the second one may lead to deviations from the conditions for an optimal linearization as defined previously.
The evaluation and the improvement of the robustness has become a typical target for optimization software. Here, as an optimization software we define software packages that incorporate algorithms that can search the design space and identify circuit parameters such that the targeted design specifications are met, if possible under all technology variations. In the context of this work, a Philips in-house optimization tool called ADAPT [52] was used to verify the robustness of the manual circuit parameterization. Further in this section, the circuit parameterization that is a direct result of the analytical elaboration is called “manual”. Respectively, the parameterizations found with ADAPT are called “optimized”. Each evaluation consists of one or more simulations, such that all circuit characteristics are determined in all required (temperature) corners. The employed circuit simulator for these optimization tasks was Pstar, the Philips in-house analog circuit simulator.
Two optimization runs are evaluated in this section. The goal of the 1st one (OPT1) is to find a better optimum close to the manually parameterized circuit by only allowing a subset of the operation variables (circuit parameters that the tool can vary in order to modify the behavior of the circuit) to change during optimization. For the second one (OPT2) the restrictions on the operation variables are less stringent so that
162 Chapter 8: Analysis and design of high performance transconductors
a larger design space can be explored by ADAPT. The comparisons are made between the manual reference design and the two optimized designs found by ADAPT.
To facilitate interpretation of the results and to gain additional insight, the THD performance of the V-I converter is visualized as a function of the input signal amplitude at a given input signal frequency. The input signal amplitude shown in the graphs is larger than the optimization range. The reason for plotting values outside the optimization is to show the trend outside that range.
Fig. 8.17. The THD of the manual design vs. the OPT1 design, measured for an input signal amplitude vm <0.5V, at the input frequency of 1MHz, across –40±C, 25±C,
125±C.
As can be seen in Fig. 8.17, the manual design has inferior THD performance at 125±C. Thus, the OPT1 performance is better with respect to robustness against temperature variations.
Due the two different restrictions on the design space, the two optimized results also have a significantly different parameterization. For OPT1, ADAPT increased the effective gate-to-source overdrive voltage of the input pairs via a decrease of the W/L ratio. The tool had increased the length of the input transistors by 15%. In OPT2 another possibility for improvement was exploited. The tool had also increased the ratio between the two degeneration resistances making the bigger pair more dominant thus increasing the transconductance of the stage and allowing higher degeneration.
8.4.4. Evaluation of robustness with ADAPT 163
Fig. 8.18. The THD of the manual design vs. the OPT2 design, measured for an input signal amplitude Vm <0.5V, at the input frequency of 1MHz, across –40±C, 25±C,
125±C.
Up to now, we have only taken an environmental variation, being the temperature, into account. Good performance over environmental corners does not guarantee general robustness. Often, improved 1st-cut circuit performance goes at the expense of decreased robustness of the circuit with respect to global process variations and mismatch.
Fig. 8.19. The THD average and standard deviation with vm <0.25V, with input frequency 1MHz, and for temperatures of –40±C, 25±C.
164 Chapter 8: Analysis and design of high performance transconductors
Therefore, we conduct a few additional simulations to demonstrate the good robustness of the optimized solutions. Fig. 8.19 shows the average value of the THD and, more importantly, the standard deviation of the THD, as a function of the input signal amplitude vm. The four curves have been offset a bit so that the error bars don't overlap completely. It is clear from the curves that THD robustness (and thus circuit robustness) is good for both the manual design as well as the optimized designs.
Due to the complexity of the transconductor optimization in terms of design space size and strongly nonlinear interdependencies, the use of ADAPT for this kind of optimization task showed to be especially advantageous.
Moreover, we also assess the improved robustness with respect to environmental conditions (temperature) and process variability. The two optimized solutions reveal the potential of the circuit topology to fulfill quite a wide range of application requirements.
8.5. Conclusions
In this chapter the analysis and the design of high performance transconductors was treated. A method for normalized evaluation of transconductor topologies based on MOS differential pairs was introduced. Its application on several circuit implementations was shown. The achievable dynamic range for a certain minimum current consumption was established. A new circuit solution with highly improved linearity was introduced. The results from the transistor level simulations with a state of the art technology were presented. They confirmed the superior performance of the new circuit solution and the applicability of the method in actual transistor design. The very close match between the theoretical expectations and the simulation results showed that the analysis can be used for the derivation of the actual design rules for circuit dimensioning. The method can be generally applied for evaluation of transconductor circuits.
9. Chapter 9
Decimation via Recursive Bitstream Conversion
In this chapter, the requirements towards the decimation filter (decimator) for the sigma-delta ADC are discussed. The decimation via a recursive bitstream conversion algorithm (REBIC) [54] is studied in detail. The theoretical backgrounds and the properties of REBIC as a decimation algorithm are conceptualized, further investigated and elaborated. The properties of REBIC decimators for different decimation factors and filter orders are evaluated with high-level simulations. The trade-off between stability and performance is illustrated with a practical design example of third order REBIC decimation filters with a decimation factor of four. The realization of higher decimation factors is elaborated and the impact on the achievable decimator performance is investigated. The issues that arise from a particular hardware implementation, like the finite word-length and the speed limitation of the hardware are studied by an investigation of the required digital hardware blocks and their implementation into an FPGA.
9.1. Decimation in Sigma-Delta ADC
SDMs are preferred AD converters for low power applications due to their high power efficiency. However, many new mobile applications require a significant increase of the conversion bandwidth and aim higher and higher sampling frequencies. The higher sampling frequency poses significant design challenges not only upon the design of the core SDM but also upon the design of the consequent digital signal processing circuitry. Part of this digital signal processing is performed in the ADC. In this context, the resources in digital domain in terms of power, memory and silicon area become a major concern for the efficiency of the data conversion path that utilizes SD ADCs. A correct estimation of the power consumption of the ADC and a realistic comparison with other types of converters are only possible if the power and the area that are used in the digital part are included in the overall design specifications.
A general block diagram of a single bit SD ADC is shown in Fig. 9.1. The analog input signal ( )inx t is converted by the SDM into a digital bitstream [ ]sa nT 1 that toggles between one and zero with a maximal frequency of one half of the applied clock frequency sf .
The information is encoded in the digital bitstream, i.e. in the particular order of digital symbols. The SDM output signal has a large frequency bandwidth such that a major part of its spectral content spreads up to 2sf . However, due to the oversampling of the input signal, only the low frequency portion of this bandwidth contains information that has to be further processed.
1 The digital signals in the chapter are treated as sequences and not as time functions. However, for a better readability and clarity the time period associated with the particular signal processing step is initially given. Later on in this chapter the time period is normalized.
166 Chapter 9: Decimation via Recursive Bitstream Conversion
Fig. 9.1. Block diagram of SD ADC that includes a SDM on the left and a decimation filter on the right.
The digital processing of the complete high-speed signal is very inefficient. That
introduces a need for a digital filter that can suppress the unwanted part of the spectrum before any further signal processing. Consequently, the bandwidth of the sufficiently filtered output signal can be reduced via sub-sampling without performance degradation due to aliasing in the baseband. The sub-sampling is quantified by a factor q that is named decimation factor, or decimation coefficient. In most systems, the decimation factor is chosen as an integer, because that significantly simplifies the computations in the digital domain. The sampling frequency can at most be reduced to the Nyquist frequency for the particular signal bandwidth. At the output of the decimation filter, the signal [ ]sb nqT has a low rate and an amplitude resolution R that is much higher than the resolution of the SDM output. The actual value of R depends on the implemented decimation ratio, the dynamic range of the original bitstream and on the particular decimator implementation.
The functional requirements towards the digital processing in the SD ADC can be summarized as:
• Base band filtering • Decrease of the sampling rate
Those two functions are used with a common name: decimation filter or decimator. Ideally, the decimator does not introduce signal band attenuation and has a stop band
attenuation that is higher than the dynamic range of the SDM. In such a case, the dynamic range of the whole ADC is determined by the SDM and is not influenced by the decimation filter. Moreover, the stop band attenuation, together with the width of the transition band determines the amount of aliasing in the baseband that can be introduced by the decrease of the sample rate. Those two factors introduce a trade-off between the steepness of the filter and its stop band attenuation, such that the limited steepness can be compensated with a stronger stop-band attenuation. Intuitively, the requirements for the decimation filter increase with the increase of the SDM dynamic range, sampling frequency and signal bandwidth.
Another factor that has to be taken into account in the decimator design is the specific format that is used by the subsequent digital signal processing.
The decimation filter can be designed to encode the data in the required digital format. One of the most widely used formats is the pulse-code modulation (PCM) that is illustrated in Fig. 9.2. The PCM data consist of R bit digital words processed with a sample rate ,s Rf , such that the amplitude information is encoded with R bit accuracy. Respectively, for PCM at Nyquist rate, R should correspond to the ENOB of the SDM.
Decimation Filter
Loop Filter Sampler- Q
sf[ ]sa jT( )inx t
R
[ ]sb jqT
1Decimation
FilterLoop Filter Sampler- Q
sf[ ]sa jT( )inx t
R
[ ]sb jqT
1
9.2. Decimation cost factors 167
Fig. 9.2. 4-bit coding of a sine wave.
9.2. Decimation cost factors
The efficiency of the decimator implementation can be evaluated with respect to the following factors:
• The number of filter coefficients that are required for the implementation of the
filter function and respectively the required memory size that is needed for their storage. Complexity of the coefficients depends on the number and type of mathematical operations that are performed in the filter. The most common operations are shifting, addition and multiplication that require correspondingly increasing computational complexity and power.
• The clock speed at which the particular mathematical operation is executed also determines the power that is consumed by the filter.
• The minimum digital word length that is required for lossless signal processing. The word length is very much dependent on the particular filter implementation and is in most cases limited by the available memory.
All of the above factors lead to area and power requirements for the filter. The power
consumption is of major importance as it does not scale directly with technology and is critical for many applications.
At the transistor level, the dynamic power consumed by a conventional CMOS device is in first order approximated as proportional to the clock frequency and the square of the supply voltage:
P ∂ 2
clock ddf V (9.1) where ddV is the supply voltage, and clockf is the clock frequency [59]. In the advanced
technologies and for very high frequencies, the impact of the transistor lengths and of the overlap capacitances also becomes significant. For a specific filter function, halving the clock frequency without changing ddV decreases the power consumption in half, but does not affect the total energy consumed. Energy is the time integral of power, so energy consumption is not reduced as long as the same number of clock cycles are required to do the same calculation. However, reducing the clock frequency allows ddV to be reduced, or for a fixed
t
integer code
PCM code: 1111 1110 . ...
0000
168 Chapter 9: Decimation via Recursive Bitstream Conversion
ddV , allows lower current settings leading to energy savings. The current can be reduced, mainly because of the decreased impact of the parasitic capacitances at lower frequencies.
In order to avoid aliasing, in a typical decimator implementation, the sample rate decrease is applied only after low-pass filtering (LPF). The flow that is typically used is shown in Fig. 9.3a, where N is the output word length of the applied LPF. The value of N may vary significantly with respect to the particular LPF implementation. The decimated 2T and the high speed 1T clocks in Fig. 9.3 are related by the decimation factor q :
2 1T qT= (9.2)
In practice, the implementation of the LPF is not ideal and is characterized by some stop
band attenuation, transition band and signal band ripple and/or attenuation. That is why, for lossless signal transfer, an equalization filter (EF) should be added in the decimation chain, as shown in Fig. 9.3b.
a) b)
Fig. 9.3. a) Block diagram of the decimation process, b) Block diagram of the standard practical decimation with signal equalization.
The standard decimation approach shown in Fig. 9.3 is most often used but is not optimal in terms of complexity and power consumption. Several drawbacks have to be pointed out:
• The decimation chain structure is fixed, such that the equalization filter (see Fig. 9.3b) is applied after the down sampling and the possibility to include it in the preceding blocks is not taken into account. In this way a possible structural optimization of the decimator is ignored.
• The performance of the decimator depends on the implementation and complexity of the LPF, such that for a FIR implementation a very big filter is required for a good performance. On the other hand, a direct IIR implementation is rather power consuming because of the intermediate output samples that are calculated at full speed and are needed for the computation of the future output samples. In both implementations (FIR and IIR), large decimation steps are very costly. That is why, typically the decimator is implemented as a cascade of decimators by 2.
• The LPF structure and implementation is chosen beforehand. That limits the possibility for structural optimization and may lead to overhead in terms of power consumption and area.
Next, an alternative decimation architecture is elaborated that is characterized by a specific approach in the analytical description of the decimation filter and leads to a significant improvement of the efficiency of the decimation chain.
LPF1
[ ]1a jT∞ q
[ ]2b jT
NqN
EFLPF1
[ ]1a jT∞ q
[ ]'2b jT
NqN
LPF1
[ ]1a jT∞ q
[ ]2b jT
NqN
EFLPF1
[ ]1a jT∞ q
[ ]'2b jT
NqN
9.3. Theoretical fundaments of REBIC 169
9.3. Theoretical fundaments of REBIC
From the discussion up to now, it can be pointed out that the decimation filter is efficient in terms of power, when the majority of the signal processing is done with a low sample rate and when the filter topology uses a minimal number of stages and filter coefficients that require little energy per operation.
In [54] a signal processing algorithm named recursive bitstream conversion (REBIC) is introduced. Here, the description of the algorithm is generalized and the most important signal processing steps are underlined and elaborated.
REBIC maps to each other two discrete sequences with different amplitude resolutions and different sample rates using an efficient mapping algorithm. The mapping is bi-directional (see Fig. 9.4):
• Forward REBIC: approximates an ideal decimator with an implementable analytical description: a known high-bitrate SDM bitstream is efficiently mapped to a low-bitrate PCM signal (see Fig. 9.4a). The mapping is approximate because, in practice, the low-pass filters in Fig. 9.4a are not ideal and are substituted with realistic filters.
• Reverse REBIC: Alternatively, the PCM signal can be mapped to a noise shaped bitstream (see Fig. 9.4b), such that an ideal interpolator/serializer can be approximated. This process is extensively studied in [55], [56], [57] and [58] and will not be further treated here.
a) b)
Fig. 9.4. Block diagram of REBIC, a) Forward REBIC: SDM bitstream to PCM conversion, b) Reverse REBIC: PCM to noise shaped bitstream conversion.
SDM bitstream
ideal decimator
=
ideal interpolator/serializer
Mapper
[ ]2b jT[ ]1a jT
[ ]'2x jT [ ]2y jT
PCM signal
PCM signal
noise shaped bitstream
LPFT1
1
[ ]1a jT [ ]2b jT
[ ]1x jT
m
LPFT2
∞ q
LPFT2
SDM bitstream
ideal decimator
=
ideal interpolator/serializer
Mapper
[ ]2b jT[ ]1a jT
[ ]'2x jT [ ]2y jT
PCM signal
PCM signal
noise shaped bitstream
LPFT1
1
[ ]1a jT [ ]2b jT
[ ]1x jT
m
LPFT2
∞ q
LPFT2
170 Chapter 9: Decimation via Recursive Bitstream Conversion
In this section, the forward REBIC is investigated in detail. The algorithm describes the signal processing steps that are required to derive the complete decimator chain from 1[ ]a jT to 2[ ]b jT as indicated in Fig. 9.4. Firstly, the equivalent discrete sequences '
2[ ]x jT and 2[ ]y jT are derived. From that equivalence, the PCM signal is expressed recursively. In the basic derivation, an arbitrary low-pass filter can be used for the LPF indicated in Fig. 9.4. For a particular application, when the properties of the SDM bitstream 1[ ]a jT , in terms of SNRq in the base band, are know; the required LPF functions can be chosen. With a chosen LPF, an analytical description of a practical decimation filter is derived.
The construction of a REBIC system is based on several important theoretical relations that, as will be demonstrated later in this chapter, introduce significant improvement with respect to the standard decimation flow that was discussed in section 9.2. The construction of a forward REBIC system is explained next.
• As shown in Fig. 9.4a, a mathematical relation can be established between the bitstream 1[ ]a jT and the PCM signal 1[ ]b jqT if the two discrete sequences are filtered with equivalent low-pass filter functions, indicated in the figure as LPFT1 and LPFT2. If the two discrete sequences ( 1[ ]x jT and 2[ ]y jT ) are equal at equidistant time intervals T2, they can be related mathematically. Then the redundancy in 1[ ]x jT can be removed and the resulting sequence denoted as '
2[ ]x jT .
a) b)
Fig. 9.5. a) Block diagram of the bitstream equalization with IIR integrator types of filters, b) Block diagram of bitstream equalization with initial signal parallelization.
• LPFT1 and LPFT2 can have arbitrary low-pass characteristics. A simple and efficient implementation for those filters is as a cascade of discrete-time integrators. The discrete time integrators realize filters of an IIR type, assure good performance and have a simple implementation. However, as indicated in Fig. 9.5a, in this configuration the IIR1,T1 operates at the high sample rate and as a result is very inefficient.
• The drawback of using a high sample rate recursive filter IIR1,T1 can be avoided, if the positions of the sample rate decreaser and IIR1,T1 are interchanged [60], [61] (see Fig. 9.5b), such that firstly the sample rate is decreased and then the filtering is applied. This change requires a serial-to-parallel converter to effectively decrease the
IIR1,T1
=
1
[ ]1a jT [ ]2b jT
[ ]1x jT
[ ]2y jT
m
IIR2,T2
[ ]'2x jT
∞ qclock T2
S/P
=
1
q
[ ]1a jT [ ]2b jT
[ ]'2x jT [ ]2y jT
IIR2,T2IIR’1,T2
m
9.3. Theoretical fundaments of REBIC 171
speed of the signal before the actual filtering and a polyphase filter IIR’1,T2 with q inputs and one output that operates with a clock period 2T .
The block diagram at the left hand side of Fig. 9.5b maps 1[ ]a jT to '2[ ]x jT . The
combination of a recursive filter with a sample rate decrease can be described [60] with a transfer function in z-domain given in (9.3). Expression (9.3) describes a recursive filter with a numerator part that operates at the high bitrate and realizes a FIR filter and a denominator part that operates with the low bitrate and realizes an IIR filter. The resulting filter is efficient in terms of power and area because it is recursive and the major part of it operates at the low sample rate.
( )( )2
1'1 2
1,
{ [ ] [ ]}' q
T
FIR za jT x jT
IIR z→ → (9.3)
With the help of Fig. 9.5b and (9.3), the complete decimator chain from 1[ ]a jT to 2[ ]b jT
can be represented in z-domain as a cascade of filters. The decimated signal 2[ ]b jT can be derived from the intermediate signal '
2[ ]x jT derived in (9.3), via multiplication with the inverse of
22,TIIR 2. The process and the resulting filter function are illustrated in Fig. 9.6.
Fig. 9.6. Block diagram for the construction of the complete decimator.
In comparison with the standard decimator chain from Fig. 9.3, several advantages of the decimator synthesized in Fig. 9.5 and Fig. 9.6 have to be pointed out:
• In the right hand side of Fig. 9.6 the complete transfer function of the decimator is given. The algorithmic derivation of the decimator and its description with a single transfer function allow the derivation of a structurally optimized filter. Such a filter potentially has a much higher efficiency than the standard chain derivation.
• As illustrated further on, the FIR filter can be implemented such that the sample rate decrease is performed first. In such a case, the decimation process begins with a sample rate decrease and the power efficiency of the decimator is immediately improved.
2 It hast to be pointed out that 2, 2TIIR does not need to be a minimum phase filter, because its transfer function does not participate directly in the decimation filter but is a part of the total filter described in the Fig. 9.6.
[ ]1a jT
[ ]2b jT
( )( )
1
2
1,
1,'T
qT
FIR z
IIR z
( )22,
1q
TIIR z
[ ]1a jT
[ ]2b jT
( )( ) ( )
1
2 2
1,
1, 2,'T
q qT T
FIR z
IIR z IIR z[ ]'2x jT
172 Chapter 9: Decimation via Recursive Bitstream Conversion
• The utilization of recursive filters further increases the efficiency of the implementation.
• The transfer function of the whole decimator chain given Fig. 9.6 incorporates a correct by design equalization block. The built-in equalization is a result of the equivalence of the discrete sequences '
2[ ]x jT and 2[ ]y jT , such that the incorporation of
22,1/ TIIR in the decimator transfer characteristics introduces the required signal equalization.
The most important design parameter in the forward REBIC is the LPF function (see Fig. 9.4), because it determines the precision of the approximation of the ideal decimator. The choice of this filter depends on the precision with which the analog input signal is encoded in the bitstream. Because of that, the LPF function determines the complexity of the implementation. A final step in the algorithm is the realization of the analytical description of the decimator into an implementable hardware architecture. This process can be realized in several different ways and is governed by the properties of the available hardware in terms of speed, allowed size of the digital words and the available memory. All of the above steps are elaborated in detail in the Sections 9.4, 9.5 and 9.6. Firstly, however, an in-depth analysis of REBIC properties is given and the possible system design choices are elaborated.
9.3.1. Spectral equivalence of multi-rate signals
This sub-section treats in more detail the derivation of the discrete sequences 1[ ]x jT and 2[ ]y jT as indicated in Fig. 9.4 and the analytical description of the decimation filter
illustrated in Fig. 9.6. In Fig. 9.7. the signal 1[ ]x jT represents the filtered version of the SDM output bitstream na and 2[ ]y jT the filter PCM signal. At the right hand side of Fig. 9.7. the corresponding spectra 1( )j TX e ω and 2( )j TY e ω are given.
In order to facilitate the mathematical manipulations and further on, the choice of a filter structure, a particular sample number k from the low-speed high-resolution signal is denoted as kb . Due to the different sample rates, during some time interval 2jT , qj samples of the high-speed bitstream are produced. Each sample can be identified with an index n and the bitstream is respectively denoted as na .
a) b)
Fig. 9.7. Time and frequency domain representations of: a) A high sample rate discrete sequence; b) low sample rate discrete sequence.
j
x[jT1]
j
x[jT1]
1 2 3 4 5 6 7 8 9 10
j
y[jT2]
j
y[jT2]
1 2 3 4 5
ω
1Tπ
1Tπ
( )1j TX e ω
1Tπ
−1
2Tπ
ω
1Tπ
1Tπ
( )1j TX e ω
1Tπ
−1
2Tπ
ω2Tπ
−
( )2j TY e ω
2Tπ
2Tπ
2
2Tπ ω
2Tπ
−
( )2j TY e ω
2Tπ
2Tπ ω
2Tπ
−
( )2j TY e ω
2Tπ
2Tπ ω
2Tπ
−
( )2j TY e ω
2Tπ
2Tπ
2
2Tπ
9.3.1. Spectral equivalence of multi-rate signals 173
The spectra of the signals 1[ ]x nT and 2[ ]y nT are described with the following equations:
( ) [ ]1 11
j T jn T
nX e x nT e
∞−
=−∞
= ∑ω ω (9.4)
( ) [ ]2 22
j T jn T
nY e y nT e
∞−
=−∞
= ∑ω ω (9.5)
Due to the integer ratio q between the two sampling periods, the spectral content of the
two signals that falls in the fundamental interval of 2( )j TY e ω is related by the expression:
( ) 12 2
21 ( )
0
1 iq j Tj T T
i
Y e X eq
πωω
− −
=
=
∑ (9.6)
If 1( ) 0j TX e ω = for 2Tω π≥ in the fundamental interval of 1( )j TX e ω , as suggested in
Fig. 9.7., then in the fundamental interval of 2( )j TY e ω the following relation is valid:
( ) ( )2 1
2
1 , for j T j TY e X eq T
ω ω πω= ≤ (9.7)
Expression (9.7) shows that if the two spectra 1 2( ) and ( )j T j TX e Y eω ω are low-pass filtered to
the fundamental interval 2T≤ω π of the lowest clock, in this interval, the spectral content of the two sequences differs only by a scaling factor 1/q.
The condition for spectral equivalence, as described in (9.7), can be assured if the bitstream na and the low-speed high-resolution signal kb are filtered with the same filter with an impulse response ( )h t , such that all frequencies above 2Tπ are ideally completely suppressed. The two sampled versions of the continuous-time impulse response ( )h t are given by 2[ ]h jT and 1[ ]h jT , here 2[ ]h jT is the sub sampled version of 1[ ]h jT .
Fig. 9.8. Serial to parallel converter.
high-speed SDM bitstream
unit delayq
1a
unit delay1
D triggerq
D trigger1
qa
1T
2T
Parallel low-speed data
174 Chapter 9: Decimation via Recursive Bitstream Conversion
The filter 2[ ]h jT operates at the lower sample rate 2T and can be applied to the high-speed signal na without loss of information if all the samples in the bitstream are processed. That can be done at a lower sample rate only if the bitstream is parallelized. The simplest way to perform a serial-to-parallel conversion and a change of the rate of the signal is illustrated in Fig. 9.8. The bitstream is shifted with the high clock frequency through q unit delay cells and is read out as a q bit digital word at the lower clock frequency.
As indicated in Fig. 9.5a, the signals filtered with 1[ ]h jT and 2[ ]h jT can be denoted respectively as 1[ ]x jT and 2[ ]y jT , and are derived via discrete convolutions of the signals na and kb with the corresponding discrete impulse responses. The convolutions are written as:
( ) [ ] [ ]( ) [ ] [ ]
1
2
1 1
2 2
j Tn
j Tk
X e x jT a h jT
Y e y jT b h jT
ω
ω
→ = ∗
→ = ∗ (9.8)
where the symbol * denotes convolution. The convolution summations are developed next,
shifted through “time” intervals k and n with the respective sample periods 1T and 2T :
[ ] [ ]1 1 1nn
x jT a h jT nT∞
=−∞
= −∑ (9.9)
[ ] [ ]2 2 2kk
y jT b h jT kT∞
=−∞
= −∑ (9.10)
In equation (9.7), the spectral content in the base band of the SDM bitstream was equated
with the spectral content of an ideal PCM signal. Consequently, this spectral equivalence can be used to derive a relation between their corresponding discrete sequences in time domain. From (9.7) and (9.8), it follows that expression (9.10) is equal at equidistant time instances
2T to the product of (9.9) and a scaling factor of 1 q :
[ ] [ ]2 2 2 21
k nk n
b h jT kT a h jT nT qq
∞ ∞
=−∞ =−∞
− = −∑ ∑ (9.11)
Expression (9.11) gives a general relation between the two discrete sequences. It has a
practical application when the summations are limited to an arbitrary time interval 2pT that contains p samples of the low sample rate sequence. Respectively, for the same time interval, qp samples from the high sample rate signal are produced. Based on (9.11), the summation that includes p samples of the low sample rate sequence is given as:
[ ] [ ]1 1
2 2 2 20 0
1p qp
k nk n
b h jT kT a h jT nT qq
− −
= =
− = −∑ ∑ (9.12)
Expression (9.12) can be further simplified with the following notations: 1) Because only
the period 2T participates in the expression, it can be normalized to 1: 2 1T = ; 2) The substitutions 1j j→ + and 1p p→ + are introduced as they simplify the formula manipulation. With the help of the above simplifications, expression (9.12) is represented as:
9.3.2. Spectral properties of the REBIC decimation filter 175
[ ] [ ]1
0 0
1( 1) ( 1)p pq q
k nk n
b h j k a h j n qq
+ −
= =
+ − = + −∑ ∑ (9.13)
Expression (9.13) maps the filtered SDM bitstream to a filtered PCM signal with the help
of an arbitrary low-pass system filter such that the spectral equivalence described in (9.7) is satisfied. The filter has continuous-time impulse response ( )h t that has two discrete time versions: 1[ ]h jT and 2[ ]h jT that are equivalent at discrete time intervals corresponding to the low sample rate 2T .
In practice, the SDM bitstream na is known and the system filter impulse response ( )h t can be chosen to fulfill the requirements of a particular system. Then with the help of (9.13), the PCM signal kb can be reconstructed. The reconstruction in fact defines a decimation filter. The mathematical description of this decimation filter can be derived if kb is represented as a function ( )1, [ ]na h nTχ of the bitstream and the system filter. A detailed derivation of the function ( )1, [ ]k nb a h nTχ= is shown in Appendix D. Next, the properties of ( )1, [ ]na h nTχ as a decimation filter are studied and generalized.
9.3.2. Spectral properties of the REBIC decimation filter
The spectral properties of the decimation filter are evaluated in the frequency domain. However, from (9.13), it can be seen that after the development of the convolution summations, the evaluation requires extensive mathematical manipulations. A simpler approach can be applied that avoids the convolution. For example, we can neglect for the moment the discrete-time character and the sub-sampling and treat the signals as continuous time because that allows the application of the Laplace transform. After subsequent sampling, the exact signals can be constructed. The continuous time description of (9.11) is:
( ) ( ) ( ) ( )b t h t a t h t∗ = ∗ (9.14)
with ( ), ( ) and ( )a t h t b t describing the continuous time equivalents of the signals in (9.8).
The signals and b h at the left hand side of (9.14) are in reality discrete sequences (see Fig. 9.4) with time interval 2T and and a h at the right hand side of (9.14) are discrete sequences with time interval 1T that are sub-sampled (decimated) to interval 2T after the convolution of their 1T representation. Therefore, we have to use in the continuous-time processing separate Laplace transforms for the first pair (b and h) while for the second pair (a and h) we have to apply Laplace transform on the combined (convolved) signals. The Laplace transformations then are given as:
( ) ( )LT
b t B s→
( ) ( )LT
h t H s→ (9.15)
( ) ( ) ( )LT
a t h t AH s∗ →
176 Chapter 9: Decimation via Recursive Bitstream Conversion
The third expression in (9.15) shows that the Laplace transform is applied after the convolution of the bitstream with the filter impulse response. The Laplace transform maps convolution on multiplication. After subsequent sampling at interval 2T , the function in (9.15) can be rewritten as:
( ) ( ) ( )*2
02
1 2k
B s B s j k T B sT
∞
=
→ + =∑ π
( ) ( ) ( )*2
02
1 2k
H s H s j k T H sT
∞
=
→ + =∑ π (9.16)
( ) ( ) ( )*2
02
1 2 Ak
AH s AH s j k T H sT
π∞
=
→ + =∑
From (9.14) with the help (9.16), the following relation is derived:
( ) ( ) ( )2 2 20 0 0
2 2 2k l m
B s j k T H s j l T AH s j m T∞ ∞ ∞
= = =
+ + = +∑ ∑ ∑π π π (9.17)
A simplified form of (9.17) with 2s j fπ→ is given by the expression:
( ) ( ) ( )* * *2 2 2AB j f H j f H j fπ π π= (9.18) From (9.18), the low speed, high resolution signal *( 2 )B j fπ can be expressed as a
function of the filter transfer function and the input sequence. The function is defined as :
( ) ( )( )
**
*
22
2AH j f
B j fH j f
ππ
π= (9.19)
where ( ) ( )*2
02 2A
kH f AH j f j k Tπ π
∞
=
= +∑ .
Expression (9.19) can be used for the evaluation of the REBIC properties as a decimation algorithm. Next, the magnitude spectrum of ( )B f is derived graphically. The manipulation of the spectrum in terms of filtering, sampling and equalization is illustrated with subsequent plots of the frequency spectrum.
9.3.2. Spectral properties of the REBIC decimation filter 177
a) b)
Fig. 9.9. Frequency spectra: a) of the high-speed signal ( 2 )A j fπ with signal band component and quantization noise component and the frequency response of the applied low-
pass filter ( 2 )H j fπ ; b) Filtered and sampled output * ( 2 )AH j fπ .
In Fig. 9.9a, the output spectrum of the SDM is shown. The signal band and the quantization noise spectrum of ( 2 )A j fπ are indicated separately. In the same figure, the application of a low-pass filter with frequency response ( 2 )H j fπ is shown. The shaded area in Fig. 9.9a indicates the quantization noise before filtering that is present in the filter frequency band. Fig. 9.9b shows the spectrum after filtering and sampling. The spectra shown in figure Fig. 9.9b represent the right hand side of (9.17): * ( 2 )AH j fπ . The mirror image of the sampled spectrum causes aliasing of the quantization noise in the baseband. In order to arrive to expression (9.19) the spectral manipulations shown in Fig. 9.10 have to be performed. Firstly, in Fig. 9.10a, the magnitude spectrum *| ( 2 ) |H j fπ is shown. The inverse spectrum:
*1 ( 2 )H j fπ that is shown in Fig. 9.10b can be seen as an equalization characteristic that compensates the filtering of a part of the signal spectrum as shown in Fig. 9.9a. The equalized spectrum, however, is deteriorated by the aliased noise in the band. Finally, the spectrum of * ( 2 )B j fπ is shown in Fig. 9.10c and can be seen as a combination of the spectrum from Fig. 9.9b and the spectrum illustrated in Fig. 9.10b.
f
f
Q-noise spectrum
signal band
2
12T
Quantization and aliased noise
* ( 2 )AH j fπ
( 2 )H j fπ
| ( 2 ) |H j fπ
2| A( j πf )|
2
1T
f
f
Q-noise spectrum
signal band
2
12T
Quantization and aliased noise
* ( 2 )AH j fπ
( 2 )H j fπ
| ( 2 ) |H j fπ
2| A( j πf )|
2
1T
178 Chapter 9: Decimation via Recursive Bitstream Conversion
a) b) c)
Fig. 9.10. Frequency spectra: a) of the double sided magnitude response of the system filter; b) of the reciprocal magnitude response of the system filter; c) final equalized
spectrum of the decimated signal * ( 2 )B j fπ .
The derivation of the decimator function and its spectral proprieties was illustrated for an arbitrary low pass system filter. Next, the choice of a particular filter function is described.
9.3.3. System filter characteristics
The development of the REBIC decimation algorithm that was described in Sections 9.3.1 and 9.3.2 was independent of the actual choice of the low pass system filter ( )h t . However, at the beginning of Section 9.3, it has been shown that the analytically defined REBIC decimator will have a very efficient implementation if:
• The system filter is of IIR type because that will result in a good performance with a simple implementation.
• The system filter would allow immediate downsampling of the high frequency bitstream such that the maximum speed signal processing can be minimized.
From Fig. 9.9 and Fig. 9.10, it can be seen that the system filter determines the amount of aliased noise in the baseband, thus the implementation of a high precision decimation requires a steep system filter. On the other hand, due to the equalizing properties of the
*
*
( 2 )( 2 )
AH j fH j f
ππ
*
1( 2 )H j fπ
f
f
f
*( 2 )H j fπ
2
12T 2
1T
*
*
( 2 )( 2 )
AH j fH j f
ππ
*
1( 2 )H j fπ
f
f
f
*( 2 )H j fπ
2
12T 2
1T
f
f
*( 2 )H j fπ
2
12T 2
1T
9.3.3. System filter characteristics 179
overall REBIC transfer, the pass and transition bands of the system filter do not need to be strictly defined. That allows the application of relatively simple filters.
A filter that fulfils the above requirements is a cascade of tapped integrators (Fig. 9.11) where the output of each integrator is multiplied by a weighting coefficient iα .
Fig. 9.11. Cascade of weighted integrators.
The cascade in Fig. 9.11 can be described with the following impulse response:
[ ] [ ] m0
Mm
m
h k u k kα=
= ∑ (9.20)
where [ ]u k is the Heaviside step function and M is the number of integrators included in
the cascade. The impulse response defined in (9.20) can be used directly for the definition of a REBIC decimation structure.
As will be illustrated in Section 9.4 the goal of system filter representation (9.20) is to minimize the number of multiplications that are used for the implementation of the REBIC decimator. In addition, mα coefficients serve as modifiers of each filter branch and, as will be illustrated further on; allow a trade-off between suppression of the high frequencies and REBIC stability. In the extreme case all mα coefficients can be chosen equal to one or zero. When an iα coefficient is chosen to be equal to zero, the respective filter branch is excluded from the overall filter transfer. Such a modification can be applied for the exclusion of the low order filter parts in order realize a more aggressive filter function. When all mα are chosen to be equal to one, the system filter properties are fixed. The resulting impulse response in then given as:
[ ] [ ]0
Mm
mh k u k k
=
= ∑ (9.21)
The impulse response in (9.21) defines ideal integrators, that have a maximum suppression
of the high frequency components and their implementation does not require any multiplication. However, (9.21) defines an unstable filter. The stability of the system filter cannot be addressed properly at this point because what matters is the stability of the REBIC decimator and a stable system filter does not guarantee an overall stable system. In Section
( )A z
( ) ( )H z A z
1α
∑
0α mα
1∫ 2∫ m∫
…
( )A z
( ) ( )H z A z
1α
∑
0α mα
1∫ 2∫ m∫( )A z
( ) ( )H z A z
1α
∑
0α mα
1∫ 2∫ m∫
1α
∑∑
0α mα
1∫ 1∫ 2∫ 2∫ m∫ m∫
…
180 Chapter 9: Decimation via Recursive Bitstream Conversion
9.5.1, the stability of the decimator is evaluated and an efficient way for the realization of a stable REBIC structure based on (9.21) is demonstrated.
As already illustrated in Section 9.3, the system filter participates implicitly in the definition of the REBIC decimation filter. The mathematical steps that are required for the incorporation of (9.20) in the REBIC decimator are given in Appendix D. A possible REBIC implementation is illustrated with the design example given in the following section.
9.4. Design example
The mathematical description of the decimation filter has to be mapped on a hardware architecture. Next, a design example that illustrates this process and the possible design choices is elaborated in detail. For simplicity, a decimation factor 4q = is chosen and the system filter is chosen to be of second order (M=2). Using expression (D.16) from Appendix D, the decimation filter is described with the following equation:
( ) ( ) ( )( )2 2 2
1 1 10 0 0 0
p
m
m m mp m mii p p i pm m m i
b A A b C r− − −= = = =
= + − +∑ ∑ ∑ ∑α α α (9.22)
For the system order defined above, expression (9.22) is expanded as:
( ) ( ) ( )
( ) ( ) ( ) ( )
( ) ( ) ( ) ( ) ( )
0 0 1 1 0 10 00
1 1 1 1 1 1 1 0 1 1 1
2 2 22 2 1 1 0 1 1 1 2 1
2
p
p
p
p p pp
p p p p p
pp p p p p
b
b
b
A b rA
A A b r r
A A b r r r
− − −
− − − −
− − − − −
− + + ++ + = + + − + + + − + + +
ααα
α α α
α α α
(9.23)
where the binomial coefficient miC is different from one only for the term when 2 i=1m ,= . From Appendix D:
( )11 ( 1)
pq q
nn pq
mmp aA p n q
q
+ −
=
= + −∑ and ( ) ( )1 1
0 0
1 ( 1) ( 1)pq p
n kn k
m mmp a br p n q p k
q
− −
= =
= + − − + −∑ ∑ .
Several approaches can be chosen for mapping (9.23) on hardware. Here, each branch that
corresponds to a particular mα modifier is treated separately. Such an approach simplifies the mathematics, and allows the application of a modular design, such that the filter can be easily extended or decreased according to the particular system requirements. For 4q = , M=2 and for time moment 1p = , the 1mA expressions in the first term in the right hand side of (9.23) are written as:
( )7
41
1 2 44 n
n
mm aA n
=
= −∑ (9.24)
The individual 1mA expressions are then expanded as:
9.4. Design example 181
( )( )
( )( )
( )( )
( )
( )
( )
7
4
7
4
7
4
0
4 5 6 7
011
11 4 5 6 7
212 2 2 2
4 5 6 7
1 18 44 4A1 1A 8 4 4 3 24 16
A 11 4 3 28 4 644
nn
nn
nn
a
a
a
n a a a a
n a a a a
a a a an
=
=
=
− + + +
= − = + + +
+ + +−
∑
∑
∑
(9.25)
From (9.25), it can be seen that the first part of the filter uses summations and
multiplications that have a straight forward implementation. The second part in the right hand side of (9.23) can be mapped on a more comprehensible
structure when its mathematical description is done in the z-domain. For example, the following substitutions can be introduced: ( ) ( )
1 10 0 0 1pA z A z z A− −
−= = , ( )
1 1
1( ) pBz B z z b− −
−= = and
( )1 1
1( )m m m pR z R z z r− −
−= = . In the z-domain the second term of (9.23) is described as:
1 1 10 0 0 0 0
1 1 1 11 1 1 1 0 1
1 1 1 1 12 2 2 2 0 1 22
R A z Bz R z
R A z Bz R z R z
R A z Bz R z R z R z
− − −
− − − −
− − − − −
= − + = = − + + = − + + +
α α
α α
α α
(9.26)
The expressions in (9.26) can be regrouped as follows:
( ) ( )
( ) ( )
( ) ( )
1 10 0
1 1 11 1 0
1 1 1 12 2 0 1
1
1
1 2
R z A B z
R z A B z R z
R z A B z R z R z
− −
− − −
− − − −
− = −
= − = − +
− = − + +
(9.27)
The 0R that is derived in the first line of (9.27) is substituted in the second and third lines
of (9.27) and 1R is substituted in the third line, in order to derive:
( )
( ) ( ) ( )
00
011 2
0 02 12 2 2 3
1
1 1
2 21 1 1 1
A BRz
A BA BRz z
A B A BA B A BRz z z z
−=
−−−
= = +− −
− −− −= + + +
− − − −
(9.28)
From (9.22), it can be seen that each output can be represented as a summation of the
weighted direct input and a combined term that contains the history. From (9.23) and (9.28), the REBIC decimator can be represented with the help of (9.28) as:
182 Chapter 9: Decimation via Recursive Bitstream Conversion
( ) ( )( )
( )( ) ( ) ( )
00
11 0
0 1 2 1 2
12 0 01
2 2 2 3
1
1 1
2 21 1 1 1
A z BzA Bz z A BB
z z
A Bz z A B A BA Bz z z z
α
α α α α
α
−
−
−+
− − − + + = + +
− − − − −− + + +
− − − −
(9.29)
The complete description of the decimation filter with discrete-time building blocks can
then be done when the expansions of the individual terms as derived in (9.25) are substituted in (9.23). The substitution results in a z-domain description of the decimation filter. The implementation of this description into building blocks is illustrated in Fig. 9.12.
Fig. 9.12. Third order REBIC, with a decimation factor of 4. The required structural extensions for higher decimation factors are indicated with doted lines in the direct part of the
structure.
The mpA and mR are indicated in the figure. From (9.25) and Fig. 9.12, it can be seen that 4q = consecutive samples of the bitstream are parallelized and down sampled 4q = times to
the lower clock frequency. Each group of 4q = samples is weighted by a set of weighting coefficients. The number of sets corresponds to the order of the chosen system filter. The weighting coefficients depend on the chosen decimation factor q , such that for higher factors the set of weighting coefficients is extended. The core of the decimator is a recursive filter that consists of 1M + branches with 1m + integrators per branch.
22
1
2
3
4
11
22
33
44
S
…
S
…
z-1na
z-1 z-1
∞ ∞ ∞ ∞
z-1
∞
…
1
4
9
16
11
44
99
1616
S
1 16α
11z−
11z−
-+
2 16α
2 64α
0 4α
1 4α
2 4α
+-
+-
+-
-+
-+
SS 1z
z−1z
z−
11z−
11z−
11z−
11z− S 1
zz−1
zz−
11z−
11z−
0α0α
S B
21,A α
22,A α
11,A α
00,A α
10,A α
20,A α
1z−1z−1z−
1z−1z−1z−
2α 2α
1α1α
0R
1R
2R
0A
1A
2A
Serial to parallel converter
9.5. Evaluation of the decimator characteristics 183
The recursive part of the filter described in Fig. 9.1 is not canonical and can be further simplified. Here we preserve the structure as algorithmically derived in order to show the possible extensions for higher order filters and the possibility to modify the filter transfer with the mα coefficients.
9.5. Evaluation of the decimator characteristics
From system perspective the derived decimator structure and its possible extensions have to be evaluated with respect to stability boundaries of operation, the achievable decimation ratios and the impact of the order of the system filter.
9.5.1. Evaluation of stability Due to its recursive character, the stability of the REBIC decimation filter is not
guaranteed and its evaluation should be incorporated in the design process [ 62]. From Fig. 9.12, it can be concluded that the recursive path of the filter is not directly influenced by the decimation factor and can remain unaltered for a broad range of decimation factors, as far as the system filter and the recursive path provide enough aliasing suppression for the specific system. That also means that the stability is not influenced by the particular choice of decimation factor. On the other hand, the order of the chosen system filter and the particular implementation of the recursive path introduce the possibility for instable operation. Here, the stability of the example described in Fig. 9.12 is evaluated and then conclusions for the general case are drawn. The stability can be evaluated from the poles of the closed-loop transfer function described in z-domain. With respect to the iα coefficients, the recursive part of the implementation in Fig. 9.12 can be divided into three individual closed-loop branches (without the summation point for kb ) or treated as a single third order structure that combines all individual branches. The stability of the individual branches does not guarantee stability of the whole block. Yet, the three branches are investigated individually, because of the option to simplify the filter by choosing one or more of the iα coefficients to be zero and thus removing the respective branch from the filter. The stability of the complete system can be decided from an evaluation of the complete transfer characteristic. Next, both approaches are explored.
The three branches have open-loop gains described respectively by the expressions (9.32), (9.34) and (9.36), given in the second column of Table 9.1. The stability of each branch can be established separately, from the poles of the respective closed-loop transfer functions. The poles are given by the general expression:
( ) ( ) 0D z N z− = (9.30)
where ( ), ( )D z N z are respectively the denominator and the numerator of the open-loop
transfer functions. The stability of each branch, can be established from the roots of expressions (9.33), (9.35) and (9.37), given in the third column of Table 9.1. For a stable filter the poles described by (9.30) should be inside the unit circle. If we denote the roots of (9.30) as irt , the filter parameterization is stable if:
( ) 1iMagnitude rt < (9.31)
184 Chapter 9: Decimation via Recursive Bitstream Conversion
As the roots of (9.30) might be complex, the magnitude of the roots has to be evaluated. The stable range of the filter parameters can be easily evaluated graphically with a plot of
( )iMagnitude rt with respect to the mα coefficients. An example for the stability evaluation of the third order branch is given in Fig. 9.13.
Fig. 9.14. Stability region of the third order branch.
The boundaries for each iα coefficient that guarantee the stability of the respective branch are shown in the last column of Table 9.1. The iα coefficients modify the positions of the poles of the closed loop transfer function such that for a stable system all of them remain inside the unit cycle. The penalty of the stabilization with the iα coefficients is in the introduction of a non-integer multiplication that increases the required length of the digital word. The increase depends on the precision with which the iα coefficients are implemented.
Table 9.1, Evaluation of stability with respect to the system order (SO), where SO=3’ stands for the complete 3rd order REBIC structure
(9.32) (9.33) (9.34) (9.35) (9.36) (9.37) (9.38) (9.39)
3’
3
2
1
Stability Condition
Determination of closed loop poles
Open loop transfer functionSO
3’
3
2
1
Stability Condition
Determination of closed loop poles
Open loop transfer functionSO
0
1zα
−−
( )1
21zα
−−
( )
22 2 2
3
4 31
z zz
α α α− +−
−
( )( )
20 2 0 1 2 0 1 2
3
( 4 ) 2 3
1
z z
z
α α α α α α α α+ − + + + + +−
−
01 0z α− + =
212 1 0z z α− + + =
( )( ) ( )
3 22
2 2
3 4
3 1 1 0
z z
z
α
α α
− + +
+ + − + =
00 2α< <
unstable
22 13
α< <
( )( )
3 22 0 2
1 0 2 1 0
3 4 3(1 3 )
3( 2 ) 1 0
z z z
z
α α α
α α α α α
− − − + − −
− + − − − − =
0
1 2
0 1
αα α
< ++ + ≤
9.5. Evaluation of the decimator characteristics 185
Expression (8.39) defines the open-loop transfer ( )G z of the complete recursive part. If the poles in ( )G z are relatively close to the zeros the system response tends towards first order. For 0 10, 0α α≠ = , the transfer function has two real poles, positioned far from the zeros. In this way, a more aggressive decimation filter can be achieved. A more aggressive transfer function can be achieved for 0 0α = , however, the system should be stabilized with a small coefficient 1 0α ≠ , such that a stable filter is realized.
An alternative simpler way to stabilize the decimator that uses only a third order branch ( 0 1 20, 0, 1 α α α= = = ) is shown in Fig. 9.15. A coefficient 0< <2ρ is introduced as shown in Fig. 9.15. For <2ρ , the system is stable. Ideally, ρ should be close to two, in order to provide the most aggressive filter. However, the choice of ρ requires an investigation of the particular hardware implementation and is discussed further on.
Fig. 9.15. Stabilized third order structure 0 1 20, 0, 1 and <2α α α ρ= = = .
In this sub-section it was shown that there are several design options to assure the stability of the REBIC implementation. A stable REBIC implementation can be achieved by introduction of pole/zero modifiers ( i , α ρ ) into the transfer characteristic of the recursive part that shift the poles of the stability determining equation (9.30) inside the unit circle.
The modifiers require multiplication and complicate the hardware implementation of the algorithm as they require an increase of the digital word.
Here, it was also pointed out that special attention has to be paid that not only the stability of the individual branches is assured but of the whole recursive part of the decimators as well.
9.5.2. Ideal system evaluation In this sub-section the performance of the derived decimation filter is evaluated with high-
level simulations. A fourth order SDM is used as a test case. The dynamic range in 5MHz bandwidth is evaluated for a -3dB FS signal and oversampling ratios from 20 to 100. The
r
1
2
3
4
S
S
z-1na
z-1 z-1
∞ ∞ ∞ ∞
1
4
9
16
S
11z−
1 16
1 64
1 4
+-
+-
+-
SS 1z
z−
11z−
kb1A
2A
0A
1z−
rr
1
2
3
4
11
22
33
44
S
S
z-1na
z-1 z-1
∞ ∞ ∞ ∞
1
4
9
16
11
44
99
1616
S
11z−
11z−
1 16
1 64
1 4
+-
+-
+-
SS 1z
z−1z
z−
11z−
11z−
kb1A
2A
0A
1z−1z−
186 Chapter 9: Decimation via Recursive Bitstream Conversion
performance of the modulator is evaluated by spectral analysis of the output bitstream. The bitstream that is produced by the SDM is processed with a third order REBIC decimator, shown in Fig. 9.15, with =1.5ρ and decimation factors of 4, 8 and 16. The transient output of the REBIC decimator is evaluated via spectral analysis. The results from the evaluation are shown in Fig. 9.16.
Fig. 9.16. Comparison of the simulated performance of SDM bitstream and
decimated by 4, 8 and 16 PCM signal.
The REBIC output spectra for OSR=100 and the three studied decimation factors are shown in Fig. 9.17. From Fig. 9.16 and Fig. 9.17 can be concluded that:
• Third-order REBIC decimation by factors 4 and 8 is not introducing any noise or distortion in the signal and the precision of the original bitstream is fully preserved for a very large range of oversampling ratios and dynamic range of the input signal. A loss of 4dB is introduced for the decimation by 8 and the highest studied OSR (and dynamic range). This loss is due to the truncation of the ρ coefficient, that decreases the suppression of the decimation filter. This effect can be observed only for very high dynamic ranges and decimation factors.
• For a decimation factor of 16, the performance of the decimator sharply decreases. This can be explained with the folding of aliasing components into the baseband, as already illustrated in Fig. 9.9 and Fig. 9.10.
• The third order system filter is insufficient to prevent aliasing in the signal band for decimation factors of 16 and higher. When such a decimation factor is required, the order of the system filter has to be increased.
In Fig. 9.17, the REBIC decimated spectra of a third order system that implements decimation factors of 4, 8 and 16 are shown. For low decimation factors the signal processing is faultless. However, for q = 16, the performance is significantly degraded due to the quantization noise aliased in the band of interest.
9.5.2. Ideal system evaluation 187
Fig. 9.17. Comparison of the third-order REBIC output spectrum for q = 4, 8 and 16.
9.6. Hardware implementation
The analysis and evaluation presented so far use the algorithmic implementation of the decimation filter built with ideal building blocks. An important aspect of the decimator design is the implementation of the ideal model with digital logic that is constrained by the technology limitations. Moreover, every real design is constrained by the available hardware resources in terms of chip area and power consumption as those determine the cost of the design. The goals of the hardware implementation that is studied in this sub-section can be summarized as:
• Study of the possible design choices for the digital hardware implementation of the functional blocks described in the previous section.
• Evaluation of the actual hardware resources that are needed for the implementation of REBIC decimators with different decimation factors and with different precision. The impact of the finite length of the digital word that can be practically implemented is established.
• The technological portability of the algorithm is evaluated. The main concern in that respect is the impact of the possible speed critical paths in the structure that may limit the application of the algorithm for higher clock speeds.
The hardware implementation of REBIC was investigated in a prototyping environment for digital hardware: Xilinx System Generator. The third order stabilized REBIC decimation filter from Fig. 9.15 was constructed and studied in detail. A third-order, decimator by 8 was implemented into a Virtex Xilinx FPGA and measured. The ideal structure given in Fig. 9.15 was implemented into real hardware blocks. The three functional blocks in Fig. 9.15: the serial to parallel converter, the direct part and the recursive integrating part are shown in Fig. 9.18. The resolution of the digital signal at the inputs and outputs of each block is indicated. The direct part has output word length 1wl and the integrating part has output word length 2wl .
188 Chapter 9: Decimation via Recursive Bitstream Conversion
Fig. 9.18. Block diagram of the hardware implementation. The S/P is implemented according to Fig. 9.8 and produces q downsampled outputs. Thus
the only high frequency operation that is performed in the decimator is a q-times shift of the bitstream. The S/P conversion is not critical in terms of timing, because for the parallel conversion, the data is resampled with q-times lower clock speed. The direct part of the REBIC algorithm requires multiplications with predetermined coefficients. The number of those coefficients (NC) depends on the decimation factor q and the order M of the loop filter, and can be evaluated by the expression:
( 1) 1NC M q= − − (9.40)
The value of NC increases linearly for higher q factors and system filter order. For
decimation factors that are a power of two, each multiplication can be easily replaced with a simple shift and a summation.
Pipelined LUT The coefficients in the direct part have to be implemented within a digital word with a
finite length ( 1wl ). The required resolution of the coefficients determines 1wl . The word length increases for higher q factors because of the higher coefficient resolution that have to be implemented. Thus higher decimation factors require a larger ROM with more depth.
The multiplication with a limited number of precalculated coefficients can be efficiently implemented with a look-up-table (LUT). For a particular decimation factor, the LUT can be implemented with a single hardware block. Alternatively, pipelined LUTs can be used (see Fig. 9.19).
Fig. 9.19. Pipelined implementation of the LUT.
S/P converter
Pipelined LUTS
Integrating part 1 q
wl1
wl1
wl1
wl2
S/P converter
Pipelined LUTS
Integrating part 1 q
wl1
wl1
wl1
wl2
9.6. Hardware implementation 189
The main advantage of pipelining is the introduction of modularity in the design such that the LUT can be easily extended to accommodate high q factors. In addition the pipelined LUT is easily synchronized and the stored coefficients can be extracted simultaneously, without timing uncertainties. The construction of the pipelined LUT is demonstrated in Fig. 9.19. Each doubling of the decimation factor doubles the number of LUT cells and adds a summation that increases the required word length by one. The summations are synchronized with the clock. That is why the pipelining introduces some initial delay (latency) in the filter. The initial latency in terms of clock periods corresponds to the level of pipelining.
It is important to initialize the registers in the pipeline with zeros, in order to avoid fault results from the integrating part during the latency phase.
The realization of the direct part with pipelined LUTs assures correct operation irregardless of the size of the pipeline and the decimation factor.
Integrating part The integrating part consists of summators, discrete time integrators, unit delays and
multipliers. Again, the multipliers are realized through shifting and adding/subtracting. In the ideal block diagram in Fig. 9.15, two types of discrete integrators are present. Forward Euler integration defined by ( )1 1z − that can be implemented with the block diagram in Fig. 9.20a,
and Backward Euler defined as ( )1z z − and implemented with the block diagram shown in Fig. 9.20b.
Fig. 9.20. Hardware implementation of discrete time integrators: a) Forward Euler and b) Backward Euler.
Fig. 9.21. Implementation of non-integer ρ coefficient.
The stabilization coefficient ρ as derived in Section 8.5.1 is also realized in the integrating part. It can be implemented with shifting and subtracting as shown in Fig. 9.21.
b)
a)
ρ
190 Chapter 9: Decimation via Recursive Bitstream Conversion
Each shift, however, requires enlargement of the incoming word. That is why the precision of the implementation of ρ should be decided with respect to the dynamic range of the input bitstream.
The studied third order REBIC has only three integrators and can be very easily and efficiently implemented. The length of the digital word in the integrating part ( 2wl ) increases due to the recursive character of the algorithm. That is why the length of the digital word has to be truncated to a value, that is a trade-off between the acceptable degradation of the performance and the available storage capacity.
The number of bits in the truncated digital word should be equal or higher than the resolution in bits of the SDM bitstream that is processed with the REBIC decimator.
The performance of the hardware implementation of the decimator was evaluated on two levels. Firstly, the implementation was simulated on structural level without the timing limitations of the actual technology. This evaluation established the impact of the finite word length on the performance of the decimator and verified the required hardware resources.
Secondly, the decimator was implemented in a Virtex FPGA chip. The main limitation of the implementation was the maximum clock speed of operation of the FPGA of 100MHz, that limited the applicable input bandwidth .
The FPGA implementation allows for fast digital prototyping and evaluation. However, several drawbacks of an FPGA implementation have to be pointed out:
• The design uses built-in blocks: registers, accumulator, scalers and adders. Those are optimized for programmability and reusability and not for area and power. Thus the area that is used remains hidden for the designer.
• The speed of the circuit implemented within an FPGA is significantly lower than an optimized dedicated implementation. That is due to the routing and placing algorithms that fit the design into the dedicated FPGA resources.
Benchmarking Though the FPGA implementation cannot demonstrate the full potential of the REBIC
decimator, it allows for a better comparison with other decimation techniques with the help of the arguments pointed out in Section 9.2. Due to the immediate downsampling, the recursive filter structure with built-in equalization and the very low number of multiplications, the REBIC decimator requires significantly lower power and area than the most widely used decimators (typical examples are [79], [80], [81]), especially for higher (q > 4) decimation factors. For the decimation of very high accuracy bitstreams, the stability of the higher order REBIC implementations requires a special attention and can be guaranteed only with coefficients’ adjustments. That in turn requires one or more multiplications and increases the digital word-length. For those specific cases, a fair comparison with other decimation techniques is possible only in the context of particular design specifications.
9.7. Conclusions
In this chapter the theoretical fundaments and the practical implementation of a REBIC decimation filter were evaluated in detail. The theory of the forward REBIC was generalized. Special attention was given to the algorithmic derivation of the decimation structures, the stability of higher order decimators and the constrains in the practical hardware implementation.
It was shown that the REBIC decimator is a powerful signal processing approach that has a very efficient implementation in terms of area and power. REBIC algorithmic complexity pays off with its very simple and robust implementation.
10. Chapter 10
Design examples This chapter treats the transistor implementation and the evaluation of the prototypes of
several building blocks and ADC implementations studied in the previous chapters. Firstly, the implementation of the V-I converter studied in Chapter 8 is discussed. Secondly, the implementations of a first and second order ASDM discussed in Chapters 4 and 5 are elaborated. Then, two SDM designs are described that take advantage of lower limit cycle modes in order to achieve high efficiency and robustness. The first SDM is based on second-order feedback topology, while the second one uses a 5th order feed-forward implementation.
The V-I converter, the ASDMs and the second order SDM are prototyped in a standard digital 0.18 mµ CMOS technology. The 5th order SDM is prototyped in standard digital 90nm CMOS process. The most relevant measurement results for each implementation are provided and conclusions are drawn.
10.1. V-I converter design
A stand alone V-I converter described in Chapter 8 has been fabricated in a standard 0.18 mµ five metal digital CMOS process [63], [64]. The resistors are implemented in the n+ POLY layer. The occupied area is less than 0.02mm2 and 200µA are consumed from a 1.8V power supply.
The target application was an input stage of a CT SDM with signal bandwidth of up to 5MHz and resolution of up to 12 bit and with minimal power consumption. These requirements determine the required noise levels and linearity of the V-I converter such that the SNR, the THD and the SFDR should be at least 72dB in the application bandwidth.
The theoretical study in Chapter 8 showed that the V-I converters based on a combination of linearization techniques can achieve a significantly higher linearity without penalty in the power consumption. That is why a V-I converter that uses simultaneously cross-coupling and resistive degeneration was implemented.
10.1.1. Circuit description and layout
The circuit implementation is shown in Fig. 10.1. The core of the V-I converter is implemented with the input transistors M1 to M4, the degeneration resistors R1 and R2 and the tail current sources M5 to M8. As elaborated in Chapter 8, those transistors are determining the basic performance parameters of the V-I converter implementations.
The input pairs are loaded with cascaded current sources M9 to M12. Transistors M13 to M19 implement a common mode feedback that tracks the variation of
the output common mode voltage via M13 and M14 such that the difference between the two output nodes is transformed into a current that via the cascoded current mirror M15, M16 and M17 gives the reference current that is copied into the active load transistors of the input pair M19, M19 and M10.
192 Chapter 10: Design Examples
The parameterization of the transistors was discussed in detail in Chapter 8, here special attention is given to the measurement results.
Fig. 10.1. Detailed circuit schematic.
In Fig. 10.2 the chip photograph of the standalone V-I converter is shown. Special attention is paid to the layout in order to assure equal electrical and mechanical environment of the transistors in the core transconductor. For the purpose, dummy structures have been extensively used.
The output of the converter is directly connected to standard analog I/O cells.
Fig. 10.2. Chip photograph.
M9 M10
M11 M12
M13
M14
M15
M16 M17
M18
M19
M20
M21
M3 M1 M2 M4
M7 M5 M6 M8
M9 M10
M11 M12
M13
M14
M15
M16 M17
M18
M19
M20
M21
M3 M1 M2 M4
M7 M5 M6 M8
10.1. V-I converter design 193
10.1.2. Measurement set-up
The performance of the V-I converter was measured via static and dynamic measurements of the transconductor characteristics.
The dynamic performance of the V-I converter was evaluated with the measurement setup shown in Fig. 10.3. The output of the signal generator (SG) was low-pass (LP) filtered in order to assure spectral purity of the input signal. At the input and at the output, respectively, single-ended-to-differential (SE_to_DIF) and differential-to-single-ended (DIF_to_SE) conversion of the signals was done via transformers. The output signal was measured with a spectrum analyzer (SA) in a low-distortion mode. The evaluation of a stand-alone V-I converter is complicated due to several limitations of the implementation and the available measurement equipment. These limitations can be summarized as follows:
• Very low level of the V-I converter output signal. This low level is due to the direct application of the V-I converter output to the I/O ring without special buffers. The measurements were performed by converting the difference between the two output currents into a voltage across an external resistor and this voltage was then measured. For a correct evaluation, the external resistor was chosen small with respect to the output impedance of the stage, so that the operation of the circuit is not influenced. A 10k Ohm resistor was used whereas the output impedance of the V-I converter is approximately 1.5M Ohm.
• A limited bandwidth of the setup due to the capacitive load built-up by the I/O ring and the packaging. This load was estimated to be in the order of 2pF. Again this problem is emphasized by the lack of special output buffers and limited the frequency range of operation to approximately 15MHz.
• The limited dynamic range of the spectrum analyzer in a low-distortion mode limited the resolution of measurement setup to 78dB. This resolution determined the level of spurious and distortion components that can be detected.
• The linearity of the input and output transformers Fig. 10.3 is below 75dB for the measured frequency range.
Fig. 10.3. Setup for dynamic measurements.
10.1.3. Experimental results
Fifteen ICs from a single batch were evaluated via static and dynamic measurements.
10.1.3.1. Static measurements Via a static measurement, the output signal as a function of a DC sweep of the input
voltage was established. The measurement was done with a high precision digital multimeter in differential mode.
SGV-I BIAS
SA
LP
SE_to_DIF DIF_to_SE
194 Chapter 10: Design Examples
For a quantitative evaluation, the Integral Nonlinearity (INL) was calculated. The measured V-I characteristic was subtracted from an ideal straight line generated via a Least Mean-Squared (LMS) fit. The results are summarized in Table 10.1.
Table 10.1. V-I converter static performance
10.1.3.2. Dynamic measurements
For a full-scale 400mVpp, 4.9MHz input signal an SFDR of 75dB was measured, see Fig. 10.4.
Fig. 10.4. Measured SFDR with 4.9MHz sine input signal in a frequency band between 4.8MHz and 15MHz.
This SFDR is determined by the second harmonic distortion component as stated above. The third harmonic is 1 to 3dB lower than the second harmonic in all measured samples. The distortion behavior with respect to the frequency of the input signal is plotted in Fig. 10.5. The measured SFDR is almost flat up to approximately 10MHz. For higher frequencies the SFDR starts to decrease, mainly due to the attenuation of the signal component. In turn, both even and odd order harmonics start to increase mainly due to the different frequency behavior of the larger main differential pair and the smaller supplementary pair. That deteriorates the effectiveness of the harmonic suppression.
SFDR=75dBSFDR=75dB
INL, [%FS]FS
0.6600mV
0.1400mV
0.08200mV
Maximal Measured INL% Full Scale
INL, [%FS]FS
0.6600mV
0.1400mV
0.08200mV
Maximal Measured INL% Full Scale
10.1. V-I converter design 195
Fig. 10.5. SFDR with respect to the frequency of the input signal at 400mVpp.
Table 10.2. Summary of the measured performance of the V-I converter
The measurement results summarized in Table 10.2 show that the V-I converter achieves comparable performance in terms of SFDR and bandwidth with the best reported implementations (see comparison tables given in [45] and [47]) and at the same time has approximately four times lower power consumption.
10.1.4. Conclusions
A transconductor design was prototyped that achieves an SFDR of 75dB and SNR of 70dB in 8MHz bandwidth for a differential input signal of 400mV peak-to-peak in 1.8V CMOS technology with total power consumption of 360µW. The utilized linearization principle allows for a simultaneous suppression of third and fifth-order harmonic components in the V-I characteristic with only 25% decrease of the transconductance of the basic differential pair. Due to the flat optimal parameterization the circuit is relatively robust to process spread and temperature variations.
The design confirmed that the combined application of linearization techniques leads to a significant linearity improvement with an acceptable small area increase. A boosting of the output current can facilitate the measurement of the stand-alone V-I converter and show the full potential of the presented technique.
200mACurrent Consumption
70dBSNR [1k-8MHz]
75dBSFDR [0-10MHz]
400mVVin,PP
<0.02mm2Area
1.8VSupply Voltage
0.18mm, CMOSTechnology
200mACurrent Consumption
70dBSNR [1k-8MHz]
75dBSFDR [0-10MHz]
400mVVin,PP
<0.02mm2Area
1.8VSupply Voltage
0.18mm, CMOSTechnology
196 Chapter 10: Design Examples
10.2. High performance ASDMs
In Chapters 4 and 5, the properties of ASDMs with a binary quantizer are studied. Here their transistor implementation is treated and the measurement results from the manufactured prototypes are described and analyzed.
The circuit implementations and the trade-offs in the design are discussed (see also [66], [67] and [71]) for first and second order ASDMs ( 1ASDM and 2ASDM ) that use a binary quantizer with hysteresis. The targeted performance of 75dB SINAD in 8MHz frequency band is determined by the HDSL front-end specifications.
As described previously, the ASDMs sustain asynchronous LC oscillations for zero input. Here, the oscillation frequency cf is addressed as the main design parameter that determines the spectral properties of the ASDM output signal and consequently the quality of the amplitude-time transformation. The analytical and graphical derivations of the LC frequency that were described previously are used for the definition of the required circuit parameterization. The impacts of the filter order and the properties of the non-linear element on the LC mechanism are elaborated and taken into account. The ASDMs transistor implementations and layout are described, the design choices and the trade-offs in the transistor parameterization are pointed out. Measurement results are presented and conclusions are drawn.
10.2.1. Implementation of first and second order ASDMs
Expression (10.1) that was derived in Chapter 5, gives a relation between the properties of the linear part of the ASDM loop ( )L jω and the binary quantizer with hysteresis being the chosen type of quantizer. The equation is valid for ASDMs that exhibit LC oscillations.
( )1,3,5...
1 Im /4
∞
=
= + − ∑ ck
hL jkk
πω (10.1)
Here expression (10.1) is used as a starting point for the construction of two ASDMs and
for the parameterization of their transistor implementations. The exact frequency of the LC can be determined for a particular filter choice. Due to the presence of a hysteresis, LC oscillations are possible in an ASDM implementation with a first order loop filter. Loop filters of first ( ( )1L jω ) and of second order ( ( )2L jω ) are defined respectively as follows:
( ) ( ) ( )( )( )
1 21 2
1 2
+= =
+ + +p z p p
p p p z
jL j L j
j j jω ω ω ω ω
ω ωω ω ω ω ω ω ω
, (10.2)
The DC gain of ( )1L jω and ( )2L jω in (10.2) is normalized to 1 and for the second order
system two different poles 1 2p p ω ω, and a zero zω are introduced. The above filter definitions are substituted in equation (10.1) and the LC frequency is calculated (see Chapter 4) in both cases as:
10.2. High performance ASDMs 197
1 21 22 2= =p p p
c cz
h h
ω π ω ω πω ωω
, (10.3)
As illustrated in Chapter 3, the second order filter with two poles and a zero can be
implemented with a feedback topology. A fully differential implementation of the second-order ASDM is described with the block diagram shown in Fig. 10.6 and uses mg C− stages as CT integrators in a feedback loop topology. A block diagram for the first order ASDM is derived from the block diagram for the second order ASDM, when the blocks with index 2 are omitted. The stages 1mg and 2mg are transconductors that, together with the capacitances
Int1C and Int 2C , implement the CT integrators. The blocks 1,2FB represent the feedback transfer,
1,2A are gain stages and BQh is a binary quantizer with hysteresis h .
Fig. 10.6. Block diagram of first and second order ASDM
For the system described Fig. 10.6, expressions (10.3) are rewritten for the LC frequencies of the first and second order transistor implementations of the ASDM, as follows:
1 1 1 2 1 21 1 2 1 2
1 1 22 2= =m m m
c cInt Int Int
A g A A g gFB FB FBhC hC C
π πω ω, (10.4)
From (10.4), it follows that the LC frequency can be controlled via the hysteresis value, the
gain in the feed forward path of the loop and the frequency characteristics of the loop filters. As already stated, a sufficiently high LC frequency is a very important parameter for the
realization of a high performance ASDM. The LC frequency has to exceed significantly the signal band of interest in order to avoid the appearance of the LC spectral components (spurious tones) in the signal band. In Fig. 10.7 the achievable SFDR is evaluated in the 3µ frequency band ( : input signal frequencyµ ) for two orders of the loop filter as a function of the ratio cω µ between the input signal frequency and the LC frequency. From the figure, it can be concluded that for the target HDSL specifications, an cω of at least 120MHz is needed for both first and second order ASDMs.
- +
+ -
- +
+ -
+ -
- +
+ -
- +
- +
+ -
- +
+ -
- +
+ -
- +
+ -
-+
+ -
-+
+ -
-+
+ -
-+
+ -
+ -
- +
gm1 gm2A1
A2
FB1
FB2
CInt1 CInt2
Vi Vout
BQh
198 Chapter 10: Design Examples
Fig. 10.7. Estimation for the achievable SFDR for first and second order ASDM at 80% MD in a frequency band 3m. The plot is normalized with respect to the center
frequency of the LC and input frequency m.
At system level, cf is controlled via the loop filter properties, the gain in the loop, and the hysteresis levels of the quantizer. However, every transistor implementation is introducing additional limitations as finite bandwidth, nonlinearity and noise, and cost factors like chip area and power consumption. Next, these factors are discussed for each circuit building block and their impact on the system behavior is evaluated.
In Fig. 10.8 the implemented, fully differential circuit schematic of the first order ASDM is shown. The Common Mode Feedback (CMFB) circuits and the biasing circuits are omitted for simplicity.
Fig. 10.8. Circuit schematic of the first order ASDM (a) input V-I converter, (b) mg stage; (c) integrating capacitances, (d) feedback, (e) broad band amplifier, (f) quantizer with hysteresis, (g) output buffer with 50 Ohm driving capability.
The output buffers (only the last stage is shown in Fig. 10.8g) are out of the loop and are needed only to provide the high driving capability required by the measurement setup. They
Out
Feedback
Bias Cntr
Bias
Bias(a) Bias
(c)
(e)
(d)
(f) (g)
In
(b)
Out
Feedback
Bias Cntr
Bias
Bias(a) Bias
(c)
(e)
(d)
(f) (g)
In
(b)
CINT
Mq
Vdda1 Vdda2
wc/m
10.2. High performance ASDMs 199
were implemented as a chain of matched blocks with a separate power supply and 50 Ohm driving capability.
10.2.1.1. Design of loop filter and gain stages
The mg C− integrators are chosen for the implementation of the ASDM loop filters due to their speed advantage and low power consumption [65]. An important observation from Fig. 10.6 is that the first transconductance stage m1g is outside the modulator loop and as a result its non-idealities are not suppressed by the loop mechanism. That is why the performance of this stage determines to a great extent the dynamic range, the SNDR and the bandwidth of the whole ASMD and consequently demands a careful design. The most significant challenge in its implementation is the realization of a large input dynamic range with high linearity. The V-I converter that is described in the first section of this chapter is used in the implementation of the integrators (Fig. 10.8(a)). In order to improve the noise performance, the stage is significantly up-scaled such that the flicker noise energy in the base-band is decreased below the noise specifications. The increased transistor sizes also provide for a better matching and as a result for a better signal differentiality and overall robustness of the linearization mechanism. In 1ASDM , m1g occupies half of the chip area and consumes almost half of the current.
The second transconductor m2g is inside the loop, where the amplitude information of the input signal is already positioned in the zero crossings (in time) of the LC oscillations. Thus the ASDM operation is much less sensitive to the static amplitude distortion introduced inside the loop. However, care is taken that no clipping would occur. The clipping is introducing non-linearity that is changing the loop transfer and leads to a decrease of the frequency of the LC oscillations.
The linearity and noise specifications for the m2g and the gain stages are significantly decreased. These are downscaled and altogether consume less than 20% of the total power used in the second order implementation. However, care is taken that no clipping would occur at any point inside the loop.
As elaborated in Chapter 5, a linear gain in the feed-forward path is in fact decreasing the effective hysteresis value and can be used as an additional instrument to achieve a higher LC frequency cf . Here such gain is added in the ASDM implementation in order to relax significantly the requirements towards the quantizer by allowing a larger hysteresis and hence save power that otherwise should be invested in the speed of the comparator regeneration. However, the gain stages 1,2A add, via their parasitic poles, an additional phase delay in the loop. In order to prevent a change in the system order, the parasitic poles of the gain stages should be well beyond the frequency of operation. The bandwidth limitation allows the utilization of a relatively small gain. The optimum between gain and bandwidth is then solved by trying to keep the lowest possible current consumption. For the particular design, a gain of 15dB in a band of 300MHz is implemented in 1,2A .
200 Chapter 10: Design Examples
10.2.1.2. Design of feedback
In practice 1,2FB are implemented as switched-current sources (Fig. 10.8d), such that the switches are controlled by the binary output signal. The feedback current is matched to the feed forward current such that an approximately 80% modulation depth is implemented when a maximum input signal is applied. The maximum input signal is chosen after the evaluation of the linear dynamic range of the first stage and with respect to this DR the feed forward and feedback currents are dimensioned such that for a maximum input signal the feedback current is exceeding with 20% the feed forward current.
The 1,2FB blocks have a twofold operation: firstly, they transfer the output voltage into a
current that is integrated in Int1C and secondly a scaling of the feedback signal is performed such that the maximum dynamic range of the loop is corresponding to the maximal linear dynamic range for input transconductance m1g . The loop is dimensioned for peak performance for about 80% modulation depth. For signals with higher amplitude the loop enters its overload region and the harmonic content in the base-band is rapidly increasing. In Fig. 10.8 the transistor implementation of the first-order ASDM is shown. For the second-order ASDM, the same building blocks m1g , 1A and comparator are used. The comparator is implemented via a cascade of differential pairs with a cross-coupled load that introduces positive feedback (only the first from two identical blocks is shown in Fig. 10.8(f)). The m 2g ,
2A blocks have the same structure as their counterparts in the single loop but are optimized for higher gain and bandwidth. Output buffers with a high driving capability are used in order to facilitate the measurements.
10.2.1.3. Design of asynchronous BQh
The BQh is implemented as an asynchronous comparator with positive feedback. As said, the comparator is a cascade of source-coupled differential pairs (only the first from two identical blocks is shown in Fig. 10.8f). The first comparator stage is making a decision for the polarity of the input signal. The second one increases the rise and fall times of the signal and implements high driving capability. A hysteresis can be introduced in the comparator via a proper parameterization. The static hysteresis value is given by the equation:
bias
q q
I 1=2W /L 1H
ox
VC
δµ δ
−+
(10.5)
where the feedback coefficient cc dc= (W/L) (W/L)δ is the ratio between the cross-coupled
and the diode-connected transistors, biasI is the tail biasing current and W/L is the ratio of the width and the length of the input pair. For >1δ , the load acts as a negative resistance and hysteresis is introduced [38]. For 1δ < the stage acts as an amplifier.
The design of the comparator should resolve the following tradeoffs: • The value of HV should be small, especially for 2ASDM in order to achieve the
desired frequency of the LC oscillations.
10.2. High performance ASDMs 201
• However, from expression (10.5), it follows that the implementation of a small HV requires an increase of the power consumption or a decrease of the transistor sizes.
• Small transistors, however, suffer from higher mismatch and susceptibility to process variations. In order to assure regenerative operation in the process corners an additional increase of the power consumption is required.
Fig. 10.9. Layout of a first order ASDM.
The overall symmetry and a short propagation of the loop are mandatory in order to minimize the impact of the layout introduced parasitics.
10.2.1.4. Performance limitations and tradeoffs
The performance of the ASDM is defined as the maximum frequency band that can be processed within the linearity specification. On one hand the performance is determined by the maximum LC frequency that can be achieved. For a design that is robust with respect to process spread and temperature variations the LC frequency can be pushed higher with higher gain in the feed-forward path. That would result in an increase of the required power consumption. On the other hand the quality of the gm-C filter implementation determines the quality of the conversion in the base-band, with respect to SFDR and SNR. Again the performance can be improved with higher power consumption. The implemented circuit solution tries to resolve these tradeoffs for a bandwidth of 12MHz dictated by the HDSL front-end specifications.
Integration
capacitance
Asynchronous
comparator
Output
buffer
AmplifierCT filter
202 Chapter 10: Design Examples
10.2.2. Experimental results
The ASDM has an analog broadband output signal that ideally has only two amplitude levels but with transitions in time occurring with the period of the LC. The properties of such a signal can be established via measurements of its spectrum with a spectrum analyzer. The performance of the manufactured 1ASDM and 2ASDM circuits is established from the spectrum measurements.
In this section, several aspects of the operation of 1ASDM and 2ASDM are demonstrated via measurement examples. The 1ASDM was designed to operate with a LC frequency of 150MHz. In Fig. 10.10a) the output spectrum of 1ASDM for 1MHz input signal and modulation depth of approximately 10%, is shown. For this modulation depth, the Bessel components start to appear around the fundamental of the LC frequency at frequencies that have been theoretically established in Chapter 5. In Fig. 10.10b) the output spectrum of
2ASDM is shown for an input signal with a frequency of 8.1MHz and for modulation depth of 10%.
a) b)
Fig. 10.10. Measured output spectrum for a modulation depth of 10% for a) First order ASMD for 1MHz test signal and b) Second order ASDM for 8.1MHz test signal
In Fig. 10.11a) the 1ASDM output spectrum is shown for a MD of 50%. The Bessel components and their multiples are occupying a significant part of the output spectrum. However, the spectral purity in the base-band is still within the required accuracy. As estimated in Fig. 10.7, for such cf , the base-band free from spurious LC tone tones is 8MHz. The spectral purity of the base band is preserved up to a MD of around 80%. For higher MD, the loop is overloaded and the Bessel components appear above the noise floor and deteriorate the performance. The main difference in the performance of 1ASDM and 2ASDM is in the larger frequency band of 14MHz that can be converted with the predefined quality by the second order loop. In Fig. 10.11b) the output spectrum of 1ASDM in overload (90% MD) conditions is illustrated.
The presented ASDM designs are dimensioned in such a way that the overload condition for the modulators occur simultaneously with the overload of the first transconductor. Such
10.2. High performance ASDMs 203
an implementation is most efficient in terms of power and area. a) b)
Fig. 10.11. Measured output spectrum: a) 1ASDM for 1MHz test signal and modulation depth of 50%, b) 1ASDM for 1MHz input signal and overload (90% MD).
The peak SFDR and SNR in the baseband are measured for a maximum input signal that corresponds to 80% MD. In Fig. 10.12 the measured SFDR is plotted versus the frequency of the peak input signal. Three regions of operation with respect to the frequency of the input signal can be distinguished. The first one is up to half base-band (4 and 6MHz respectively). For this region, the second and third order harmonic distortion components of the input signal fall within the evaluated band.
Fig. 10.12. Measured SFDR with input amplitude at 80% MD in the base-band of each modulator for different frequencies of the input signal.
As the input frequency is still low with respect to that of the LC, the performance is determined mostly by the linearity of the first transconductor. For an input signal in the upper
2nd order
1st order
Spurious free bands
2nd order2nd order
1st order1st order
Spurious free bands
Frequency bands with “quasi-ideal” linearity: spurious are hidden in the noise floor
Bandwidth of the SFDR for 1st and 2nd order ASDM
Frequency [MHz]
SFD
R [d
B]
2nd order
1st order
Spurious free bands
2nd order2nd order
1st order1st order
Spurious free bands
Frequency bands with “quasi-ideal” linearity: spurious are hidden in the noise floor
Bandwidth of the SFDR for 1st and 2nd order ASDM
Frequency [MHz]
SFD
R [d
B]
2nd order
1st order
Spurious free bands
2nd order2nd order
1st order1st order
Spurious free bands
Frequency bands with “quasi-ideal” linearity: spurious are hidden in the noise floor
Bandwidth of the SFDR for 1st and 2nd order ASDM
Frequency [MHz]
SFD
R [d
B]
2nd order
1st order
Spurious free bands
2nd order2nd order
1st order1st order
Spurious free bands
Frequency bands with “quasi-ideal” linearity: spurious are hidden in the noise floor
Bandwidth of the SFDR for 1st and 2nd order ASDM
2nd order
1st order
Spurious free bands
2nd order2nd order
1st order1st order
Spurious free bands
Frequency bands with “quasi-ideal” linearity: spurious are hidden in the noise floor
Bandwidth of the SFDR for 1st and 2nd order ASDM
Frequency [MHz]
SFD
R [d
B]
204 Chapter 10: Design Examples
half of the observed frequency band, the loop displays a “quasi-ideal” SFDR because the harmonics of the input signal fall outside the observed signal band and for both implementations the Bessel components in the base-band cannot be distinguished from the noise floor. The dynamic range of the measurement setup was 100dB and all Bessel components below that value are undetectable. The third frequency region is at the edge of the modulator’s base-band. The Bessel components start to enter the band and the performance is rapidly decreasing.
Fig. 10.13. SFDR of 1ASDM measured at 80% Modulation Depth, for a worst- case input frequency of 2.7MHz.
The measured SFDR for maximum input signal is shown in Fig. 10.13. For this measurement, a differential input signal of 400mVpp was used that corresponds approximately to 80% modulation depth. The frequency of the input signal is 2.7MHz and corresponds to the worst situation because the second and the third order distortion components fall into the evaluated signal band. The odd order harmonic distortion is due to the V-I converter of which the performance starts to degrade for those amplitudes. The measured odd harmonics correspond to the simulated levels of –75dB. However, in the SFDR an even order component with the same magnitude is visible. This is due to the transformer used for single ended to differential conversion at the input.
Fig. 10.14 shows the measured SFDR of 1ASDM and 2ASDM with respect to the amplitude of the input signal. The characteristic of both modulators is linear up to amplitudes corresponding to 80% MD.
10.2. High performance ASDMs 205
Fig. 10.14. SFDR of 1ASDM with respect to the amplitude of the input signal.
In Fig. 10.15, photographs of the implemented ASDM integrated circuits are shown. a) b)
Fig. 10.15. Chip photographs: a) 1ASDM , b) 2ASDM .
The measured performance is summarized in Table 10.3.
206 Chapter 10: Design Examples
Table 10.3. Measured performance summary of first and second order ASDMs
0.18mm, 1.8V CMOS First Order ASDM Second Order ASDM
Area with (out) buffer 0.040 (0.026) mm2 0.054 (0.04) mm2
Idle limit cycle frequency 150MHz 120MHz
SFDR [0-8/12MHz] 75dB 72dB
SNR [20k-8MHz] 70dB 70dB
Current Consumption 800mA 1200mA
10.2.3. Conclusions
An example of an ASDM topology was given. A design procedure for the parameterization of ASDM building bocks was presented. The trade offs in the transistor level design and the performance limiting factors of a first and second order ASDM were discussed. First and second order ASDMs were implemented in a standard, digital 0.18µm CMOS process. Both designs use a quantizer with hysteresis to achieve LC frequencies of 150MHz and 120MHz, respectively. The first order modulator achieves a SFDR of 75dB in a in a bandwidth of 8MHz, while the second order modulator achieves a SFDR of 72dB in 12MHz bandwidth. The second order ASDM achieves a 50% higher signal bandwidth for an increase of less than 20% in the chip area and approximately 50% in the current consumption. The performance of both modulator implementations is limited by the circuit noise. The SNR and the linearity of the input V-I stage can be further improved with higher power consumption.
The measurement results confirm the theoretical studies presented in Chapters 4 and 5. For applications with a moderate frequency band of up to 10MHz, the implementations of
both the first and the second order ASDMs achieve a sufficiently high LC frequency. In such a case, the usage of a first order modulator is recommended due to the ease of implementation.
10.3. Second order SDM design
This section describes the implementation and measurement results of a second-order, feedback SDM that has been designed to operate with a dominant sub-harmonic LC of 125MHz when sampled with a 1GHz clock. The main goal of the design is the implementation of a simple second order SD ADC that converts a signal band of 5MHz with a very high sampling clock of 1GHz and utilizes a specific LC behavior. As elaborated previously, the nominal SDM operation with a high sampling clock requires very broadband amplifiers, a high speed comparator, and a careful control of the extra loop delay and the layout parasitics. Here it is demonstrated that those issues can be significantly alleviated if the SDM is designed to operate at lower frequency sub-harmonic LCs. The implementation aims the introduction of several sub-harmonic LCs with lowest frequency as low as 8sf . The
10.3. Second order SDM design 207
measurement results demonstrate that such an operation still can make use of the high sampling clock and trades off performance for simplicity and allows for a significant decrease of the power consumption. This design broadens the knowledge in the field and was an important step for the industrial design presented in Section 10.4.
10.3.1. Block diagram and parameterization
The block diagram of the second order SDM is shown in Fig. 10.16. The transconductors 1 2m ,g and the amplifiers 1 2,A are re-used from the second order ASDM implementation from Section 10.2. The asynchronous quantizer, with 8mV hysteresis, also has the same topology as previously described. In order to implement a SD ADC, a sampling latch is placed after the asynchronous quantizer (see Fig. 10.16) that digitizes the two-level output signal of the quantizer. A specific property of the implementation is that the quantization in amplitude and in time is performed in two consecutive blocks. This SDM implementation maximally re-uses the topology and the building blocks of the second order ASDM from Section 10.2. The position of the sampler is also attractive from an implementation point of view because the sampler acts on a well-defined two level signal. In this way, the probability for quantizer metastability at the sampling moments is significantly decreased because the time duration of the weak signal provided to the sampling switch is minimized. The speed of the quantizer is now determined by the speed of the regenerative switching of the asynchronous quantizer. On the other hand, the speed of the quantizer is less critical because the desired LC behavior allows for a significant quantizer hysteresis and extra loop delay.
The idle LC behavior of the modulator is evaluated in Fig. 10.17 with the help of the graphical application of the describing function description of the binary quantizer with hysteresis, derived in Chapter 5. The loop filter and the quantizer are parameterized such that four sub-harmonic LCs are possible with frequencies 2 4 6 8s s s sf , f , f , f . The sampling delay, the switching and the propagation times in the quantizer and the sampling switch are incorporated in the LC mechanism. The total extra loop delay approaches 40% of the clock period and is determining the low phase boundary of the higher frequency sub-harmonic LCs with frequencies 2 and 4s sf f (see Fig. 10.17).
Fig. 10.16. Block diagram of the implemented second order SDM
Such an operation makes the LCs with frequencies 6 8s sf , f dominant for busy operation.
-
+
+
+ -
+ -
- ++ -
- +
- -
- ++ -
+ -
-+-
-+
+ -
+ -
- +
g m1 gm2A1
A2
FB1
FB2
CInt1 CInt2
Vout
gm2A1
A2
FB1
FB2
CInt1 CInt2
Vi Vout
+ -
- +
Latch
CLK
CLKN
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+
+
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- +
- -
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+ -
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g m1 gm2A1
A2
FB1
FB2
CInt1 CInt2
Vout
gm2A1
A2
FB1
FB2
CInt1 CInt2
Vi Vout
+ -
- +
Latch
CLK
CLKN
208 Chapter 10: Design Examples
Fig. 10.17. Evaluation of the idle limit cycle behavior of the second order SDM from Fig. 10.16.
It has to be pointed out that the LC behavior in Fig. 10. 17 is not implemented by adding an extra time delay but is a result of the loop filter high frequency behavior which in turn is controlled by the current consumption of the opamps. That means that the opamps are parameterized for loop frequencies of 6 and 8s sf , f and only the sampling latch has to operate at the maximal clock speed.
Fig. 10.18. MatLab evaluation for idle mode and for a -25dBFS signal.
In Fig. 10.18, an SDM that uses the loop filter with characteristics shown in Fig. 10.17 is evaluated under MatLab via transient simulations. The output spectrum for idle operation is compared with the spectrum with a mid-scale input signal. As predicted in Chapter 6, in idle mode, the SDM exhibits the lowest possible LC with frequency of 8sf . As Fig. 10.17 and Fig. 10.18 indicate, this LC is also dominant for busy operation. That can be concluded from
10.3. Second order SDM design 209
the bump in the output spectrum for frequencies around the frequency of the idle LC.
10.3.2. Evaluation and measurements
The SDM has been implemented in a standard digital 0.18µm CMOS process. An example of the output spectrum of the simulated transistor implementation is given in Fig. 10.20 for a 1MHz sine input signal. The spectral bump at 125MHz indicates that the desired LC behavior is realized.
Fig. 10.19. Transistor simulation of the output spectrum for -3dBFS input signal.
• The transistor level simulations established an SNDR of 64dB in a signal band of 5MHz.
Fig. 10.20. Measured output spectra of the second order SDM with 1GHz clock for -6dBFS input signal.
210 Chapter 10: Design Examples
This result matches the expectation of the theoretical evaluation described in Chapter 7. In Fig. 10.20, the measured output spectrum of the second order SDM with 1GHz clock for -6dB FS input signal is shown. Instead of the intended idle LC with frequency 8sf / , the measured ICs exhibit an idle LC of 83MHz (or 12sf / ).
The lower LC is a result from several factors, the dominant among which are: • The impact of the parasitics added by the layout was not taken into account into the
evaluation and because of that was not compensated. • The phase margin for the lower LCs was not sufficiently evaluated over PVT such
that the implemented phase margin appeared to be insufficient. In Table 10.4, the performance of the implementation is summarized.
Table 10.4. Measured Performance Summary
Due to the activation of lower LCs the performance is lower than expected. However, it has
to be pointed out that the measured SNR agrees with the predictions of the LC noise model from Chapter 7 for loop oscillations with frequency 12sf .
For the measured mode of operation, the SDM achieves 55dB SNDR in 5MHz signal bandwidth and consumes 2.1mA from 1.8V supply. Those parameters result in a FOM of 0.8pJ/conv. As the absolute value of the sampling frequency is not included in the FOM and there are only a few SDMs that utilize a sampling clock above 500MHz, a comparison with respect to the achieved FOM is rather difficult. In Table 10.5 the design is compared with several state-of-the-art designs based on single bit quantizers, that either use a high oversampling ratio or a high nominal clock frequency. For the FOM calculation the SNDR is used in the evaluation of the ENOB. From the comparison, it can be concluded that the designs that use high OSR or high nominal sampling frequency achieve lower FOM. That can be explained with the higher bandwidth specification of the building blocks and the relative increase of the impact of the parasitic loop delays. These effects increase the overall power consumption of the design.
The power efficiency of the design described in this section is below the expectations due to the lower measured SNDR. The achieved FOM is still competitive, especially for the target conversion bandwidths, however, as the current settings were fixed and dimensioned for a higher frequency LC, the FOM of 0.3 pJ/conv. expected from simulations was not achieved. An evident advantage of the design is the simplicity of the implementation of the second order loop filter.
3.8mWPower consumption
1000Clock frequency [MHz]
83Dominant limit cycle frequency [MHz]
0.068 (0.05)Area total (core) [mm2]
5Signal bandwidth [MHz]
55SNDR [dB]
0.18 µm, 1.8V, CMOSTechnology
3.8mWPower consumption
1000Clock frequency [MHz]
83Dominant limit cycle frequency [MHz]
0.068 (0.05)Area total (core) [mm2]
5Signal bandwidth [MHz]
55SNDR [dB]
0.18 µm, 1.8V, CMOSTechnology
10.3. Second order SDM design 211
Table 10.5. Comparison FOM and complexity
1 2 3 4 Here, it has to be pointed out that the measured performance with a dominant LC of
83MHz is significantly better then the performance that can be expected by a second order SDM that operates with 83MHz sampling clock. If a sampling clock of 83MHz is used, the realized OSR is only 8 and such second order SDM can achieve a DR of less then 35dB. This comparison demonstrates the advantage of the operation at a lower LC. The comparison between different modes of operation is further elaborated in Section 10.4. for another design example.
10.3.3. Conclusions
An SDM design was described that uses a specific LC behavior that allows to trade-off performance for power consumption. The SDM operates at a dominant sub-harmonic LC of 83MHz when sampled with 1GHz clock. It has been demonstrated that such LC operation leads to significantly reduced design specifications with respect to the optimal operation with 1GHz clock because effectively the design requirements for the majority of building blocks are determined by the 83MHz loop oscillations. Only the sampling latch has to operate at a maximum clock speed. At the same time, the measured SNDR is well above the SNR achievable with SDM that operates at lower (83MHz) clock speed. The measurement results confirmed the expected behavior and performance as theoretically established in Chapters 6 and 7.
The design led to the establishment of the dominant influences on the LC behavior of SDM
1 From the provided measurement data can be concluded that the SDM operates with a dominant limit cycle of 8sf . 2 The referenced power consumption is an estimation based on transistor simulations. 3 The referenced power consumption is an estimation based on transistor simulations. 4 In brackets the FOM expected from transistor simulations is given.
0.230.18 µm667232640M10M13[78]3
0.8 (0.3)40.18 µm55601001G5M12This work
0.20.18 µm727440153.6M3.84M15[23]
50.6 µm566264400M3.1M15[24]1
0.3890nm81881004M20k13[18]
90nm
0.18 µm
0.35 µm
0.18 µm
0.5µm
CMOSProcess
1.359893264M1M14[75]
1.2262771001.538M16k13[17]
4.377803221.07M200k15[21]
0.56363.562.51G8M13[77]2
0.4275.5763264M1M15[76]
Q bits OSR DR
[dB]SNDR [dB]
fS, [Hz]
FOM[pJ/conv.]
Signal BW [Hz]LRef.
0.230.18 µm667232640M10M13[78]3
0.8 (0.3)40.18 µm55601001G5M12This work
0.20.18 µm727440153.6M3.84M15[23]
50.6 µm566264400M3.1M15[24]1
0.3890nm81881004M20k13[18]
90nm
0.18 µm
0.35 µm
0.18 µm
0.5µm
CMOSProcess
1.359893264M1M14[75]
1.2262771001.538M16k13[17]
4.377803221.07M200k15[21]
0.56363.562.51G8M13[77]2
0.4275.5763264M1M15[76]
Q bits OSR DR
[dB]SNDR [dB]
fS, [Hz]
FOM[pJ/conv.]
Signal BW [Hz]LRef.
212 Chapter 10: Design Examples
operating with a high nominal clock frequency and provided indispensable information for the successful design of the SDM described in Section 10.4. Although, the design does not improve state-of-the-art in terms of FOM, it shows the potential of the design approach for the realization of additional degrees of freedom for performance optimization via the implementation of a specific LC behavior.
10.4. Fifth order SDM design
The last design that is discussed in this chapter is an extensively reconfigurable CT, 5th-order, 1-bit SDM [69], [74]. In order to implement a multi-mode functionality in terms of dynamic range/bandwidth, the SDM is designed programmable from 85dB@100kHz to 52dB@10MHz in 121 steps. A detailed description of the design and the measured performance can be found in [74]. Here, in line with the main objective of this thesis (an elaborate analysis of the LC behavior of SDM) several very important aspects of the design are treated. Firstly, in Section 10.4.1 the SDM architecture is described. The programmability that allows for the realization of different modes of operation and different LC behavior is elaborated. Section 10.4.2 concentrates on the design instruments that can be used for the realization of a particular LC behavior. The mechanisms to control the phase properties of the SDM loop filter and the extra loop delay (phase and time) are discussed. The graphical application of the LC analysis is extensively used for the evaluation of the SDM behavior. In Section 10.4.3 the possibility to optimize the design performance and cost by implementing a specific LC behavior is illustrated with a measurement example for Bluetooth (BT) mode of operation.
10.4.1. Modulator architecture and programmability
The multi-mode capability requires programmability and flexibility, and introduces a higher level of conceptual considerations in the design of the whole system and of the SDM in particular. The block diagram of a configurable 5th order SDM is given in Fig. 10.21.
Fig. 10.21. Block diagram of multi-mode SDM.
Extensive programmability is introduced in the ADC in order to optimize the performance for each specific bandwidth-clock combination. The sample frequency of the modulator can be programmed from 13MHz to 400MHz and is split into 11 sub-ranges. In order to
FF
delay control
timing generation
Clock
Vin
Dout
VrefVcom
FF
delay control
timing generation
Clock
Vin
Dout
VrefVcom
10.4. Fifth order SDM design 213
implement the desired unity-gain frequencies, each sample frequency sub-range requires a separate set of capacitor values for the integrators in the loop filter. Each mode reuses part of the biggest capacitance that is required for the lowest clock range. In this way, the area over-head for multi-mode operation is minimized. The signal bandwidth of the ADC is programmed via the two local feedback coefficients that implement local resonators and realize the notches in the loop filter. Those coefficients are implemented with resistors, and can be set to 11 different values. By re-using the resistor values in each clock-defined mode, only 11 resistor values are required. The combination of these feedback resistors and the different integrator capacitors in the loop filter give the 121 different bandwidth settings.
The reference current of each of the circuits used in the SDM is programmable with 4-bit accuracy. In this way, the minimum required power consumption can be set in each mode depending on the noise requirements and the desired LC behavior.
10.4.2. Loop timing and phase control
In Chapter 6, the importance of the phase transfer of the linear part of the SDM loop for the realization or avoidance of a particular LC behavior is elaborated in detail. In Chapter 7, it is shown that the SDM LC behavior can be used as an optimization criterion for power and area efficient SDM design. In this section the hardware implementation of a phase control in the loop and consequently of a control for the LC behavior is described. As an example, the particular system implementation described in Section 10.4.1 is used.
The mechanism to control the phase properties of a closed loop system are well known from control theory. Here, the specific aspects of the design of CT SDM are pointed out. The phase characteristic of the SDM loop is determined by:
• Extra time delay in the loop; • Unity gain frequencies of the integrators; • Parasitic poles and zeros in the integrator implementations; • Parasitics due to layout.
The two types of parasitics are discussed separately due to the different stages of their
introduction in the design and the different approaches for their compensation. Next, each of the above factors and their impact on the power consumption is discussed in
more detail, and illustrated with simulation examples. As elaborated in Chapter 6, the total phase rotation in the SDM loop has a component that
is determined by the extra time delay in the loop. The extra time delay might be deliberately introduced or might be a result of the chosen clocking scheme. The impact of the extra time delay becomes evident and even dominant with the increase of the nominal clock speed. If the desired mode of operation does not allow the existence of lower LCs, a very well controlled timing scheme is required. In [74], the extra loop delay was made programmable in order to optimize the trade-off between the delay given to the quantizer for a decision and its power consumption. The delay can be increased when the loop speed is not critical and consequently the current consumption of the comparator can be decreased in order to save power. In some situation the desired performance can only be achieved if the extra loop delay is minimal. On the other hand, the realization of a minimal delay requires an increase of the power consumption.
A fifth order chain of integrators combined in a feed forward architecture that implements a loop filter described by the transfer function given as:
214 Chapter 10: Design Examples
( ) ( )( )4 3 2
1 1 2 1 2 3 1 2 3 4 1 2 3 4 5 1 2 3 4 52 2
3 2 3 5 4 5
a a a a a=s s +b s +b
ug s ug ug s ug ug ug s ug ug ug ug s ug ug ug ug ugL sug ug ug ug
+ + + +
(10.6) where ia are feed forward coefficients, ib are the feedback coefficients and iug are the
unity gain frequencies of the integrators. The coefficients ib are not incorporated in the nominator of (10.6) as the impact is negligible. As illustrated in Fig. 10.21, the feed forward and feedback coefficients can be implemented as resistors. In Fig. 10.22 the frequency response of the loop filter for WLAN mode is shown. The local feedback coefficients are responsible for the notches in the magnitude response shown in Fig. 10.22a) and have impact only in the low frequency signal band. The local feedback coefficients do not influence the phase behavior at higher frequencies (above the signal band) and because of that have a very small impact on the LC behavior. As explained in Chapter 6, at high frequencies, the loop filter phase has to approach first order behavior o(90 ) in order to prevent instability and performance deterioration. The unity gain frequencies of the integrators are usually chosen such that a graceful decrease of the filter order from 5th to 1st is implemented such that at high frequencies only one integrator is active and the loop filter phase is 90 . Thus, the optimal SDM design is confined to a careful implementation of the loop filter phase characteristics with an accent on the high frequency range where the sampling most actively influences the behavior of the loop. In the context of phase control a very important factor, orthogonal to the above three is the power consumption of the transistor implementation that is required for the realization or the manipulation of the desired phase behavior.
In Fig. 10.22b), the phase response of the ideal loop filter from (10.6) is shown. The ideal parameterization of the loop filter leads to a phase response that approaches 90 for high frequencies.
a) b)
Fig. 10.22. Frequency response of the loop filter in WLAN mode, a) magnitude response, b) phase response.
However, in a practical situation it is impossible to implement such a phase response due to the impact of the parasitic poles in the loop filter, the extra loop delay and the parasitic
10.4. Fifth order SDM design 215
influences from the layout. On top of that, the phase behavior has to be guaranteed in the process corners and with respect to temperature and supply voltage variations. From the perspective of the LC model of SDM operation that means that at least the first and the second sub-harmonic LCs should be possible for the particular filter parameterization. In most modes of operation the low frequency sub-harmonic LCs have to be avoided and in order to guarantee the robustness of the implementation their respective phase margins have to be carefully evaluated.
As elaborated in Chapter 7, the low frequency LCs are especially harmful for the performance when a lower OSR is used for the particular mode of operation. For the WLAN mode of 10MHz signal bandwidth (ideal loop filter shown in Fig. 10.22) and clock frequency of 440MHz, the OSR is only 22, which makes compulsory the implementation of only the first and the second sub-harmonic LCs in order to achieve a maximal performance.
Next, several design techniques that can be used for the realization of the desired LC behavior are elaborated.
10.4.2.1. Phase correction with zeroes
A powerful approach for the realization of the desired LC behavior is via corrections of the actual loop filter phase response that results from a particular realization of the integrators. Such corrections can be implemented by introducing high frequency zeros in the loop filter. As the high frequency phase behavior is determined by the first OTA in the loop filter, the correction zeros have to influence its frequency behavior. That limits the possibilities of how to implement such correction zeros. Two approaches are described next.
In Fig. 10.23, the input of the loop filter is shown. The feed forward capacitor in Fig. 10.23 (1) implements a high frequency transmission path to the output and can be dimensioned to compensate the phase loss at high frequencies. A high frequency zero can also be implemented in the first integrator as illustrated in Fig. 10.23 (2) where a resistor is introduced in series with the integrating capacitance of the first integrator.
Fig. 10.23. First two integrators of the loop filter are shown; the first phase correction mechanism is a feed forward capacitor (1) and the second is a high frequency
zero implemented via a resistor (2) in series with the integration capacitor of Int1.
Int1
vin
idacInt2
…
1
2
Int1
vin
idacInt2
…
Int1
vin
idacInt2
…
1
2
216 Chapter 10: Design Examples
The impacts of both loop filter modifications are shown in Fig. 10.24, where simulation results for the loop filter phase response are compared. Both phase correction techniques are compared with the loop filter phase response without compensation.
From Fig. 10.24, it can be seen that without phase correction, the loop filter phase characteristic results in dominant low frequency LCs that in turn will deteriorate the SDM performance. The feed forward correction significantly improves the phase characteristics but might be insufficient to increase the phase boundary of the first sub-harmonic LC and consequently would not lead to the desired performance. When the two correction techniques are simultaneously applied, the loop filter phase reaches closely the desired behavior and results in an optimal SDM performance.
Fig. 10.24. Phase characteristics of the loop filter5, schematic simulations without phase compensation, with feed forward compensation, and with extra zero and feed
forward compensation.
The phase corrections can be implemented for virtually no extra cost and are powerful tool for the realization of the desired phase behavior. However, their impact on the loop filter phase is significant only at certain frequencies. The phase loss can be compensated in the whole high frequency range, by a decrease of the extra loop delay as illustrated next.
10.4.2.2. Phase loss compensation with extra current
In Fig. 10.25 several simulations of the loop filter phase response are compared. Firstly, the comparison between schematic and extracted simulations (1 and 2) shows the loss of phase due to layout parasitics.
5 The phase reversal at each +/- 180 deg. crossing is an artifact from the simulator.
10.4. Fifth order SDM design 217
Fig. 10.25. Phase characteristics of the loop filter, schematic simulations with low (1) and high (3) power and extracted layout simulations with low (2) and high (4) power.
The phase loss can be compensated by an increase of the power consumption of the integrators such that the parasitics poles are shifted to higher frequencies (Fig. 10.25 (3,4)).
An evident drawback of this type of phase loss compensation is the required increase of the integrators’ current consumption and the difficulty to investigate the required phase loss compensation on a system level without complex models for the OTAs’ implementation.
Another drawback is the relatively limited possibility to change the high frequency characteristics of the loop filter only via a push up of the current consumption. However, a simple increase of the OTAs’ bandwidth through utilization of a higher current can be applied after the determination of the required phase margins with simulations of the extracted layout.
10.4.3. Measurement example: low power Bluetooth mode
The state-of-the-art multi-mode design has to fulfill the specifications of each mode with an acceptable increase of the overall cost. In general, the parameterization of the transistor circuits is determined by the mode of operation that requires the highest performance.
This parameterization, however, may introduce an unacceptable increase of the design costs in terms of power and chip area for other less demanding modes of operation. This problem can be significantly alleviated if a specific LC behavior is introduced for the non-critical modes of operation. In this section, this concept is illustrated with a measurement example.
The area of the CT SDM is determined to a great extent by the integration capacitances used in the loop filter. These capacitances in turn scale down with the increase of the sampling frequency because the same SNRq can be realized with less strong filtering of the signal band. As the noise at the upper edge of the signal band (see Fig. 10.26) has a dominant contribution to the overall SNRq, smaller capacitances can be used in the loop filter such that a fixed ratio is kept between the sampling frequency and the unity gain frequencies of the integrators. Thus the increase of clock frequency is very beneficial for area reduction.
1
3
2
4
218 Chapter 10: Design Examples
Fig. 10.26. Comparison of the output spectra for two clock frequencies and two set of capacitor values.
However, the increase of clock frequency introduces several significant drawbacks: • More power is required in the loop filter and in particular for the implementation of
the desired magnitude-phase relations. The high speed comparator and the requirement for a big gain-bandwidth product for the OTAs are determining the required power increase.
• A significant overhead in terms of SNRq is introduced for the modes that have a relatively small conversion bandwidth.
In this example, the ADC performance in bluetooth (BT) mode (desired DR of 74dB in a signal bandwidth from 500kHz to 1.5MHz) is measured for several clock and coefficient settings and the minimal power consumption for meeting the BT specifications is established. The BT standard is chosen because of the severe requirements for power consumption and area dictated by the enormous market of very low cost applications.
The performance of the SDM implementation for a BT mode of operation is thermal noise limited. That means that for a sampling clock in the interval from 100MHz to 400MHz, the maximally achievable SNR is determined by the thermal noise floor. The quantization noise, depending on the chosen clock speed and coefficient settings, always remains 10dB to 50dB below the thermal noise floor and is not influencing the measured performance. This very large overhead forces an investigation of the possibilities to decrease the cost of the design for this particular mode of operation. Here, the insight of the LC behavior is used for a specific optimization of the modulator behavior such that the BT specifications are met with a significant decrease of the current consumption.
BT specifications are measured with the ADC settings listed in Table 10.6. The LC behavior is modified for each measurement through variation of the clock frequency sf , the coefficients of the loop filter and the extra loop delay τ . The loop filter coefficients in turn are modified by adjustments of the integration capacitances and the bias currents of the OTAs. The primary goal is to find the minimum required current consumption, that is why firstly the bias current is decreased and then the need to change the integration capacitances is evaluated.
Edge of the signal band: highest noise
10.4.3. Measurement example: low power Bluetooth mode 219
Table 10.6. BT: limit cycle modes, measurement summary
Mode sf [MHz]
Possible limit cycle frequencies
SNR [dB]
Currentcons. [mA]
int,totalC[pF]
τ [ps]
Measured spectrum
1 400 sf 2 , sf 4 74 6.1 3 200 Fig. 10.27
2 400 sf 2 , *sf 4 74 5.1 3 350 Fig. 10.28
3 400 sf 2 , sf 4 , sf 6 , *sf 8 74 3.4 4 500 Fig. 10.29
4 200 sf 2 , sf 4 74 4.4 6 NA Fig. 10.30a)
5 200 sf 2 , *sf 4 74 3.4 6 NA Fig. 10.30b)
6 100 sf 2 , sf 4 74 3.4 12 NA Fig. 10.31 In the third column of Table 10.6 the dominant LC for the particular mode of operation is
marked with ‘*’. For modes 4 to 6 the extra loop delay is not applicable (NA) because the maximum implemented τ of 750ps is not sufficient to influence further the operation of the SDM. The six different modes of operation shown in Table 10.6 make use of different clock frequencies and implement different LC behavior. Next, the SDM operation in each mode is described in more detail.
Mode 1: Nominal limit cycle behavior and 400sf MHz=
In Fig. 10.27 the output spectrum for 400MHz clock mode is plotted for nominal 6 coefficients parameterization that results in a nominal LC behavior when only the first two sub-harmonic LCs with frequencies 2sf , 4sf are possible and operational.
Fig. 10.27. Measured SDM output spectrum in BT mode for nominal filter settings and sf =400MHz.
Such LC behavior can be concluded from the measured output spectrum shown in Fig.
6 Due to the highest theoretically achievable performance when only the first two sub-harmonic limit cycles are possible sf 2 , sf 4 such SDM operation will be called nominal.
220 Chapter 10: Design Examples
10.27. In such a mode of operation, the SDM achieves a maximal SNRq. However, due to the thermal noise limitation the overall DR is 74dB. The current consumption and capacitance area are listed in Table 10.6. In this mode the smallest capacitances are used in the loop filter but it also requires the highest current consumption. The current is used for the increase of the quantizer speed such that the extra loop delay τ can be set to a minimal value. In addition, the OTAs are biased at a higher current in order to compensate for the loop filter phase loss at high frequencies. In this mode, for the applied clock frequency of 400MHz, the nominal SDM operation introduces an enormous margin of 50dB for quantization noise with respect to the thermal noise floor.
The performance margin can be utilized if a lower sampling clock is used for this particular mode or if a specific LC behavior is implemented, as described next.
Mode 2: Dominant lower limit cycle ( 4sf ) behavior and 400sf MHz=
The overhead in SNRq can be utilized if a specific LC behavior is introduced. In Fig. 10.28 the output spectrum is shown for the same sf of 400MHz and the same int,iC values.
However, a longer decision time is given for the comparator (the extra loop delay τ is increased) and respectively lower current settings are used. The bias currents of the OTAs are also decreased. Those adjustments increase the impact of the loop delay on the loop filter phase characteristics. Consequently, the number of signal transitions in the loop that occur with a maximum speed of 2sf decreases, while the number of transitions with frequency
4sf increases. As elaborated in Chapter 7, this behaviour indicates that the second sub-harmonic LC with frequency 4sf (see Fig. 10.28) is the dominant LC in the SDM operation. As illustrated in Table 10.6 the desired specifications are met with a 16% decrease of the current consumption. Due to the high sampling frequency, the capacitance area remains the same as in Mode 1.
Fig. 10.28. Measured SDM output spectrum in BT mode with sf =400MHz for dominant LC with frequency 4sf .
A further decrease of the current consumption can be achieved if the SDM is parameterized to operate also at lower sub-harmonic LCs and a lower frequency LC is made dominant.
10.4.3. Measurement example: low power Bluetooth mode 221
Mode 3: Dominant lower limit cycle ( 8sf ) behavior and 400sf MHz=
In Fig. 10.29 the SDM is programmed to operate also at sub-harmonic LCs with frequencies 6sf and 8sf . Again such an operation is realized via an optimization of the loop phase behaviour via a decrease of the bias currents of the OTAs and the comparator. However, in order to preserve the desired noise suppression in the signal band, the integrating capacitances of the first OTA have to be increased with approximately 25%.
Fig. 10.29. Measured SDM output spectrum in BT mode with sf =400MHz for dominant LC with frequency sf 8 .
In this mode of operation the impact of the quantization noise in the signal band is increased, however, a significant margin of 10dB with respect to the thermal noise is still realized. From Table 10.6, it can be seen that the same performance is measured in the signal band. However, the current consumption is decreased with almost 50% with respect to the nominal mode of operation. The minimal power consumption that is required to meet the BT DR specs is also evaluated for lower clock frequencies of 200MHz and 100MHz. The respective modes of operation denoted as Modes 4,5 and 6 are illustrated next.
Modes 4 and 5: Nominal and dominant 4sf LC behavior and 200sf MHz=
In Fig. 10.30a) and b) the measured output spectra for 200MHz clock are shown when the SDM operates, respectively, in nominal LC mode a) and with dominant sf 4 LC b). Due to the lower clock speed, the required capacitance area is doubled with respect to 400MHz clock operation. However, the lower clock requires lower current consumption. Again, by a modification of the LC behaviour a further decrease of the current consumption can be introduced.
222 Chapter 10: Design Examples
a) b)
Fig. 10.30. Measured SDM output spectrum in BT mode with sf =200MHz for a) nominal operation, b) dominant / 4sf .
Mode 6: Nominal LC behavior and 100sf MHz=
In a final measurement a clock frequency of 100MHz is used. The output spectrum is shown in Fig. 10.31. As summarized in Table 10.6, such operation requires the largest integration capacitances and uses minimal power to achieve the desired specifications. Due to the relatively low OSR, the LC behavior cannot be improved significantly in order to achieve a further decrease of the power consumption. Moreover, the overhead of approximately 10dB in SNR is useful as a safety margin and does not require further optimization.
Fig. 10.31. Measured SDM output spectrum in BT mode with sf =100MHz and nominal operation.
The low power BT modes that utilize a specific LC behavior can be introduced in the multi mode implementation without significant overhead in area. Thus the advantages of the multi-
10.4.3. Measurement example: low power Bluetooth mode 223
mode implementation and single IP block can be preserved and at the same time the target performance can be achieved with a significant decrease of 50% of the power consumption.
10.4.4. Conclusions fifth order SDM
In Section 10.4, a fifth order configurable SDM was described that can be parameterized to operate at various clock speeds and LC modes.
Several design techniques for the modification of the SDM loop filter phase response and LC behavior were illustrated. Their main advantages are the simple evaluation done with a standard AC analysis and the low cost implementation of the phase corrections
Measurement results for a BT test case were described. They illustrated the possibility to use a specific LC behavior in order to optimize the cost of the transistor implementation in terms of area and power consumption. As elaborated in Chapter 7, the operation at lower frequency sub-harmonic LC modes brings the advantage of the decreased area requirements of the higher clock speeds and at the same time enables the optimization of the power consumption of the SDM by allowing a significantly lower frequency of operation for the majority of SDM building blocks.
10.5. Conclusions
In this chapter several designs that illustrate the theoretical work done in the scope of the thesis were described.
The presented measurement results of the highly linear V-I converter analyzed in Chapter 8 proved the potential of the combined linearization techniques based on harmonic balancing to achieve very good linearity for a state-of-the-art power consumption.
The measurements of the first and second order ASDMs showed that the theory from Chapters 4 and 5 gives a very good description of the ASDM properties and performance and can be successfully used in the design parameterization.
The measurements performed on the second and the fifth order SDMs showed that the insight in the LC behavior of SDM opens very important new opportunities for design optimization. The possibility to introduce a specific LC behavior in the SDM operation adds a new degree of freedom in the design process that allows for a better resolution of the trade-off performance vs. design cost. This notion is especially relevant in a multi-mode context. The LCM of SDM operation introduces a new level of understanding of the modulator properties and behavior and brings us closer to the understanding and the implementation of the fundamental limits that determine the SDM performance and thus reaching the optimal design for each application.
224 Chapter 10: Design Examples
11. Chapter 11
Main Conclusions Here the main conclusions from the presented theoretical and experimental research are
drawn.
A framework of analysis and synthesis that was developed identified the asynchronous and synchronous SDMs as closed-loop non-linear systems that exhibit limit cycle oscillations.
The Fourier expansion method and the DF method offer a solid theoretical basis for analysis of ASDMs.
The DF theory that builds quasi-linear representation of the non-linear element with respect to a particular type of input signal, is applicable when in the studied systems, the inputs of the non-linear elements sufficiently approximate the type of the input signals for which the particular DF is defined. In the context of the SDM analysis, DFs for sinusoidal, for DC plus sinusoidal and for two sinusoidal inputs can be used, as those combinations of input signals represent very closely the input signals that appear in practice in oversampled (or with a high limit cycle frequency) SDMs .
The analysis of the ASDM operation, with the help of the Fourier expansion method and the DF method, showed that both methods can be complementary used for the calculation of the frequency and the amplitude of the ASDM idle limit cycle oscillations.
The Fourier expansion method gives exact solution for the system parameters. It however, is computationally intensive and practically applicable only for binary and three level quantizers.
The DF representation of the quantizer results in an approximate solution for the ASDM system parameters. When the loop filter is of a 3rd and higher order, the error from the introduction of the DF becomes negligible. The strength of the DF method is in the simplicity of the evaluation that can incorporate much larger range of non-linear elements and loop filters.
The new multi-limit-cycle model of SDM operation demonstrated that sampled DFs can be used to model the clock added phase shift in the closed-loop phase/magnitude relation. The model established the possible sub-harmonic limit cycles and revealed that in idle mode the SDM operates at the sub-harmonic limit cycle with the lowest frequency. It also established the phase margins that have to be assured by design in order to prevent lower frequency limit cycles. That is why the model can be used for the evaluation of the stability of the desired limit cycle behavior.
In order SDM to be able to process an input signal at least two limit cycle modes have to be implemented. When an input signal is applied, the SDM switches between the possible limit cycles. The switching is a result of the accumulated signal dependent phase shifts evaluated at each clock instance.
In SDM, each of the possible limit cycles is characterized by some phase boundary that determines the duration of the time intervals between the switching for which the
226 Chapter11: Main Conclusions
SDM operates at a particular limit cycle. The switching is governed by the properties of the SDM loop filter, the quantizer and the extra intended and parasitic loop delays. The properties of the input signal are encoded in the output bitstream via transitions between the possible limit cycles. Those transitions occur between strings with different frequencies and time durations and lead to the low frequency content in the output bitstream. Between two transitions, the SDM output is in steady state and does not contain actual information about the instantaneous amplitude of the input signal. The SDM input signal and the particular SDM properties in terms of phase boundaries determine the dynamics of the transitions between the limit cycles. As long as the SDM limit cycle state is not changed, the signal change is not incorporated in the output bitstream and a quantization error is introduced.
The harmonic compensation method is a powerful mechanism that can be used for the linearization of the V-I characteristics via a combination of linearization techniques. The analysis and the measurement of the new transconductor structure showed its potential to realize highly linear and power efficient transconductors.
With the help of the recursive bitstream conversion algorithm, very simple and power efficient decimator implementations can be defined.
Appendix A
Analytical evaluation of ASDMs In this appendix, several mathematical procedures that are used in the evaluation of
ASDMs driven with DC and harmonic inputs are described.
Appendix A.1
Characteristics equation for BQ0 and DC input
Expression (5.5) is derived from the convolution of the residue signal ( )r t and the
impulse response of the loop filter ( )l t , that is written as follows:
( )i t = -1{ ( ) ( )1
sin cos2 1 4 *i
k
k d k tV d l tk
π ωπ
∞
=
− − −
∑ } (A.1)
( ) ( )1
sin( ) 2 1 4 Re ijki
k
k di t V d e L jkk
ωπ ωπ
∞
=
= − − − ∑ (A.2)
If the DC value of the impulse response of the filter ( )L jω is given by ( )0L G= ,
expression (A.2) can be rewritten, as follows:
( )( ) ( ) ( )( )( )1
sin2 1 4 e Re Im cos sini i i ik
k dV d G R L k j L k k t j k tkπ ω ω ω ωπ
∞
=
− − − + + ∑ (A.3)
In turn, (A.3) is simplified as follows:
( )( ) ( ) ( )( )1
sin( ) 2 1 4 Re cos Im sini i i ik
k di t V d G L k k t L k k tkπ ω ω ω ωπ
∞
=
= − − − − ∑
(A.4)
228 Appendix A. Evaluation of ASDMs
Appendix A.2
Generalization of the filter representation The analytical description of the DC modulated LC frequency iω and the modulation
parameter d with respect to the applied DC voltage iV is confined to the establishment of a close form solution for the characteristic infinite summations that appear in the right hand side of (5.8) and (5.9) are repeated here for convenience:
( ) ( )1
1 sin 22 1 Re ik
k dV d L kG k
π ωπ
∞
=
− − = − ∑ (A.5)
( ) ( )2
1 1
sin 1 1 cosIm Im4 2i i
k k
h k d kaL k L kk k
π π ω ω∞ ∞
= =
−= = ∑ ∑ (A.6)
Table A.1, Decomposition of the studied filter functions in real and imaginary parts
In the first column of Table A.1 the studied filter functions are given. Respectively, in the second and in the third column of the table those functions are decomposed in real and imaginary parts. For simplification, the substitution p ix ω ω= is used.
When the respective filter representations from Table A.1 are substituted in (A.5) and (A.6) three types of terms are established:
Filter function ( )L jkω Real part, ( )Re ikω Imaginary part, ( )Im ikω
1
pjkω ω+ ( )2 2
c
xk xω +
( )2 2c
kk xω +
( )2
1
pjkω ω+
( )2 2 2
24 2 2
i p
i
k
k x
ω ω
ω
+−
+
( )22 2 2
2
i
kx
k xω−
+
( )2z
p
jk
jk
ω ω
ω ω
+
+ ( )
( )
2 2 2
24 2 2
2i p
i
p z zk
k x
ω ω ω ω ω
ω
− +
+
( )( )
2 2 2
23 2 2
2i
i
p p zk k
k x
ω ω ω ω
ω
− +−
+
( )3
1
pjkω ω+
( )2 2 3
36 2 2
3 i p p
i
k
k x
ω ω ω
ω
−−
+
( )3 2 2
35 2 2
3i p
i
k k
k x
ω ω
ω
−
+
( )3z
p
jk
jk
ω ω
ω ω
+
+ ( )
( )
4 4 2 2 3
36 2 2
3i i p p z p z
i
k k
k x
ω ω ω ω ω ω ω
ω
− + − +
+
( ) ( )( )
2 3 2
35 2 2
3 3p p z i p z
i
k k
k x
ω ω ω ω ω ω
ω
− + − +
+
( )( )( )3
z t
p
jk jk
jk
ω ω ω ω
ω ω
+ +
+
( )( )
( )( )( )
4 4 3
36 2 2
2 2 2
36 2 2
3
3 3
i p t z p t z
i
i p p t z p t z
i
k
k x
k
k x
ω ω ω ω ω ωω
ω
ω ω ω ωω ω ω ω
ω
− − +−
+
+ − +−
+
( )( )( )
( )( )( )
5 5 3 3 2
36 2 2
2
36 2 2
3 3
3
i i p t z p t z
i
i p t z p t z
i
k k
k x
k
k x
ω ω ω ωω ω ω ω
ω
ω ω ωω ω ω ω
ω
− + + − ++
+
− + ++
+
Appendix A.2 Generalization of the filter representation 229
( ) ( ) ( )2 2 2 2 2 21 1 1
1 cos sin 1; ;p p pk k k
ak ak kk x k x k x
∞ ∞ ∞
= = =+ + +∑ ∑ ∑ (A.7)
where in (A.7) 2a dπ= . For a first order filter ( 1p = ) the first two infinite summations
from (A.7) are tabulated in [16] and are given by the expressions:
( ) ( )2 2 21
1 1coth2 2k
x f xk x x x
π π∞
=
= − =+∑ (A.8)
( )( )( ) ( )2 2 2
1
coshcos 12 sinh 2k
x aak g xk x x x x
π ππ
∞
=
−= − =
+∑ (A.9)
A closed-form representation for the third term in (A.7) can be found via integration of
(A.9) with respect to a in the interval {0, }a a∈ , as follows:
( )( )( ) ( )2 2 2 2 2 2
1 10
sinhcos sin 12 2 sinh
a
k k
x ak k ad h xk x k k x x x x
π πρ ρ πρπ
∞ ∞
= =
−−= = − =
+ +∑ ∑∫ (A.10)
where ρ is a substitution variable for a in the integration. For higher order filters ( 1p > ) expressions (A.7), can be derived via differentiation of
(A.8), (A.9) and (A.10) with respect to x , as follows:
( ) ( )( ) ( )
( )2 2 2 21 1
2 12
p p
pp ppk k
f x x f xx k x k x
∞ ∞
= =
−= ⇒ =
+ +∑ ∑ (A.11)
( ) ( )
( )( )
2 21
cos2
p
pppk
g x ak g xx k x
∞
=
= − =+
∑ (A.12)
( ) ( )
( )( )
2 21
sin2
p
pppk
h x ak h xx k k x
∞
=
= − =+
∑ (A.13)
where, for example in (A.11), notation ( ) ( )pf x indicates the thp derivative of ( )f x with
respect to x . The closed-form solution for an arbitrary filter order can be found from expressions (A.11), (A.12) and (A.13), and the closed form solutions for a first order system that are given in (A.8) to (A.10).
From (A.8) and (A.9) the auxiliary function ( )p x is defined, as follows:
( ) ( ) ( ) ( ) ( )( )( )
cosh cosh2 sinh
x a xp x f x g x
x xπ ππ
π
− −= − =
(A.14)
230 Appendix A. Evaluation of ASDMs
In expressions (A.8) to (A.10), the DC modulated LC frequency iω and the modulation parameter d participate implicitly in the expressions. As the goal of the mathematical manipulation is their explicit derivation, the hyperbolic functions in (A.8) to (A.10) are approximated with their series expansions, as follows:
( ) ( )3 5
7sinh6 120z zz z O z= + + + (A.15)
( ) ( )2 4
6cosh 12 24z zz O z= + + + (A.16)
With the help of the first two terms of the series expansions (A.15) and (A.16),
expressions (A.8) to (A.14) can be represented, as follows:
( ) ( )2 4
2 4
6 90f x x O xπ π
= − + (A.17)
( ) ( )2 4 6p x A Bx Cx O x= + + + (A.18)
( ) ( )2 4 6'h x D Ex Fx O x= + + + (A.19)
( ) ( )2 4
1 1 1 2p x f g B Cx O x= − = − − + (A.20)
( ) ( )22 2 2p x f g C O x= − = + (A.21)
( ) ( )2 4
1 2h x E Fx O x= − − + (A.22)
( ) ( )22h x F O x= + (A.23)
As shown further on, the expressions that participate in the higher terms in (A.17) to (A.23)
like ,C E and F have a negligible impact on the studied behavior and can be ignored. The dominant first order components are given, as follows:
( )2
2 14 2a aA d dπ π= − + = − (A.24)
( )4 3 2 2 4
22 148 12 12 3a a aB d dπ π π
= − + − = − − (A.25)
( )( )3 2 2 3
' 1 1 212 4 6 3a a aD d d dπ π π
= − + = − − (A.26)
Next, the above mathematical procedure is applied for the derivation of the closed-form
solutions for the characteristic equations of the studied filter functions. In this evaluation, the
Appendix A.2 Generalization of the filter representation 231
notations Re Impq pq and are used respectively for the right hand side of (A.5) and (A.6). The indexing ,p q denotes of a filter with denominator order (and filter order) of p and numerator order (and number of zeros in the transfer characteristic) of q .
• First order filter:
From the characteristic equations (A.5) and (A.6), with the help of Table A.1, for the first order filter can be written:
( ) ( ) ( )11 2 21 1
1 sin 2 1 sin 2 1Re Rei ik k i
k d k dk L kG k G k k x
π πω ωπ π ω
∞ ∞
= =
= − = +∑ ∑
(A.27)
The closed-form solution of the infinite summation in (A.27) is given by expression (A.10). When the truncated series expansion of the hyperbolic functions shown in (A.15) is also substituted, the real characteristic equation for a first order filter is given as:
( ) ( ) 311 2
'Re pi
i i i
D Ek h x x xG G Gω
ωπ ω π ω π ω
= = + (A.28)
Following the same procedure for the second characteristic equation can be written:
( ) ( ) ( ) ( )211
1Im2 2i
i i
Ak f x g x O xωω ω
= − − = − + (A.29)
• Second order filter:
( )2 2 2 421 12 2
1 12 2 'i i
R x h h x E D Ex O xG Gπ ω π ω
= − = − + + − (A.30)
( ) ( )3 321 1 12 2
1
p i
BI x g f x O xω ω
= − − = + (A.31)
• Second order filter with a zero:
( ) ( ) ( ) ( )2 2 422 12 2 2
1 2 2 z p zp z p p z
i i i
D ER h h x O xG G G
ω ω ωω ω ω ω ωπ ω π ω π ω
− = − − − = − +
(A.32)
( ) ( )
22 12 2
2 3 21 ...2 2 2
p p z p z
i i i i
BAI p p xω ω ω ω ω
ω ω ω ω
− − = − − = − − +
(A.33)
232 Appendix A. Evaluation of ASDMs
• Third order filter:
( )3
2 331 1 2 1 24 6 4 3
3 41 33 4p p p
i i i i
ER h h h x h x O xG G G
ω ω ωπ ω ω π ω π ω
= − − = − + = −
(A.34)
( )2 231 1 23 3
1 42 2i i
BL p x p O xω ω
− = − = + (A.35)
• Third order filter with a zero:
( ) ( ) ( ) ( ) ( )
( ) ( ) ( ) ( )
( ) ( ) ( )
( ) ( )
3
32 1 22 2 4
2 41 22
2 2 4 42
32 3
5 3 41
45 31
45 31 '
' 14 3
p p z p p z
i i i
p zp z
i p p
p zp z
i p p
p zi i
R h x h x h xG
h x x h x x h xG
D Ex Ex O x O xG
D E x O xG G
ω ω ω ω ω ω
π ω ω ω
ω ωω ωπ ω ω ω
ω ωω ωπ ω ω ω
ω ωπ ω π ω
− −= − − − =
−−
= − + + = −−
= − + + − + + = −
= + − + +
(A.36)
( ) ( ) ( ) ( )
( ) ( )( ) ( ) ( )( )( ) ( ) ( )
232 1 23
2 4 2 43
24
3 5
1 3 42
1 3 2 ' 4 '2
3 '2
z p p zi
z p p zi
z p p z p
i i
L p x x p x
B D x O x D x O x
B DO x
ω ω ω ωω
ω ω ω ωω
ω ω ω ω ω
ω ω
= − − − =
= − − − + − − + =
− += − + +
• Third order filter with two zeros:
( ) ( )
( ) ( )
3 2 2
12 2
33 2 3 2
24
3 3 7 5 5 3
17 5 5 4
p t z p p t p z p t z
i i
i p p p t p z t z
i
h x h xR
Gh x
ω ω ω ω ω ω ω ω ω ωωω ω
π ω ω ω ω ω ω ω ωω
ω
− − − + + −+ +
= − − + +
(A.37)
( ) ( )
( ) ( )
2
1 13
33 3 2 2
2 23
5 3 311
2 2 2 2 2
p p t p z t z
i i
i p p p t p z t z
i
f g f gL
f g
ω ω ω ω ω ωωω ω
ω ω ω ω ω ω ω ωω
ω
− − +− + − +
= − + + + + −
(A.38)
Appendix A.2 Spectrum of the ideal duty cycle modulation 233
Appendix A.3
Spectrum of the ideal duty cycle modulation From (5.21) the phase of the complex signal is given as:
( ) ( )it t dtλ ω= ∫ (A.39)
From ( )2 2 1 cos 2cos2m m
tv t v µµ + =
and sin 2cos 22
ttdt µµµ
=∫ , when (5.20) and (5.21)
are replaced in (A.39) the integral described with (A.39) can be solved as follows:
( ) ( )( )2
2
22
1 cos
1 sin 22
sin 22 4
c m
c c m
c mc c m
t v t dt
tt v dt
v t tt v
λ ω µ
µω ω
ω µω ωµ
= − =
−= − =
= − +
∫
∫ (A.40)
Of a primary interest are the first harmonic component and the base-band. That is why the
summation is limited to the zero and first component (k=0,1). Then (A.40) that describes the output spectra that emerges around the carrier frequency simplifies to the following expression:
( ) ( )
( )2 2
0,1
2cossin cos sin 22 2 2 4
2 1 4
m cm c mv tv t v t
y t d t
ωπ µ ωπ µµ
π
− − + = − −
(A.41) Nested sinusoidal functions of the type shown at the left hand side of (A.42) appear in
expression (A.41). Those can be substituted with Bessel functions of the first kind ( )nJ x with argument x and order n. The decomposition into Bessel functions is shown in the right hand side of (A.42).
( ) ( )( )
( ) ( ) ( )
2 11
0 21
sin( sin ) 2 sin 2 1 ;
cos( sin ) 2 cos 2 ;
nn
nn
x J x n
x J x J x n
α β α β
α β α β
∞
−=
∞
=
+ = + −
+ = + +
∑
∑ (A.42)
234 Appendix A. Evaluation of ASDMs
The first of the expansions in (A.42) contains only Bessel function of odd order, while the second expression contains the even orders Bessel functions. In the further mathematical evaluation of (A.41) according to (A.42), the following substitutions are made:
cos sin2
t tπµ µ = +
, 2
mva π= ,
( )222
m co
v ωω
−= and
2
4c mvb ωµ
= then (A.42) is represented
as:
( )
( ) ( ) ( ) ( ) ( )
( ) ( ) ( )
( ) ( ) ( ) ( )
0,1
2 1 0 2 01 1
0 2 11
2 1 2 01 1
cos
8 sin 2 1 2 cos 42 2
8 cos 2 12
cos16 cos 2 1 cos 4
2
m
l ml l
nl
m
l ml m
y t v t
J a l t J b J b t m t
J b J a l tv t
J a l t J b t m t
µ
π π µ ω µπ
π µπ
µπ µ ω µ
π
∞ ∞
−= =
∞
−=
∞ ∞
−= =
= −
− + − + + + − + + = − + − + +
∑ ∑
∑
∑ ∑
(A.43) where the indexes l,m are positive integers. Further simplification can be made when the
following equations ( )cos 2 1 02
l π− = and ( )sin 2 1 1
2l π− = ± , are substituted as follows:
( ) ( ) ( )
( ) ( ) ( ) ( )
( )
sin 2 1 cos 2 1 2 12 2 2
cos 2 1 cos 2 1 sin 2 1 sin 2 12 2
sin 2 1
l t l l t
l l t l l t
l t
π π πµ µ
π πµ µ
µ
+ − + = − + − =
= − − − − − =
= ± −
(A.44)
Then from (A.43) follows:
( )
( ) ( ) ( )
( ) ( ) ( ) ( )( )
0,1
0 2 11
2 1 2 01 1
cos
8 sin 2 1
16 sin 2 1 cos 4
m
ll
n ml m
y t v t
J b J a l t
J a J b l t t m t
µ
µπ
µ ω µπ
∞
−=
∞ ∞
−= =
= −
± − ± − ± − +
∑
∑ ∑
(A.45)
Appendix B
Application of DF forms in SDM analysis In this appendix, firstly the DF of BQ0 with respect to two input sinusoids is used for the
establishment of the active idle limit cycle in idle mode for a SDM loop with two possible idle limit cycles. Secondly, the calculation of the DF of BQ0 with respect to a combination of input sinusoid and DC signal is given. Finally, in Appendix B.3, the derivation of the sampled DFs for a BQ0 that described the SDM operation when driven with sinusoidal input signals, are shown.
Appendix B.1
Magnitude relations in sampled TSIDFs for BQ0
As discussed in Chapter 3, the TSIDF can take two different forms depending on the relative amplitudes of the two sinusoidal signals with respect to which the TSIDFs are derived. For BQ0, in the presence of two limit cycles with amplitudes
1 2 and LC LCA A , and
frequencies 1 2 and LC LCω ω , the two possible TSIDF forms are given in (B.1) and (B.2) from [9],
as: For the sinusoid with higher amplitude when
1 21LC LCk A A= > :
( ) ( ) ( ) ( )1 21
1
22 2
8, 1 = − − LCA LC LCLC
N A A E k k K kk Aπ
, (B.1)
where the complete elliptic integrals ( ) and ( )K k E k of the first and second kind
respectively, are defined as: ( ) 1
1
2
2 20 1 sin
=−
∫ LC
LC
dK k
k
π ϕ
ϕ and ( )
1 1
22 2
0
1 sin= −∫ LC LCE k k dπ
ϕ ϕ .
Respectively, for the second lower amplitude sinusoid when 1<k :
( ) ( )2 12
1
2
8, =LCA LC LC
LC
N A A E kAπ
(B.2)
In [9], via power series expansion of (B.1) and (B.2) in the forms given in (B.3), it is
demonstrated that if TSIDF is applied for a ASDM with binary quantizer, the two describing functions (B.1) and (B.2) are related by expression (B.4).
236 Appendix B. Application of DF forms in SDM analysis
( )
( )
1 212
1 222
2 4
2 4
2 1 3, 1 ...4 64
4 1 3, 1 ...8 64
= − − −
= + + +
LC
LC
A LC LCLC
A LC LCLC
N A A k kA
N A A k kA
π
π
(B.3)
( )( )
1 21
2 12
, 12,
≈LC
LC
A LC LC
A LC LC
N A A
N A A (B.4)
For the sampled TSIDF treated here, for a given loop filter, a fixed relation exists for the
amplitudes of the two idle limit cycles (an example for an ideal integrator is given in (6.5). Respectively, for a first order ideal integrator, from (6.5), the following ratio is established between the magnitudes of the two sampled TSIDFs.
( )( )
1 21
2 12
,1
,2
, , 116.9, ,
≈LC
LC
A LC LC s
A LC LC s
N A A
N A A
ϕ
ϕ (B.5)
For stability reasons, the loop filter phase behavior for frequencies sf 2 and sf 4 (and
lower sub-harmonic limit cycle frequencies, should those exist) should not exceed that of a second order filter. At the limit when the loop filter is of a second order, the TSIDF are related by the expression:
( )( )
1 21
2 12
,1
,2
, , 11.6, ,
≈LC
LC
A LC LC s
A LC LC s
N A A
N A A
ϕ
ϕ (B.6)
From the above derivation can be concluded that the ratio between the two sampled
TSIDFs in a stable low-pass SDM is always 1.6< .
Appendix B.2 Derivation of DIDF for BQ0 237
Appendix B.2
Derivation of DIDF for BQ0
The conditions for BQ0 switching are described by the expression:
( )1 when sin 0
sin1 when sin 0
in i i
in i i
in i i
Q LC LCQ LC LC
Q LC LC
V A ty V A t
V A t
ωω
ω
+ ≥+ = − + < (B.7)
From sin 0Q LC iin i
V A ϕ+ = → arcsin( )i Q LCin iV Aϕ = . Apparently, iϕ is the phase LCi
tω for which the BQ0 changes its state.
The Dual Input DFs (DIDF) for BQ0 can be derived for the signal component, as follows:
( ) ( )
( )
( )
2
,0
2
0
2
2
1, sin2
11
2
2 2 arcsin
i in in i i i
in
i i
i i
i
in
i
i
in i
in in
DC i LC Q Q LC LC LCQ
LC LC
QLC
i Q LCQ Q
N A V y V A dV
d d
Vd
V AV V
π
π ϕ π ϕ
π ϕ
π
π ϕ
ω ωπ
ω ω
πω
ϕπ π
+ −
+
−
= +
+ − +
= +
= =
∫
∫ ∫
∫ (B.8)
The DIDF for BQ0 can be derived for the limit cycle component, as follows:
( ) ( )
( )
( )
2
0
2
0
2
2
2
1, sin sin
sin 1 sin1
2sin
4 4cos 1
+ −
+
−
= +
+ − +
= +
= = −
∫
∫ ∫
∫
i i in in i i i i
i
i i
i i i i
i
i
i i
i
in i
i i
LC LC Q Q LC LC LC LCLC
LC LC LC LC
LCLC LC
i Q LCLC LC
N A V y V A dA
d d
Ad
V AA A
π
π ϕ π ϕ
π ϕ
π
π ϕ
ω ω ωπ
ω ω ω ω
πω ω
ϕπ π
(B.9)
238 Appendix B. Application of DF forms in SDM analysis
Appendix B.3
Derivation of sampled TSIDFs for BQ0
In appendix B.1 the TSIDF was used to identify the active idle LC, when two LCs are possible in the SDM loop. The calculation there made use of the fact that the relation between the amplitudes of the two idle LCs is known. When a sinusoidal input signal with a variable amplitude is applied, it may have a lower or higher amplitude than the amplitude of each possible LC. Each possible case needs to be studied in order to determine the SDM behavior.
Using the DF theory discussed in Chapter 3, the limit cycle TSIDF for a BQ01 that is driven by two sinusoids that represent the input signal and the thi limit cycle fundamental frequency, is derived by solving the double integral2 given in (B.10). The TSIDF for the signal is shown in (B.19).
( ) ( )2 2
, , 1 120 0
1, sin sin sin2
= + ∫ ∫LC i i i i iiLCi
A Qin AC LC Qin AC LC LC LC LCA
N V A y V A d dV
π π
ϕ ϕ ϕ ϕ ϕπ
(B.10)
where ,Q ACinV is the amplitude of the signal component at the quantizer input, 1 tϕ µ= with
µ defining the frequency of the SDM input signal and LC LCi itϕ ω= with LCi
ω defining the frequency of the thi limit cycle, and LCi
A is its amplitude. Expression (B.10) is evaluated for BQ0 by taking into account the following switching conditions:
( ) 1, 1
1
1 when sin sin 0sin sin
1 when sin sin 0i
in i i
i
i LCQ AC LC LC
i LC
ky V A
k
ϕ ϕϕ ϕ
ϕ ϕ
± ≥+ = − ± <
(B.11)
where ,i LC Q ACi ink A V= . The angle that satisfies the switching condition 1sin sin 0
ii LCkϕ ϕ± =
is -11 sin ( sin )
ii LCkϕ ϕ= . Therefore, for the case when , > 1
in iQ AC LC iV A k→ < , expression (B.10) can be written as:
( ) ( )
( )
1
1
2
120
, 2 sin sin 20
1 10 sin sin
sin4,
sin sin−
−
−
=
− +
∫∫
∫ ∫
i
LC in i ii LCiii
i i
i LCi
LC
A Q AC LC LCkLC
LC LCk
d
N V A dA
d d
π
π
ϕ π
ϕ
ϕ ϕ
ϕπ
ϕ ϕ ϕ ϕ
(B.12) After solving the inner integrals, (B.12) is written in the form:
1 The BQ0 is a static, memoryless and odd non-linear element. 2 Several possible derivations of expression (B.10) are given in [9].
Appendix B.3 Derivation of sampled TSIDFs for BQ0 239
( ) ( )( )2
, 20
8, cos arcsin sin= ∫LC in i i iii
A Q AC LC i LC LCLC
N V A k dA
π
ϕ ϕπ
(B.13)
The impact of sampling in the SDM loop is introduced by adding the phase delay ,s iϕ to
the TSIDF and by taking into account that the amplitude of the signal component at the quantizer input is evaluated only at discrete moments n and is given by , ,inQ n ACV . The
sampled TSIDF for the thi limit cycle in the presence of an input signal is derived from the TSIDF given (B.13) as:
( ) ( )( ),
2
, , , 20
8, , cos arcsin sins i
LC in i i iii
jA Q n AC LC s i i LC LC
LC
N V A e k dA
πϕϕ ϕ ϕ
π−= ∫
(B.14) Expression (B.14) can be simplified with the following trigonometric identities:
( )( ) ( )( )2 2 2cos arcsin sin 1 sin arcsin sin 1 sin= − = −i i ii LC i LC i LCk k kϕ ϕ ϕ and the substitution
of the complete elliptic integral of the second kind: ( ) ( ) ( )2
2 2
0
1 sin= −∫ i ii i LC LCE k k t d tπ
ω ω .
The simplified expression for the complex representation of the TSIDF for the limit cycle component at the quantizer input is then given as:
( ) ( ),, , , 2
8, , s i
LC in iii
jA Q n AC LC s i i
LC
N V A e E kA
ϕϕπ
−= (B.15)
The comparison of (B.16) with (B.2) shows that the sampled TSIDF differs from the usual
TSIDF by the added phase component and by the evaluation of the signal component at discrete time moments.
Using the condition for limit cycle oscillations given in (6.16), for a first order loop filter described in (6.20) and by using the complex representation of the sampled TSIDF in (B.15), the phase condition for maintaining limit cycle oscillations in the presence of a sinusoidal input signal is given by the solution of the following equation:
( )( ), ,2
8 cos cos sin sin 0i i
i s i i s i iLC LC
E kA
ϕ ρ ϕ ρπ ω
+ = ` (B.16)
From (B.15), again by using the general form in (6.16), and the loop filter description
from (6.20), the magnitude condition for limit cycle oscillation is given by the solution of the following equation:
( )( ), ,2
8 cos sin sin cos 1i i
i s i i s i iLC LC
E kA
ϕ ρ ϕ ρπ ω
+ = (B.17)
From (B.16) and (B.17) via trigonometric identities, the conditions for LC oscillation in a
first order SDM with BQ0 when driven with a sinusoidal input and , > 1in iQ AC LC iV A k→ < are
given by the system:
240 Appendix B. Application of DF forms in SDM analysis
( ) ( )
( ) ( )
,2
,2
8 sin 1
8 cos 0
+ =
− =
i i
i i
i s i iLC LC
i s i iLC LC
E kA
E kA
ϕ ρπ ω
ϕ ρπ ω
(B.18)
In analogy to (B.10), the signal TSIDF is described with the double integral:
( ) ( ),
2 2
, , 1 1 12, 0 0
1, sin sin sin2
= + ∫ ∫Qin AC i i i iV Qin AC LC Qin AC LC LC LCQin AC
N V A y V A d dV
π π
ϕ ϕ ϕ ϕ ϕπ
(B.19)
Appendix C
V-I normalization and Taylor series expansion
In this appendix, the formalization of the transconductor characteristics for the normalized circuit parameterization is applied for expressions (8.4) to (8.7). The results are given for each of the four circuits under consideration.
SP: 2
14
wm w= − (C. 1)
CCP: 2 2
1 21 2 1 21 1
4 4w wm m m w w= − = − − − (C. 2)
In the above expression ( )1
1 pm m
p+
= , ( )2 1m m p= + , ( )( )111
q pw w
p q+
=+
and
211
pw wq
+=
+. With such a representation, the impact of cross-coupling can be
represented and evaluated as a ratio between the sizes and the currents in the two cross-coupled pairs. Expression (C. 2) can be represented as a nonlinear function of p and q:
CCP: ( )
( )( )
( )( ) ( )
( )( )
( )( )
2 22 2 2
2 22
1 1 1 111 1 1 14 1 4 1
q p w q p p w ppm wp p q p qp q q
+ + + + = − − − + + + + + +
(C. 3)
For the RDP circuit, the function ( )m f w= , (normalized of ( )0 ii f v= ) is rather inconvenient for mathematical evaluation. That is why the reverse function ( )w f m= (8.6) is used in the derivation of the initial expression and consequently for the normalized one:
RDP: 1 12mw x m m= + + − − (C. 4)
For the RCCP circuit, the mathematical treatment unifies the approaches that are
used for the CCP and RDP circuits. The local resistive feedback in each transistor pair
is normalized as 11
gt
R Ixv
= and 22
gt
R Ixv
= . Then using (C. 3) and (C. 4), the
( )w f m= relation is derived as two functions for the two transistor pairs:
242 Appendix C. V-I normalization and Taylor series expansion
( )( )
( )( )
( ) ( )1
1 1 1 11 1
1 2 1p q q p m p m pmw xq p p q p p
+ + + + = + + − − + +
(C. 5a)
( )( ) ( ) ( )21 1 1 1 1 11 2 1
q m pw x m p m pp q
+ += + + + − − + + +
(C. 5b)
The following step is to represent the derived expressions with their series
expansion.
SP: 3 5
...8 128
w wm w= − − − (C. 6)
CCP: [ ] [ ] [ ]3 5, , , ...m w p q w p q w p qτ χ σ= − − (C. 7)
where: [ ] 1 (1 ), 1(1 ) (1 )
p qp q pp q p
τ +
= − + + , [ ] 1 (1 ), 1
8(1 ) (1 )p qp q q
q q pχ
+= − + +
and
[ ] 22
1 (1 ), 1(1 )128(1 )
p p qp q qq pq
σ + +
= − ++
RDP: ( ) 3 52 1 7 ...2 8 128
xw m m m
+= + + + (C. 8a)
At this point, due to the properties of the series expansion (for example [53]), we can return to the intended form ( )m f w= , by inversing the series:
RDP: ( )
( )( )
53
4 7
2 72 2 ...2 2 2 2
w xw wmx x x
+= − −
+ + + (C.8b)
For the RCCP, we apply the procedure as follows: firstly expressions (C.5a) and (C.5b) are represented in their series expansion, then the inverse series are calculated and finally the results are subtracted (cross-coupling results in subtraction of the output current). The exact functions, are not provided as they are too big, however, they are fully reproducible by following the described evaluation steps. Here, we use the simplified notation:
RCCP: [ ] [ ] [ ] [ ]3 5 7, , 1, 2 , , 1, 2 , , 1, 2 , , 1, 2 ...m w p q x x w p q x x w p q x x w p q x xρ ψ ζ ω= − − −
(C. 9)
Appendix D
Incorporation of the system filter function in REBIC
In this appendix, through several mathematical manipulations of expression (9.13), the high-resolution low-rate signal kb is expressed as a function of the system filter impulse response [ ] h jT and the high-frequency bitstream na . It is demonstrated that the function that is derived is recursive by nature and for the construction of kb previous samples of a and b are required. Firstly, expression (9.13) is repeated for convenience:
[ ] [ ]1
0 0
1( 1) ( 1)p pq q
k nk nb h p k a h p n q
q
+ −
= =
+ − = + −∑ ∑ (D.1)
Both sides of equation can be further developed mathematically. From the left hand side of
(D.1), the part the summation that corresponds to the current moment k p= can be extracted from the summation. The left hand side is then rewritten as:
[ ] [ ]1
0 0( 1) ( 1) [1]
p p
k k pk kb h p k b h p k b h
−
= =
+ − = + − +∑ ∑ (D.2)
The right hand side of (D.1) can also be separated in two parts. The first part combines the
last q samples of a and the second part combines the a samples taken previously to the current time moment. The right hand side of (D.1) can be represented as:
[ ] [ ] [ ]1 1 1
0 0
1 1 1( 1) ( 1) ( 1)pq q pq pq q
n n nn n n pq
a h p n q a h p n q a h p n qq q q
+ − − + −
= = =
+ − = + − + + −∑ ∑ ∑
(D.3) Combining again (D.2) and (D.3) according to (D.1) and after rearrangement of the terms,
the low bitrate signal at a current moment p can be expressed as:
[ ] [ ]
[ ] [ ]
1
1 1
0 0
11 ( 1)
1( 1) ( 1)
pq q
p nn pq
pq p
n kn k
b h a h p n qq
a h p n q b h p kq
+ −
=
− −
= =
= + − +
+ + − − + −
∑
∑ ∑ (D.4)
The mapping of (D.4) into a structure requires a choice for the system filter [ ] h jT . Using (9.20), the filter definitions in (D.4) can be expressed as:
244 Appendix D. Incorporation of the system filter function in REBIC
[ ] ( )m0
( 1) ( 1)M
m
mh p n q p n q
=
+ − = + −∑α (D.5)
After substitution of (D.5) in (D.4), the following expression is derived:
( )
( ) ( )
1
1 1
0 0
m m0 0
m m0 0
1[1] ( 1)
1 ( 1) ( 1)
pq q
p nn pq
pq p
n kn k
M Mm
m m
M Mm m
m m
b a
a b
h p n qq
p n q p kq
+ −
=
− −
= =
= =
= =
= +
+ −
+ −
+ − + −
∑
∑ ∑
∑ ∑
∑ ∑
α α
α α
(D.6) The first term at the right hand side of (D.6) represents the last q samples of the bitstream
na , the second term describes previous instances of the bitstream and the third one gives previous instances of the low bitrate signal. Expression (D.6) contains a recursive part that can be expressed in a compacter form. The derivation of such a compact form can be easily illustrated for a particular order M of the system filter. If M=2 , the summations in (D.6) can be developed as follows. With [1] 1h = , the left side of the equation is equal to:
2
m 0 1 20
p p p pm
b b b bα α α α=
= + +∑ (D.7)
The first term in the summation at the right side of (D.6) is then:
m 0 1 2
2
mp 0 p 1 p 2 pm 0
A A A A=
= + +∑α α α α (D.8)
where in (D.8):
( )11 ( 1)
pq q
nn pq
mmp aA p n q
q
+ −
=
= + −∑ (D.9)
The second and third terms in (D.6) can be combined in a common summation as:
2
m mp 0 0 p 1 1p 2 2 pm 0
r r r r=
= + +∑α α α α (D.10)
where
( ) ( )1 1
0 0
1 ( 1) ( 1)pq p
n kn k
m mmp a br p n q p k
q
− −
= =
= + − − + −∑ ∑ (D.11)
Expression (D.11) can be developed according to (D.10) in order to derive the individual
terms. The mpr terms are developed next, as:
Appendix D. Incorporation of the system filter function in REBIC 245
( ) ( )
( ) ( )
( ) ( )
1 1
0 0
1 1
0 0
1 1
0 0
0 0
01 1
1
22 2
1 ( 1) ( 1)
1 ( 1) ( 1)
1 ( 1) ( 1)
pq p
n kn k
pq p
n kn k
pq p
n kn k
p
p
p
a b
a b
a b
p n q p kqr
r p n q p kq
rp n q p k
q
− −
= =
− −
= =
− −
= =
+ − − + −
= + − − + −
+ − − + −
∑ ∑
∑ ∑
∑ ∑
(D.12)
The summations for na in (D.12) have boundaries between 0 and 1n n pq= = − . That
summation interval can be divided in two as from 0 up to 1n n pq q= = − − and from up to -1n pq q n pq= − = . The second summation boundary for na , with the help of (D.9)
can be identified as ( )-1m pA . Respectively, from the summation for kb the term that corresponds to time moment 1p − can be extracted. The regrouping of (D.12) in the separated summation boundaries is then described as:
( )
( ) ( ) ( ) ( )
( ) ( ) ( )
1 1 2
0 0
1 1
0
1 1
0 0
1
0 11
1 10
22
1
( 1)1 1
1 1( 1)
1 2( 1) 2
pq q q pq q p
n n kn pq q n k
pq q pq
n nn pq n
pq q pq p
n n kn pq n k
p
p p
p kpk
p
p
a a b p
a a
a a b
bq q
r
r p n q b p n q b p kq q
rp n q b p n q
q q
− + − − − −
= − = =
+ − −
= =
+ − − −
= = =
−
−
−=
−
+
− + −
= + − − + − − −
+ − − + − −
∑ ∑ ∑
∑ ∑
∑ ∑
∑
( )
( ) ( )
1
1 1
0 0
2 21 pq p
n kn k
a b
p k
p n q p kq
− −
= =
− + + − − −
∑
∑ ∑
(D.13)
Expression (D.13) can be significantly simplified when the recursive relations are
identified. For example, in the second line of (D.13), the expression
( ) ( )1
0
1
0
1 pq
nn
p
kk
a p n q b p kq
−
=
−
=
− − −∑ ∑ , can be compared with the second line of (D.12) and easily
identified as ( )1 1pr − . Through equivalent comparisons, for the third term in (D.13), (the individual terms are marked with square parenthesizes) the recursive relation can be derived as:
( ) ( ) ( )
( ) ( ) ( ) ( )
( ) ( ) ( ) ( ) ( )
0 1 1 0 10
1 1 1 1 0 1 1 1
2 2 1 1 0 1 1 1 2 12
p p pp
p p p p p
p p p p p p
A b rr
r A b r r
r A b r r r
− − −
− − − −
− − − − −
− + = − + + − + + +
(D.14)
Finally, the complete description of the decimation filter can be derived by combining
(D.7), (D.8), (D.10) and (D.14) and is given by the expression:
246 Appendix D. Incorporation of the system filter function in REBIC
( ) ( ) ( )( )( ) ( ) ( ) ( )
( ) ( ) ( ) ( ) ( )
0 0 1 1 0 10 00
1 1 1 1 1 1 1 0 1 1 1
2 2 22 2 1 1 0 1 1 1 2 1
2
p
p
p
p p pp
p p p p p
pp p p p p
b
b
b
A b rA
A A b r r
A A b r r r
− − −
− − − −
− − − − −
− + +++ + = + + − + + + − + + +
ααα
α α α
α α α
(D.15) Expression (D.15) can be given in compacter form for the general case of an M order
system filter as:
( ) ( ) ( )( )1 1 10 0 0 0
p
M M M m
m m mp m mii p p i pm m m i
b A A b C r− − −= = = =
= + − +∑ ∑ ∑ ∑α α α (D.16)
where in (D.16) mi
mC
i
=
is a binomial coefficient.
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[76] K. Philips, P.A. Nuijten, R. Roovers, A. van Roermund, F.M. Chavero, M. Pallares, A. Torralba, “A continuous-time Sigma-Delta ADC with increased immunity to interferers”, IEEE JSSC, Vol. 39, Issue 12, Dec. 2004, pp: 2170 – 2178.
[77] R. Schoofs, M. Steyaert, W. Sansen, “A 1 GHz continuous-time sigma-delta A/D converter in 90 nm standard CMOS”, Microwave Symposium Digest 2005, IEEE MTT-S International, June 2005.
[78] R. Schoofs, M. Steyaert, W. Sansen, “A 7.51mnW1,-bit Continuous-Time Sigma-Delta A/D Converter for WLAN Applications”, ISCAS May 2006, pp: 4.
[79] H. Aboushady, Y. Dumonteix, M.M. Louerat, H. Mehrez, “Efficient polyphase decomposition of comb decimation filters in sigma-delta analog-to-digital converters”, TCAS II (analog and digital signal processing), Oct. 2001, pp: 898-903.
[80] Y. Gao, L. Jia, J. Isoaho, and H. Tenhunen, “A comparison design of comb decimators for sigma–delta analog-to-digital converters”, Anal. Integr. Circuits Signal Processing, vol. 22, pp. 51–60, Jan. 2000.
[81] P. C. Maulik, M. S. Chadha, W. L. Lee, and P. J. Crawley, “A 16-bit 250-kHz delta–sigma modulator and decimation filter,” IEEE JSSC, vol. 35, pp. 458–467, Apr. 2000.
252 References
Original Contributions
• Derivation of generalized analytical expressions in terms of a system of characteristic equations that describe ASDMs’ properties in idle mode. The characteristic equations are applicable for ASDMs built with binary quantizer, binary quantizer with hysteresis, and three level quantizer. They give exact solutions for the amplitudes and the frequencies of the possible idle limit cycles for an arbitrary loop filter.
• Procedure for the exact mathematical evaluation of the impact of the ASDM loop filter on the modulator operation when driven with DC and harmonic inputs.
• Multi-limit-cycle model of the SDM operation. The model uses sampled describing functions for the analytical description of the interaction between the sampling clock and the inherent asynchronous oscillation mechanisms in the closed-loop non-linear sampled SDMs. It demonstrates that the SDM operation is based on the switching between two or more limit cycles.
• Criterion for SDM stability that uses the multi-limit cycle model of SDM operation for the definition of simple design rules that assure the stability of the desired SDM limit cycle behavior. The criterion can be used for a quick and simple check for the possible limit cycles and incorporates the impact of the loop filter, the quantizer and the extra loop delays.
• New model for the evaluation of the quantization noise that is introduced in the signal band by the SDM operation. The model distinguishes between amplitude and time quantization and demonstrates that the quantization noise depends on the implemented limit cycle behavior.
• Two design procedures for an optimal SDM parameterization. The first aims a maximal performance for a given loop filter order and clock speed. The second aims efficient in terms of power and area SDM implementation. The design procedures require an evaluation of the SDM limit cycle behavior and give guidelines for its optimization.
• Analysis and parameterization of a novel transconductor circuit that implements harmonic compensation via a combination of resistive degeneration and cross-coupling. The proposed circuit construction and parameterization result in a significant simultaneous suppression of the third and the fifth order harmonic components in the transconductor characteristic.
• IC design, implementation and measurement of:
Stand-alone highly linear and power efficient transconductor stage;
First and second order ASDMs that operate with limit cycle frequencies of respectively, 140MHz and 120MHz;
Second order SDM with a feedback topology that operates with 1GHz clock and with a dominant limit cycle of 8sf ;
254 Original Contributions
Fifth order extensively programmable SDM with a feed-forward topology that can operate with a range of clock speeds and can realize various limit cycle behaviors for an optimal solution of the trade-off performance/power consumption.
• Conceptualization and elaboration of the recursive bitstream conversion algorithm and its fundamental properties; and its application for the synthesis of power and area efficient decimators for SD ADCs.
11. List of Publications
S. Ouzounov, H. Hegt, A. van Roermund, “A Generalization of the Theory of Operation of SDMs”, IEEE JSSC, submitted. S. Ouzounov, H. Hegt, A. van Roermund, “Multi-limit-cycle Model for SDMs”, IEEE TCAS I, submitted. S. Ouzounov, H. Hegt, A. van Roermund, “Limit Cycle Model of Quantization Noise in SDM operation”, IEEE TCAS I, submitted. S. Ouzounov, R. van Veldhoven, C. Bastiaansen, R. van Wegberg, K. Vongehr, G. Geelen, L. Breems, A. van Roermund “A 1.2V, 121-Mode Continuous-Time SDM for Wireless Receivers in 90nm CMOS “, ISSCC 2007, vol. 50, Feb. 2007, pp:242-243. S. Ouzounov, E. Roza, H. Hegt, G.v.d Weide, A.v. Roermund, “Design of MOS transconductors with low noise and low harmonic distortion for minimum current consumption”, Integration, the VLSI Journal of Elsevier, Volume 40, Issue 3, 1 April 2007, Pages 365-379. S. Ouzounov, H. Hegt, A. van Roermund, “Sub-harmonic Limit-cycle Sigma-delta Modulation, Applied to AD Conversion”, Analog Circuit Design, Springer Netherlands, December 2006, ISBN 978-1-4020-5185-2, pp. 97-125. S. Ouzounov, R. van Veldhoven, C. Bastiaansen, R. van Wegberg, K. Vongehr, “CMOS090 Multi-Mode Sigma-Delta ADC for Wireless Applications”, Philips Analog Seminar, July 2006. S. Ouzounov, H. Hegt, A. van Roermund, "Sigma-Delta Modulators Operating at a Limit Cycle", IEEE TCAS II, vol. 53, no. 5, May 2006 pp. 399 – 403. S. Ouzounov, H. Hegt, A. van Roermund, "Sub-harmonic Limit-Cycle Sigma-Delta Modulation, Applied to AD Conversion", AACD 2006, April 2006. S. Ouzounov, E. Roza, H. Hegt, G.v.d. Weide, A. van Roermund, "Analysis and Design of High-Performance Asynchronous Sigma Delta Modulators with a Binary Quantizer”, Invited paper, IEEE JSSC, vol. 41, no. 3, March 2006 pp.:588 – 596. S. Ouzounov, E. Roza, H. Hegt, G.v.d. Weide, A. van Roermund, “A CMOS V-I Converter with 75dB SFDR and 360mW Power Consumption", Invited paper, IEEE JSSC, vol. 40, no.7, July 2005, pp. 1527-1532. S. Ouzounov, E. Roza, H. Hegt, G.v.d. Weide and A. van Roermund, "Design of High-Performance Asynchronous Sigma Delta Modulators with a Binary Quantizer with Hysteresis", Proceeding of CICC, Oct. 2004, pages 181-184.
256 List of Publications
S. Ouzounov, E. Roza, H. Hegt, G.v.d. Weide and A. van Roermund, "A CMOS V-I Converter with 75dB SFDR and 360mW Power Consumption", Proceeding of ESSCIRC, Sept. 2004, pages 235-238. S. Ouzounov, E. Roza, H. Hegt, G.v.d. Weide and A. van Roermund "An 8MHz, 72 dB SFDR Asynchronous Sigma-Delta Modulator with 1.5mW Power Dissipation", Proceeding of the Symposium on VLSI Circuits, June 2004, pages 88-91. S. Ouzounov, E. Roza, H. Hegt, G.v.d. Weide and A. van Roermund, "A DLL-based Poly-phase Sampler for a Sigma-Delta ADC", ProRISC 2004. S. Ouzounov, H. Hegt, A. van Roermund, “Implementation of a Tunable Integrated Analog RC Filter for a Sigma-Delta ADC in CMOS18 Technology”, ProRISC 2001
Patents: S. Ouzounov, H. Hegt, A. van Roermund, “A Method for Calibration of Time-Constants of SDM Loopfilter”, submitted. S. Ouzounov, H. Hegt, A. van Roermund, “A Method and Apparatus for Realization of Optimal Operation of SDMs”, submitted.
Future Work
The theoretical developments that are described in this thesis open several important opportunities for further research. Some possible extensions of this work that might have a high industrial relevance are outlined next.
• In the scope of this thesis, the limit cycle model of SDM operation and the limit cycle model for the quantization noise were primarily used for the evaluation of SDM stability and for the definition of an optimal, in terms of performance, power and area, SDM parameterization. However, those models can also be applied for the analysis of many other aspects of SDM operation and design. For example, the models can be used in the analysis of the impact of the loop filter topology, the non-idealities of the building blocks and the clock jitter.
• It is of practical interest to establish the applicability of the limit cycle model of the SDM operation when the application of the DF theory is questionable. For example, when the SDM input signal has a frequency close to the frequency of a possible limit cycle mode, it may lead to a disturbance of this limit cycle. Such a situation exists in practice when an SDM is used in the receiver chain of a communication system and strong interferers and blockers disturb the SDM input signal.
• Another important direction for future work can be sought in the relation between the SDM limit cycle behavior, the loop filter parameterization and the transitions in the SDM output bitstream. The SDM limit cycle behavior can be established with a simple measurement of the output bitstream. This opens the room for the introduction of new types of SDM calibration methods that establish the SDM limit cycle properties by measuring the output bitstream, and subsequently regulate the loop filter time constants such that the desired SDM limit cycle behavior is achieved.
• The ASDM property to convert continuous-amplitude continuous-time signals into discrete-amplitude continuous-time signals without quantization noise and with low power consumption has been underexposed. The theoretical developments presented in this thesis can be a good starting point in the investigation of new applications for those types of converters.
258 Future Work
Summary
Here, the main theoretical and experimental results achieved in the scope of the thesis are summarized and put into perspective. Their scientific and industrial relevance is discussed and several advances in state-of-the-art are pointed out. Firstly, the theoretical advances made in the understanding, description and analysis of ASDMs, SDMs, V-I converters and decimation filters are pointed out. Secondly, the results from the performed experiments in terms of high level or transistor simulations and IC measurements are summarized.
Despite the long record of applications that have used SDMs, for years, the fundamental mechanisms that govern their operation have not been fully explained. Namely, their non-linear nature has often been overlooked and the great majority of theoretical studies in the field have used linear approximations for their description and analysis. Several phenomena in the SDM operation, like the appearance of limit cycles, dead zones, stability conditions, impact of extra loop delays and the optimal SDM parameterization have not been fully explained. On the other hand the application areas that use SDMs is growing, and so are the requirements towards the SDM performance and power efficiency.
In this thesis, a different approach has been taken for the description, the analysis, and as a result, for the design of SDMs. Inspired from the insights in the limit cycle operation of ASDMs, we studied the well-known SDMs as non-linear, clock-synchronized, closed-loop systems. The complexity of non-linear analysis has been alleviated with the introduction of sampled DFs that allow the representation of the strongly non-linear quantizer functions as signal dependent linear gains. Such a representation of the quantizer is justified by the presence of low pass filters in the SDM loop and by the utilization of oversampling in the SDM construction. It has been shown that these two factors allow the application of the DF theory for the analysis of the SDM operation.
In the first three chapters of this thesis, the theoretical base for the study of ASDMs and SDMs was introduced. The basic principles of the Fourier expansion method and the DF analysis were described. Their application for the analysis of ASDMs was demonstrated.
Chapter 4 treated the ASDM operation in idle mode. With the help of both studied methods, the conditions for existence, the frequency, and the amplitude of the possible idle limit cycles in the ASDM operation were established. It was shown that with the help of the Fourier expansion method, the operation of each ASDM, for a particular quantizer, can be described with a system of characteristic equations, from which the limit cycle properties can be established. In this way, the existing theories were unified and generalized. Further, it was shown that the DF method offers an alternative, simpler but in some cases only approximate evaluation. In the worst case, of a first order loop filter, the DF results deviate about 36% from the exact solution. For third and higher order loop filters, the deviation is already negligible. The power of the DF method is in the simplicity with which a great variety of quantizer functions can be treated.
In Chapter 5, the ASDM analysis was extended to incorporate the impact of DC and harmonic inputs. A mathematical procedure was proposed for the exact calculation of the variations of the limit cycle frequency and duty cycle for DC input. The calculation of the characteristics equations for DC input was illustrated for a basic set of loop filters that can be used for extension of the analysis to all loop filter functions of a practical importance. For this purpose, the filter had to be represented via partial fractional decomposition into the basic filter functions. It was also demonstrated that with the Fourier expansion method, the
260 Summary
ASDM output spectrum for harmonic inputs can be described analytically. Again, as in idle case, as an alternative method for analysis, DFs were used. Their strength for a simple verification of the ASDM limit cycle behavior for DC and harmonic inputs was shown. The two methods were seen as complementary to each other: Describing functions can be used for a quick analysis of the basic properties, while the computationally intensive Fourier expansion method can be applied when an exact description of the ASDM output signal is required.
In Chapter 6, a new limit cycle model of SDM operation was introduced. It described the interaction of the sampling clock with the underlying asynchronous mechanism that is due to the non-linear closed loop nature of the SDMs. The new model is able to identify and describe in terms of conditions for existence, frequency and amplitude, the possible idle limit cycle modes in the SDM operation. The limit cycle model is further extended to incorporate the situation when the SDM is driven with an input signal. It shows that in this case the SDM switches between the possible limit cycles. The model illustrates that this switching is governed by the properties of the SDM loop filter, the quantizer and the extra intended and parasitic loop delays. The design procedures for the realization of a particular limit cycle behavior were explained. Simulation results for various loop filters and quantizer configurations are provided that confirm the power of the model to relate the limit cycle behavior with the parameterization of the SDM implementation.
In Chapter 7, with the help of a new limit cycle model for the quantization noise, the SDM LC behavior was related to the achievable performance. The possibility to implement a specific LC behavior in order to solve in an optimal way the trade-off between power consumption, chip area, and performance, was conceptualized and verified with high-level simulations. In Chapter 10, in the context of a multimode SDM implementation, it was demonstrated that a specific limit cycle behavior can be introduced in order to reduce the required power consumption and area for many modes of operation. Several design techniques that allow modification of the SDM LC behavior were described. It is pointed out that via the introduction of poles and zeroes in the loop filter transfer characteristics that modify the SDM limit cycle behavior, the designer can implement a robust SDM that requires a minimal power consumption for the desired performance.
In Chapter 8, special attention was given to the design of linear and power efficient V-I converters. The V-I converters were identified as a key building block in the SDM design that can determine the performance of the whole system. The linearity of the V-I converters was pointed out as the most challenging aspect of their implementation. In order to generalize their analysis a normalization procedure for the transconductor analysis was introduced. Then the harmonic compensation method was identified as a powerful mechanism for the linearization of the V-I characteristics. Based on the analysis a new transconductor structure was proposed and compared via simulations, with the most widely used alternative methods for transconductor linearization. In Chapter 10 the IC implementation of the new V-I converter circuit was described. The measurement results confirm the analytic study and the power efficiency of the circuit implementation.
In Chapter 9, the decimation process via the recursive bitstream conversion (REBIC) algorithm was conceptualized, extended and elaborated. A possible implementation into digital hardware was described. It was demonstrated that the REBIC algorithmic complexity pays off with a very simple and power efficient implementation. The proposed REBIC implementation is characterized by an immediate downsampling of the SDM output bitstream, uses recursive filters and at the same time requires a minimal number of multiplications. Stability of a third-order decimator was evaluated and a simple way for the implementation of a stable third-order filter, with decimation factors of 4 and 8, was described.
Samenvatting
Op deze plaats worden de voornaamste theoretische en experimentele resultaten, die in het kader van het proefschrift zijn bereikt, samengevat en in perspectief geplaatst. Hun wetenschappelijke en industriële relevantie wordt besproken en verscheidene vorderingen in de huidige stand van zaken worden naar voren gebracht. Ten eerste worden de gemaakte theoretische vorderingen in het begrip, de beschrijving en analyse van asynchrone sigma-delta modulatoren (ASDM’s), synchrone sigma-delta modulatoren (SDM’s), spanning-stroom omzetters (V-I omzetters) en decimatiefilters naar voren gebracht. Ten tweede worden de resultaten samengevat van de experimenten uitgevoerd met hoog-niveau of transistorsimulaties en metingen aan geïntegreerde schakelingen (IC’s).
Ondanks de lange reeks van toepassingen die SDM’s hebben gebruikt, worden al jaren de fundamentele mechanismen die hun werking bepalen, niet volledig begrepen. Hun niet-lineaire karakter wordt namelijk vaak over het hoofd gezien en de grote meerderheid aan theoretische studies in het vakgebied hebben lineaire benaderingen gebruikt voor hun beschrijving en analyse. Verscheidene fenomenen in de werking van de SDM, zoals het optreden van limit cycles, dode zones, stabiliteitsvoorwaarden, de invloed van extra lusvertragingen en de optimale SDM parametrisering zijn niet volledig opgehelderd. Aan de andere kant nemen de toepassingsgebieden die SDM’s gebruiken toe, evenals de eisen aan de prestatie en vermogensefficiëntie van een SDM.
In dit proefschrift is een andere benadering gekozen voor de beschrijving, analyse, en dientengevolge, voor het ontwerp van SDM’s. Geïnspireerd door de inzichten in de werking van limit cycles van ASDM’s, bestudeerden we de welbekende SDM’s als niet-lineaire, met een klok gesynchroniseerde, gesloten lus systemen. De complexiteit van niet-lineaire analyse werd verlicht door de introductie van bemonsterde beschrijvende functies (BF’s), die de voorstelling van de sterk niet-lineaire kwantisatiefuncties door signaal afhankelijke lineaire versterkingsfactoren mogelijk maken. Een dergelijke voorstelling van de kwantisator wordt gerechtvaardigd door de aanwezigheid van laagdoorlaatfilters in een SDM lus en door de toepassing van overbemonstering in de constructie van een SDM. Er wordt aangetoond dat deze twee factoren de toepassing van de BF theorie voor een analyse van de werking van een SDM mogelijk maken.
In de eerste drie hoofdstukken van dit proefschrift werd de theoretische basis geïntroduceerd voor de studie van ASDM’s en SDM’s. De basisprincipes van de Fourier expansiemethode en BF analyse werden beschreven. Hun toepassing voor de analyse van ASDM’s werd aangetoond.
Hoofdstuk 4 behandelde de werking van de ASDM zonder ingangssignaal. Met behulp van beide bestudeerde methoden werden de bestaansvoorwaarden, de frequentie en de amplitude vastgesteld van de mogelijke limit cycles van de ASDM zonder ingangssignaal. Er werd aangetoond dat met behulp van de Fourier expansie methode, de werking van elke ASDM, voor een bepaalde kwantisator, beschreven kan worden door een systeem van karakteristieke vergelijkingen waaruit de limit cycle eigenschappen vastgesteld kunnen worden. Op deze wijze werden de bestaande theorieën met elkaar verenigd en gegeneraliseerd. Verder werd het aangetoond dat de BF methode een alternatieve, simpelere maar in sommige gevallen slechts een benaderende evaluatie biedt. In het slechtste geval, voor een eerste orde lusfilter, wijken de BF resultaten ongeveer 36% af van de exacte oplossing. Voor derde en hogere orde lusfilters is de afwijking reeds verwaarloosbaar. De
262 Samenvatting
kracht van de BF methode ligt in de eenvoud waarmee een grote verscheidenheid aan kwantisatiefuncties beschreven kan worden.
In hoofdstuk 5 werd de ASDM analyse uitgebreid om de invloed van constante en harmonische input op te nemen. Een wiskundige procedure werd voorgesteld voor de exacte berekening van de variaties in de limit cycle frequentie en duty cycle. De berekening van de karakteristieke vergelijkingen voor een constante input werd geïllustreerd voor een basisverzameling van lusfilters, die kan worden gebruikt voor de uitbreiding van de analyse naar alle lusfilterfunkties die van praktisch belang zijn. Voor dit doel moest het filter via partiële breuksplitsing gerepresenteerd worden in de basis filterfuncties. Er werd ook aangetoond dat het ASDM uitgangsspectrum voor harmonische ingangssignalen analytisch beschreven kan worden met de Fourier expansiemethode. Opnieuw werden, zoals in de situatie zonder ingangssignaal, BF’s gebruikt als een alternatieve analysemethode. Hun kracht om het ASDM limit cycle gedrag eenvoudig te verifiëren, werd aangetoond voor constante en harmonische input. De twee methoden werden gezien als complementair aan elkaar: Beschrijvende functies kunnen worden gebruikt voor een snelle analyse van de basis eigenschappen, terwijl de rekenintensieve Fourier expansiemethode kan worden toegepast als er een exacte beschrijving van het ASDM uitgangssignaal nodig is.
In hoofdstuk 6 werd een nieuw limit cycle model voor de SDM geïntroduceerd. Het beschreef de interactie van de bemonsteringsklok met het onderliggende asynchrone mechanisme dat het gevolg is van het niet-lineaire gesloten lus karakter van SDM’s. Het nieuwe model is in staat om, in termen van bestaansvoorwaarden, frequentie en amplitude, de mogelijke limit cycle modi van een SDM zonder ingangssignaal te identificeren en beschrijven. Het limit cycle model werd verder uitgebreid om de situatie op te nemen waarbij een SDM wordt bedreven met een ingangssignaal. Het laat zien dat in dit geval de SDM schakelt tussen de mogelijke limit cycles. Het model laat zien dat dit schakelen wordt bepaald door de eigenschappen van het SDM lusfilter, de kwantisator en de extra bedoelde en parasitaire lusvertragingen. De ontwerpprocedures voor de realisatie van een bepaald limit cycle gedrag werden uitgelegd. Simulatieresultaten voor uiteenlopende lusfilters en kwantisatorconfiguraties werden verschaft, die de kracht van het model bevestigen om limit cycle gedrag te relateren aan de parametrisatie van de implementatie van de SDM.
In hoofdstuk 7 werd, met behulp van een nieuw limit cycle model voor de kwantisatorruis, het limit cycle gedrag van een SDM gerelateerd aan de haalbare prestatie. De mogelijkheid om een specifiek limit cycle gedrag te implementeren met als doel om op een optimale manier de inruil tussen vermogensverbruik, chipoppervlak en prestatie op te lossen, werd tot een theorie gevormd en geverifieerd met hoog niveau simulaties. In de context van een multimodus SDM implementatie werd in hoofdstuk 10 aangetoond dat een specifiek limit cycle gedrag kan worden geïntroduceerd met als doel om het vermogensverbruik en het oppervlak te reduceren voor veel werkingsmodi. Verscheidene ontwerptechnieken werden beschreven die verandering van het SDM limit cycle gedrag mogelijk maken. Er wordt naar voren gebracht dat via de introductie van polen en nulpunten in de karakteristieken van de lusfilteroverdracht, die het SDM limit cycle gedrag veranderen, de ontwerper een robuuste SDM kan implementeren die een minimaal vermogensverbruik nodig heeft voor de gewenste prestatie.
In hoofdstuk 8 werd er speciale aandacht gegeven aan het ontwerp van lineaire en vermogensefficiënte V-I omzetters. De V-I omzetters werden geïdentificeerd als de belangrijkste bouwblokken in het ontwerp van een SDM die de prestatie van het gehele systeem kunnen bepalen. De lineariteit van de V-I omzetters werd aangewezen als het meest uitdagende aspect van hun implementatie. Om hun analyse te generaliseren werd er een normalisatieprocedure geïntroduceerd voor de transconductantieanalyse. Daarna werd de
Samenvatting 263
harmonische compensatiemethode aangewezen als een krachtig mechanisme om de V-I karakteristiek te lineariseren. Een nieuwe transconductantiestructuur werd op basis van deze analyse voorgesteld en via simulaties vergeleken met de meest gebruikelijke alternatieve methoden voor transconductantielinearisatie. In hoofdstuk 10 werd de IC implementatie van de nieuwe V-I omzetter beschreven. De meetresultaten bevestigen de analytische studie en de vermogensefficiëntie van de geïmplementeerde schakeling.
In hoofdstuk 9 werden de ideeën gevormd, uitgebreid en tot in detail uitgewerkt van het decimatieproces via het recursieve bitstream conversiealgoritme (REBIC). Een mogelijke implementatie op digitale hardware werd beschreven. Er werd aangetoond dat de complexiteit van het REBIC algoritme zich uitbetaalt in een erg eenvoudige en vermogensefficiënte implementatie. De voorgestelde REBIC implementatie wordt gekarakteriseerd door een directe verlaging van de bemonsteringsfrequentie van de uitgangsbitstream van de SDM, gebruikt recursieve filters en vereist tegelijkertijd een minimaal aantal vermenigvuldigen. De stabiliteit van een derde orde decimator werd geëvalueerd en een eenvoudige manier werd beschreven om een stabiel derde orde filter te implementeren met decimatiefactoren van 4 en 8.
264 Samenvatting
Acknowledgements
Herewith, I would like to acknowledge the people that have determined or influenced my work and my life during the busy years of my Ph.D. work.
Firstly, I would like to express my gratitude to Hans Hegt, who as my daily-talk supervisor (over the years), did not gave up on me and supported me in the most difficult moments. Hans the teacher: always looking for the best way to educate; Hans the scientist: always ready to have a critical look; and of course, Hans the person: whose character I will always admire.
Then I would like to thank Professor Arthur van Roermund for opening for me the door of structural thinking and showing me the path of scientific approach and universal technical knowledge. I would never forget the fruitful, eye-opening discussions with him.
I would like to thank Engel Roza for being the initiator, the inspiriting factor or the first reference for many subjects of my work. He threw me in the deep waters of advanced research, abstract thinking and high personal standards and convinced me that swimming is not a nice future but a requirement. I will always admire his passion for science and his ability to see the things in life and in science from a different perspective.
I also want to thank Gerard van der Weide for his coaching and support and Peter Scholtens and Henk Termeer for helping me with my tapeouts and spearing me a third sleepless night in a row for my second tapeout.
I want to thank Valery Mladenov for bringing me to The Netherlands, introducing me to my wife and the many personal and technical discussions we have had over the years.
I want to thank Georgi Radulov for being my closest “Bulgarian connection” in The Netherlands and the pleasant talks we have had, manly on Bulgarian topics, and for convincing me that I can compete (beat) him in every game and especially chess and tennis.
I want to express my special thanks to Jeroen Tol for translating the summary of my thesis and for being one of the few Dutch friends that I have who helped me to improve my Dutch and to get some real cultural awareness for the country I am leaving in.
It has been a pleasure to work in the MsM group in TU Eindhoven and meet such great guys as Johan van der Tang, Achie, Kostas, Vojkan and Maja, Pieter van Beek, Athon, Dusan, Emanuele and Pieter Harpe. I want to thank Linda, Piet, Oto, Gerard and Margot for creating the atmosphere in the group and for being always helpful and concerned.
I want to thank Emilia Bazhlekova for helping me with the mathematics of the series expansions of the filter functions and Ivan Bazhlekov for his friendly advice and support.
I highly appreciated the support from the Mixed-signal Circuits and Systems group at Philips Research (now NXP Research).
I want to thank my AMoS colleagues for giving me the opportunity to strengthen my knowledge and confidence in a pleasant, very collegial and highly professional atmosphere.
Stepping on personal grounds, I want to mention the small Bulgarian community in Eindhoven that in my first years in The Netherlands bridged the social gap and was a source of fun and relaxation; my friends: Veronika and Hans, Emi and Ivan, Eli and Goro, Gabi and Alain, Maria and Kamen, Kiro, Mircho, Sasho, Krisi and Alex, and the whole Bulgarian community.
264 Acknowledgements
I want to thank my Bulgarian friends, back in the homeland or all around the world with whom I managed to preserve and develop contact and whose friendship supported me in the years: Kolio, Niki, Peter and Barbara, Bobi, Ani and Ivan, Liub and Iliicho.
I want to express my gratitude to my grandmother, my parents and my brother for their love and appreciation of all my deeds and for providing me with the safe harbor where I can always return from my journeys. I want to thank my cousins Angelina, Maria and Vania who with their regular mails kept the link with my family.
Finally, I want to thank Mariya for entering my life, giving me our lovely daughter and for keeping me alert about the important things in life. I hope she would forgive me the long days at work and the weekends I have missed in writing.
Biography
Sotir Ouzounov was born in Bulgaria, on February 21, 1973. He received his M.Sc. degree in Electrical Engineering from Technical University of Sofia, Bulgaria, in 1997. His graduation project was on the application of Fuzzy Logic in the control of mobile robots and was done in Technical University Ilmenau, Germany with DAAD scholarship.
After graduation he worked as a hardware design engineer in the Melexis, Bulgaria where he was involved in the design of industrial IC test equipment.
In 2000, he joined as a Ph.D. student the Mixed-Signal Microelectronics group at Eindhoven University of Technology, The Netherlands. He has been working on high-speed asynchronous and synchronous sigma-delta converters and the associated circuits.
In 2005 he joined NXP Semiconductors as a senior analog designer and project technical lead, where he was working on multi-mode sigma-delta ADCs for wireless receivers.
In June 2008, he joined Philips Research Laboratories in Eindhoven as a senior research scientist.
The author has more than fifteen journal and conference publications and is a reviewer of several professional journals.
268 Biography