mult logic opt

7/27/2019 Mult Logic Opt

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ECE 4514Digital Design II

Spring 2008

Lecture 18:

Patrick SchaumontSpring 2008

ECE 4514 Digital Design IILecture 18: Optimizing Area

Optimizing Area

A Tools/Methods Lecture

Patrick Schaumont


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Optimization and Backend Verification

Previous 4 lectures (Lecture 13-16):How to get Verilog mapped into hardware

Next 2 lectures:How to optimize Verilog for hardware implementationToday (Lecture 17): Optimize for (smaller) areaThursday (Lecture 18): Optimize for (higher) performance




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Why do we need optimization?

A given algorithm can be implemented in manydifferent ways in digital hardware

Each implementation is characterized byA certain area (In FPGA: Slices)A certain cycle budget (the amount of cycles needed tocomplete one iteration through the algorithm)



The application domain and other externalrequirements provide constraints for the area or theperformance (=cycle_budget -1)

'Create a circuit not larger than can fit in a Spartan3S100

FPGA ...' (area)'Create an implementation that can complete at least 500million additions per second ..' (performance)


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Area-Delay Product

Area(eg. Slices)

Assume that a given designcan be implemented in 5

different ways, and that all ofthem have the same Area-Delayproduct. All these points lie on

a hyperbole, sinceArea x Delay = Constant



Delay = Performance -1(e.g. cycles)

implementation to use?

By introducing CONSTRAINTS


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Area-Delay Product

An Area constraint

Area(eg. Slices)

Area Constraint




'Smaller then ...'


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Area-Delay Product

An Area constraint

Area(eg. Slices)

Most optimal point (smallest delay)for given area constraint

Area Constraint




'Smaller then ...'


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Area-Delay Product

A Performance Constraint

Area(eg. Slices) Performance ConstraintFaster then ...'





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Area-Delay Product

If no constraint is given, all points with the same area-delay product are equally optimal

Area(eg. Slices)

Suboptimalpoints





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Area-Delay Product

Sub-optimal points

Area(eg. Slices) Suboptimal because:

for any area constraint,blue point is faster

AND smaller





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Area-Delay Product

Sub-optimal points

Area(eg. Slices) Suboptimal because:

for any speed constraint,blue point is faster AND

smaller





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Area-Delay Product

Optimal points dominate sub-optimal points

Area(eg. Slices)




This point outperformsall points in the rectangle

defined with this pointas a corner


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Area-Delay Product

Finding all the optimal points for a random collection

Area(eg. Slices)

In a real design, the set of solutions willnever lie on a nice hyperbole, but

look more as a cloud of points





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Area-Delay Product


Area(eg. Slices)

You can find the optimal ones by drawing

a rectangle for each of them and eliminatingsuboptimal points





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Area-Delay Product


Area(eg. Slices)

You can find the optimal ones by drawing

a rectangle for each of them and eliminatingsuboptimal points





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Area-Delay Product


Area(eg. Slices)

Finally, you can draw a 'staircase' curve

the reflects all the optimal solutionsfor your design.





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Area-Delay Example

Area-delay product for an AES Sbox (component of anencryption algorithm) using different architectures




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Where do constraints come from?

Constraints are defined by the application domain orthe system that will integrate a given digital design

Application Domain(E.g. Speech Processing in Mobile Phone)

Real-Time Constraints

Cost (E.g. x $/Phone)max die size



. .Freq = 4 KHz)

for package y

Speech CoderDigital Design

Delay (Cycles)

Area

Clock Frequency

Battery Type,Capacity

Power Budget


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Area Optimization - Overview

Resource Sharing

Hardware Sharing Factor

Examples:An unshared multiplierA shared multiplier




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Resource Sharing

Unshared case

f1 f1in out

CombinationalLogic

CombinationalLogic



clk

in

out

in0 in1 in2 in3 in4

out0 out1 out2 out3 out4


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Resource Sharing

Shared case

f1in

out

CombinationalLogic

0

1



clk

in

out

in0 -- in1 -- in2 ---- out0 -- out1 -- out2

c

c


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Resource Sharing

Registers are relatively big compared to combinationallogic (recall: 6 gates for a D flip-flop); whilemultiplexers are small (3 gates for a mux)

Therefore, the equation is easy to satisfy



Af1 + Areg > Amux


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Resource Sharing trade-off area & performance

f1in

out

CombinationalLogic

c

0

1 f1 f1in out

CombinationalLogic

CombinationalLogic

1x function f1

2x function f1



1 register

1 input each cycleTHROUGHPUT 1 input eachtwo cycles

LATENCY Total compute time perinput is two cycles

Total compute time perinput is two cycles

Smaller

Faster


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The Hardware Sharing Factor (HSF) expresses thepotential amount of resource sharing in a digital design

DigitalLo ic

Input

DataRatefin

Output

DataRatefout



Design

fCLK

HSF = f CLK / max(f in , fout )

HSF is the amount of clock cycles available per data item


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Different styles of design will be reflected with adifferent HSF

1

10

Unmultiplexed, Maximum-throughput Hardware

Lowly Multiplexed Hardware(simple FSM-based control)



100

1000

Medium Multiplexed Hardware(control based on simple Picoblaze-like sequencers)

HSF

'infinite' Microprocessors(control is software !)

Highly Multiplexed Hardware(control based on complex microcoded sequencers)


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Spartan3: 70 LUTs, 10.6 ns delay



Shift-expansion

Adder-tree


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Example: An unshared multiplier

The idea of a shared implementation is to 'chop' thecombinational logic in smaller similar pieces, andexecute these similar pieces over multiple clock cycles

a, b qa * b



"f1" "f1" "f1"

Stages with similar operation,separated by registers


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For a multiplication, repeated add-shift is the obvious'repeating' part to be shared.

15 1 1 1 1

12 1 1 0 0X



0 0 0 01 1 1 1

1 1 1 1

1 0 1 1 0 1 0 0180

Instead of adding4 partial products

at one, generateonly a single one

at-a-time andaccumulate the

result


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module syn_ex3(q, a, b);output [15:0] q;reg [15:0] q;input [7:0] a, b;

reg [15:0] tmp [7:0];

always @(a or b) begintmp[0] = b[0] ? a : 15'b0;

8 * 8 bit multiplicationwritten using add-shift



tmp[1] = tmp[0] + (b[1] ? {a, 1'b0} : 15'b0);tmp[2] = tmp[1] + (b[2] ? {a, 2'b0} : 15'b0);tmp[3] = tmp[2] + (b[3] ? {a, 3'b0} : 15'b0);tmp[4] = tmp[3] + (b[4] ? {a, 4'b0} : 15'b0);tmp[5] = tmp[4] + (b[5] ? {a, 5'b0} : 15'b0);tmp[6] = tmp[5] + (b[6] ? {a, 6'b0} : 15'b0);tmp[7] = tmp[6] + (b[7] ? {a, 7'b0} : 15'b0);q = tmp[7];

end endmodule


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Spartan3: 108 LUTs, 20ns delay ..

Patrick SchaumontSpring 2008ECE 4514 Digital Design IILecture 18: Optimizing Area


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Shared multiplier


reg [15:0] tmp [7:0];


tmp/q

a 0

+Share the adder bymapping one

statement per clock cyle



end endmodule


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Shared multiplier

module syn_ex4(q, done, a, b, start, clk);output [15:0] q;reg [15:0] q;output done;input [ 7:0] a, b;

input start;input clk;reg [ 4:0] ctr;reg [15:0] shiftA;


reg : s ;

always @(posedge clk) beginctr


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Shared multiplier

module syn_ex4(q, done , a, b, start , clk);output [15:0] q;reg [15:0] q;output done;input [7:0] a, b;


Controller


reg : s ;



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Shared multiplier

module syn_ex4(q, done, a, b, start, clk);output [15:0] q;reg [15:0] q;output done;input [7:0] a, b;


B shifts down, A shifts up


reg : s ;



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Shared multiplier

module syn_ex4(q, done, a, b, start, clk);output [15:0] q;reg [15:0] q;output done;input [7:0] a, b;


Accumulator


reg : s ;



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Sh i d f d l


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Sharing may reduce area at expense of delay

Area(LUT)

unsharedmultiplier

108 LUT, 20 ns


Delay

sharedmultiplier

36 LUT, 32 ns

Oth S l ti ibl


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Other Solutions are possible ...


reg [15:0] tmp [7:0];


Create an implementationwith two adders

Rewrite code to twostatements per clock cycle



end endmodule

Oth S l ti ibl


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Other Solutions are possible ...


reg [15:0] tmp [7:0];


Create an implementationwith four adders

Rewrite code to fourstatements per clock cycle


tmp[1] = tmp[0] + (b[1] ? {a, 1'b0} : 15'b0);

tmp[2] = tmp[1] + (b[2] ? {a, 2'b0} : 15'b0);tmp[3] = tmp[2] + (b[3] ? {a, 3'b0} : 15'b0);tmp[4] = tmp[3] + (b[4] ? {a, 4'b0} : 15'b0);tmp[5] = tmp[4] + (b[5] ? {a, 5'b0} : 15'b0);tmp[6] = tmp[5] + (b[6] ? {a, 6'b0} : 15'b0);tmp[7] = tmp[6] + (b[7] ? {a, 7'b0} : 15'b0);q = tmp[7];

end endmodule



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Area(LUT)

unsharedmultiplier

108 LUT, 20 ns


Delay

sharedmultiplier

36 LUT, 32 ns

This will generateadditional intermediate

solutions


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Example Full Adder > Half Adder


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Example Full Adder -> Half Adder

Propagate '0' into Ci

SABCi0


Co

Half Adder: S = A B, Co = A & B

Example: constant multiplication


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(* mult_style = "lut" *)

module syn_ex6(q, a);output [15:0] q;input [7:0] a;

assign q = a * 215;


endmodule

215 = 11010111

Spartan3: 36 LUT 13 5 ns


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Spartan3: 36 LUT, 13.5 ns

Cfr: 70 LUT, 10ns for full 8*8 bit



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(* mult_style = "lut" *)

module syn_ex6(q, a);output [15:0] q;input [7:0] a;

assign q = a * 64;



endmodule

When constant is a power of two,multiplication becomes a

hardwired shift: no LUT's needed at all!

mult logic opt

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