mukul resume internship_summer
TRANSCRIPT
MUKUL MISHRA 7825 McCallum Blvd, Dallas, TX – 75252
Email: [email protected] , [email protected] +1(682)256-8741 | https://www.linkedin.com/in/mishramukul
Objective: To obtain a challenging Co-op/Internship position in the field of Analog mixed signal/RF IC design (VLSI Design) starting
Summer 2017.
Education: The University of Texas at Dallas, Texas, USA GPA 3.56 Masters in Electrical Engineering June 2018 (Expected) Dr. A.P.J. Abdul Kalam Technical University, INDIA GPA 3.8 Bachelors in Electronics and Telecommunication Engineering May 2012
Work Experience: System Engineer | Tata Consultancy Services, Mumbai, India Mar, 2013- June, 2016
Involved in developing Perl and shell scripts for File processing and validation.
Worked as team-lead for Test planning, test-design and automation & legacy scripts migration.
Interacting with the clients in requirement and scope finalization. ASIC Engineer(Intern) | R V VLSI Design Centre, Bangalore, India July 2012 – Feb 2013
Worked on complete Full-custom and ASIC design flows.
Logic Design, RTL coding and FSM-Optimization for cryptography algorithms and Test-environment development.
Standard cell library designing and characterization
Exposure to the STA for different Paths in the circuit and detailed Knowledge on types of Delays and Constraints in the Circuit, using PrimeTime STA Tool.
Exposure to Full Custom Chip Design and designing layout for various combinational and sequential circuits using ICStudio and detailed analysis for DRC, LVS and PEX using Calibre.
CAD Skill: Frontend: Mentor Graphics QuestaSim 6.4b, Modelism 10.4, Xilinx ISE 14.2. Backend: Design Compiler (Synthesis), Prime Time (STA), Virtuoso, IC Studio (Layout), Synopsys IC Compiler (ICC) (Physical
Design), Microwave Office. Scripting/ Programming Languages: Verilog, Perl, Shell scripting, Tcl/tk, C, JAVA-J2EE
Relevant Projects:
End to end design implementation for standard Algorithm TDES (Triple Data Encryption Standard): Coding in Verilog HDL, design & characterization of a standard cell library of IBM 130 nm for synthesis of design, Placement and routing of design and pre/post power and timing analysis using Primetime.
Design of 90nm, 130nm and 180nm standard cell library using IC Studio. Characterization Response of layout-netlist (with parasitic), DRC, Layout optimization, LVS and parasitic extraction.
Design of a 2-stage Operational Amplifier for TSMC CMOS 0.35 um technology.
DRC and LVS correction for random Layout (900+ errors): Detailed knowledge of DRC rules (enclosure, extension, overlap, spacing) LVS debugging strategy.
Designed a Layout for Full Adder, D-Flip Flop, Universal & all Basic Gates and checked for all DRC’s LVS and PEX.
Novel Sub-Miniaturized Wilkinson power divider based on small phase delay and measuring return-loss, directivity, insertion loss of proposed design in Microwave office AWR.
Floorplan and P&R for I2C Protocol using ICC: Automatic Place and Route concepts for Functional blocks and full chip IC’s. issues for macro-placement and IR drop specs, Timing closure for PD & DFM
Relevant Courses:
Analog IC Design, VLSI Design, RF and Microwave Circuits, RF Amplifiers, RF IC Design, Computational Electromagnetics
Work Authorization: F-1 VISA