MTVV 2009---

Automated tests generationfrom SysML models

July 1st 2009

---

Jonathan Lasalle

219 avril 2023

Outline

Test Designer

VETESS project

SysML/SysML4MBT

Test Generation Strategies

Conclusion and future works

319 avril 2023

Test Designer

PIVOT FILEUML Java

TEST MODELUML4ST

RSM

Test Designer™ TestsTests

419 avril 2023

Example : front lightings

Vehicle front lightings Management(HighLights + HeadLights)

Actions :• Turn on/off HighLights• Turn on/off HeadLights

4 possible states :• All Lights OFF• HighLights Only• HeadLights Only• All Lights ON

519 avril 2023

UML4ST (UML for Smartesting)

1 class diagram (static view)

1 object diagram (representation of the initial state of the system)

619 avril 2023

UML4ST (UML for Smartesting)

1 statemachine diagram (dynamic view)

Trigger : Operation CallGuard : Boolean expression (OCL) Action : OCL expression

719 avril 2023

Outline

Test Designer

VETESS project

SysML/SysML4MBT

Test Generation Strategies

Conclusion and future works

819 avril 2023

VETESS project

VETESS = Vérification de systèmes embarqués VEhicule par génération automatique de TESts à partir des Spécifications

Project labelized by the Competitiveness Cluster «Véhicule du Futur» (2008/2010)

Project members :• Smartesting : editor of MBT’s software (Test Designer)• Clemessy : concepteur de bancs de validation• PSA : car manufacturer• LIFC : Model Based Testing experience (MBT)• MIPS : Model Driven Engineering experience (MDE)

9April 19, 2023

VETESS project

Specification of systems under test (SUT) with SysML behavioral models

Automated tests generation from SysML models with Test Designer (Smartesting)

Export and execution of tests on TestInView platform (Clemessy)

Automation of this process with a tools framework which contains those parts.

1019 avril 2023

Tools framework

ibd [block] PowerSubsystem [Alternative 1 - Combined Motor Generator ]

emg:Electr icMotorGenerator

trsm:Transmission

ice:InternalCombustionEngine

acl:accelerator

ecu:PowerControlUnit

ft:FuelTankAssy

dif:Differential

r fw:ChassisSubsytem.FrontWheel

lfw:ChassisSubsytem.FrontWheel

Por t:FuelTankF itting

Port:ICEFuelF itting

fuelDelivery

torqueOut:Torque

torquein:Torque

spline

fuelSupply:Fuel

epc:Electr icalPowerController

bp:BatteryPack

i1:Electr icCurrent

i2:Electr icCurrent

fp:FuelPump

fi:FuelInjector

fdistbp:BrakeSubsystem.BrakePedal

<>

<>

<><>

4

fuelReturn:Fuel

<>

<>

<>

<>

g1:Torque

t2:T

orqu

e

t1:Torque

ice

ctr l

I_ICECmds

I_ICECmds

ctr l

ctr l

I_ICEData I_ICEData

trsmepc

c3

c2

c1

I_IEPCCmdI_IEPCData

I_IEPCDataI_EPCCmd

I_TRSMData

I_TRSMCmd

I_TRSMCmd

I_TRSMData

<>

<>

<>

r ightHalfShaft

<>

<><>

leftHalfShaft

TEST MODEL SysML4MBT

PAPYRUS

UML4STMetaModel

SysML4MBTMetamodel

PIVOT FILEUML Java

TEST MODEL UML4ST

PAPYRUS

TEST MODELUML4ST

RSM

Test Designer

™

TestsTests

EmbeddedEmbeddedDedicated testsDedicated tests

Adaptation layerAdaptation layer(TestInView Library)(TestInView Library)

+

+

1119 avril 2023

Scientific challenge

To consider models with parallelism

Reactive systems (Transmission of Signals)

To consider the system and his environment

Test Generation strategies dedicated to those problematics

1219 avril 2023

Outline

Test Designer

VETESS project

SysML/SysML4MBT

Test Generation Strategies

Conclusion and future works

1319 avril 2023

SysML

System Modeling Language

Modeling language for system engineering

Subset of UML with extensions

OMG : SysML 1.0 since September 2007

SysML = UML profile

Fit to modeling embedded system

1419 avril 2023

SysML diagrams

Diagrams in both :• Use-Case diagram• Sequence diagram• Activity diagram• State Machine

diagram• Package diagram

Variation of UML :• Class diagram

=> Block diagram• Composite Structure

diagram=> Internal Block diagram

Only on SysML• Parametric diagram : physics equations• Requirement diagram

1519 avril 2023

SysML4MBT : block diagram

1 block diagram=> static view

1619 avril 2023

SysML4MBT : block diagram

Flow ports :• Controller

outActionHead outActionHigh

• HeadLights inActionHead

• HighLights inActionHigh

1719 avril 2023

SysML4MBT : internal block diag.

1 internal block diagram=> interconnections between blocks

1819 avril 2023

SysML4MBT : state machine diag.

1 or more statemachine diagram(s)=> dynamic view of system parts

SEND 1

RECEIVE 1

SEND 1

SEND 2

SEND 2

SEND 3

SEND 3 SEND 4

SEND 4 RECEIVE 4

RECEIVE 3

RECEIVE 2

1919 avril 2023

Scientific challenge

To consider models with parallelism

Reactive systems (Transmission of Signals)

To consider the system and his environment

Test Generation strategies dedicated to those problematics

OK => Several state machine diagrams

OK => ports + signal

OK => Several state machine diagrams

2019 avril 2023

Outline

Test Designer

VETESS project

SysML/SysML4MBT

Test Generation Strategies

Conclusion and future works

2119 avril 2023

Test Generation Strategy : TD

Test Designer• All behaviors• For each behavior

=> 1 test case which passes through the behavior

• Action of a transition:IF (BOOL) THEN

Action AElse

Action B

TEST 1(with BOOL = true)

TEST 2(with BOOL = false)

2219 avril 2023

Test Generation Strategy : DUvar

Uses state variablesFor each variable Var• For each behavior B1 which defines Var (Var = 5)

For each behavior B2 which uses Var(Var2 = Var)

– B1/B2 is a pair

Criteria :• All_Uses : Coverage of each pair B1/B2 (1 path)• All_Def_Use_Paths : Coverage of all paths for each

pair B1/B2

2319 avril 2023

Test Generation Strategy : ComCover

Uses connectorsFor each connector Connect• For each Behavior B1 which sends signal on

Connect For each Behavior B2 which receives signal sent

by B1– B1/B2 is a pair

Criteria• All_Receives : Coverage of each pair B1/B2 (1 path)• All_Send_Receive_Paths : Coverage of all paths for

each pair B1/B2

2419 avril 2023

Test Generation Strategy : Scenario

Scenarios defined by the user

3 ideas:• With valuated paths

Ex : CallOp1(5), CallOp2(4), CallOp1(8)

• With not-valuated paths : Ex : CallOp1(?), CallOp2(?), CallOp1(5)

• With not-valuated not-complete paths : Ex : CallOp1(?), ?, CallOp2(6)

Experimentations

FrontLightings FrontWiper (manual)

Nb statemachine 3 6

Nb states (4,2,2) (1,1,1,1,14,2)

Nb transitions (8,2,2) (2,2,2,1,20,3)

Nb tests algo TD 12 30

Coverage Algo TD All_transitions

Nb tests DUvar 0 15

Coverage All_Uses None None

Nb tests ComCover 8 13

Coverage All_Receives DU-PATHS None

Coverage DUvar+ComCover

DU-PATHS DU-PATHS

2519 avril 2023

2619 avril 2023

Outline

Test Designer

VETESS project

SysML/SysML4MBT

Test Generation Strategies

Conclusion and future works

27April 19, 2023

Conclusion & Outlook

ibd [block] PowerSubsystem [Alternative 1 - Combined Motor Generator ]

emg:Electr icMotorGenerator

trsm:Transmission

ice:InternalCombustionEngine

acl:accelerator

ecu:PowerControlUnit

ft:FuelTankAssy

dif:Differential

r fw:ChassisSubsytem.FrontWheel

lfw:ChassisSubsytem.FrontWheel

Por t:FuelTankF itting

Port:ICEFuelF itting

fuelDelivery

torqueOut:Torque

torquein:Torque

spline

fuelSupply:Fuel

epc:Electr icalPowerController

bp:BatteryPack

i1:Electr icCurrent

i2:Electr icCurrent

fp:FuelPump

fi:FuelInjector

fdistbp:BrakeSubsystem.BrakePedal

<>

<>

<><>

4

fuelReturn:Fuel

<>

<>

<>

<>

g1:Torque

t2:T

orqu

e

t1:Torque

ice

ctr l

I_ICECmds

I_ICECmds

ctr l

ctr l

I_ICEData I_ICEData

trsmepc

c3

c2

c1

I_IEPCCmdI_IEPCData

I_IEPCDataI_EPCCmd

I_TRSMData

I_TRSMCmd

I_TRSMCmd

I_TRSMData

<>

<>

<>

r ightHalfShaft

<>

<><>

leftHalfShaft

TEST MODEL SysML4MBT

PAPYRUS

UML4STMetaModel

SysML4MBTMetamodel

PIVOT FILEUML Java

TEST MODEL UML4ST

PAPYRUS

TEST MODELUML4ST

RSM

Test Designer

™

TestsTests

EmbeddedEmbeddedDedicated testsDedicated tests

Adaptation layerAdaptation layer(TestInView Library)(TestInView Library)

+

+DUvar

ComCover

Scenario

The End

Questions?

28April 19, 2023