m.tech credit seminar presentation tthh nnoovember 2002 ...esgroup/es_mtech02_sem/... · arup...

1818thth November 2002November 2002

Hardware Configurations Hardware Configurations for DSPfor DSP--based Real Time based Real Time

SimulatorsSimulatorsSupervisor: Prof Mukul ChandorkarSupervisor: Prof Mukul Chandorkar

Arup ChakrabortyArup Chakraborty(02307015)(02307015)

Electronic Systems Group,Electronic Systems Group,EE Department,EE Department,

IIT BombayIIT Bombay

M.Tech Credit Seminar Presentation

Arup ChakrabortyArup Chakraborty 22

What is Real Time Simulation?What is Real Time Simulation?

♣♣ SimulationSimulationReproduction of reality and its complexity through Reproduction of reality and its complexity through execution of a model of the reality.execution of a model of the reality.

♣♣ Real time SystemsReal time SystemsSystems responding to external events within or Systems responding to external events within or after a specified time interval. after a specified time interval.

♣♣ Real time SimulationReal time SimulationTiming constraints imposed by the reality itself. Timing constraints imposed by the reality itself. Simulation time Simulation time •• Simulated time.Simulated time.


HardwareHardware--inin--Loop SimulationLoop Simulation

HILS is one example of real time simulation.HILS is one example of real time simulation.

♣♣ A tool for testing embedded controller. A tool for testing embedded controller. ♣♣ Behaves as the world external to it.Behaves as the world external to it.

♣♣ NonNon--viable alternative testing procedures.viable alternative testing procedures.♣♣ Control & maintenance of testing environment difficult.Control & maintenance of testing environment difficult.♣♣ Safety considerations. Safety considerations. ♣♣ Reduction in the product development cycle.Reduction in the product development cycle.


Why DSP and Multiprocessing ?Why DSP and Multiprocessing ?

DSPsDSPs in real time simulations in real time simulations ♣♣A lot of computational power, less expensive.A lot of computational power, less expensive.♣♣Real time I/O operations, fast data movement.Real time I/O operations, fast data movement.

Complex simulations require multiple processors Complex simulations require multiple processors ♣♣Increased computational capability.Increased computational capability.♣♣Scalability, flexibility.Scalability, flexibility.♣♣Different dedicated processors to respond to Different dedicated processors to respond to

different different events.events.


Multiprocessing Systems Multiprocessing Systems –– Traditional Traditional ApproachesApproaches

Tightly Coupled Systems:Tightly Coupled Systems:Several processors having access to shared system Several processors having access to shared system resourcesresources–– shared bus / memory / I/O devices.shared bus / memory / I/O devices.

♣♣ High speed data transfer, almost no software overhead.High speed data transfer, almost no software overhead.♣♣ Tight control of system resources.Tight control of system resources.♣♣ Bus / memory access arbitration necessary.Bus / memory access arbitration necessary.♣♣ Not very scalable.Not very scalable.


Traditional Approaches (contd.)Traditional Approaches (contd.)

LooselyLoosely Coupled Systems:Coupled Systems:♣♣ Each processor node is an independent system.Each processor node is an independent system.♣♣ No memory or I/O space sharing.No memory or I/O space sharing.♣♣ Communicate with other processors through I/O devices. Communicate with other processors through I/O devices. ♣♣ CPU cycles lost due to communication overhead.CPU cycles lost due to communication overhead.♣♣ Expensive. Expensive. ♣♣ Allows large physical separation of the processors.Allows large physical separation of the processors.


Practical Real Time Systems in usePractical Real Time Systems in use

Try to keep the best of both ends.Try to keep the best of both ends.

Hardware Coordinated Multiprocessor SystemsHardware Coordinated Multiprocessor Systems♣♣ Hardware control circuit (MPR) on each board.Hardware control circuit (MPR) on each board.♣♣ MPRsMPRs connected through MPC.connected through MPC.♣♣ OnOn--board monitor circuits watch state registers. board monitor circuits watch state registers. ♣♣ Offloads control activities from general purpose data busOffloads control activities from general purpose data bus♣♣ Low overhead, latency, scalable.Low overhead, latency, scalable.♣♣ Extra hardware requiredExtra hardware required..


Concurrent Computer Corporation’s ApproachConcurrent Computer Corporation’s Approach

Multiple single board systems connected through Multiple single board systems connected through i.i.shared bus, the shared bus, the VMEbusVMEbusii.ii.separately interconnected onseparately interconnected on--board cards, the board cards, the RCIMsRCIMs

Multiple ways of communication:Multiple ways of communication:♣♣Shared memory.Shared memory.♣♣VMEbusVMEbus as networking medium.as networking medium.♣♣Mailbox interrupts, VME interrupts.Mailbox interrupts, VME interrupts.♣♣Through Through RCIMsRCIMs. .

Tight control of system resources.Tight control of system resources.


Replicated Shared Memory NetworkReplicated Shared Memory Network

♣♣ A replicated memory and a network card at each node.A replicated memory and a network card at each node.♣♣ Connected in serial ring network.Connected in serial ring network.♣♣ Local memory updates and interrupts transmitted Local memory updates and interrupts transmitted

through the network.through the network.♣♣ Minimum software overhead; short, fixed length Minimum software overhead; short, fixed length

transmissions.transmissions.♣♣ Large number of processors, large physical distance.Large number of processors, large physical distance.

Examples: SCRAMnet, SCRAMnet+ Examples: SCRAMnet, SCRAMnet+


Switched Network Interconnect Switched Network Interconnect –– RACEwayRACEway

♣♣ Uses 6Uses 6--port crossbar switches.port crossbar switches.♣♣ 6 processors can be interconnected using one switch.6 processors can be interconnected using one switch.♣♣ Switch supports 3 simultaneous communication paths, Switch supports 3 simultaneous communication paths,

each at the rate of 160 MB/s.each at the rate of 160 MB/s.


IPC using Multiple Dual Ported IPC using Multiple Dual Ported RAMsRAMs

♣♣ Each processor shares a DPR with each of its immediate Each processor shares a DPR with each of its immediate neighbour. neighbour.

♣♣ Each processor shares a DPR with the “network Each processor shares a DPR with the “network controller”controller”


Application Specific Topology Application Specific Topology

♣♣ Custom interconnection mechanism for a particular Custom interconnection mechanism for a particular application.application.

♣♣ Direct link provided.Direct link provided.♣♣ Needs no kind of bus arbitration logic.Needs no kind of bus arbitration logic.♣♣ Works well for small system.Works well for small system.♣♣ Not scalable.Not scalable.


Ordered Memory Access (OMA) ArchitectureOrdered Memory Access (OMA) Architecture

♣♣ Essentially a shared memory architecture with a “central Essentially a shared memory architecture with a “central transaction controller”.transaction controller”.

♣♣ Bus access grants according to “bus access order” list.Bus access grants according to “bus access order” list.♣♣ Eliminates bus conflicts entirely.Eliminates bus conflicts entirely.


ConclusionConclusion

♣♣ What we looked at ?What we looked at ?–– a survey of what are available.a survey of what are available.

♣♣ Which is the best one ?Which is the best one ?–– depends on the application.depends on the application.


THANK YOUTHANK YOU


Real Time Clock and Interrupt Modules (Real Time Clock and Interrupt Modules (RCIMsRCIMs))

RCIMsRCIMs: on board cards interconnected through PCI bus.: on board cards interconnected through PCI bus.♣♣ Programmable real time clocks.Programmable real time clocks.♣♣ Synchronized clocks.Synchronized clocks.♣♣ input and output interrupts.input and output interrupts.♣♣ Support distributed interrupts. Support distributed interrupts.

m.tech credit seminar presentation tthh nnoovember 2002 ...esgroup/es_mtech02_sem/... · arup...

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