MSP432™ Низкое потребление

высокая производительность Low-power at its best, performance at its core

1

Вячеслав Прокопий

инженер по применению, Компэл

Октябрь 2015

v.prokopiy@compel.ru

ti@compel.ru

2

Содержание

Часть 1

Обзор MSP432

Ядро и Периферия

– Система питания

– Ядро Cortex-M4F и прерывания

– Тактирование

– Память

– Цифровые модули

– Аналоговые модули

Миграция ПО

Часть 2

• Экосистема и демонстрации

– MSPWare

– TI Cloud Development Tools

– EnergyTrace+

• Тренинг на MSP432 LaunchPad

– Программирование из облака

– Демо из коробки

Часть 3 и 4

• Тренинг с TI-RTOS

Обзор MSP432

3

БОЛЬШЕ ПРОИЗВОДИТЕЛЬНОСТИ

ДЛЯ РАЗРАБОТЧИКОВ НА MSP430™

МЕНЬШЕ ПОТРЕБЛЕНИЯ

ДЛЯ РАЗРАБОТЧИКОВ НА ARM®

БЕЗ КОМПРОМИССОВ

Переход на новый уровень

вычислений и аналоговой

производительности с максимизацией

ультра-низкого потребления MSP430

Уменьшение энергозатрат и увеличение

производительности с самым

низкопотребляющим контроллером на базе

Cortex®-M4F

INTRODUCING MSP432™ MCUs:

LOW-POWER AT ITS BEST; PERFORMANCE AT ITS CORE

4

Получите низкое потребление и высокую

производительность с линейкой

масштабируемых16-битных и 32-битных

контроллеров MSP

MSP432™ MCUs: PERFORMANCE AT ITS CORE

Selecting the high-

performance ARM®

Cortex®-M4F core

Highest Coremark

score: 3.41/MHz

Incorporating

high-performance

peripherals and

features

• Simultaneously read

and erase from flash

• Execute up to 200%

faster with DriverLib in

ROM vs. Flash

• 14-bit 1MSPS ADC with

13.2ENOB, differential

mode & 2 window

comparators

48MHz ARM®

Cortex®-M4F

• Full ARM instruction set

• DSP extensions

• FPU engine

Industry-leading

ultra-low-power

• Active power:

95 μA per MHz

• Sleep mode:

850 nA (with RTC)

• ULPBench score: 167.4

DriverLib in-ROM

14-bit ADC

8-channel DMA

NVIC with tail-chaining

Peripheral & SRAM memory bit-band

Independent flash banks

Selectable RAM retention

Integrated LDO & DC/DC

128-bit Flash buffer & pre-fetch

5

MSP432 MCU Wide voltage range: 1.62-3.7V

MSP432 | 32-bit Cortex-M4F

• 32-bit pipeline architecture

• Harvard architecture

• Cortex-M4 with DSP extension

instruction set

• Floating Point Unit

• Standard Cortex-M Debugger

Module, Serial Wire Debug, ITM

Trace support

• Core modules including DMA,

SysTick, & Interrupt (NVIC)

6

MSP432™ MCUs: LOW-POWER AT ITS BEST

Optimizing the

architecture for

ultra-low power

Industry’s lowest

power ARM

Cortex-M4F MCU

48MHz ARM®

Cortex®-M4F

• Full ARM instruction set

• DSP extensions

• FPU engine Driver Lib in-ROM

128-bit Flash buffer & pre-fetch

14-bit ADC

8 channel DMA

NVIC with tail-chaining

Peripheral & SRAM memory

bit-band

Independent flash banks

Selectable RAM retention

Integrated LDO & DC/DC

MSP432 MCU

7

Optimizing peripherals for

ultra-low power

• Save 40% more power

with the integrated DC/DC

vs. LDO

• Save 30nA per RAM bank

with selectable RAM

retention

• Consume minimal power

(375uA) when sampling

sensors at 1MSPS with 14-

bit ADC

• DriverLib in ROM

consumes up to 35% less

power than Flash

Wide voltage range: 1.62-3.7V

Industry-leading

ultra-low-power

• Active power:

95 μA per MHz

• Sleep mode:

850 nA (with RTC)

• ULPBench score: 167.4

MSP432™ MICROCONTROLLERS

8

Software

Differentiation

• MSPWare – leverage

C-code portable MSP430 peripherals and

analog

• RTOS - TI-RTOS, FreeRTOS, Micrium, RTX

• ARM 3rd Party Ecosystem

• IDEs - CCC™, IAR, KEIL and gcc

Packages

LaunchPad

• MSP-EXP432P401R

• $12.99

Target Board

• MSP-TS432PZ100

• $89.00 5x5mm²

9x9mm²

16x16mm²

• Industry’s lowest power ARM® Cortex®-M4F MCU ─ Best ULPBench score

of 167.4. As low as 850nA Standby, 95µA/MHz Active; Deep sleep to Active:

<10us typ

• Wide supply range ─ 1.62-3.7V, including flash operation, enabling multiple

battery technologies and eliminating external regulation

• Integrated high-performance and low-power analog ─ Including 1MSPS 14-

bit ADC, 375uA at 1MSPS

• Secure MCU environment – Flash IP protection & integrated AES-256

encryption

• Simplified portability from MSP430 - Leverage software & know-how from

existing MSP430 designs

Using 430 Peripherals, Analog & Low Power Modes

Tools

Status

• LaunchPad and Target Board available

• Sampling 256KB (XMS432P401RIPZR)

• Pin-for-pin roadmap to 2MB

Temperature 85°C

Up to 256 KB Flash

Up to 64 KB SRAM

Bootstrap Loader

4× I2C or SPI

Real-time JTAG

4× UART or SPI

4× 16-bit Timer/PWM/CCP

2× 32-bit GP Timers

Watchdog Timer

24ch, 14-bit 1 MSPS SAR ADC

Voltage Reference

2× Analog Comparators

Capacitive Touch I/O

Real-Time Clock DMA (8 ch)

AES-256

CRC32

Temperature Sensor

Analog Comms Peripherals Security

Systick Timer

Driver Libraries

Debug

System Modules

Memory Programmable DCO

Low-Power OSC

NVIC SWD

ARM®

Cortex™-M4F 48 MHz

WIC ITM FPU MPU

Power & Clocking

32KB ROM

1.62V – 3.7V Operation

Same as MSP430

MSP432P4x

TI Confidential – Maximum Restrictions

TI’S INDUSTRY-LEADING LOW-POWER MCU PORTFOLIO: SCALABILITY FROM 16-BIT TO 32-BIT, PLUS WIRELESS MCUs

9

16-bit MSP430 MCUs

• The industry leader in ultra-low-

power, rich peripherals and analog

integration.

• World’s only portfolio of ultra-low-

power embedded FRAM MCUs.

• Growing portfolio of more than 500

ultra-low-power MCUs across

13,000+ customers.

32-bit MSP432 MCUs

• Industry’s lowest power ARM®

Cortex®-M4F MCUs. Period.

• High performance MCUs without

sacrificing power consumption.

• Pin-for-pin platform scalability up to

2MB; sampling 256KB today.

SimpleLink Wireless MCUs

• Focus on ease of use and low power.

• Support for more than 14 wireless

protocols including Bluetooth Smart,

Sub-1 GHz, 6LoWPAN, ZigBee and

more.

• Portfolio includes SimpleLink Wi-Fi

and new ultra-low power platform.

MSP430™

MCUs

MSP432™

MCUs

SimpleLink™

Wireless MCUs

Система питания MSP432

10

Power | Feature Overview

• Wide supply range with true 1.8V+/-10% operation: 1.62V-3.7V

• Two internal core voltages for system frequency power-scaling

– 1.2V: 1-24MHz operation

– 1.4V: 1-48MHz operation

• Two internal voltage regulators to adapt for power requirements/profiles

– LDO: default regulator

– DC-DC: additional regulator for better efficiency @ higher frequency

– DC-DC: requires longer start-up time and transitions from Sleep Modes

• Supply Voltage Monitor & Supervisor

– Low performance modes for extremely low power in LPM3/4/x.5

• DriverLib-assisted power state transitions & configurations 11

128kHz

1MHz

high MHz

48MHz

32-50kHz

Power | Regulators: LDO & DC-DC

12

LDO DC-DC

Default regulator at startup Secondary, requires external inductor

VCC = [1.62V-3.7V] VCC = [2.0V-3.7V]

Available in all power modes Available in LPM0 & Active Modes

Flexible with scalable output loads for low power

modes

Efficient, optimized for high-speed/high-load

operations

Fast on/off switching operations Slow on/off/failsafe switching from/to LDO

MSP432 ACTIVE Low-Frequency

(Active/LPM0) LPM0

LPM3

LPM4 LPM3.5 LPM4.5

Current 100uA/MHz (DCDC)

166uA/MHz (LDO) 70uA

65uA/MHz (DCDC)

100uA/MHz (LDO) <900nA <670nA <100nA

CPU Retention

FLASH

SRAM Retention Retention

LDO In LDO mode Low Drive Mode In LDO mode Low Drive Mode Low Drive Mode

DC-DC In DCDC mode In DCDC mode

PSS Bandgap Sampled Mode Sampled Mode

Clocks Only BCLK Only BCLK

Core Domain Logic Retention

Backup Domain

Logic (RTC/WDT) Active Active

I/O State Retention Retention Retention

LPM3 & LPM4

Ultra low leakage

modes with full state

retention (as low as

900nA typ with RTC

active)

LPM0

CPU off, all peripherals & clocks

active

Low-Frequency modes

Special low power low frequency option

available for both active and LPM0 modes

Total device current consumption below

80uA

CPU execution at 128KHz max, Flash,

SRAM and peripherals remain active at the

lower speeds

Active modes at Core Voltage 0

Low power, medium performance mode : 0 – 24MHz

Can be used with regulation either through LDO (for

maximum efficiency) or DCDC

Active modes at Core Voltage 1

High performance, high efficiency mode : 0 – 48MHz

Can be used with regulation either through LDO or DCDC

(for maximum efficiency)

LPMx.5 modes

Ultra low leakage modes, with no state retention

(as low as 670nA typ with RTC active)

LPM3.5: allows wake up from RTC & WDT

events

LPM4.5: allow reset wake up through reset

Power | MSP432 Flexible Operating Modes

Cortex-M Interrupt Nested Vector Interrupt Controller (NVIC)

14

Interrupts | Nested Vectored Interrupt Controller (NVIC)

• Handles exceptions and interrupts

• 8 programmable priority levels, priority grouping

• 7 exceptions and 71 Interrupts

• Automatic state saving and restoring: R0–R3, R12, LR, PSR, and PC

• Automatic reading of the vector table entry

• Pre-emptive/Nested Interrupts

• Tail-chaining

– Deterministic: always 12 cycles or 6 with tail-chaining

t

ADC interrupt

Timer_A interrupt

Main application (foreground)

Система тактирования

CS | High-level Features

• Flexible clock sources & distribution: – 5 clocks from 7 sources (2 external, 5 internal)

– Selections suitable for high-speed & low-power operations

• Wide range of operating frequency – 10kHz to 48 MHz

– Fine intermediate steps with dividers & tuning

• Configurable & robust system: – Run-time lockable configuration

– Failsafe mechanism with interrupts for external sources

CS | HF & LF Oscillators Frequency Oscillators MCLK SMCLK HSMCLK ACLK BCLK Comments

HF

1-48 MHz DCO ✔ ✔ ✔

Internal integrated digitally

controlled oscillator.

1-48 MHz HFXT

✔ ✔ ✔

High frequency crystal.

Frequency range is SW

configurable.

24MHz MODOSC ✔ ✔ ✔

Internal osc. option for

peripherals such as ADC

5MHz SYSOSC

Internal, direct clock for ADC

failsafe for HFXT

LF

32kHz LFXT ✔ ✔ ✔ ✔ ✔ Low-frequency oscillator

32kHz

128kHz

REFO

✔ ✔ ✔ ✔ ✔

Internal low-frequency oscillator.

Failsafe* (32kHz) for LFXT

10kHz VLO ✔ ✔ ✔ ✔

Internal ULP LF oscillator

Clock selection for WDT

CS | High-accuracy tune-able DCO

• 6 tune-able frequency ranges

– Each range has calibrated center frequency

– Example: [8-16MHz] range has a calibrated 12MHz center frequency

• Tune-able within each frequency range

– Center Frequency +/- 212 steps DCOTUNE register

• DCO accuracy:

– Internal resistor: + 2.65 % [Calibrated]

– External resistor : + 0.4 % [91kΩ + 0.1% ]

• Failsafe for internal resistor mode

19

3MHz 48MHz 24MHz 12MHz 6MHz 1.5

Calibrated Center Frequency

Frequency Range

8MHz 16MHz 4MHz

CS | Clock availability in power modes

Power Modes MCLK SMCLK HSMCLK ACLK BCLK Comments

Active ✔ ✔ ✔ ✔ ✔

Low-Frequency

Modes ✔ <128kHz

✔ <128kHz

✔ <128kHz

✔ ✔

ACLK, BCLK always

<128kHz

LPM0 ✘ ✔ ✔ ✔ ✔

LPM3 ✘ ✘ ✘ ✘ ✔

LPM3.5 ✘ ✘ ✘ ✘ ✔

LPM4.5 ✘ ✘ ✘ ✘ ✘

Память

21

Memory | Overview

22

Memory Size Speed Features

Flash 256kB

Sector: 4kB

16MHz Speed boost with 128-bit buffer & pre-

fetch

Powerful security

features

SRAM 64kB

Bank: 8kB

48MHz Dynamic bank power-down & retention options for

low power

ROM 32kB 48MHz Robust DriverLib APIs integrated to save

application space

Lower power

execution

BSL 8kB 16MHz UART/I2C/SPI Boot-Strap Loader provided

• Independent banks simultaneous read/execute and program/erase operations

• 128-bit buffer Power savings & higher effective speed with ARM’s pre-fetch

• Hardware assisted operations

– Burst data comparison for fixed patterns (data fill check)

– Flash program modes with auto-computed parity & auto-verify:

– Write immediate, 128-bit full word write, or 4*128-bit burst mode

• All flash operations encompassed into robust ROM DriverLib APIs 23

} 128kB

Bank 1

Bank 2

4kB 4kB

4kB

25

6k

B

Individually [un-]protected

from write/erase

Memory | Flash Features

> 105 erase cycles

Memory | RAM

• Up to 64KB of banked SRAM architecture

• 8 dynamically configurable banks:

– Enable/disable banks to optimize active mode power consumption

– Retain/not retain content in DSL to optimize LPM3 leakage power

consumption

SRAM banks Memory size

Bank 0 enable/retention (always enabled) 8KB

Bank 1 enable/retention 16KB

Bank 2 enable/retention 24KB

. . . …

Bank 6 enable/retention 56KB

Bank 7 enable/retention 64KB

Memory | Memory Map

0x00000000 Flash

0x01000000 ROM

0x20000000 SRAM

0x22000000 Bit-banded SRAM

0x40000000 Peripherals (Registers)

0x42000000 Bit-banded Peripherals

0xE0000000 Instrumentation, ETM, etc.

256kB

- Interrupt Vector Table

- Application Code

Peripheral Driver Library

Ultra-low-leakage SRAM

- 64kB = 8 x 8kB banks

- Bit-banded

Bit-Band

Bit-Band

Peripheral Space

- Register directly

accessible

- Bit-banded

Digital Peripherals

26

Timers: TimerA, Timer32, RTC, WDT

eUSCI: UART, SPI, I2C

GPIO

DMA

Timers | Overview

Timer Instances # of Bits Lowest Operating mode Interval PWM Main/Other

Function

Timer_A 4 16 LPM0, LPM0_LF ✔✔ ✔ Capture,

Compare

Timer32 2 32 LPM0, LPM0_LF ✔✔

SysTick 1 24 LPM0, LPM0_LF ✔✔

RTC 1 32* LPM3, LPM3.5 ✔ RTC

WDT 1 LPM3, LPM3.5 ✔ WDT

27

RTC & WDT: only have a few selection of pre-set intervals ✔

✔✔ Timer_A, Timer32, SysTick: configurable intervals with 16/32/24-bit granularity

+

eUSCI | Serial Communication

• I2C

– 400kHz & up to 1MHz

– 4 hardware slave addresses supported with

dedicated TX/RX interrupts

– Byte counter for autonomous operation

• UART

– Enhanced baud rate generation

– Auto baud rate detection

• SPI

– 3 & 4-wire modes

– Up to 14MBps

eUSCI A0

eUSCI A1

eUSCI B0

SPI, UART

SPI, I2C

Digital I/O | Overview

• Ultra low-leakage IOs (± 20 nA Max)

• Capacitive touch function available on all IOs

• Pull-up/Pull-down

• Interrupt/Wake-up capability available on 6 ports (48 pins)

• Port Map: 30 digital functions available to each of 24 port-mappable IOs

• Up to 4 pins with 20mA max output, suitable for optional high-drive functionality

(P2.0-P2.3)

• 8 IOs with glitch filtering capability

29

• Single 32-bit AHB-Lite master interface for transferring data

• Supports multiple DMA transfer data widths and address increment values

• 1-1024 transfers in a single DMA access

• Each DMA channel has 2 channel control data structures (primary/alternate)

stored in RAM

• Channel control data is stored in RAM

• Multiple DMA transfer types:

– Basic, Auto-Request, Ping-Pong, Memory Scatter-Gather, Peripheral Scatter-Gather

• Each DMA channel has a programmable priority level.

• Error indication in case any transfer comes back with a bus error response.

30

DMA | PL230 MicroDMA

Analog Modules

ADC14, COMP_E, REF

31

ADC14 | Overview • 14-bit Accuracy

– INL <= +/- 2 LSB;

– DNL <= +/- 1 LSB

– ENOB 13-bit

• 32-input channels

• Single-ended & differential Inputs

• 2 Window comparators – High interrupt

– Low interrupt

– In [Between] interrupt

• Separate internal channels for AVcc and TempSensor

• Ultra Low current consumption – Single ended 210uA @ 1.8V, 1Msps

– Differential 260uA @ 1.8V, 1Msps

+ Internal

Channel

Mapping 0

1

0

1

0

1

32

-inp

ut c

ha

nn

els

14-bit ADC

Core

Enhanced

ADC

Memory

14-bit

Window

Comparator

Enhanced

Clock

Reference external internal

external internal

external internal

Differential

Measurement

Interrupt

...

= New Feature = Enhanced

Feature

33

Comp_E | Overview

• Interrupt driven for low power

• Uses the REF module like ADC14

• Up to 15 external input channels

• Ultra-low-power comparator mode

• Software selectable RC filter

• Selectable reference voltage generator

• Voltage Hysteresis generator

• Output internally connected to Timer A capture input (for event capture

& capacitive touch implementations)

MSP432 Security

34

Security | AES256 Benefits

• HW acceleration AES ( FIPS PUB 197)

• Accelerates AES en- and decryption by one to two orders of magnitude

• Lower power & off-loads CPU

Performance

• 128-bit of data are en- or decrypted with a 128-bit key within 167 MCLK cycles, 256-bit encryption in 234 cycles

Features

• 128-, 192-, and 256-bit key lengths

• On-the-fly key expansion

• Off-line key generation for decryption

• Shadow registers for initial key

• 128 bit truly random seed to generate the random key

• Block mode with DMA: OFB, ECB, etc.

35

Applications include Securing of communication channels like RF links, UART communications, etc.

Security | Device Security Overview

• JTAG Protection

– Device is fully secure from debug accesses.

• IP Protection (Regional security)

– Up to 4 regional secure zones of memories can be configured in flash

– These zones are non-intrusive to debug (JTAG/debugger) and code outside

this region.

– Regular debug allowed outside these regional secure zones.

• Combination of regional and full-chip security

– This is a combination of the above two where:

• Debug accesses are blocked for the entire device

• Code/Data access restrictions and protections apply for the secure regions.

36

Security | JTAG security

• Similar to MSP430 JTAG security control

• Code is developed and loaded into Flash by customer

• Device is then completely locked from external accesses (full chip secure)

• All memory areas within the device can be accessed by the customer’s code.

Customer’s

Code

to be

Secured

Code Memory (Flash)

Debugger

Free memory

Security | IP Protection

• Up to 4 regions of code can be

setup to be secured against:

– Debugger accesses

– Code accesses from other regions

• Remaining regions of memory are

still open for debug/code accesses

Customer Secure Code 3

Customer Secure Code 2

Customer Secure Code 4 Debugger

Free memory

Free memory

Free memory

Free memory

Debugger

Debugger

Customer Secure Code 1 Debugger

Debugger

Debugger

Debugger

Debugger

• Enables multi vendor development scenario with specific vendors’ protected

software IP can be protected in secure regions

• Code in secure zones can only be called into as APIs • Direct read accesses result in an exception

• Secure encrypted updates. Encrypted with AES and 128bit password

MSP430 <-> MSP432 Porting

39

MSP Platform Portability M

SP

430

MS

P432

MSP430 Modules

MSP 16-bit core

430

MSPWare

Register-

Level

Driver

Library

430

MSP Debugger

LaunchPad

BoosterPacks

Target Board

BSL

ULP Tools: ULP Advisor & EnergyTrace

IAR IDE Energia

CCS IDE

GCC

CMSIS

ARM Modules

New MSP432 Modules

ARM M4F 32-bit core

432

ARM

432

ARM Keil

ULP Tools: ULP Advisor & EnergyTrace+

Intrinsics & Interrupts New for MSP432 Same as MSP430

Slight modifications

from MSP430

430 430

MSPWare Register-

Level

Driver

Library

Libraries

Libraries

Intrinsics & Interrupts

RTOSs

Hardware Software Development Tools Development Kits

Porting | Code Compatibility Module C-code DriverLib Recommendation

CO

RE

SY

ST

EM

Core/CPU New New msp430dna.h, intrinsic support available

Power New New Develop new code using DriverLib APIs

CS New New Develop new code using DriverLib APIs

Flash & RAM New New Develop new code using DriverLib APIs

NVIC New New Develop new code using DriverLib,

CMSIS, or MSP432 intrinsics

ISR Small changes Small changes Special consideration for flag clearing & power modes when entering/exiting

ISRs

Intrinsics Some MSP430 intrinsics supported on MSP432 msp430dna.h converts applicable ones, helps guide through changing non-

compatible ones to msp432/CMSIS intrinsics

MS

P430

Digital: Timer_A, eUSCI, GPIO,

AES

100% Portable 100% Portable Port existing code, check & verify data types.

ADC14 Portable, new registers

added

Portable, new APIs added Port existing code, update code utilizing new features (14-bit, flag check,

etc.), check & verify data types.

COMP_E, REF 100% Portable 100% Portable Port existing code, check & verify data types.

AES, CRC 100% Portable 100% Portable Port existing code, check & verify data types.

AR

M

DMA New New Use DriverLib APIs

Timer32 New New, similar to TivaC Simple modules: use C-code, DriverLib, or CMSIS

SysTick New New, similar to TivaC Simple modules: use C-code, DriverLib, or CMSIS

Application Code Take care of data types (16-bit, 32-bit, native int, signs, etc.) Try to use

explicit C99 types (uint32_t) if possible.

• Header file definitions, register names, bits compatible to MSP430

• Existing register-access code compatible on MSP432

• MSP430 DriverLib APIs also compatible on MSP432

• See interrupt/NVIC component below for specific interrupt changes.

• Double-check if code has specific data-type (16-bit vs. 32-bit) requirements

• New core system configuration code required.

• No need to develop code from scratch: take advantage of DriverLib APIs and

example to quickly configure and bring up system

• Utilize new core features such as DC-DC, tunable DCO, dual flash banks,

SRAM bank controls, etc.

• CPU: check native data types, different code execution deterministic due to

3-stage pipeline

• Existing applicable MSP430 intrinsics usable on MSP432

• Non-compatible MSP430 intrinsics are detected & guided to convert to

MSP432 intrinsics

• CMSIS core intrinsic functions also available.

• Register access code available, but DriverLib APIs recommended for complex

module such as DMA

• DriverLib APIs Similar to Tiva C DriverLib APIs

• CMSIS register definitions compatible with other ARM devices.

Porting | Direct Register Access

MSP430

MSP432

Porting | DriverLib I2C Master Initialization MSP430

MSP432

MSP Platform Portability M

SP

430

MS

P432

MSP430 Modules

MSP 16-bit core

430

MSPWare

Register-

Level

Driver

Library

430

MSP Debugger

LaunchPad

BoosterPacks

Target Board

BSL

ULP Advisor & EnergyTrace

IAR IDE

Energia

CCS IDE

GCC

CMSIS compliant

ARM Modules

New MSP432 Modules

ARM M4F 32-bit core

432

ARM

432

ARM Keil

ULP Advisor & EnergyTrace+

Intrinsics & Interrupts New for MSP432

Same as MSP430

Slight modifications

from MSP430

430 430

MSPWare

Register-

Level

Driver

Library

Libraries

Libraries

Intrinsics & Interrupts

RTOSs

Hardware Software Development Tools Development Kits

www.ti.com/lit/pdf/slaa656

MORE ECOSYSTEM WITH EASY-TO-USE TOOLS AND SOFTWARE

TI Cloud IDE: • Resource Explorer

• Code Composer

Studio™

• PinMux

MSPWare™: • Driver library

• App notes &

user’s guides

• Example code

• Tutorials

Optimization

tools: • ULP Advisor

• EnergyTrace+™

Choose from

your favorite

IDEs

Develop or

access code

and collateral

online, instantly

Ease code

development

with easy to

use APIs and

examples

Optimize your

code and

system for

ultra-low-power

operation

MSP432™

LaunchPad Easy to use,

low-cost

evaluation kit

with integrated

emulator and

EnergyTrace+

technology

1 Get started here

2 Connect to your computer

3

4

5

6

• CCS

• IAR

• Keil

CONNECTIVITY | DISPLAY | SENSORS

BoosterPacks

Expand MSP432 LaunchPad evaluation

with easy to use, low-cost BoosterPack

add-on daughter boards

45

MORE ECOSYSTEM WITH EASY-TO-USE TOOLS AND SOFTWARE

Choose

from your

favorite

IDEs

Ease code

development

with easy to

use APIs and

examples

3

5

46

Notable Feature Free 32KB version Free 32KB version

Advanced debugging

tools

C-SPY® and

C-STAT

Free 32KB version

CMSIS-pack: RTX & DSP

Debuggers • XDS110

• XDS200

• Segger J-Link

• XDS110

• XDS200

• Segger J-Link

• IAR I-jet

• XDS110

• Keil uLink

• Segger J-Link

MSPWare™ • Driver library

• App notes &

user’s guides

• Example code

• Tutorials

• CCS

• IAR

• Keil

MSP432 Software

47

Software | TI Resource Explorer with MSPWare

48

• Embedded developer’s toolbox for “One stop learning” – Intuitively categorizes and organizes development resources to simplify your creative process.

• Includes collateral & resource packages for TI microcontrollers – MSPWare | StellarisWare | C2000 ControlSUITE | Hercules Tools

• Automatically updates over the web – Ensure that developers have the latest and greatest documentation & resources

– Get up-to-date device-support resources as MSP portfolio continues to grow

Software | MSP Register-Level

• Traditional MSP register-level access code fully supported

• Header files provide complete register & bit definitions

• Complete portability for common peripherals across 16 & 32-bit platforms

• 100+ code examples for MSP430-shared & new MSP432 peripherals

49

WDTCTL = WDTPW | WDTHOLD; // Stop WDT P5SEL1 |= BIT4; // Configure P5.4 for ADC P5SEL0 |= BIT4; __enable_interrupt(); // MSP432: Enable master interrupt SCS_NVIC_ISER0 = INT_ADC14_BIT; // MSP432: Enable ADC14 interrupt ADC14CTL0 = ADC14SHT0_2 | ADC14SHP | ADC14ON ADC14CTL1 = ADC14RES_2 ADC14MCTL0 |= ADC14INCH_1; // A1 ADC input select; ADC14IER0 |= ADC14IE0; // Enable conv. interrupt SCS_SCR &= ~SCS_SCR_SLEEPONEXIT; // MSP432: Wake up on exit from ISR

c code example

Software | Driver Library

• Driver Library offers easy-to-understand functions

• No more cryptic registers to configure

• MSP430/432 shared peripherals also share

DriverLib APIs reduce porting effort

Driver

Library Traditional

C code

Low level

programming

Software | CMSIS

• Cortex Microcontroller Software Interface Standard (CMSIS)

• Standardized hardware abstraction layer for the Cortex-M4 processor series

51

Software | CMSIS

53

typedef struct { uint8_t RESERVED0[12]; union { /* WDT_CTL Register */ __IO uint16_t reg; struct { /* WDT_CTL Bits */ __IO uint16_t IS : 3; __O uint16_t CNTCL : 1; __IO uint16_t TMSEL : 1; __IO uint16_t SSEL : 2; __IO uint16_t HOLD : 1; __IO uint16_t PW : 8; } bit; } CTL; } WDT_Type; #define WDT ((WDT_Type *) __WDT_BASE__)

#define WDTCTL \ (HWREG16(0x4000480C)) /* WDTCTL Control Bits */ #define WDTIS0 (0x0001) #define WDTIS1 (0x0002) #define WDTIS2 (0x0004) #define WDTCNTCL (0x0008) #define WDTTMSEL (0x0010) #define WDTSSEL0 (0x0020) #define WDTSSEL1 (0x0040) #define WDTHOLD (0x0080) #define WDTPW (WDTPW_VAL) #define __WDT_BASE__ (0x40004800)

MSP definition CMSIS definition

Software | CMSIS Core & Intrinsics

54

// Wait for interrupt, a.k.a. go to sleep/deep-sleep __attribute__((always_inline)) static inline void __wfi(void) { __asm(" wfi"); } // Enable Interrupts __attribute__((always_inline)) static inline void __enable_irq(void) { __asm(" cpsie i"); }

#define __sleep() __wfi() #define __enable_interrupt() __asm(" cpsie i") #define __disable_interrupt() __asm(" cpsid i")

cmsis_ccs.h

mspcompatibility.h

Translated & re-defined for

additional MSP ease of use

How ULP is your application?

Silicon

Hardware design

Software

Power consumed is made up of many factors.

Hardware is only half of the equation. We need Optimized

software

ULP Advisor Tool can get you all the way there

Software | ULP Advisor™

ULP Advisor | Now with MSP432 Rules

56

ULP# Name ULP 1.1 Ensure LPM usage

ULP 2.1 Leverage timer module for delay loops

ULP 3.1 Use ISRs instead of flag polling

ULP 4.1 Terminate unused GPIOs

ULP 5.1 Avoid processing-intensive operations: modulo, divide. (MSP430 only)

ULP 5.2 Avoid processing-intensive operations: double-precision floating point

ULP 5.3 Avoid processing-intensive operations: (s)printf()

ULP 6.1 Avoid multiplication on devices without hardware multiplier (MSP430 only)

ULP 6.2 Use MATHLIB for complex math operations (MSP430 only)

ULP 7.1 Use local instead of global variables where possible

ULP 8.1 Use 'static' & 'const' modifiers for local variables (MSP430 only)

ULP 9.1 Use pass by reference for large variables

ULP 10.1 Minimize function calls from within ISRs

ULP 11.1 Use lower bits for loop program control flow (MSP430 only)

ULP 11.2 Use lower bits for port bit-banging (MSP430 only)

ULP 12.1 Use DMA for large memcpy() calls

ULP 12.1b Use DMA for potentially large memcpy() calls

ULP 12.2 Use DMA for repetitive transfer

ULP13.1 Count down in loops / Write loops with the termination test at the bottom

ULP 14.1 Use unsigned variables for indexing

ULP 15.1 Use bit-masks instead of bit-fields

ULP 16.1 Detect for > 4 parameters passed in function call (MSP432 only)

ULP 17.1 Use bit-banding for bit manipulation (MSP432 only)

ULP 18.1 Use natural-size integer variables for computation, convert to smaller size for storage (MSP432 only)

Verbose version:

EnergyTrace+[CPU States]+[Peripheral States]

EnergyTrace™ Real-Time Power Consumption Technology for MSP430™ and MSP432™ MCUs

Features/Devices All MSP430 MCUs MSP432 MCUs FR5969 (based on Wolverine platform)

Current Monitoring x x x

CPU State (PC) x x

Peripheral/System State x

EnergyTrace™

technology

EnergyTrace+™

technology

EnergyTrace++™ technology

Current Monitoring: Real-time monitoring of total energy usage of MCU

CPU State: Real-time monitoring of energy usage according to code being handled by CPU

Peripheral/System State: Real-time monitoring of energy usage by specific peripheral

MSP432 RTOS

58

Real-time Kernel

MCU

Drivers

Connectivity Wi-Fi

Middleware File Systems

Power

Manager

Sensors

Unique to TI-RTOS:

Simplify power

management for MCU

“RTOS Core” standard offering from all RTOS

solutions

Broad offering from TI-

RTOS Drivers

Broad Middleware

offering from TI-RTOS

& CMSIS User Application

Tasks

What is TI-RTOS?

Real-time Kernel

IoT MCU

Drivers

Connectivity Wi-Fi, Bluetooth®

Smart, ZigBee®,

Cellular (via PPP),

Wired TCP/IP,

TLS/SSL

Other

Middleware USB, File

Systems

User

Application

Tasks

Power

Manager

Sensors

T

I

-

R

T

O

S

APls

TI-RTOS development tools

• TI-RTOS works with the TI Code Composer Studio (CCS), IAR, and GCC toolchains

• The RTOS Object Viewer enables developers to study the state of OS objects such

as tasks, stacks, and semaphores

– Available for CCS and IAR

• The RTOS Analyzer enables developers to look at execution history including

context switching and per-task CPU load

– Available for CCS

How TI-RTOS helps developers

• Provides pre-tested embedded software modules

– Connectivity protocols, power management, real-time kernel, …

– Eliminates need for these to be developed from scratch

– Enables developers to focus on their areas of application expertise

• No licensing hassles to use

– Completely free to use and deploy

• Reduced effort to port existing applications to new devices

– RTOS isolates application from hardware specifics

• Simpler development and maintenance of multi-function

applications

– Using multiple priorities and threads to integrate different functions

– Add new features without modifying real-time response

TI-RTOS kernel, drivers, & power manager

Real-time Kernel

IoT MCU

Drivers

Connectivity Wi-Fi, Bluetooth Smart,

ZigBee, Cellular (via

PPP), Wired TCP/IP,

TLS/SSL

Other

Middleware USB, File

Systems

User

Application

Tasks

Power

Manager

Sensors

T

I

-

R

T

O

S

APls

TI-RTOS kernel

• Designed for real-time applications

– Scheduler is deterministic so kernel system calls complete

operation in a predictable time

– Interrupt latency is low

– “Zero-latency Interrupts” enable kernel to be used in hard real-

time applications

• Low footprint to meet MCU memory constraints

– Kernel is highly configurable so unneeded functions are excluded

– Static configuration enables very low footprints by eliminating

need for heaps or create/delete calls if desired

• Tick suppression for enhanced low-power performance

Kernel services

IPC Services: Events, Mailboxes,

Semaphores, Gates

Threading Services:

Tasks, Software Interrupts,

Clocks, Idle

Debug &

Analysis: Logging,

diagnostics,

Hooks, stack

checking

Memory

Managers:

Heap, fixed-

sized buffers

Device-specific

services: Interrupt

and power

management, timers,

exception handling

An integrated approach to power management

Clock module: • Provide next

scheduled

event

Drivers & stacks: • Request peripheral clocks and

power domains be enabled

• Set power-down constraints in

critical sections

Power manager: • Manage clock gates & power domains

• Power-down and wake-up routines

• Power-down and wake-up latencies

• Record power-down constraints

Power policy:

• Run in idle

task

• Select power

saving mode

Impact of TI-RTOS power manager

Power Mode Wake-up Time to

CPU Active

Current Used

Active NA 4.145 mA

WaitForInterrupt A few cycles 2.028 mA

IDLE 1.4 µs 796 µA

STANDBY 14 µs 1-2 µA

• TI MCU offers low power modes that consume exponentially less power

compared to simply sleeping the main Cortex-M core (WaitForInterrupt)

– The default power policy uses the latency data combined with its

knowledge of the next scheduled event to select the lowest possible

power state, thus greatly extending battery life

– Note: The data below is from the SimpleLink™ CC2640 wireless

MCU

67

TI-RTOS device drivers & board support

• Driver APIs are consistent across device families

– Makes applications easy to port to other device supported by TI-RTOS

• Drivers are designed for use with RTOS

– Thread-safe

– Block (on a semaphore) when waiting for I/O so CPU is released for another

thread to run

• Each supported board has a “board.c” file that contains the code for initializing all the

peripherals

• Drivers are “power-aware” for ultra low-power MCU devices

C28 C28+M3 TM4C MSP432 MSP430 CC3200 CC26xx

Real-time clock Y Y Y Y

Timer Y Y Y Y Y Y Y

UART Y Y Y Y Y Y

DMA-based UART Y Y

I2C Y Y Y Y Y Y

I2S Y

SPI Y Y Y Y Y Y

SPI-SD Y Y Y Y Y

PWM Y Y Y

Camera Y

EMAC Y Y

USB Y Y Y

Watchdog Y Y Y Y Y

TI-RTOS device drivers

TI-RTOS connectivity & middleware

Real-time Kernel

IoT MCU

Drivers

Connectivity Wi-Fi, Bluetooth®

Smart, ZigBee®,

Cellular (via PPP),

Wired TCP/IP,

TLS/SSL

Other

Middleware USB, File

Systems

User

Application

Tasks

Power

Manager

Sensors

T

I

-

R

T

O

S

APls

TI-RTOS: wireless connectivity

• TI-RTOS supports all on-chips stacks in TI SimpleLink™

wireless MCUs out-of-box

• TI-RTOS supports the SimpleLink™ Wi-Fi CC3100

wireless network processor out-of-box Device Wireless Stack Comments

CC3200 Wi-Fi CC3200 Wi-Fi host driver pre-tested on TI-RTOS

CC2630 ZigBee Stack runs by default on TI-RTOS

CC2640 Bluetooth Smart Stack runs by default on TI-RTOS

MCU + CC3100 Wi-Fi TI-RTOS offers pre-integrated CC3100 host drivers using SPIs

on MSP430, MSP432 and TM4Cx

Hardware

Ethernet

Packet

Driver

Serial

Port

Driver

Timer

Driver

User

LED

Driver

Hardware Adaptation Layer

Serial IF

PPP

TI-RTOS TCP/IP stack

Supports both IPv4 and IPv6

Standard BSD Sockets interface

Zero-copy sockets interface available

Highly configurable to meet footprint constraints

PPP/Serial Interface allows use with third-party cellular modems

SSL/TLS requires a licensing fee

TCP/IP Key Features

NAT

IF

Manager

Route

Manager

Ethernet IF

ARP

IP

TCP UDP ICMP IGMP

Standard BSD Sockets Interface

T

L

S

S

N

T

P

H

T

T

P

T

F

T

P

T

E

L

N

E

T

D

N

S

D

H

C

P

USB stack

Hardware

SD card, mouse,

UART, ….

Drivers

DMA

Driver

USB

Driver

Hardware Adaptation Layer

Class Driver

Application

MSC Host Class Driver

HID Host & Device Class Drivers

CDC Device Class Driver

Examples for each class driver

Example of using MSC Host Driver under FAT file system

USB Key Features

Host

M

S

C

H

I

D

Device

C

D

C

H

I

D

C

O

N

F

I

G

U

R

A

T

I

O

N

File system

• TI uses an open source software called FatFs

• Key features:

– Both native and C RTS file APIs may be used

• C RTS APIs (fopen (), fread (), fwrite (), …) are plugged into file system

– Supports FAT12, FAT16, FAT32, and VFAT

• Long file names (VFAT) are not supported in the default build

• TI does NOT indemnify against VFAT patents

• Drivers options:

– SD Card (via SPI driver)

– USB flash drive (via USB MSC host)

Summary

• TI-RTOS enables developers to focus on their specific areas

of applications expertise by providing pre-tested software

building blocks:

– Multitasking kernel and device drivers

– Connectivity solutions: TCP/IP, Wi-Fi, BLE, and USB

– Advanced, easy-to-use power management

• Preemptive multitasking design paradigm simplifies

development and maintenance of embedded applications

• TI-RTOS no-cost licensing removes commercial barriers to

deployment

For more information

• www.ti.com web page: www.ti.com/tool/ti-rtos

– Product brochure, white paper, manuals, software downloads

• e2e forum: http://e2e.ti.com/support/embedded/tirtos/

• Wiki: http://processors.wiki.ti.com/index.php/Main_Page

– Select ‘TI-RTOS’ category

• Download page:

– http://software-

dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/tirtos/index.html

MSP432 RTOS

76

Real-time Kernel

MCU

Drivers

Connectivity Wi-Fi

Middleware File Systems

User Application

Tasks

Power

Manager

Sensors

TI-RTOS

freeRTOS

RTX (CMSIS-RTOS)

Micrium OS

RTOS Options

RTOS Features Comparison

77

Scheduler Type CMSI

S

Services Interrupt

Latency

Specific

Device

Support

Device Drivers Size Low

Power Support

TI-RTOS

By TI

• Pre-emptive X • Tasks

• Swis

• Hwis

• Software

Timers

• Semaphores

• Mutex

• Mailbox

• Events

• Zero-latency

interrupts

supported (115 cycles for ISRs with

TI-RTOS calls)

• Systick

• Interrupts

• Exception

Handling

• SPI

• SPI-SD

• I2C

• UART

• Timer

• RTC

• Timestamp

• Watchdog

4K to

20K

• Tick Suppression,

• Device specific Power

Manager

ARM RTX

By Keil

• Round-robin

(default)

• Pre-emptive

• Cooperative

√ • Tasks

• SWIs

• Software

Timers

• Semaphores

• Mutex

• Mailbox

• Events

• Zero-latency

interrupts

supported

• Systick X <4K • Tick Suppression,

• Device specific support

coming soon

FreeRTOS

By Real

Time

Engineers

Ltd

• Pre-emptive

• Cooperative

X • Tasks

• Co-routines (task share stack)

• Direct TASK

notifications

• Software

Timers

• Semaphore

• Mutex

• Events

• Zero-latency

interrupts

supported

• Systick

X 5K to

10K

• Tick Suppression,

• Pre and post sleep

macros for

customization,

• Idle task hook.

Micrium OS

By Micrium

• Pre-emptive X • Tasks

• Software

Timers

• Semaphores

• Mutex

• Mailbox

• Events

• Unknown • Systick

X 5K to

24K

• Idle Task Hook

• Tick suppression coming

soon

RTOS Tools Comparison

78

Object

Viewer

Execution

Graph

Logging RTOS

Config

Tool

Signal Plots Compiler

support

Examples License

Certified

Cost

TI-RTOS

By TI

√ √ √ √ √

(GUI

composer)

• CCS

• IAR

• GCC

> 50 • BSD Free

ARM RTX

By Keil

√

√

X √

√

• IAR

• Keil

• GCC

• Cosmic

2 • BSD Free

FreeRTOS

By Real Time

Engineers Ltd

√

3rd party

Standalone

√

3rd party

Standalone

√

3rd party

Standalone

X √

3rd party

Standalone

• CCS

• IAR

• Keil

• GCC

• Tasking

1 • Modified GPL

• SafeRTOS

Free

Micrium OS

By Micrium

√

√

√

X √

• CCS

• IAR

2 • Micrium

• SIL3/SIL4

Contact

Micrium

MSP432 & TI-RTOS

• Developed and maintained by TI

• Fully supported on MSP432 with

> 50 examples. Out of the box

examples for supported booster-

packs.

• Power Manager to simplify &

optimize power during runtime

• Power-aware Drivers that work

with TI-RTOS kernel or can even

be used with another RTOS

• Underlying structure for Energia

MT - first hobbyist-oriented multi-

thread IDE supporting MSP432

79

BoosterPack Supported

CC3100 Booster Pack

SD-Card BoosterPack

TMP006 BoosterPack

Sharp Memory LCD BoosterPack

RF430CL330 NFC Transponder

TPL0401EVM Board

Components Supported

Kernel

Wi-Fi

FAT File System

Device Drivers

Power Manager

Instrumentation

IDE: CCS, IAR, & GCC Tools

Device Drivers

Real-time clock NEW!

Timer

UART

I2C

SPI

SPI-SD

PWM NEW!

Watchdog

GPIO

TI-RTOS Power Manager

AM1_LDO

AM0_LDO

AM1_LPR

AM0_LPR

AM1_DCDC

AM0_DCDC

RESET

FlashCtl_setWaitState(FLASH_BANK0, waitsNew);

FlashCtl_setWaitState(FLASH_BANK1, waitsNew);

/* now change clocks and dividers */

CS_setDCOCenteredFrequency(

PowerMSP432_perfLevels[level].DCORESEL);

CS_initClockSignal(CS_MCLK,

PowerMSP432_perfLevels[level].clockSource,

PowerMSP432_perfLevels[level].DIVM);

CS_initClockSignal(CS_HSMCLK,

PowerMSP432_perfLevels[level].clockSource,

PowerMSP432_perfLevels[level].DIVHS);

CS_initClockSignal(CS_SMCLK,

PowerMSP432_perfLevels[level].clockSource,

PowerMSP432_perfLevels[level].DIVS);

FlashCtl_enableReadBuffering(FLASH_BANK0,

FLASH_DATA_READ);

FlashCtl_enableReadBuffering(FLASH_BANK0,

FLASH_INSTRUCTION_FETCH);

FlashCtl_enableReadBuffering(FLASH_BANK1,

FLASH_DATA_READ);

FlashCtl_enableReadBuffering(FLASH_BANK1,

FLASH_INSTRUCTION_FETCH);

changedStateOK = PCM_setPowerState(stateNew);

Power_setPerformanceLevel(level)

MSP432 Power Sequence

Active-mode Transition

Using MSP432 DriverLib Using TI-RTOS Power Manager

AMx_LDO

SLx_LDO

AMx_LPR

SLx_LPR

AMx_DCDC

SLx_DCDC

1MCLK 3MCLKs 1MCLK 3MCLKs 1MCLK 3MCLKs

Sleep-mode Transition

RTC_C_holdClock();

WDT_A_holdTimer();

PCM_setPowerState(PCM_LPM3); Power_sleep()

Energia MT – Powered by TI-RTOS

81

??

Single sketch code hard to write for

multiple LEDs at different rates

Multiple sketches makes code clean and easy to write

• Complex single sketches to simple multiple sketches

• Run sketches in parallel

• Automagic low power

• The power of an RTOS for everybody without the complexity!

• Easy to create interactive component libraries

See video!

MSP432 CMSIS-DSP & CMSIS-RTX

• Leverage ARM standard CMSIS-DSP library

82

MSP432 LEARNING RESOURCES

• GrLib

• SimpleLink Wi-Fi

• CMSIS-DSP

• MSP-DSP coming

E2E Support for

MSP430 and

MSP432

RTOS

Libraries

E2E Support

MSP432 Training

Resources 7 MSP432 Training Portal ti.com/msp432trainingseries

8 MSP432 App Notes 9

10

11

• TI-RTOS

• freeRTOS

• CMSIS-RTX

• micriumOS

83

MSP432 Webinar https://training.ti.com/webinar-use-msp432-microcontrollers-bring-high-performance-low-power-applications

MSP432 Deep-dive http://dev.ti.com/tirex/#/Search/dive

MSP Workshop coming soon!

Application Note SLAA#

Porting Guide SLAA656

Optimizing Power SLAA668

Using DCDC & LDO SLAA640

Low-Frequency Modes SLAA657

Tunable DCO SLAA658

Software IP Protection SLAA660

BSL & Security SLAA659

ULPBench SLAA658

Debugging in ROM SLAA663

Часть 2: Demos & Hands-on

С использованием лаунчпэда MSP432

84

MSP432 Ecosystem & Demos

85

It’s all in MSPWare

86

MSP432 Entry

!!!New!!!

Training

MSP432

DriverLib

It’s all in MSPWare

87

Your one-stop shop for all

technical collateral

• User’s Guides

• Application Notes

• Deep-dive Training

• Code Examples

TI Cloud Development Tools

• TI-REX Cloud: All MSP432 Content on the browser, just a click away

• CCS Cloud: Develop your MSP432 application anywhere, anyhow

88

Hands-on/Demo 1 LaunchPad Out of Box Experience

89

Hands-on/Demo 2 Programming MSP432 from the Cloud

90

TI Cloud Development Tools

• TI-REX Cloud: All MSP432 Content on the browser, just a click away

• CCS Cloud: Develop your MSP432 application anywhere, anyhow

91

ULP Advisor | Now with MSP432 Rules

92

ULP# Name ULP 1.1 Ensure LPM usage

ULP 2.1 Leverage timer module for delay loops

ULP 3.1 Use ISRs instead of flag polling

ULP 4.1 Terminate unused GPIOs

ULP 5.1 Avoid processing-intensive operations: modulo, divide. (MSP430 only)

ULP 5.2 Avoid processing-intensive operations: double-precision floating point

ULP 5.3 Avoid processing-intensive operations: (s)printf()

ULP 6.1 Avoid multiplication on devices without hardware multiplier (MSP430 only)

ULP 6.2 Use MATHLIB for complex math operations (MSP430 only)

ULP 7.1 Use local instead of global variables where possible

ULP 8.1 Use 'static' & 'const' modifiers for local variables (MSP430 only)

ULP 9.1 Use pass by reference for large variables

ULP 10.1 Minimize function calls from within ISRs

ULP 11.1 Use lower bits for loop program control flow (MSP430 only)

ULP 11.2 Use lower bits for port bit-banging (MSP430 only)

ULP 12.1 Use DMA for large memcpy() calls

ULP 12.1b Use DMA for potentially large memcpy() calls

ULP 12.2 Use DMA for repetitive transfer

ULP13.1 Count down in loops / Write loops with the termination test at the bottom

ULP 14.1 Use unsigned variables for indexing

ULP 15.1 Use bit-masks instead of bit-fields

ULP 16.1 Detect for > 4 parameters passed in function call (MSP432 only)

ULP 17.1 Use bit-banding for bit manipulation (MSP432 only)

ULP 18.1 Use natural-size integer variables for computation, convert to smaller size for storage (MSP432 only)

Hands-on/Demo 3 EnergyTrace+

93

Verbose version:

EnergyTrace+[CPU States]+[Peripheral States]

EnergyTrace™ Real-Time Power Consumption Technology for MSP430™ and MSP432™ MCUs

Features/Devices All MSP430 MCUs MSP432 MCUs FR5969 (based on Wolverine platform)

Current Monitoring x x x

CPU State (PC) x x

Peripheral/System State x

EnergyTrace™

technology

EnergyTrace+™

technology

EnergyTrace++™ technology

Current Monitoring: Real-time monitoring of total energy usage of MCU

CPU State: Real-time monitoring of energy usage according to code being handled by CPU

Peripheral/System State: Real-time monitoring of energy usage by specific peripheral