msp430x4xx family user's guide (rev. g › ~ccharles › clinic › msp430.pdfpc program counter see...

MSP430x4xx Family

2007 Mixed Signal Products

User’s Guide

SLAU056G

Related Documentation From Texas Instruments

iii

Preface

Read This First

About This Manual

This manual discusses modules and peripherals of the MSP430x4xx family ofdevices. Each discussion presents the module or peripheral in a generalsense. Not all features and functions of all modules or peripherals are presenton all devices. In addition, modules or peripherals may differ in their exactimplementation between device families, or may not be fully implemented onan individual device or device family.

Pin functions, internal signal connections and operational parameters differfrom device to device. The user should consult the device-specific data sheetfor these details.

Related Documentation From Texas Instruments

For related documentation see the web site http://www.ti.com/msp430.

FCC Warning

This equipment is intended for use in a laboratory test environment only. Itgenerates, uses, and can radiate radio frequency energy and has not beentested for compliance with the limits of computing devices pursuant to subpartJ of part 15 of FCC rules, which are designed to provide reasonable protectionagainst radio frequency interference. Operation of this equipment in otherenvironments may cause interference with radio communications, in whichcase the user at his own expense will be required to take whatever measuresmay be required to correct this interference.

Notational Conventions

Program examples, are shown in a special typeface.

Glossary

iv

Glossary

ACLK Auxiliary Clock See Basic Clock Module

ADC Analog-to-Digital Converter

BOR Brown-Out Reset See System Resets, Interrupts, and Operating Modes

BSL Bootstrap Loader See www.ti.com/msp430 for application reports

CPU Central Processing Unit See RISC 16-Bit CPU

DAC Digital-to-Analog Converter

DCO Digitally Controlled Oscillator See FLL+ Module

dst Destination See RISC 16-Bit CPU

FLL Frequency Locked Loop See FLL+ Module

GIE General Interrupt Enable See System Resets Interrupts and Operating Modes

INT(N/2) Integer portion of N/2

I/O Input/Output See Digital I/O

ISR Interrupt Service Routine

LSB Least-Significant Bit

LSD Least-Significant Digit

LPM Low-Power Mode See System Resets Interrupts and Operating Modes

MAB Memory Address Bus

MCLK Master Clock See FLL+ Module

MDB Memory Data Bus

MSB Most-Significant Bit

MSD Most-Significant Digit

NMI (Non)-Maskable Interrupt See System Resets Interrupts and Operating Modes

PC Program Counter See RISC 16-Bit CPU

POR Power-On Reset See System Resets Interrupts and Operating Modes

PUC Power-Up Clear See System Resets Interrupts and Operating Modes

RAM Random Access Memory

SCG System Clock Generator See System Resets Interrupts and Operating Modes

SFR Special Function Register

SMCLK Sub-System Master Clock See FLL+ Module

SP Stack Pointer See RISC 16-Bit CPU

SR Status Register See RISC 16-Bit CPU

src Source See RISC 16-Bit CPU

TOS Top-of-Stack See RISC 16-Bit CPU

WDT Watchdog Timer See Watchdog Timer

Register Bit Conventions

v

Register Bit Conventions

Each register is shown with a key indicating the accessibility of the eachindividual bit, and the initial condition:

Register Bit Accessibility and Initial Condition

Key Bit Accessibility

rw Read/write

r Read only

r0 Read as 0

r1 Read as 1

w Write only

w0 Write as 0

w1 Write as 1

(w) No register bit implemented; writing a 1 results in a pulse.The register bit is always read as 0.

h0 Cleared by hardware

h1 Set by hardware

−0,−1 Condition after PUC

−(0),−(1) Condition after POR

Contents

vii

Contents

1 Introduction 1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Architecture 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Flexible Clock System 1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Embedded Emulation 1-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Address Space 1-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.1 Flash/ROM 1-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.2 RAM 1-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.3 Peripheral Modules 1-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.4 Special Function Registers (SFRs) 1-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.5 Memory Organization 1-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 System Resets, Interrupts, and Operating Modes 2-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 System Reset and Initialization 2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1 Brownout Reset (BOR) 2-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1.2 Device Initial Conditions After System Reset 2-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Interrupts 2-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 (Non)-Maskable Interrupts (NMI) 2-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Maskable Interrupts 2-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 Interrupt Processing 2-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.4 Interrupt Vectors 2-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5 Special Function Registers (SFRs) 2-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Operating Modes 2-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 Entering and Exiting Low-Power Modes 2-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Principles for Low-Power Applications 2-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Connection of Unused Pins 2-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

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3 RISC 16-Bit CPU 3-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 CPU Introduction 3-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 CPU Registers 3-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.1 Program Counter (PC) 3-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Stack Pointer (SP) 3-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Status Register (SR) 3-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 Constant Generator Registers CG1 and CG2 3-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.5 General-Purpose Registers R4 to R15 3-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Addressing Modes 3-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Register Mode 3-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Indexed Mode 3-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 Symbolic Mode 3-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4 Absolute Mode 3-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.5 Indirect Register Mode 3-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.6 Indirect Autoincrement Mode 3-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.7 Immediate Mode 3-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Instruction Set 3-17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Double-Operand (Format I) Instructions 3-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Single-Operand (Format II) Instructions 3-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 Jumps 3-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4 Instruction Cycles and Lengths 3-72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.5 Instruction Set Description 3-74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 16-Bit MSP430X CPU 4-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 CPU Introduction 4-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Interrupts 4-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 CPU Registers 4-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.1 The Program Counter PC 4-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 Stack Pointer (SP) 4-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 Status Register (SR) 4-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4 The Constant Generator Registers CG1 and CG2 4-11 . . . . . . . . . . . . . . . . . . . . . . 4.3.5 The General Purpose Registers R4 to R15 4-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 Addressing Modes 4-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1 Register Mode 4-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.2 Indexed Mode 4-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.3 Symbolic Mode 4-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.4 Absolute Mode 4-29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.5 Indirect Register Mode 4-32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.6 Indirect, Autoincrement Mode 4-33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.7 Immediate Mode 4-34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5 MSP430 and MSP430X Instructions 4-36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.1 MSP430 Instructions 4-37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.2 MSP430X Extended Instructions 4-44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6 Instruction Set Description 4-58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.1 Extended Instruction Binary Descriptions 4-59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.2 MPS430 Instructions 4-61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.3 Extended Instructions 4-113 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.4 Address Instructions 4-156 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

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5 FLL+ Clock Module 5-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 FLL+ Clock Module Introduction 5-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 FLL+ Clock Module Operation 5-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2.1 FLL+ Clock features for Low-Power Applications 5-6 . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 LFXT1 Oscillator 5-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3 XT2 Oscillator 5-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.4 Digitally-Controlled Oscillator (DCO) 5-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.5 Frequency Locked Loop (FLL) 5-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.6 DCO Modulator 5-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.7 Disabling the FLL Hardware and Modulator 5-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.8 FLL Operation from Low-Power Modes 5-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.9 Buffered Clock Output 5-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.10 FLL+ Fail-Safe Operation 5-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 FLL+ Clock Module Registers 5-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 Flash Memory Controller 6-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Flash Memory Introduction 6-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Flash Memory Segmentation 6-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.1 SegmentA on F47x Devices 6-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Flash Memory Operation 6-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3.1 Flash Memory Timing Generator 6-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 Erasing Flash Memory 6-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3 Writing Flash Memory 6-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.4 Flash Memory Access During Write or Erase 6-17 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.5 Stopping a Write or Erase Cycle 6-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.6 Marginal Read Mode 6-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.7 Configuring and Accessing the Flash Memory Controller 6-18 . . . . . . . . . . . . . . . . . 6.3.8 Flash Memory Controller Interrupts 6-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.9 Programming Flash Memory Devices 6-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4 Flash Memory Registers 6-21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 Supply Voltage Supervisor 7-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 SVS Introduction 7-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 SVS Operation 7-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.1 Configuring the SVS 7-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.2 SVS Comparator Operation 7-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.3 Changing the VLDx Bits 7-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.4 SVS Operating Range 7-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3 SVS Registers 7-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8 16-Bit Hardware Multiplier 8-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Hardware MultiplierIntroduction 8-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Hardware Multiplier Operation 8-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2.1 Operand Registers 8-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2 Result Registers 8-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.3 Software Examples 8-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.4 Indirect Addressing of RESLO 8-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.5 Using Interrupts 8-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3 Hardware Multiplier Registers 8-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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9 32-Bit Hardware Multiplier 9-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 32-Bit Hardware Multiplier Introduction 9-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 32-Bit Hardware Multiplier Operation 9-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.2.1 Operand Registers 9-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.2 Result Registers 9-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.3 Software Examples 9-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.4 Fractional Numbers 9-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.5 Putting it all together 9-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.6 Indirect Addressing of Result Registers 9-17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.7 Using Interrupts 9-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.8 Using DMA 9-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.3 32-Bit Hardware Multiplier Registers 9-21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10 DMA Controller 10-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 DMA Introduction 10-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 DMA Operation 10-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.2.1 DMA Addressing Modes 10-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.2 DMA Transfer Modes 10-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.3 Initiating DMA Transfers 10-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.4 Stopping DMA Transfers 10-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.5 DMA Channel Priorities 10-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.6 DMA Transfer Cycle Time 10-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.7 Using DMA with System Interrupts 10-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.8 DMA Controller Interrupts 10-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.9 Using the USCI_B I2C Module with the DMA Controller 10-18 . . . . . . . . . . . . . . . 10.2.10 Using ADC12 with the DMA Controller 10-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.11 Using DAC12 With the DMA Controller 10-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.12 Writing to Flash With the DMA Controller 10-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.3 DMA Registers 10-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11 Digital I/O 11-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Digital I/O Introduction 11-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Digital I/O Operation 11-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.2.1 Input Register PxIN 11-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.2 Output Registers PxOUT 11-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.3 Direction Registers PxDIR 11-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.4 Pullup/Pulldown Resistor Enable Registers PxREN (MSP430x47x only) 11-4 . . . 11.2.5 Function Select Registers PxSEL 11-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.6 P1 and P2 Interrupts 11-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.7 Configuring Unused Port Pins 11-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.3 Digital I/O Registers 11-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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12 Watchdog Timer, Watchdog Timer+ 12-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 Watchdog Timer Introduction 12-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 Watchdog Timer Operation 12-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.1 Watchdog Timer Counter 12-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.2 Watchdog Mode 12-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.3 Interval Timer Mode 12-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.4 Watchdog Timer Interrupts 12-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.5 WDT+ Enhancements 12-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.6 Operation in Low-Power Modes 12-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.7 Software Examples 12-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.3 Watchdog Timer Registers 12-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13 Basic Timer1 13-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1 Basic Timer1 Introduction 13-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 Basic Timer1 Operation 13-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.2.1 Basic Timer1 Counter One 13-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.2 Basic Timer1 Counter Two 13-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.3 16-Bit Counter Mode 13-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.4 Basic Timer1 Operation: Signal fLCD 13-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.5 Basic Timer1 Interrupts 13-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.3 Basic Timer1 Registers 13-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14 Real Time Clock 14-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.1 RTC Introduction 14-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2 Real-Time Clock Operation 14-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.2.1 Counter Mode 14-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.2 Calendar Mode 14-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.3 RTC and Basic Timer1 Interaction 14-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.4 Real-Time Clock Interrupts 14-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14.3 Real-Time Clock Registers 14-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15 Timer_A 15-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1 Timer_A Introduction 15-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2 Timer_A Operation 15-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15.2.1 16-Bit Timer Counter 15-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.2 Starting the Timer 15-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.3 Timer Mode Control 15-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.4 Capture/Compare Blocks 15-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.5 Output Unit 15-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.6 Timer_A Interrupts 15-17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15.3 Timer_A Registers 15-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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16 Timer_B 16-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.1 Timer_B Introduction 16-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16.1.1 Similarities and Differences From Timer_A 16-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2 Timer_B Operation 16-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16.2.1 16-Bit Timer Counter 16-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.2 Starting the Timer 16-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.3 Timer Mode Control 16-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.4 Capture/Compare Blocks 16-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.5 Output Unit 16-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.6 Timer_B Interrupts 16-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16.3 Timer_B Registers 16-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

17 USART Peripheral Interface, UART Mode 17-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.1 USART Introduction: UART Mode 17-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.2 USART Operation: UART Mode 17-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

17.2.1 USART Initialization and Reset 17-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.2.2 Character Format 17-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.2.3 Asynchronous Communication Formats 17-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.2.4 USART Receive Enable 17-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.2.5 USART Transmit Enable 17-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.2.6 USART Baud Rate Generation 17-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.2.7 USART Interrupts 17-17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

17.3 USART Registers: UART Mode 17-21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

18 USART Peripheral Interface, SPI Mode 18-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.1 USART Introduction: SPI Mode 18-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2 USART Operation: SPI Mode 18-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

18.2.1 USART Initialization and Reset 18-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2.2 Master Mode 18-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2.3 Slave Mode 18-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2.4 SPI Enable 18-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2.5 Serial Clock Control 18-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2.6 SPI Interrupts 18-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

18.3 USART Registers: SPI Mode 18-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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19 Universal Serial Communication Interface, UART Mode 19-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.1 USCI Overview 19-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.2 USCI Introduction: UART Mode 19-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3 USCI Operation: UART Mode 19-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

19.3.1 USCI Initialization and Reset 19-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3.2 Character Format 19-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3.3 Asynchronous Communication Formats 19-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3.4 Automatic Baud Rate Detection 19-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3.5 IrDA Encoding and Decoding 19-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3.6 Automatic Error Detection 19-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3.7 USCI Receive Enable 19-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3.8 USCI Transmit Enable 19-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3.9 UART Baud Rate Generation 19-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3.10 Setting a Baud Rate 19-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3.11 Transmit Bit Timing 19-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3.12 Receive Bit Timing 19-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3.13 Typical Baud Rates and Errors 19-21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3.14 Using the USCI Module in UART Mode with Low-Power Modes 19-25 . . . . . . . . 19.3.15 USCI Interrupts 19-25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

19.4 USCI Registers: UART Mode 19-27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20 Universal Serial Communication Interface, SPI Mode 20-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.1 USCI Overview 20-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.2 USCI Introduction: SPI Mode 20-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.3 USCI Operation: SPI Mode 20-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20.3.1 USCI Initialization and Reset 20-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.3.2 Character Format 20-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.3.3 Master Mode 20-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.3.4 Slave Mode 20-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.3.5 SPI Enable 20-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.3.6 Serial Clock Control 20-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.3.7 Using the SPI Mode with Low Power Modes 20-12 . . . . . . . . . . . . . . . . . . . . . . . . . 20.3.8 SPI Interrupts 20-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20.4 USCI Registers: SPI Mode 20-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

21 Universal Serial Communication Interface, I2C Mode 21-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.1 USCI Overview 21-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2 USCI Introduction: I2C Mode 21-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3 USCI Operation: I2C Mode 21-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

21.3.1 USCI Initialization and Reset 21-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3.2 I2C Serial Data 21-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3.3 I2C Addressing Modes 21-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3.4 I2C Module Operating Modes 21-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3.5 I2C Clock Generation and Synchronization 21-21 . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3.6 Using the USCI Module in I2C Mode With Low-Power Modes 21-22 . . . . . . . . . . 21.3.7 USCI Interrupts in I2C Mode 21-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

21.4 USCI Registers: I2C Mode 21-25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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22 OA 22-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.1 OA Introduction 22-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2 OA Operation 22-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

22.2.1 OA Amplifier 22-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2.2 OA Input 22-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2.3 OA Output 22-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2.4 OA Configurations 22-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

22.3 OA Modules in FG42x0 Devices 22-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.3.1 OA Amplifier 22-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.3.2 OA Inputs 22-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.3.3 OA Outputs 22-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.3.4 OA Configurations 22-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.3.5 Switch Control 22-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.3.6 Offset Calibration 22-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

22.4 OA Registers 22-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.5 OA Registers in FG42x0 Devices 22-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

23 Comparator_A 23-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.1 Comparator_A Introduction 23-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.2 Comparator_A Operation 23-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

23.2.1 Comparator 23-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.2.2 Input Analog Switches 23-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.2.3 Output Filter 23-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.2.4 Voltage Reference Generator 23-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.2.5 Comparator_A, Port Disable Register CAPD 23-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.2.6 Comparator_A Interrupts 23-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.2.7 Comparator_A Used to Measure Resistive Elements 23-7 . . . . . . . . . . . . . . . . . . . .

23.3 Comparator_A Registers 23-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

24 LCD Controller 24-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.1 LCD Controller Introduction 24-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2 LCD Controller Operation 24-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

24.2.1 LCD Memory 24-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.2 Blinking the LCD 24-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.3 LCD Timing Generation 24-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.4 LCD Voltage Generation 24-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.5 LCD Outputs 24-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.6 Static Mode 24-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.7 2-Mux Mode 24-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.8 3-Mux Mode 24-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2.9 4-Mux Mode 24-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

24.3 LCD Controller Registers 24-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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25 LCD_A Controller 25-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.1 LCD_A Controller Introduction 25-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.2 LCD_A Controller Operation 25-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

25.2.1 LCD Memory 25-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.2.2 Blinking the LCD 25-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.2.3 LCD_A Voltage And Bias Generation 25-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.2.4 LCD Timing Generation 25-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.2.5 LCD Outputs 25-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.2.6 Static Mode 25-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.2.7 2-Mux Mode 25-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.2.8 3-Mux Mode 25-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.2.9 4-Mux Mode 25-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

25.3 LCD Controller Registers 25-21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

26 ADC12 26-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.1 ADC12 Introduction 26-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.2 ADC12 Operation 26-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

26.2.1 12-Bit ADC Core 26-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.2.2 ADC12 Inputs and Multiplexer 26-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.2.3 Voltage Reference Generator 26-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.2.4 Auto Power-Down 26-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.2.5 Sample and Conversion Timing 26-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.2.6 Conversion Memory 26-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.2.7 ADC12 Conversion Modes 26-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.2.8 Using the Integrated Temperature Sensor 26-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.2.9 ADC12 Grounding and Noise Considerations 26-17 . . . . . . . . . . . . . . . . . . . . . . . . 26.2.10 ADC12 Interrupts 26-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

26.3 ADC12 Registers 26-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

27 SD16 27-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.1 SD16 Introduction 27-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.2 SD16 Operation 27-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

27.2.1 ADC Core 27-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.2.2 Analog Input Range and PGA 27-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.2.3 Voltage Reference Generator 27-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.2.4 Auto Power-Down 27-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.2.5 Analog Input Pair Selection 27-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.2.6 Analog Input Characteristics 27-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.2.7 Digital Filter 27-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.2.8 Conversion Memory Registers: SD16MEMx 27-10 . . . . . . . . . . . . . . . . . . . . . . . . . 27.2.9 Conversion Modes 27-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.2.10 Conversion Operation Using Preload 27-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.2.11 Using the Integrated Temperature Sensor 27-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.2.12 Interrupt Handling 27-17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

27.3 SD16 Registers 27-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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28 SD16_A 28-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.1 SD16_A Introduction 28-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.2 SD16_A Operation 28-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

28.2.1 ADC Core 28-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.2.2 Analog Input Range and PGA 28-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.2.3 Voltage Reference Generator 28-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.2.4 Auto Power-Down 28-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.2.5 Analog Input Pair Selection 28-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.2.6 Analog Input Characteristics 28-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.2.7 Digital Filter 28-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.2.8 Conversion Memory Register: SD16MEMx 28-12 . . . . . . . . . . . . . . . . . . . . . . . . . . 28.2.9 Conversion Modes 28-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.2.10 Conversion Operation Using Preload 28-17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.2.11 Using the Integrated Temperature Sensor 28-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.2.12 Interrupt Handling 28-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

28.3 SD16_A Registers 28-22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

29 DAC12 29-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.1 DAC12 Introduction 29-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.2 DAC12 Operation 29-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

29.2.1 DAC12 Core 29-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.2.2 DAC12 Reference 29-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.2.3 Updating the DAC12 Voltage Output 29-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.2.4 DAC12_xDAT Data Format 29-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.2.5 DAC12 Output Amplifier Offset Calibration 29-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.2.6 Grouping Multiple DAC12 Modules 29-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29.2.7 DAC12 Interrupts 29-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

29.3 DAC12 Registers 29-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

30 Scan IF 30-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.1 Scan IF Introduction 30-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.2 Scan IF Operation 30-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

30.2.1 Scan IF Analog Front End 30-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.2.2 Scan IF Timing State Machine 30-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.2.3 Scan IF Processing State Machine 30-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.2.4 Scan IF Debug Register 30-26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.2.5 Scan IF Interrupts 30-27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.2.6 Using the Scan IF with LC Sensors 30-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.2.7 Using the Scan IF With Resistive Sensors 30-32 . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.2.8 Quadrature Decoding 30-33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

30.3 Scan IF Registers 30-35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

31 Embedded Emulation Module (EEM) 31-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.1 EEM Introduction 31-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2 EEM Building Blocks 31-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

31.2.1 Triggers 31-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2.2 Trigger Sequencer 31-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2.3 State Storage (Internal Trace Buffer) 31-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2.4 Clock Control 31-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

31.3 EEM Configurations 31-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1Introduction

Introduction

This chapter describes the architecture of the MSP430.

Topic Page

1.1 Architecture 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Flexible Clock System 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Embedded Emulation 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Address Space 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 1

Architecture

1-2 Introduction

1.1 Architecture

The MSP430 incorporates a 16-bit RISC CPU, peripherals, and a flexible clocksystem that interconnect using a von-Neumann common memory addressbus (MAB) and memory data bus (MDB). Partnering a modern CPU withmodular memory-mapped analog and digital peripherals, the MSP430 offerssolutions for demanding mixed-signal applications.

Key features of the MSP430x4xx family include:

� Ultralow-power architecture extends battery life

� 0.1-μA RAM retention

� 0.8-μA real-time clock mode

� 250-μA / MIPS active

� High-performance analog ideal for precision measurement

� 12-bit or 10-bit ADC — 200 ksps, temperature sensor, VRef

� 12-bit dual-DAC

� Comparator-gated timers for measuring resistive elements

� Supply voltage supervisor

� 16-bit RISC CPU enables new applications at a fraction of the code size.

� Large register file eliminates working file bottleneck

� Compact core design reduces power consumption and cost

� Optimized for modern high-level programming

� Only 27 core instructions and seven addressing modes

� Extensive vectored-interrupt capability

� In-system programmable Flash permits flexible code changes, fieldupgrades and data logging

1.2 Flexible Clock System

The clock system is designed specifically for battery-powered applications. Alow-frequency auxiliary clock (ACLK) is driven directly from a common 32-kHzwatch crystal. The ACLK can be used for a background real-time clock selfwake-up function. An integrated high-speed digitally controlled oscillator(DCO) can source the master clock (MCLK) used by the CPU and high-speedperipherals. By design, the DCO is active and stable in less than 6 μs.MSP430-based solutions effectively use the high-performance 16-bit RISCCPU in very short bursts.

� Low-frequency auxiliary clock = Ultralow-power stand-by mode

� High-speed master clock = High performance signal processing

Embedded Emulation

1-3Introduction

Figure 1−1. MSP430 Architecture

ACLK

BusConv.

Peripheral

MAB 16-Bit

MDB 16-Bit

MCLK

SMCLK

ClockSystem

Peripheral PeripheralPeripheral

Peripheral Peripheral Peripheral

Watchdog

RAMFlash/

RISC CPU16-Bit

JTA

G/D

ebug

ACLKSMCLK

ROM

MDB 8-Bit

JTAG

1.3 Embedded Emulation

Dedicated embedded emulation logic resides on the device itself and isaccessed via JTAG using no additional system resources.

The benefits of embedded emulation include:

� Unobtrusive development and debug with full-speed execution,breakpoints, and single-steps in an application are supported.

� Development is in-system subject to the same characteristics as the finalapplication.

� Mixed-signal integrity is preserved and not subject to cabling interference.

Address Space

1-4 Introduction

1.4 Address Space

The MSP430 von-Neumann architecture has one address space shared withspecial function registers (SFRs), peripherals, RAM, and Flash/ROM memoryas shown in Figure 1−2. See the device-specific data sheets for specificmemory maps. Code access are always performed on even addresses. Datacan be accessed as bytes or words.

The addressable memory space is 128 KB with future expansion planned.

Figure 1−2. Memory Map

0FFE0hInterrupt Vector Table

Flash/ROM

RAM

16-Bit Peripheral Modules

8-Bit Peripheral Modules

Special Function Registers

0FFFFh

0FFDFh

0200h

01FFh

0100h

0FFh

010h0Fh

0h

Word/Byte

Word/Byte

Word

Byte

Byte

Word/Byte

10000hFlash/ROM

Access

Word/Byte

1.4.1 Flash/ROM

The start address of Flash/ROM depends on the amount of Flash/ROMpresent and varies by device. The end address for Flash/ROM is 0FFFFh fordevices with less than 60kB of Flash/ROM; otherwise, it is device dependent.Flash can be used for both code and data. Word or byte tables can be storedand used in Flash/ROM without the need to copy the tables to RAM beforeusing them.

The interrupt vector table is mapped into the upper 16 words of Flash/ROMaddress space, with the highest priority interrupt vector at the highestFlash/ROM word address (0FFFEh).

Address Space

1-5Introduction

1.4.2 RAM

RAM starts at 0200h. The end address of RAM depends on the amount of RAMpresent and varies by device. RAM can be used for both code and data.

1.4.3 Peripheral Modules

Peripheral modules are mapped into the address space. The address spacefrom 0100 to 01FFh is reserved for 16-bit peripheral modules. These modulesshould be accessed with word instructions. If byte instructions are used, onlyeven addresses are permissible, and the high byte of the result is always 0.

The address space from 010h to 0FFh is reserved for 8-bit peripheral modules.These modules should be accessed with byte instructions. Read access ofbyte modules using word instructions results in unpredictable data in the highbyte. If word data is written to a byte module only the low byte is written intothe peripheral register, ignoring the high byte.

1.4.4 Special Function Registers (SFRs)

Some peripheral functions are configured in the SFRs. The SFRs are locatedin the lower 16 bytes of the address space, and are organized by byte. SFRsmust be accessed using byte instructions only. See the device-specific datasheets for applicable SFR bits.

1.4.5 Memory Organization

Bytes are located at even or odd addresses. Words are only located at evenaddresses as shown in Figure 1−3. When using word instructions, only evenaddresses may be used. The low byte of a word is always an even address.The high byte is at the next odd address. For example, if a data word is locatedat address xxx4h, then the low byte of that data word is located at addressxxx4h, and the high byte of that word is located at address xxx5h.

Address Space

1-6 Introduction

Figure 1−3. Bits, Bytes, and Words in a Byte-Organized Memory

15

7

14

6

. . Bits . .

. . Bits . .

9

1

8

0

Byte

Byte

Word (High Byte)

Word (Low Byte)

xxxAh

xxx9h

xxx8h

xxx7h

xxx6h

xxx5h

xxx4h

xxx3h

2-1System Resets, Interrupts, and Operating Modes

System Resets, Interrupts,and Operating Modes

This chapter describes the MSP430x4xx system resets, interrupts, andoperating modes.

Topic Page

2.1 System Reset and Initialization 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Interrupts 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Operating Modes 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Principles for Low-Power Applications 2-16. . . . . . . . . . . . . . . . . . . . . . . .

2.5 Connection of Unused Pins 2-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 2

System Reset and Initialization

2-2 System Resets, Interrupts, and Operating Modes

2.1 System Reset and Initialization

The system reset circuitry shown in Figure 2−1 sources both a power-on reset(POR) and a power-up clear (PUC) signal. Different events trigger these resetsignals and different initial conditions exist depending on which signal wasgenerated.

Figure 2−1. Power-On Reset and Power-Up Clear Schematic

PORLatchS

R

PUCLatch

S

R

Resetwd1

Resetwd2

SS

Delay

RST/NMI

WDTNMI†

WDTTMSEL†WDTQn†

WDTIFG†

EQU†

MCLK

POR

PUCS

(from flash module)KEYV

SVS_POR

0 V

VCC

0 V

BrownoutReset

† From watchdog timer peripheral module

~ 50us

A POR is a device reset. A POR is only generated by the following threeevents:

� Powering up the device

� A low signal on the RST/NMI pin when configured in the reset mode

� An SVS low condition when PORON = 1.

A PUC is always generated when a POR is generated, but a POR is notgenerated by a PUC. The following events trigger a PUC:

� A POR signal

� Watchdog timer expiration when in watchdog mode only

� Watchdog timer security key violation

� A Flash memory security key violation



2.1.1 Brownout Reset (BOR)

All MSP430x4xx devices have a brownout reset circuit. The brownout resetcircuit detects low supply voltages such as when a supply voltage is appliedto or removed from the VCC terminal. The brownout reset circuit resets thedevice by triggering a POR signal when power is applied or removed. Theoperating levels are shown in Figure 2−2.

The POR signal becomes active when VCC crosses the VCC(start) level. Itremains active until VCC crosses the V(B_IT+) threshold and the delay t(BOR)elapses. The delay t(BOR) is adaptive being longer for a slow ramping VCC. Thehysteresis Vhys(B_ IT−) ensures that the supply voltage must drop belowV(B_IT−) to generate another POR signal from the brownout reset circuitry.

Figure 2−2. Brownout Timing

t(BOR)

VCC(start)

VCC

V(B_IT−)

Set Signal forPOR circuitry

V

V(B_IT+)

hys(B_IT−)

As the V(B_IT−) level is significantly above the V(MIN) level of the POR circuit,the BOR provides a reset for power failures where VCC does not fall belowV(MIN). See the device-specific data sheet for parameters.



2.1.2 Device Initial Conditions After System Reset

After a POR, the initial MSP430 conditions are:

� The RST/NMI pin is configured in the reset mode.

� I/O pins are switched to input mode as described in the Digital I/O chapter.

� Other peripheral modules and registers are initialized as described in theirrespective chapters in this manual.

� Status register (SR) is reset.

� The watchdog timer powers up active in watchdog mode.

� Program counter (PC) is loaded with address contained at reset vectorlocation (0FFFEh). CPU execution begins at that address.

Software Initialization

After a system reset, user software must initialize the MSP430 for theapplication requirements. The following must occur:

� Initialize the SP, typically to the top of RAM.

� Initialize the watchdog to the requirements of the application.

� Configure peripheral modules to the requirements of the application.

Additionally, the watchdog timer, oscillator fault, and flash memory flags canbe evaluated to determine the source of the reset.



2.2 Interrupts

The interrupt priorities are fixed and defined by the arrangement of themodules in the connection chain as shown in Figure 2−3. The nearer a moduleis to the CPU/NMIRS, the higher the priority. Interrupt priorities determine whatinterrupt is taken when more than one interrupt is pending simultaneously.

There are three types of interrupts:

� System reset� (Non)-maskable NMI� Maskable

Figure 2−3. Interrupt Priority

BusGrant

Module1

Module2

WDTTimer

Modulem

Modulen

1 2 1 2 1 2 1 2 1NMIRS

GIE

CPU

OSCfault

Reset/NMI

PUC

Circuit

PUC

WDT Security Key

Priority High Low

MAB − 5LSBs

GMIRS

Flash Security Key

Flash ACCV



2.2.1 (Non)-Maskable Interrupts (NMI)

(Non)-maskable NMI interrupts are not masked by the general interrupt enablebit (GIE), but are enabled by individual interrupt enable bits (ACCVIE, NMIIE,OFIE). When a NMI interrupt is accepted, all NMI interrupt enable bits areautomatically reset. Program execution begins at the address stored in the(non)-maskable interrupt vector, 0FFFCh. User software must set the requiredNMI interrupt enable bits for the interrupt to be re-enabled. The block diagramfor NMI sources is shown in Figure 2−4.

A (non)-maskable NMI interrupt can be generated by three sources:

� An edge on the RST/NMI pin when configured in NMI mode

� An oscillator fault occurs

� An access violation to the flash memory

Reset/NMI Pin

At power-up, the RST/NMI pin is configured in the reset mode. The functionof the RST/NMI pins is selected in the watchdog control register WDTCTL. Ifthe RST/NMI pin is set to the reset function, the CPU is held in the reset stateas long as the RST/NMI pin is held low. After the input changes to a high state,the CPU starts program execution at the word address stored in the resetvector, 0FFFEh.

If the RST/NMI pin is configured by user software to the NMI function, a signaledge selected by the WDTNMIES bit generates an NMI interrupt if the NMIIEbit is set. The RST/NMI flag NMIIFG is also set.

Note: Holding RST/NMI Low

When configured in the NMI mode, a signal generating an NMI event shouldnot hold the RST/NMI pin low. If a PUC occurs from a different source whilethe NMI signal is low, the device will be held in the reset state because a PUCchanges the RST/NMI pin to the reset function.

Note: Modifying WDTNMIES

When NMI mode is selected and the WDTNMIES bit is changed, an NMI canbe generated, depending on the actual level at the RST/NMI pin. When theNMI edge select bit is changed before selecting the NMI mode, no NMI isgenerated.



Figure 2−4. Block Diagram of (Non)-Maskable Interrupt Sources

Flash Module

KEYV

System ResetGenerator

BOR

POR PUC

WDTQn EQU

PUC

POR

PUC POR

NMIRS

Clear

SWDTIFG

IRQ

WDTIE

ClearIE1.0

PUC

POR

IRQA

WDTTMSEL

Counter

IFG1.0

WDTNMI

WDTTMSEL

WDTNMIES

Watchdog Timer Module

Clear

S

IFG1.4

PUC

ClearIE1.4

PUC

NMIIFG

NMIIE

S

IFG1.1

ClearIE1.1

PUC

OFIFG

OFIE

OSCFault

NMI_IRQA

IRQA: Interrupt Request Accepted

RST/NMI

S

FCTL3.2

ClearIE1.5

ACCVIFG

ACCVIE

PUC

ACCV

WDT

SVS_POR



Oscillator Fault

The oscillator fault signal warns of a possible error condition with the crystaloscillator. The oscillator fault can be enabled to generate an NMI interrupt bysetting the OFIE bit. The OFIFG flag can then be tested by NMI the interruptservice routine to determine if the NMI was caused by an oscillator fault.

A PUC signal can trigger an oscillator fault, because the PUC switches theLFXT1 to LF mode, therefore switching off the HF mode. The PUC signal alsoswitches off the XT2 oscillator.

Flash Access Violation

The flash ACCVIFG flag is set when a flash access violation occurs. The flashaccess violation can be enabled to generate an NMI interrupt by setting theACCVIE bit. The ACCVIFG flag can then be tested by NMI the interrupt serviceroutine to determine if the NMI was caused by a flash access violation.



Example of an NMI Interrupt Handler

The NMI interrupt is a multiple-source interrupt. An NMI interrupt automaticallyresets the NMIIE, OFIE and ACCVIE interrupt-enable bits. The user NMIservice routine resets the interrupt flags and re-enables the interrupt-enablebits according to the application needs as shown in Figure 2−5.

Figure 2−5. NMI Interrupt Handler

yes

noOFIFG=1

yes

noACCVIFG=1

yes

Reset ACCVIFG

noNMIIFG=1

Reset NMIIFGReset OFIFG

Start of NMI Interrupt HandlerReset by HW:

OFIE, NMIIE, ACCVIE

User’s Software,Oscillator Fault

Handler

User’s Software,Flash Access

Violation Handler

User’s Software,External NMI

Handler

Optional

RETIEnd of NMI Interrupt

Handler

Note: Enabling NMI Interrupts with ACCVIE, NMIIE, and OFIE

To prevent nested NMI interrupts, the ACCVIE, NMIIE, and OFIE enable bitsshould not be set inside of an NMI interrupt service routine.

2.2.2 Maskable Interrupts

Maskable interrupts are caused by peripherals with interrupt capabilityincluding the watchdog timer overflow in interval-timer mode. Each maskableinterrupt source can be disabled individually by an interrupt enable bit, or allmaskable interrupts can be disabled by the general interrupt enable (GIE) bitin the status register (SR).

Each individual peripheral interrupt is discussed in the associated peripheralmodule chapter in this manual.



2.2.3 Interrupt Processing

When an interrupt is requested from a peripheral and the peripheral interruptenable bit and GIE bit are set, the interrupt service routine is requested. Onlythe individual enable bit must be set for (non)-maskable interrupts to berequested.

Interrupt Acceptance

The interrupt latency is 6 cycles, starting with the acceptance of an interruptrequest, and lasting until the start of execution of the first instruction of theinterrupt-service routine, as shown in Figure 2−6. The interrupt logic executesthe following:

1) Any currently executing instruction is completed.

2) The PC, which points to the next instruction, is pushed onto the stack.

3) The SR is pushed onto the stack.

4) The interrupt with the highest priority is selected if multiple interruptsoccurred during the last instruction and are pending for service.

5) The interrupt request flag resets automatically on single-source flags.Multiple source flags remain set for servicing by software.

6) The SR is cleared with the exception of SCG0, which is left unchanged.This terminates any low-power mode. Because the GIE bit is cleared,further interrupts are disabled.

7) The content of the interrupt vector is loaded into the PC: the programcontinues with the interrupt service routine at that address.

Figure 2−6. Interrupt Processing

Item1

Item2SP TOS

Item1

Item2

SP TOS

PC

SR

BeforeInterrupt

AfterInterrupt



Return From Interrupt

The interrupt handling routine terminates with the instruction:

RETI (return from an interrupt service routine)

The return from the interrupt takes 5 cycles to execute the following actionsand is illustrated in Figure 2−7.

1) The SR with all previous settings pops from the stack. All previous settingsof GIE, CPUOFF, etc. are now in effect, regardless of the settings usedduring the interrupt service routine.

2) The PC pops from the stack and begins execution at the point where it wasinterrupted.

Figure 2−7. Return From Interrupt

Item1

Item2

SP TOS

Item1

Item2SP TOS

PC

SR

Before After

PC

SR

Return From Interrupt

Interrupt nesting is enabled if the GIE bit is set inside an interrupt serviceroutine. When interrupt nesting is enabled, any interrupt occurring during aninterrupt service routine will interrupt the routine, regardless of the interruptpriorities.



2.2.4 Interrupt Vectors

The interrupt vectors and the power-up starting address are located in theaddress range 0FFFFh − 0FFE0h as described in Table 2−1. A vector isprogrammed by the user with the 16-bit address of the corresponding interruptservice routine. Some devices may contain more interrupt vectors. See thedevice-specific data sheet for the complete interrupt vector list.

Table 2−1. Interrupt Sources,Flags, and Vectors

INTERRUPT SOURCEINTERRUPT

FLAGSYSTEM

INTERRUPTWORD

ADDRESS PRIORITY

Power-up, externalreset, watchdog,flash password

WDTIFGKEYV

Reset 0FFFEh 15, highest

NMI, oscillator fault,flash memory accessviolation

NMIIFG OFIFG ACCVIFG

(non)-maskable(non)-maskable(non)-maskable

0FFFCh 14

device-specific 0FFFAh 13

device-specific 0FFF8h 12


Watchdog timer WDTIFG maskable 0FFF4h 10



device-specific 0FFEEh 7

device-specific 0FFECh 6

device-specific 0FFEAh 5

device-specific 0FFE8h 4




device-specific 0FFE0h 0, lowest

2.2.5 Special Function Registers (SFRs)

Some module enable bits, interrupt enable bits, and interrupt flags are locatedin the SFRs. The SFRs are located in the lower address range and areimplemented in byte format. SFRs must be accessed using byte instructions.See the device-specific data sheet for the SFR configuration.

Operating Modes


2.3 Operating Modes

The MSP430 family is designed for ultralow-power applications and usesdifferent operating modes shown in Figure 2−9.

The operating modes take into account three different needs:

� Ultralow-power

� Speed and data throughput

� Minimization of individual peripheral current consumption

The MSP430 typical current consumption is shown in Figure 2−8.

Figure 2−8. Typical Current Consumption of 41x Devices vs Operating Modes

315

AM

300

270

225

180

135

90

45

0LPM0 LPM2 LPM3 LPM4

200

55 3217 11 0.9 0.7 0.1 0.1

VCC = 3 V

VCC = 2.2 V

Operating Modes

A @

1 M

Hz

μIC

C/

The low-power modes 0−4 are configured with the CPUOFF, OSCOFF, SCG0,and SCG1 bits in the status register The advantage of including the CPUOFF,OSCOFF, SCG0, and SCG1 mode-control bits in the status register is that thepresent operating mode is saved onto the stack during an interrupt serviceroutine. Program flow returns to the previous operating mode if the saved SRvalue is not altered during the interrupt service routine. Program flow can bereturned to a different operating mode by manipulating the saved SR value onthe stack inside of the interrupt service routine. The mode-control bits and thestack can be accessed with any instruction.

When setting any of the mode-control bits, the selected operating mode takeseffect immediately. Peripherals operating with any disabled clock are disableduntil the clock becomes active. The peripherals may also be disabled with theirindividual control register settings. All I/O port pins and RAM/registers areunchanged. Wake up is possible through all enabled interrupts.

Operating Modes


Figure 2−9. MSP430x4xx Operating Modes For FLL+ Clock System

Active ModeCPU Is Active

Peripheral Modules Are Active

LPM0CPU Off, FLL+ On,

41x/42x MCLK On, 43x/44xMCLK off, ACLK On

CPUOFF = 1SCG0 = 0SCG1 = 0


LPM2CPU Off, FLL+ Off,

MCLK Off, ACLK On



MCLK Off, ACLK On

DC Generator Off


MCLK Off, ACLK Off

DC Generator Off

CPUOFF = 1OSCOFF = 1

SCG0 = 1SCG1 = 1

RST/NMINMI Active

PUC RST/NMI is Reset PinWDT is Active

POR

WDT Active,Security Key Violation

WDT Active,Time Expired, Overflow WDTIFG = 1

WDTIFG = 1

RST/NMIReset Active

VCC On

WDTIFG = 0


41x/42x MCLK On, 43x/44xMCLK off ACLK On


SCG1 SCG0 OSCOFF CPUOFF Mode CPU and Clocks Status

0 0 0 0 Active CPU is active, all enabled clocks are active

0 0 0 1 LPM0 CPU, MCLK are disabled (41x/42x peripheral MCLKremains on)SMCLK , ACLK are active

0 1 0 1 LPM1 CPU, MCLK, DCO osc. are disabled (41x/42xperipheral MCLK remains on)DC generator is disabled if the DCO is not used forMCLK or SMCLK in active modeSMCLK , ACLK are active

1 0 0 1 LPM2 CPU, MCLK, SMCLK, DCO osc. are disabledDC generator remains enabledACLK is active

1 1 0 1 LPM3 CPU, MCLK, SMCLK, DCO osc. are disabledDC generator disabledACLK is active

1 1 1 1 LPM4 CPU and all clocks disabled

Operating Modes


2.3.1 Entering and Exiting Low-Power Modes

An enabled interrupt event wakes the MSP430 from any of the low-poweroperating modes. The program flow is:

� Enter interrupt service routine:

� The PC and SR are stored on the stack

� The CPUOFF, SCG1, and OSCOFF bits are automatically reset

� Options for returning from the interrupt service routine:

� The original SR is popped from the stack, restoring the previousoperating mode.

� The SR bits stored on the stack can be modified within the interruptservice routine returning to a different operating mode when the RETIinstruction is executed.

; Enter LPM0 ExampleBIS #GIE+CPUOFF,SR ; Enter LPM0

; ... ; Program stops here;; Exit LPM0 Interrupt Service Routine

BIC #CPUOFF,0(SP) ; Exit LPM0 on RETIRETI

; Enter LPM3 ExampleBIS #GIE+CPUOFF+SCG1+SCG0,SR ; Enter LPM3

; ... ; Program stops here;; Exit LPM3 Interrupt Service Routine

BIC #CPUOFF+SCG1+SCG0,0(SP) ; Exit LPM3 on RETIRETI

Extended Time in Low-Power Modes

The negative temperature coefficient of the DCO should be considered whenthe DCO is disabled for extended low-power mode periods. If the temperaturechanges significantly, the DCO frequency at wake-up may be significantlydifferent from when the low-power mode was entered and may be out of thespecified operating range. To avoid this, the DCO can be set to it lowest valuebefore entering the low-power mode for extended periods of time wheretemperature can change.

; Enter LPM4 Example with lowest DCO SettingBIC.B #FN_8+FN_4+FN_3+FN_2,&SCFI0 ; Lowest RangeMOV.B #010h,&SCFI1 ; Select Tap 2BIS #GIE+CPUOFF+OSCOFF+SCG1+SCG0,SR ; Enter LPM4

; ... ; Program stops; Interrupt Service Routine

BIC #CPUOFF+OSCOFF+SCG1+SCG0,0(SP); Exit LPM4 on RETIRETI

Principles for Low-Power Applications


2.4 Principles for Low-Power Applications

Often, the most important factor for reducing power consumption is using theMSP430’s clock system to maximize the time in LPM3. LPM3 powerconsumption is less than 2 μA typical with both a real-time clock function andall interrupts active. A 32-kHz watch crystal is used for the ACLK and the CPUis clocked from the DCO (normally off) which has a 6-μs wake-up.

� Use interrupts to wake the processor and control program flow.

� Peripherals should be switched on only when needed.

� Use low-power integrated peripheral modules in place of software drivenfunctions. For example Timer_A and Timer_B can automatically generatePWM and capture external timing, with no CPU resources.

� Calculated branching and fast table look-ups should be used in place offlag polling and long software calculations.

� Avoid frequent subroutine and function calls due to overhead.

� For longer software routines, single-cycle CPU registers should be used.

2.5 Connection of Unused Pins

The correct termination of all unused pins is listed in Table 2−2.

Table 2−2.Connection of Unused Pins

Pin Potential Comment

AVCC DVCCAVSS DVSSVREF+ Open

VeREF+ DVSSVREF−/VeREF− DVSSXIN DVCCXOUT Open

XT2IN DVSS 43x, 44x. and 46x devices

XT2OUT Open 43x, 44x, and 46x devices

Px.0 to Px.7 Open Switched to port function, output direction

RST/NMI DVCC or VCC 47 kΩ pullup with 10nF pull downR03 DVSSCOM0 Open

TDO/TDI/TMS/TCK Open

Ax (dedicated) Open 42x devices

Sxx Open

3-1RISC 16-Bit CPU

RISC 16-Bit CPU

This chapter describes the MSP430 CPU, addressing modes, and instructionset.

Topic Page

3.1 CPU Introduction 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 CPU Registers 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Addressing Modes 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Instruction Set 3-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter 3

CPU Introduction

3-2 RISC 16-Bit CPU

3.1 CPU Introduction

The CPU incorporates features specifically designed for modernprogramming techniques such as calculated branching, table processing andthe use of high-level languages such as C. The CPU can address the completeaddress range without paging.

The CPU features include:

� RISC architecture with 27 instructions and 7 addressing modes

� Orthogonal architecture with every instruction usable with everyaddressing mode

� Full register access including program counter, status registers, and stackpointer

� Single-cycle register operations

� Large 16-bit register file reduces fetches to memory

� 16-bit address bus allows direct access and branching throughout entirememory range

� 16-bit data bus allows direct manipulation of word-wide arguments

� Constant generator provides six most used immediate values andreduces code size

� Direct memory-to-memory transfers without intermediate register holding

� Word and byte addressing and instruction formats

The block diagram of the CPU is shown in Figure 3−1.

CPU Introduction

3-3RISC 16-Bit CPU

Figure 3−1. CPU Block Diagram

015

MDB − Memory Data Bus Memory Address Bus − MAB

16Zero, ZCarry, COverflow, VNegative, N

16−bit ALU

dst src

R8 General Purpose

R9 General Purpose

R10 General Purpose

R11 General Purpose

R12 General Purpose

R13 General Purpose

R14 General Purpose

R15 General Purpose

R4 General Purpose

R5 General Purpose

R6 General Purpose

R7 General Purpose

R3/CG2 Constant Generator

R2/SR/CG1 Status

R1/SP Stack Pointer

R0/PC Program Counter 0

0

16

MCLK

CPU Registers

3-4 RISC 16-Bit CPU

3.2 CPU Registers

The CPU incorporates sixteen 16-bit registers. R0, R1, R2 and R3 havededicated functions. R4 to R15 are working registers for general use.

3.2.1 Program Counter (PC)

The 16-bit program counter (PC/R0) points to the next instruction to b

msp430x4xx family user's guide (rev. g › ~ccharles › clinic › msp430.pdfpc program counter see...

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