mr (7/7/05) t2k electronics beam structure ~ 8 (9?) bunches / spill bunch width ~ 60 nsec bunch...
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MR (7/7/05)
T2K electronics
Beam structure
~ 8 (9?) bunches / spillbunch width ~ 60 nsecbunch separation ~ 600 nsecspill duration ~ 5 sec
Time between spills ~ 3.5 secs.
~ 3.5 seconds
My understanding (some gaps)
Detector parameters (scintillator calorimeter)~ 50,000 channels (50k SiPMs)1 event / bunch + cosmics (100 Hz)
Electronics (physics) requirementsevent time: resolution ~ nssignal size: resolution? (no. of ADC bits?)dynamic range? (few 100 pC I think?)linearity?noise?
MR (7/7/05)
Trip chip
ref.: McFarland_MINERvA_Electronics.pdf (presentation at Rome T2K meeting, 6/12/04)
discusses possible use of Trip (not Trip-t) ASIC in T2K Trip-t is newer version of Trip (we would be more likely to use Trip-t but this talk still has some interesting info)
- generally positive, and gives estimates for front end costs ~ $440k for 30k channel system + $100k LV distribution + $100k DAQ
Trip ASIC (32 channels – packaged chip) integrate charge over spill (or bucket), variable preamp gain up to 4 pC dynamic range 48 stage pipeline stores analogue samples fast discriminator output -> FPGA -> timing in 5 nsec steps (could possibly do better) FPGA then passes pipeline trigger back to Trip 32 analogue samples muxed out to commercial ADC (12-bit)
MR (7/7/05)
Trip-t chip
ref.: TRIP_t_Apr05.ppt (Bellantoni – D0 AFEII Director’s Review, 13/4/05)
summarises measured performance of Trip-t & spec. improvements for 2nd version (in fab now I think)
Trip-t ASIC (32 channels - packaged)
integrate charge over spill (or bucket), variable preamp gain up to 3 pC dynamic range
48 stage pipeline stores analogue samples –> A pulse (7 bit precision)
noise < 1 fC (not sure whether this gain range dependent)
time between disc. firing (any channel) and end of integration period -> t pulse (~ 2nsec res’n)
t pulse also stored in 48 stage pipeline
disc. outputs read out during reset period -> FPGA -> pipeline trigger to Trip-t
32 A samples and 32 t samples muxed out to commercial ADCs
power < 10 mW/channel
Is above spec. adequate for T2K application?
MR (7/7/05)
McFarland_MINERvA_Electronics.pdf
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TRIP_t_Apr05.ppt
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possible new FE chip architecture
thresh
pk.hold
fast preamp
slow amp
SiPMdisc.
pk.hold
SiPM
pk.hold
SiPM
ADC
HV trim
HV trim
HV trim
control
combinedisc. O/Psand generateaddress ofchannel thatfired
e.g. 16 channels 4 bitadd.
n bits
control
fasttimingsignal
front end chip
~ 20 lines
front end digital (FPGA based)
functionality
fast time stamp (~ns)
control digitization of channel that fired
assemble data packet and transmit (channel address, time stamp, ADC value)
slow control set up HV trim, channel gains, thresholds, …
would expect one FE FPGA to deal withmore than one FE chip (maybe 8?)
nothing “particularly” difficult herefast time stamping performedoff-chip
MR (7/7/05)
Idea to keep very fast functionality off FPGA
good idea from Matt Noy
fast discriminatorO/P from FE chip
deserializer chipe.g. DS90CR486
FE FPGA
133 MHz only
800 MHz PLL
whichever line shows discriminatoroutput first -> timing at 1/6th of133MHz period (1.25 nsec.)
DS90CR486 -> 8 channels of 1:6 deserialization (8:48) => 1 chip for 8 FE chips 900 mW power => 7 mW / FE channel
MR (7/7/05)
Chip count
16 channelFE chip
16 SiPMs
FEFPGA
16 channelFE chip
16 SiPMs
16 channelFE chip
16 SiPMs
16 channelFE chip
16 SiPMs
16 channelFE chip
16 SiPMs
16 channelFE chip
16 SiPMs
16 channelFE chip
16 SiPMs
16 channelFE chip
16 SiPMs
50,000 channels50,000 SiPMs3125 FE chips (assume 16 channels)(maybe 390 deserializers)390 FE FPGAs
FEFPGA
FEFPGA
FEFPGA
FEFPGA
390 readout lines off-detector(or could combine)
MR (7/7/05)
Trip-t chip / new chip – a few pros and cons
Trip-t chip Pros
No FE chip development required no development cost – just buy chips
May be able to utilise other parts of Trip-t readout system? (or at least follow same approach)
Trip-t chip Cons
possible signal size incompatibility few pC, we need few 100 pC unless lower gain on SiPM (maybe could just attenuate?)
no HV trim (may be possible to provide with commercial components)
time resolution performance not good (but should be better for next version)
more complicated functionality than necessary for T2K (e.g. pipeline)
New chip Pros
FE specification and functionality can be tailored to SiPM everything under our control
New chip Cons
development cost risk