Moto Q GSM System

Last updated: April 26, 2007

Moto Q GSM

Moto Q GSM System Block Diagram

Moto Q GSM System Board Layout

Moto Q GSM System

RF Overview

Moto Q GSM System Antenna

Band GSM900 DCS1800 PCS1900 GSM850

Tx Frequency 880MHz - 915MHz

1710MHz - 1785MHz

1850MHz - 1910Mhz

824MHz - 849MHz

Rx Frequency 925MHz - 960MHz

1805MHz - 1880MHz

1930MHz - 1990MHz

869MHz - 894MHz

Band Support

NOTE-Accessory port only used for test purposes-Not designed to support RF cabled accessories

Moto Q GSM System RF6029

Features

EDGE Polar Modulator

Frac-N Digital GMSK Modulator

Integrated VCOs, Loop Filters, 4 RX SAW Filters, Matching, Bypass Caps

On-Chip Reference Oscillator Outputs (26MHz or 13MHz to Baseband)

Analog I/Q and Digital Baseband Interfaces

VLIF and DCR RX Modes

SAIC Capable

Two DACs: Power Amplifier Ramp and Frequency Control

10mmx10mm Leadless Package

Moto Q GSM System RF6029

RF3178Neptune

Moto Q GSM System RF3178

Features

Integrated Antenna Switch

Capable of transmitting and receiving GSM/GPRS/EDGE signals in GSM850/900/1800/1900MHz bands

Includes two separate GaAs dies for PA line-ups

One single CMOS die for the controller to control output power and RF switch

Single PHEMT die for the RF switch

Moto Q GSM System RF3178

RF6029

RF6029

Moto Q GSM System Antenna Truth Table

TX_EN B3 B2 B1 PA Module Mode VTx LB

VTx HB

VRx 850

VRx 900

VRx 1800

VRx 1900

0 0 0 0 Low power standby mode

0 0 0 0 0 0

0 1 0 0 RX850 0 0 1 0 0 0

0 X 0 1 RX900 0 0 0 1 0 0

0 X 1 0 RX1800 0 0 0 0 1 0

0 X 1 1 RX1900 0 0 0 0 0 1

1 0 0 X TX low band, low output

1 0 0 0 0 0

1 1 0 X TX low band, high output

1 0 0 0 0 0

1 0 1 X TX high band, low output

0 1 0 0 0 0

1 1 1 X TX high band, high output

0 1 0 0 0 0

Moto Q GSM System RF Interface

RX signals from antenna flow to RF6029 through RF switch inside RF3178. Signals are filtered, amplified, mixed, converted to IQ and digitized before sending to the Base Band IC.

The transmitter IQ is modulated directly into the TxVCO’s, buffered then sent to RF3178 for amplification.

Vramp used to control PA output power. Signal includes amplitude and timing of ramp up sequence, final power level, and ramping down of the TX burst. DAC values are programmed through SPI interface in the registers inside RF6029.

Vsense is used to monitor the current drain of the PA.

B1, B2 and B3 are used to control RF switch. The values of these signals are stored in register inside RF6029.

MS, MCLK, and MDI from Neptune to RF6029 are TX modulation sync, clock and TXQ/TXIB analog signals.

DRI, FSR and CLKR from RF6029 to Neptune are digital serial RX data interface frame sync or Q analog signal and digital serial RX data interface clock or IB analog signals.

OSCO from RF6029 to Neptune is a digital clock. It is used as system clock of the radio. Its frequency is dependent of OSCOM.

SPI from Neptune to RF6029 is used to program the RF6029.

TX_START, ENR, RX_ANT_EN are transmit start, digital serial RX data interface enable and receiver enable.

Moto Q GSM System Interface Block Diagram

Moto Q GSM System

Baseband Overview

Moto Q GSM System PCAP Power Distribution

(SW1) AP_CORE 1.2V ± 5%  This voltage varies between 1.0V to 1.35 depending on the AP processor State and clock rate. Source for Bulverde core.

(SW2) VBUCK, 1.875V ± 4% Source for Neptune Memory , Display IO, & Bulverde Memory.

V1 = AP_IO_REG, 2.775V ± 3% Sources PCAP Internal logic, EMU VCCIO, Camera, Display DC/DC, Keypad, Bluetooth IO,  EL Driver IO, Neptune and Bulverde I/O.

V2 =  V_AUDIO , 2.775V ± 3% Sources PCAP Internal Audio logic, Neptune audio clock.

V3 =  VAP_SRAM , 1.275V ± 3%  starts at 1.275V and then lowers to 1.05V. Sources Bulverde VCC_SRAM

V4 =  VRF_TXRX , 2.775V ± 3% Sources  PRIME Chipset.

V5 =  VRF_VCO , 2.775V ± 3% Source for PRIME Chipset.

V6 =  VCAM_AN , 2.775V ± 3% Source for Camera Analog

V7 =  VRF_LNA , 2.775V ± 3% Sources  PRIME  Chipset.

V8 =  VAP_PLL , 1.275V ± 3% Source for Bulverde VCC_PLL.

V9 =  VBB_REF , 1.575V ± 3% Source for Neptune  and PCAP RTC.

VAUX1 =  VBT_RF ,  1.875 V ± 5% Source for Bluetooth RF Base band.

VAUX2 =  VAP_MMC ,  1.8 and  3V ± 5% Source for Mini SD external flash memory and SDIO application cards.

VSIM = SIM_VCC 3.0V +- 5% Supplies SIM card power.

Moto Q GSM System PCAP Clock

32kHz clock used for power savings and RTC operations

Clock frequency generated from external 32.768 kHz crystal

PCAP also contains an internal RC oscillator that runs at 32.768 kHz nominal frequency

The RC oscillator will be used to run the debounce logic, PLL, and internal control logic.

The 32 kHz oscillator is powered at all times with valid voltage source is present at Battery, USB power, or coin cell battery for Real Time clock maintenance.

Moto Q GSM System PCAP Clock Generation

Moto Q GSM System PCAP TX Audio

Four Microphone paths supported

MICIN/MIC_OUT

AUX_MIC-/AUX_MIC+

AUX_OUT

EXT_MIC

Two headset microphone paths

EMU connector

Barrel connector (MIC2)

Microphone paths are selected through A3_MUX, A5_MUX, EXT_MIC_MUC, and MIC2_MUX

Microphone path gain is programmable by TX PGA and MIC2 PGA

Internal microphone is a single ended surface mount part biased by MICBIAS1

Moto Q GSM System PCAP TX Audio

Moto Q GSM System PCAP RX Audio

Six audio output paths supported

SPKR+/- amplifier (Handset Earpiece Speaker)

ALERT+/- amplifier (Handset Right Loudspeaker/Alert Speaker)

PGA_OUT_L amplifier (Handset Left Loudspeaker/Alert Speaker)

ARIGHT_OUT amplifier (Headset Right Speaker)

ALEFT_OUT amplifier (Headset Left Speaker)

EXT_OUT amplifier (not used)

Stereo DAC drives the internal Left/Right PGA

Voice DAC drives the internal Right PGA only

Internal multiplexers route audio to one of six supported outputs

Handset Speaker is driven by PCAP internal SPKR differential amplifier and external class D amplifier

Headset uses mini-USB connector and 2.5mm barrel connector.

Moto Q GSM System PCAP RX CODEC

Moto Q GSM System Audio Routing

Bulverde is primary source of audio except when in a voice call

Bulverde, Neptune, and Bluetooth send digital audio to PCAP through SAP interface

Control information between Bulverde and PCAP is sent through PCAP secondary SPI

PCAP has two Digital Audio Interfaces (DAI)

DAI0 is used for voice (mono) digital audio data

DAI1 is used for stereo digital audio data

Moto Q GSM System

Bulverde

SAP_CLK

SAP_FRM

SAP_RXD

SAP_TXD

Neptune-LTE2

SAP_TXD

SAP_RXD

SAP_FRM

SAP_CLK

Blue-ToothPCAP2

GPIO [88]

GPIO [38]

GPIO [37]

GPIO [50]

AP

_SP

I_CL

K AP

_SP

I_TX

D

AP

_SP

I_CS

AP

_SP

I_RX

D

GP

IO

[29]

GP

IO

[25]

GP

IO

[28]

GP

IO

[26]

AP

_AU

D_C

LK

AP

_AU

D_R

XD A

P_A

UD

_TX

D AP

_AU

D_F

RM

GP

IO

[52]

GP

IO

[81]

GP

IO

[83]

PR

I_CEP

RI_S

PI_C

LK

PR

I_MO

SI

PR

I_MISO

TXBIT

CLK

1 RX1 FS

YN

C1 R

X0

FS

YN

C0

BIT

CLK

0

SA

P_R

XDS

AP

_TX

DSA

P_F

RM

SA

P_C

LK

SS

P-

2

SSP-3SSP-1

STDA

SRDA

SC2A

SCKA

AS

AP

_RXA

SA

P_T

XAS

AP

_FSA

SA

P_C

LK

AP

_SP

I_FR

M

BTHeads

et

SA

P_C

LK

SA

P_F

RM

SA

P_T

XD

Audio Routing

Moto Q GSM System System Clock

26MHz Reference Clock

Derived from RF6029

OSCM used to shut down clock when phone is in Standby

Buffered to Neptune

Used by Neptune for MCU and DSP

32.768kHz RTC clock

Derived from RTC crystal

Buffered by PCAP to Bulverde, Neptune, and Bluetooth

Used by Neptune for low frequency peripheral interfaces

Used by Bulverde for low frequency peripheral interfaces

13Mhz Reference Clock

Derived from 13MHz crystal for Bulverde system clock and SPI interface to PCAP

Divided from 26MHz clock in Neptune for SPI interface to PCAP

Moto Q GSM System

26MHz

15.36MHz

System Clock

Moto Q GSM System Neptune LTE2

Neptune LTE2 IC derived from the Neptune LTE IC with these changes:

Increased MCU RAM size from 256Kbytes to 512Kbytes

Decreased MCU ROM size from 1.75Mbytes to 128Kbytes

The “interleaved” RAM blocks in LTE are replaced with dual-port RAM’s in order to simplify and improve the design

Parallel DMAC replaced with SLDCD smart LCD design to allow read back capability

Improved keypad interface (more columns, dual edge interrupts)

Addition of SIAC capability

Moto Q GSM System Neptune Block Diagram

Moto Q GSM System

•208MHz for the PXA270 processor•System memory interface•100MHz SDRAM•4MB to 256 MB of SDRAM memory•Support for 16, 64, 128, or 256Mbit DRAM technologies•4 Banks of SDRAM, each supporting 64 MB of memory•Clock enable (CKE) – provides 1 CKE pin to put the entire SDRAM interface into self refresh•Support up to 5 external static memory devices (SRAM, flash, or VLIO) and 1 internal flash device•PCMCIA/Compact Flash card control pins•LCD Controller pins•Full-function UART•Bluetooth UART•Hardware UART•MMC Controller pins•SSP pins•Network SSP•Audio SSP•USB Client pins•AC’97 Controller pins•Standard UART pins•I2C Controller pins•PWM pins•20 dedicated GPIOs pins•Integrated JTAG support•Single-Ended USB client

Bulverde Overview

Moto Q GSM System Bulverde Block Diagram

Moto Q GSM System Battery Interface

Main Battery interface consists of 4 pin connector

Power source

Thermal sense

Battery ID contact

Ground

In normal user mode, when charger is not attached, switch M3 turned is on to support B+ the main power source.

PCAP monitors the power switch and turns on the regulators for MCU and the other main circuitry

MCU interrogates the battery identification for validity during power up sequence

Moto Q GSM System Battery Interface

PCAP IC

A/D

POWER SW

BATT_THERMISTOR

CHARGE CURRENT

REGULATOR

REGULATOR

MCU

BATTERY ID

EMU IC I2C BUS

SPI BUS

USB/CHARGER CONNECTOR

Moto Q GSM System Charging System

When charger attached, EMU IC turns on M1 and M2 for charging

Charge current is regulated through 0.1 Ohm feed back via CHRGCTRL

MCU monitors battery temperature and charging current via A/D measurement from PCAP IC

If battery temperature is too high, MCU will send command via I2C bus to EMU IC to turn off charging

MCU calculates the maximum charge current allowed for the circuits before charging starts

Low rated chargers

When the MCU detects a lower rated charger or during transmit or receive of a “call” operation, the current shared mode will be selected.

In this mode, switch M1, M2, M3 will be on and M4 will be off so that maximum power can be generated to B+, the power source of the radio.

High rated chargers

When radio is in low power mode or “off” state, dual-path charge mode is selected

In dual-path charge mode, M1, M2, and M4 will be on but M3 will be off so that the battery can be charged efficiently

USB cable charging

MCU negotiates charging current with host PC

Maximum charging current is 500mA

Will operate in low battery condition

Initial charging current is under 100mA until the radio powers up

Moto Q GSM System Charger Block Diagram

Moto Q GSM System AP Memory Interface

64M-bytes SDRAM

128M-bytes NAND flash

Data

Address

Address

Data

•64M-bytes SDRAM running at 104MHz•128M-bytes of NAND Flash memory•NOR Interface to communicate with Bulverde•Program and user memory stored in Flash•Program and data stored in Flash are copied in RAM for execution•Sub-divided Flash for boot code, OS files, and user data

Moto Q GSM System BP Memory Interface

16-bit parallel data bus used to access 32Mbit Flash and 8Mbit SRAM

Each device is assigned a specific chip enable

Neptune chip select control register defines wait states for each device

Each wait state is the equivalent of one clock cycle, i.e. 1 / 13MHz = 77 ns.

Memory is a stack-memory by which both Flash and (P)SRAM are embedded into one single 8.0mm by 10mm Stacked-MSP (Chip Scale Package)

Moto Q GSM System Neptune Memory Interface

BURSTCLK

Neptune-LTE

FLASH (4MB)

SRAM (2MB)

ECB

CS0

LBA

R_W

OE

CLK

WAI T

CE ADV

OE WE

R_OE R_WE

EB1

EB0 R_LB R_UB

Data Bus (D [15:0]) D [15:0]

Add. Bus (A [23:0]) A [23:1]

D [15:0]

D [15:0]

A [21:0]

A [19:0]

CS1 R_CS

Moto Q GSM System Display

Color Active Matrix Liquid Crystal Display (AMLCD) module of glass construction with black pixels on white background

240 (x RGB Stripe) x 320 pixels with 262K colors.

This display module is constructed of:

Has a top glass plate, top and bottom polarizers and compensation films, color filter, liquid crystal, internal transflector, a poly-Si backplane containing the pixel transistors, and row and column driving circuitry integrated onto glass

Auxiliary Backlighting System consists of white LEDs, light guide, and LED driving circuitry

FPC with LCD controller and other necessary passive components.

Moto Q GSM System Display Interface

Moto Q GSM System Display Interface

Moto Q GSM System Keypad

46 key QWERTY keypad

Keypad interfaces to Bulverde

Bulverde uses 121 highly-multiplexed general-purpose I/O (GPIO) pins for capturing key entries

Moto Q GSM System Keypad Interface

Bulverde

Qwerty keypad

GPIO interface

GPIO 103

KP_MKOUT[0] GPIO 104

KP_MKOUT[1] GPIO 105

KP_MKOUT[2] GPIO 106

KP_MKOUT[3] GPIO 107

KP_MKOUT[4] GPIO 108

KP_MKOUT[5]

GPIO 96 KP_MKOUT[6

] GPIO 22

KP_MKOUT[7]

GPIO 100 KP_MKIN[0]

A ;

Y )

D 5

W 1

G /

J $

L @

GPIO 101 KP_MKIN[1]

U -

B #

CAPS SYM

P :

EMAIL LIGHT

HOT KEY 2 (SPKRPHN) ENTER

GPIO 102 KP_MKIN[2]

F 6

O &

X 7 JOG DIAL ALT

R 3

GPIO 97 KP_MKIN[3]

T (

E 2 CAMERA

I + BACK_1

N !

? 0

GPIO 98 KP_MKIN[4]

H \ BACK_2

C 8 LSK RSK

. '

Q "

GPIO 99 KP_MKIN[5]

K = NAV DOWN

M , NAV RIGHT NAV OK

V 9 NAV LEFT NAV UP

GPIO 95 KP_MKIN[6]

S 4 SPACE HOME SEND

Z *

GPIO 13 KP_MKIN[7]

Moto Q GSM System SIM Interface

PCAP supports 1.875 V or 3.0 SIMs

VSIM regulator controlled by VSIM_EN

Supply to card must be shut down before the SIM card is removed and the card loses contact with the radio

SIM module contains a block designed to generate clocks SIM module and SIM card

SIM TX block contains a transmit state machine, transmit shift register, and a transmit FIFO

SIM RX block contains a receive state machine, receive FIFO, and control logic.

On power up, the phone checks valid battery voltage and verify SIM card is present by reading data on SIM_I/O

No data indicates card not present

SIMPD input allows for detection of the insertion or removal of a SIM card

Moto Q GSM System SIM Interface

Baseband Processor

Power Management

VCC

SIM CARD

GND

VCC

RST

DI/O

CLK

SIM_VCC

SIM_PD

SIM_CLKSIM_RST

SIM_DIO

BATT_DET

FIGURE 12.1

Moto Q GSM System Bluetooth

UART 4-wire interface (Tx,Rx,RTS,CTS)

Adjustable baud rates from 9600 bps to 1.5Mbps.

Baud rate set by parameters stored in the optional EEPROM or by auto baud rate detection

AP Handshake Bluetooth communicates with AP through GPIO

AP wakes up Bluetooth module using BT_WAKE signal

Bluetooth module wakes up AP using BT_HOST_WAKE signal

Bluetooth module is reset by AP using BT_RESET

Audio PCM port of the Bluetooth is connected to the SAP port of the Neptune

Bluetooth audio is also connected with SSP2 port of Intel Bulverde

Power Supply PCAP powers Bluetooth module and voltage I/O lines

BT_RF regulator powers Bluetooth core and RF section

2.8 V I/O voltage used to power I/O signals

Clock System clock derived from external 15.36 crystal

32 KHz sleep clock from PCAP used during the sleep mode and auto baud rate generation

Moto Q GSM System Bluetooth Block Diagram

BT2035

Intel Bulverde

UA

RT

Tx,R

x,C

TS,R

TS

Neptune

BT_R

ES

ET

BT_W

AK

E

BT_

HO

ST_

WA

KE

PCAPB

T_R

F 1.

875V

I/O 2

.8V

15.36 MHzCrystal

SS

P2

MO

NO

SA

P

PC

M

32K

Hz

CLK