mosfet limitations jfets...1 mosfet limitations 1. technology limitations: the gate control over...
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MOSFET limitations
1. Technology limitations:
The gate control over channel conductance in MOSFETs can only be achieved if the dielectric – semiconductor interface is nearly perfect.
So far, only Si – SiO2 structure, which can be obtained by Si oxidation, meets these requirements.
SiO2 has low dielectric permittivity (3.9) this limits the transconductance or requires very thin dielectric films – hence gate leakage, defects etc.
Other dielectrics are being intensively explored, like HfO2 (ε > 20). INTEL has plans to commercialize MOSFETs using HFO2 as the gate dielectric.
MOSFET cannot have very low G-S and G-D capacitances because the gate MUST OVERLAP the source and drain contacts.
n nn
DSG
2
2. Mobility limitations
n nn
DSVds
■ We assumed constant mobility (μn) in the I-V characteristic expression.
In fact, mobility depends on the gate and drain voltages.
Scattering from the interface charges
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Junction Field-effect Transistor
The gate voltage controls the channel conductance by modulating the width of the depletion region at the p-n junction.The p-region doping is MUCH higher than in the n-region. The depletion region expands mostly into the n-channel. (For the p-channel JFET, the n-type layer will be doped higher than the p-channel)
h
4
Pinch-Off Voltage
2
21)( W
NNNNqVV
da
daGbi +
=−ε
2da 2
1)( ,N NFor WNqVV dGbi ε=−>>
Conductive channel thickness h = a - W If h = 0, the channel is not conductive at ANY DRAIN VOLTAGE
Depletion region width W:
h
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Pinch-Off Voltage
The voltage drop across the p-n junction, which COMPLETELY depletes the channel is called the PINCH-OFF VOLTAGE, Vpo. For h = 0, the depletion region width, W must be W = a, hence
2
21 aNqV dpo ε
=
h
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Threshold Voltage
If the EXTERNAL voltage applied to the gate is VG, then the pinch-off condition is:
Vbi - VG = Vpo
The THRESHOLD VOLTAGE is the external voltage applied to the gate, which causes the channel pinch-off:
Vth = Vbi – Vpo
The threshold voltage for the n-channel JFET is negative if Vbi < Vpo
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1. A Si-JFET channel is 0.2 μm thick; the doping level is 3×1017 cm-3; the channel is n-type.Find the pinch-off voltage of the channel.
a = 0.2 μm = 0.2×10-4 cm;Nd = 3×1017 cm-3;ε = 11.8;ε0 = 8.85×10-14 F/cm
221 aNqV dpo ε
=
EXAMPLES
Vpo = 9.19 V;
What would be the value of Vpo if the doping level decreases 2 times?
What would be the value of Vpo if instead, the channel thickness decreases 2 times?
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EXAMPLES
2. What is the threshold voltage of the JFET with Vpo = 9.19 V ? Assume Vbi ≈ 1 V
Vbi - VG = Vpo; VG = Vbi - Vpo = 1 V - 9.19 V = - 8.19 V;
3. What is the drain voltage for current saturation at VG = - 2 V ?
Vpo = Vbi - VG + VD; VD = Vpo - Vbi + VG = 9.19 V - 1 V + (-2 V) = 6. 19 V;
What is the drain voltage for current saturation at VG = - 4 V ?
VD = Vpo - Vbi + VG = 9.19 V - 1 V + (-4 V) = 4. 19 V;
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MEtal Semiconductor Field Effect Transistor (MESFET)
pn nn
DSG
DS G
n
• Gate control through a MOS barrier• The device in normally-off and current only flows when the gate bias inverts the channel• Both p-channel and n-channel MOSFETsare possible giving rise to CMOS• Main use: Integrated circuits, microwave operation is not yet possible
• Gate control through a Schottky barrier• The device in normally-on and negative gaebias is needed to cut the current off (in case of the n-channel MESFET)• Typically n-channel MESFETs are feasible• Main use: Microwave devices, integration not as high as the CMOS devices
MOSFET MESFET
Semi-insulating material
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MESFET models (also apply to JFETs)
• Drain saturation current
Isat = β(VGS − VT )2
where the transconductance parameter ( )2
3s n s
n po s
v Wa V v L
ε μβ
μ=
+
The threshold voltage VT = Vbi − Vpo
The pinch off voltage2
2d
pos
qN aV
ε= where a is the channel thickness
1. Square law Model: fairly accurate for devices with relatively low pinch-off voltages (Vpo = Vbi – VT ≤ 1.5 ~ 2 V)
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2. Raytheon model: For devices with higher pinch-off voltages,
• Drain saturation current
Isat =β VGS − VT( )2
1 + tc VGS − VT( )
tc is an empirical parameter that depends on the doping profile in the MESFET channel.
Incorporating the source and drain resistances VGS = Vgs − Ids Rs
Isat =2βVgt
2
1 + 2βVgt Rs + 1 + 4βVgt Rs
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100200
300400500
-1.5 -1 -0.5 0 0.5 1 -1.5 -1 -0.5 0 0.5 1
100200
300
400500
Gat e Volt age (V) Gat e Volt age (V)
Si MOSFET GaAs MESFET
0 0
Tran
scon
duct
ance
(ms/
mm
)
Sat
urat
ion
curre
nt (m
A/m
m)
Device saturation current, Isat, and device transconductance, gm = dIsat/dVgs, for a Si MOSFET and a GaAs MESFET. Gate length L = 0.5 mm for both devices.
MOSFET vs. MESFET
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MOSFET vs. MESFET
In MESFETs, owing to a very simple fabrication technology(i) the S-G and G-D spacings can be made very small,
Hence the parasitic resistance Rs and Rd are low.(ii) the gate length can be very small (well below 1 μm)
Hence high peak gm and high cut-off frequencies.
DSG
n
Semi-insulating material
Electron mobility, μn, cm2/V-s: Si GaAs1000 6000
Most of MESFETs are made using GaAs
MESFET cut-off frequencies exceed 10 GHz; MOSFETs typically have fT < 1 GHz
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Heterostructure Field-Effect Transistor (HFET)
(1) Saturation current in the velocity saturation model (applicable to short-gate devices)
Isat =gchVGT
1 + 1 +VGTVL
⎛
⎝ ⎜
⎞
⎠ ⎟
2
where VL = FsL and the channel conductance gch = q µn ns W / L
Common issues for any MOSFET – MESFET – JFET:
Achieving high channel currents (per unit device width W) requireshigh electron concentration in the channelandhigh electron drift velocity
For short-channel devices, i.e. VL << VGT, Isat becomes:
( / ) ( )sat ch L n s s s sI g V q n W L F L qn v Wμ= × = × =
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Electron Drift velocity
electric field (kV/cm)
elec
tron
vel
ocity
(100
,000
m/s
)
T = 300 K
Si
GaAs
InP
InGaAs3
2
1
00 5 10 15 20
In the heavily doped materials the peak electron velocity is lower
Heavily doped
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Heterostructure Field-Effect Transistor (HFET)
(2) Parasitic source and drain resistances:
Common issues for any MOSFET – MESFET – JFET:
Achieving high transconductance (per unit device width W) requireslow source and drain access (parasitic) resistances, which in turn requireshigh electron concentration in the channel andhigh electron mobility
gd =gdo
1 + gmo Rs + gdo Rs + Rd( )
RS = (1/qnsμn) LSG/W RD = (1/qnsμn) LGD/W
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Concentration dependence of electron mobility
T = 300 K
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after T.A. Fjeldly, T. Ytterdal and M. Shur, 1998
Undoped active layer
Very high NS; very high μ; very high vS (in sub-μ HFETs)
1960 - Accumulation layer prediction (Anderson)1969 - Enhanced mobility of 2DEG prediction (Esaki & Tsu)
1978 Enhanced mobility observed (Dingle et. al.)
1980 The first Heterojunction FET (HFET)1991 The first GaN based HFET (A. Khan)
electrons
Heterostructure Field-Effect Transistor (HFET)a.k.a High-Electron Mobility Transistor (HEMT)
The channel of HFETs is formed by 2D electron gas (2DEG)
induced channel (2DEG)
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The HFET threshold voltage
qVNqVN
At the threshold, ns is close to zero, hence the Fermi level in the GaAs is close to the bottom of the conductance band. Therefore,
VT ≈ φb −qNd di
2
2εi− ΔEc / q
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The HFET modelAbove the threshold the HFET is similar to MOSFET.
HFET channel concentration at low drain voltages:
where VGT = VG – VT;i
ii
cdε
=
ci, εi and di are the capacitance per unit area, the dielectric permittivity (total) and the thickness of the wide bandgap barrier, i.e. AlGaAs in AlGaAs/GaAs HFET
LG
Substrate
LGDLGS
DrainSourceBarrier
Buffer
(Ti/Al/Ti/Au) (Ti/Al/Ti/Au)
Ni/Au
di2D electron gas
s i GTqn c V=
MOSFETs and HFETsI-V characteristics approximations
Drain saturation voltage:
Drain saturation current:
where VL = FsL;
the channel conductance gch = q µn ns W / L - more suitable for HFETsand ns = (ci/q) VGT and gch= β×VGT more suitable for MOSFETs
β = Wμnci /L is the transconductance parameter.
21 1GT
SAT GT LL
VV V V
V
⎡ ⎤⎛ ⎞⎢ ⎥= − + −⎜ ⎟⎢ ⎥⎝ ⎠⎢ ⎥⎣ ⎦
21 1
ch GTSAT
GT
L
g VI
VV
=⎛ ⎞
+ +⎜ ⎟⎝ ⎠
22
Complete velocity saturation mode in HFETs(very short gate HFETs)
VSAT = VGT − VL 1+ VGT / VL( )2 − 1⎡
⎣ ⎢ ⎤ ⎦ ⎥
where VL = Fs L.HFET saturation current in complete velocity saturation regime (VL << VGT)
VSAT ≈ VL
Isat ≈ βVLVGT
where β = Wμnci /L is the transconductance parameter.
22 1 1GT
SAT LL
VI V Vβ⎧ ⎫⎡ ⎤⎪ ⎪⎛ ⎞= + −⎢ ⎥⎜ ⎟⎨ ⎬⎝ ⎠⎢ ⎥⎪ ⎪⎣ ⎦⎩ ⎭
for VD > VSAT:
For VL << VGT
HFET drain saturation voltage in complete velocity saturation regime (VL << VGT)
For VL << VGT
MOSFETs and HFETsI-V characteristics approximation accounting for parasitic
resistances Rs and Rd
Drain voltage:
Drain saturation current:( )2
1 1 2
ch gtsat
ch s ch s gt L
g VI
g R g R V V/=
+ + + +
ds DS d s dV V I R R( )= + +
LG
Substrate
LGDLGS
DrainSourceBarrier
Intrinsic HFET
(Ti/Al/Ti/Au) (Ti/Al/Ti/Au)
Ni/Au
RS RD
RS = Rc + Rsh LGS / W
RD = Rc + Rsh LGD / W
Rsh =1/(q ns μ)
MOSFET and HFET cutoff frequencies fT
( ) 22m s
Tgs gd
g vf
LC C ππ= ≈
+Current cutoff frequency:
fT =gm
2π Cgs + Cgd + Cp( )
2T T
maxg gdT
f ffR Cf πτ
≈ =Maximum oscillation frequency:
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State-of-the-art GaAs-based HFETs
1 μm
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State-of-the-art HFET performance