MOSFETMetal Oxide Semiconductor Field Effect Transistor

Device Structure

The transistor is fabricated on a p-type substrate, which is a single-crystal silicon wafer that provides physical support for the device. Two heavily doped n-type regions, indicated in the figure as the n+ source and the n+ drain regions, are created in the substrate. A thin layer of silicon dioxide (Si02) of thickness tox (typically 2-50nm)2, is grown on the surface of the substrate, covering the area between the source and drain regions. Metal is deposited on top of the oxide layer to form the gate electrode of the device. Metal contacts are also made to the source region, the drain region, and the substrate, also known as the body.3 Thus four terminals are brought out: the gate terminal (G), the source terminal (S), the drain terminal (D), and the substrate or body terminal (B).Another name for the MOSFET is the insulated-gate FET or IGFET. This name emphasizes the fact that the gate electrode is electrically insulated from the device body (by the oxide layer). It is this insulation that causes the current in the gate terminal to be extremely small (of the order of (10 -15

A).

Device Operation

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The source and the drain have been grounded and a positive voltage is applied to the gate. Since the source is grounded, the gate voltage appears in effect between gate and source and thus is denoted vGS. The positive voltage on the gate causes the free holes to be repelled from the region of the substrate under the gate (the channel region). These holes are pushed downward into the substrate, leaving behind a carrier-depletion region. The depletion region is populated by the bound negative charge associated with the acceptor atoms. These charges are "uncovered" because the neutralizing holes have been pushed downward into the substrate.The positive gate voltage attracts electrons from the n+ source and drain regions into the channel region. When a sufficient number of electrons accumulate near the surface of the substrate under the gate, an n region is in effect created, connecting the source and drain regions. Now if a voltage is applied between drain and source, current flows through this induced n region, carried by the mobile electrons. The induced n region thus forms a channel for current flow from drain to source. The MOSFET of the above figure is called an n-channel MOSFET or an NMOS transistor. The n-channel MOSFET is formed in a p-type substrate: The channel is created by inverting the substrate surface from p type to n type. Hence the induced channel is also called an inversion layer.The value of vGS at which a sufficient number of mobile electrons accumulate in the channel region to form a conducting channel is called the threshold voltage and is denoted Vt.

Now applying a positive voltage vDS between drain and source. The voltage vDS causes a current iD to flow through the induced n channel. Current is carried by free electrons traveling from source to drain. By convention, the direction of current flow is opposite to that of the flow of negative charge. Thus the current in the channel, iD, will be from drain to source, as indicated in the above figure. The magnitude of iD depends on the density of electrons in the channel, which in turn depends on the magnitude of vGS . Specifically, for vGS = Vt the channel is just induced and the current conducted is still negligibly small. As vGS exceeds Vt more electrons are attracted into the channel. The result is a channel of increased conductance or, equivalently, reduced resistance. The conductance of the channel is proportional to the excess gate voltage

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(vGS - Vt), also known as the effective voltage or the overdrive voltage. It follows that the current iD will be proportional to vGS - Vt and to the voltage vDS that causes iD to flow.

iD versus vDS for various values of vGS. MOSFET is operating as a linear resistance whose value is controlled by vGs. The resistance is infinite for vGS <Vt and its value decreases as vGS exceeds Vt

Operation as vDS Is Increasedlet vGS be held constant at a value greater than Vt and vDS appears as a voltage drop across the length of the channel. That is, as we travel along the channel from source to drain, the voltage increases from 0 to vDS. Thus the voltage between the gate and points along the channel decreases from vGS at the source end to vGS - vDS at the drain end. Since the channel depth depends on this voltage the channel is now no longer of uniform depth; rather, the channel will take the tapered form, being deepest at the source end and shallowest at the drain end. As vDS

is increased, the channel becomes more tapered and its resistance increases correspondingly. Thus the iD-vDS curve does not continue as a straight line but bends as shown below. Eventually, when vDS is increased to the value that reduces the voltage between gate and channel at the drain end to Vt that is, vGD = Vt or vGS - vDS = Vt t or vDS = vGS - Vt the channel depth at the drain end decreases to almost zero, and the channel is said to be pinched off. Increasing vDS beyond this value has little effect (theoretically, no effect) on the channel shape, and the current through the channel remains constant at the value reached for vDS - vGS - Vt .The drain current thus saturates at this value, and the MOSFET is said to have entered the saturation region of operation. The voltage vDS at which saturation occurs is denoted vDSsat

VDSsat = VGS - Vt

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The region of the iD-vDS characteristic obtained for vDS < vDSsat is called the triode region

iD - vDS Relationship

Where k'n is the process transconductance parameter

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The drain current is proportional to the ratio of the channel width W to the channel length L, known as the aspect ratio of the MOSFET

Resistor Loaded NMOS InverterThe input to the inverter is at the gate of the N-channel output transistor NO and VIN = VGS. The output is at the drain and VOUT = VDS = VDD – IRL RL. For VIN < Vt, transistor is in cut off mode and does not conduct drain current. Since the ID(OFF) = 0 and the output is VOUT = VDD. As the input is increased slightly above the threshold voltage transistor begins to conduct. At this point only a small current flows and the drain voltage is lightly less than VDD. As long as VDS >= VGS – Vt, transistor is operating in the saturation region. With further increase of the input, a larger drain current conducts and the output voltage continues to fall. In summary, for a low input the output is high. Conversely for a high input the output is low.

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CMOS

A very effective logic circuit can be established by constructing a p-channel and an n-channel MOSFET on the same substrate as shown in the above figure. Note the induced p-channel on the left and the induced n-channel on the right for the p- and n-channel devices, respectively. The configuration is referred to as a complementary MOSFET arrangement (CMOS) that has extensive applications in computer logic design.

CMOS InverterOne very effective use of the complementary arrangement is as an inverter, as shown in figure. As introduced for switching transistors, an inverter is a logic element that “inverts” the applied signal. That is, if the logic levels of operation are 0 V (0-state) and 5 V (1-state), an input level of 0 V will result in an output level of 5 V, and vice versa. As shown in fig. below both gates are connected to the applied signal and both drain to the output Vo. The source of the p-channel MOSFET (Q2) is connected directly to the applied voltage VSS, while the source of the n-channel MOSFET (Q1) is connected to ground. For the logic levels defined above, the application of 5 V at the input should result in approximately 0 V at the output. With 5 V at Vi (with respect to ground), VGS1 =Vi and Q1 is “on,” resulting in a relatively low resistance between drain and source as shown in Fig. below. Since Vi and VSS are at 5 V, VGS2 =0 V, which is less than the required Vt for the device, resulting in an “off” state. The resulting resistance level between drain and source is quite high for Q2. A simple application of the voltage-divider rule will reveal that Vo is very close to 0 V or the 0-state, establishing the desired inversion process. For an applied voltage Vi of 0 V (0-state), VGS1 =0 V and Q1 will be off with VSS2 = -5 V, turning on the p-channel MOSFET. The result is that Q2 will present a small resistance level, Q1 a high resistance, and Vo =VSS = 5 V (the 1-state). Since the drain current that flows for either case is limited by the “off” transistor to the leakage value, the power dissipated by the device in either state is very low.

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The DC Bias Point

The dc bias current ID can be found by setting the signal vgs to zero; thus

Where we have neglected channel-length modulation (i.e., we have assumed X = 0). The dc voltage at the drain, VDS or simply VD (since S is grounded), will be

To ensure saturation-region operation, we must have

Furthermore, since the total voltage at the drain will have a signal component superimposed on VD, VD has to be sufficiently greater than (VGS - Vt) to allow for the required signal swing.

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The Signal Current in the Drain TerminalConsider the situation with the input signal vgs applied. The total instantaneous gate-to source voltage will be

resulting in a total instantaneous drain current iD

The first term on the right-hand side of Eq. can be recognized as the dc bias current ID. The second term represents a current component that is directly proportional to the input signal vgs. The third term is a current component that is proportional to the square of the input signal. This last component is undesirable because it represents nonlinear distortion.To reduce the nonlinear distortion introduced by the MOSFET, the input signal should be kept small so that

resulting in

or, equivalently,

Where Vov is the overdrive voltage at which the transistor is operating.If this small-signal condition is satisfied, then

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The parameter that relates id and vgs is the MOSFET transconductance gm

or in terms of the overdrive voltage Vov

The Voltage Gain

The total instantaneous drain voltage vD

Under the small-signal condition, we have

which can be rewritten as

Thus the signal component of the drain voltage is

which indicates that the voltage gain is given by

The minus sign indicates that the output signal vd is 180° out of phase with respect to the input signal vgs.Small Signal FET Amplifier Operation

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From a signal point of view the FET behaves as a voltage-controlled current source. It accepts a signal vgs between gate and source and provides a current gmvgs at the drain terminal. The input resistance of this controlled source is very high—ideally, infinite. The output resistance—that is, the resistance looking into the drain—also is high, and we have assumed it to be infinite. Putting all of this together, we arrive at the circuit in Fig. below

This represents the small-signal operation of the MOSFET and is thus a small-signal model or a small-signal equivalent circuit.In the analysis of a MOSFET amplifier circuit, the transistor can be replaced by the equivalent circuit model shown in Fig. The rest of the circuit remains unchanged except that ideal constant dc voltage sources are replaced by short circuits. This is a result of the fact that the voltage across an ideal constant dc voltage source does not change, and thus there will always be a zero voltage signal across a constant dc voltage source. A dual statement applies for constant dc current sources; namely, the signal current of an ideal constant dc current source will always be zero, and thus an ideal constant dc current source can be replaced by an open-circuit in the small-signal equivalent circuit of the amplifier. The circuit resulting can then be used to perform any required signal analysis, such as calculating voltage gain.The most serious shortcoming of the small-signal model of Fig. above is that it assumes the drain current in saturation is independent of the drain voltage. But we know that the drain current does in fact depend on vDS in a linear manner. Such dependence was modeled by a finite resistance r0 between drain and source, whose value was given by

Where VA = 1/λ is a MOSFET parameter that either is specified or can be measured and ID is

Typically, r0 is in the range of 10 kΩ to 1000 kΩ. It follows that the accuracy of the small signal model can be improved by including ro in parallel with the controlled source.It is important to note that the small-signal model parameters gm and r0 depend on the dc bias point of the MOSFET.We find that replacing the MOSFET with the small-signal model of Fig. below results in the voltage-gain expression

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The Transconductance gm

This relationship indicates that gm is proportional to the process transconductance parameter

and to the W/L ratio of the MOS transistor; hence to obtain relatively large transconductance the device must be short and wide. We also observe that for a given device

the transconductance is proportional to the overdrive voltage, Vov = VGS - Vt the amount by which the bias voltage VGS exceeds the threshold voltage Vt. Note, however, that increasing gm

by biasing the device at a larger VGS has the disadvantage of reducing the allowable voltage signal swing at the drain.Another useful expression for gm can be obtained by substituting for (VGS - Vt) by

Another useful expression for gm of the MOSFET can be obtained by substituting for

by

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Frequency Response

Low-Frequency Response — FET AmplifierThere are three capacitors of primary concern as appearing in the network of Fig. below CG, CC, and CS.

(a) Capacitive elements that affect the low-frequency response of a FET amplifier

CG

For the coupling capacitor between the source and the active device, the ac equivalent network will appear as shown in Fig. (b). The cutoff frequency determined by CG will then be

For the network of Fig. a

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(b) Determining the effect of CG on the low-frequency response.

Typically, RG >>Rsig and the lower cutoff frequency will be determined primarily by RG and CG. The fact that RG is so large permits a relatively low level of CG while maintaining a low cutoff frequency level for fLG

CC

For the coupling capacitor between the active device and the load the network of Fig. (c) will result. The resulting cutoff frequency is

For the network of Fig (a)

(c) Determining the effect of CC on the low-frequency response.

CS

For the source capacitor CS, the resistance level of importance is defined by Fig. (d). The cutoff frequency will be defined by

For fig.(a), the resulting value of Req

Which for rd ≈ ∞ Ω becomes

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(d) Determining the effect of CS on the low-frequency response

High-Frequency Response —FET AmplifierAs shown in Fig.(a), there are interelectrode and wiring capacitances that will determine the high-frequency characteristics of the amplifier. The capacitors Cgs and Cgd typically vary from 1 to 10 pF, while the capacitance Cds is usually quite a bit smaller, ranging from 0.1 to 1 pF.

At high frequencies, Ci will approach a short-circuit equivalent and Vgs will drop in value and reduce the overall gain. At frequencies where Co approaches its short circuit equivalent, the parallel output voltage Vo will drop in magnitude. The cutoff frequencies defined by the input and output circuits can be obtained by first finding the Thévenin equivalent circuits for each section as shown in Fig.

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(b)The Thévenin equivalent circuit (c) Thevenin equivalent circuit for the for the input circuit output circuit

For the input circuit

and

with

and

and for the output circuit,

with

and

and

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