module 2 instruction set

MODULE 2 MCA-203 MICROPROCESSORS AND EMBEDDED SYSTEM ADMN 2014-‘17

Dept. of Computer Science And Applications, SJCET, Palai 9

2.1 INTRODUCTION

Instruction: - An instruction is a binary pattern designed inside a microprocessor to perform a

specific function.

8086 instruction size varies from one to six bytes

Fig 1. 8086 General Machine language instruction format of 8086

Byte 1 information:

• Opcode field (6-bits)—specifies the operation to be performed by the instruction

• D (1-bit)—register direction: tells whether the register which is selected by the REG field in the

second byte is the source or destination

D = 0 source operand

D= 1 destination operand

• W (1-bit)—data size word/byte for all registers

Byte = 0

Word =1

Byte 2 information:

• MOD (2-bit mode field)—specifies the type of the second operand

Memory mode: 00, 01,10—Register to memory move operation

Register mode: 11—register to register move operation

• REG (3-bit register field)—selects the register for a first operand, which may be the source or

destination


Dept. of Computer Science And Applications, SJCET, Palai 0

• R/M (3-bit register/memory field)—specifies the second operand as a register or a storage location

in memory

2.2 INSTRUCTION FORMATS

In 8086 six types of instruction formats.

1. 1-Byte instruction

2. Register to register

3. Register to/from memory with no displacement

4. Register to/from memory with displacement

5. Immediate operand to register

6. Immediate operand to memory with 16-Bit displacement.

1. 1-Byte instruction

The instruction is 1-byte long in size.

It May contain implied data or register operands (data).

The least significant 3 bits of the opcode are used for specifying the register operand, if any.

Otherwise all the 8 bits form an opcode


Dept. of Computer Science And Applications, SJCET, Palai Page 21

2. Register to Register


First byte of code denotes opcode, direction & width of operand.

Second byte denotes register operands & R/M field.

REG field denotes type of register used.

R/M field denotes register or memory location used.

The register specified by REG is a source operand if D = 0 , else it is a destination operand.

10001000 11 000 001

REG =000 indicates Register AL

R/M =001 indicates Register CL

3. Register to/from memory with no Displacement


First byte of code denotes opcode & width of operand.

Second byte denotes mod, register operands & R/M field.

MOD field denotes type of addressing mode used.

The instruction 10001011 00 000 111 indicates the operation MOV AX, [BX]

4. Register to/from memory with Displacement


First byte of code denotes opcode.

Second byte denotes register mod, register operands & R/M field.

Third byte denotes lower byte of displacement.



fourth byte denotes higher byte of displacement

5. Immediate operand to register


The first byte as well as the 3 bits from the second byte which are used for REG field in case of

register to register format is used for opcode.

Second byte denotes opcode, R/M field.

Third byte denotes lower byte of data.

Fourth byte denotes higher byte of data.

6. Immediate operand to memory with 16-bit displacement

The instruction is 5 or 6-byte long in size.

First byte of code denotes opcode.

Second byte denotes register mod, opcode & R/M field.

Third byte and fourth byte denotes lower byte and higher byte of displacement.

2.3 INSTRUCTION SET OF 8086

The entire group of instructions that a microprocessor supports is called Instruction Set.

Classification

1. Data Transfer instructions.

2. Arithmetic & Logical instructions.

3. Branch instructions.

4. Loop instructions.

5. Machine Control instructions.

6. Flag Manipulation instructions.

7. Shift & Rotate instructions.

8. String instructions.

1. Data Transfer Instructions

These instructions are used to transfer data from source to destination.

The operand can be a constant, memory location, register or I/O port address.



i. MOV Destination, Source;

Source can be register, memory location, immediate data and port address.

Destination can be register or memory location.

Both Source and Destination cannot be memory location or segment registers at the same time.

They must both be of the same type (bytes or words).

Does not affect any flag.

Examples

MOV CX, 037AH Put immediate number 037AH to CX

MOV AX, BX Copy content of register BX to AX

MOV DL, [BX] Copy byte from memory at [BX] to DL

MOV DS, BX Copy word from BX to DS register

ii. Push Source;

Source can be register, segment register or memory.

This instruction pushes the contents of specified source on to the stack.

In this stack pointer is decremented by 2.

The higher byte data is pushed first.

Then lower byte data is pushed.

iii. POP Destination;

Destination can be register, segment register or memory.

This instruction pops (takes) the contents of stack to the specified destination.

In this stack pointer is incremented by 2.

The lower byte data is popped first.

Then higher byte data is popped.

E.g.

POP AX;

POP DS;

POP [5000H];



iv. XCHG Destination, source;

This instruction exchanges contents of Source with destination.

It cannot exchange two memory locations directly.

The source and destination are of equal types.

E.g.

XCHG BX, AX;

XCHG [5000H], AX;

v. IN AL/AX, 8-bit/16-bit port address

It reads from the specified port address.

It copies data to accumulator from a port with 8-bit or 16-bit address.

DX is the only register is allowed to carry port address.

E.g.

IN AL, 80H;

IN AX, DX; //DX contains address of 16-bit port.

vi. OUT 8-bit/16-bit port address, AL/AX;

It writes to the specified port address.

It copies contents of accumulator to the port with 8-bit or 16-bit address.

DX is the only register is allowed to carry port address.

E.g.

OUT 80H, AL;

OUT DX, AX; //DX contains address of 16-bit port.

vii. LEA 16-bit register, address



LEA also known as Load Effective Address (LEA).

It loads a 16-bit register with the offset address of the data specified by the Src.


E.g.

LEA BX, [DI]: This instruction loads the contents of DI (offset) into the BX register.

viii. LDS 16-bit register, address

LDS Also known as Load Data Segment (LDS).

Loads new values into the specified register and into the DS register from four successive memory

locations.

The word from two memory locations is copied into the specified register and the word from the

next two memory locations is copied into the DS registers.

LDS does not affect any flag.

Ex: LDS BX,5000H;

ix. LES 16-bit register, address

LES Also known as Load Extra Segment (LES).

This instruction loads new values into the specified register and into the ES register from four

successive memory locations.

The word from the first two memory locations is copied into the specified register, and the word

from the next two memory locations is copied into the ES register.

LES does not affect any flag.

Ex

LES BX, 5000H;

x. LAHF

This instruction loads the AH register from the contents of lower byte of the flag register.

This command is used to observe the status of the all conditional flags (except over flow) of flag

register.

E.g. LAHF;

xi. SAHF

This instruction sets or resets all conditional flags (except over flow) of flag register with respect to

the corresponding bit positions.

If bit position in AH is 1 then related flag is set otherwise flag will be reset.



E.g. SAHF;

xii. PUSH F

It copies contents of flag register to the stack

This instruction decrements the stack pointer by 2.

E.g. PUSH F

xiii. POP F

It copies contents of memory location pointed by stack pointer to the flag register.

This instruction increments the stack pointer by 2.

E.g. POP F

2. Arithmetic Instructions

These instructions perform the operations like: Addition, Subtraction, Increment, Decrement,

Compare etc

i. ADD/ADC destination, source;

ADD instruction adds the contents of source operand with the contents of destination operand.

ADC instruction adds the contents of source operand with the contents of destination operand with

carry flag bit.

The source may be immediate data, memory location or register.

The destination may be memory location or register.

The result is stored in destination operand. AX is the default destination register.

The source and the destination in an instruction cannot both be memory locations.

The source and the destination must be of the same type (bytes or words).

Flags affected: AF, CF, OF, SF, ZF.

E.g. ADD AX,2020H;

ADD AX, BX;

E.g. ADC AX,2020H;

ADC AX, BX;

ii. INC source

This instruction increases the contents of source operand by 1.

The source may be memory location or register.

The source cannot be immediate data.

The result is stored in the same place.

E.g. INC AX;

INC [5000H];



iii. DEC source

This instruction decreases the contents of source operand by 1.

The source may be memory location or register.

The source cannot be immediate data.

The result is stored in the same place.

E.g. DEC AX;

DEC [5000H];

iv. SUB/SBB destination, source

SUB instruction subtracts the contents of source operand from contents of destination.

A SBB instruction subtracts the contents of source operand & borrows from contents of destination

operand.



The result is stored in the destination place.

E.g. SUB AX,1000H;

SUB AX, BX;

E.g. SBB AX,1000H;

SBB AX, BX;

v. CMP destination, source

Also known as Compare.

This instruction compares the contents of source operand with the contents of destination operands.



Result is, carry & zero flag will be set or reset.

E.g. CMP AX,1000H;

CMP AX, BX;

D=S: CY=0,Z=1

D>S: CY=0,Z=0

D<S: CY=1,Z=0



vi. AAA

Also known as ASCII Adjust After Addition

Corrects result in AH and AL after addition when working with BCD values.

does not have any operand and affects AF and CF flags

Is executed after ADD instruction.

Example:

MOV AH,0 ; Clear AH for MSD

MOV AL,6 ; BCD 6 in AL

ADD AL,5 ; Add BCD 5 to digit in AL

AAA ; AH=1, AL=1 representing BCD 11

vii. AAS

Known as ASCII Adjust After Subtraction.

This instruction is executed after SUB instruction.

Affects Z and C flags

If low nibble of AL > 9 or AF = 1 then:

AL = AL - 6

AH = AH – 1

AF =CF = 1

Else

AF = CF = 0

In both cases: clear the high nibble of AL.

Example;

AL =0011 1001 =ASCII 9

BL=0011 0101 =ASCII 5

SUB AL, BL; (9 - 5) Result: AL = 00000100,CF = 0

If low nibble of AL > 9 or AF = 1 then:

AL = AL + 6

AH = AH + 1

AF = 1 and CF = 1

Else

AF = 0 and CF = 0

In both cases: Clear the high nibble of AL.



AAS; Result: AL=00000100; CF = 0

viii. MUL operand

Unsigned Multiplication.

Operand contents are positively signed.

Operand may be general purpose register or memory location.

If operand is of 8-bit then multiply it with contents of AL.

If operand is of 16-bit then multiply it with contents of AX.

Result is stored in accumulator (AX).

Flags Affected: OF, CF

Ex

MUL BH // AX= AL*BH; // (+3) * (+4) = +12.

MUL CX // AX=AX*CX;

ix. DIV operand

Unsigned Division.

Operand may be register or memory.

Operand contents are positively signed.

AL=AX/Operand (8-bit/16-bit) & AH=Remainder.

E.g. MOV AX, 0203 // AX=0203

MOV BL, 04 // BL=04

DIV BL // AL=0203/04=50 (i.e. AL=50 & AH=03)

x. AAM

Also known as ASCII Adjust after Multiplication.

This instruction is executed after MUL instruction.

Corrects the result of multiplication of two BCD values.

does not work with imul instruction

Then AH=AL/10 & AL=Remainder.

updates P, S and Z flags

Example:

MOV AL, 5

MOV BL, 7

MUL BL ; Multiply AL by BL , result in AX

AAM ; After AAM, AX =0305h

xi. AAD;

Also known as ASCII Adjust before Division.



converts two unpacked BCD digits in AH and AL to the equivalent binary number in AL .

AAD updates PF, SF and ZF;

AL=AH*10 +AL & AH=0.

Ex:

1. MOV AX, 0105(unpacked BCD for 15 decimal) // AH=01, AL=05

AAD // AL=15 ,AH=00

xii. IMUL operand

Signed Multiplication.

Operand contents are signed.

Operand may be general purpose register, memory location or index register.

When a byte from source is multiplied with content of AL, the signed result (product) will be put in

AX.

When a word from source is multiplied by AX, the result is put in DX and AX.

Updates CF and OF

Ex IMUL BH // AX= AL*BH;

IMUL CX // AX=AX*CX; result in DX and AX

xiii. IDIV operand

Signed Division.

Operand may be register or memory.

when operand is a byte:

AL = AX / operand

AH = remainder

when operand is a word:

AX = AX / operand

DX = remainder

E.g. MOV AX, -0203 // AX=-0203

MOV BL, 04 // BL=04

DIV BL // AL=-0203/04=-50 (i.e. AL=-50 & AH=03)

xiv. CBW

Convert Signed Byte To Signed Word.

This instruction converts byte in AL to word in AX.

The conversion is done by extending the sign bit of AL throughout AH.

Ex: Let AX = 00000000 10011011 (–155 decimal)

CBW Convert signed byte in AL to signed word in AX

AX = 11111111 10011011 (–155 decimal)

xv. CWD

Convert Signed Word To Signed Double Word

This instruction converts word in AX to double word in DX : AX.

The conversion is done by extending the sign bit of AX throughout DX.

Ex: Let DX = 00000000 00000000, and



AX = 11110000 11000111 (–3897 decimal)

CWD Convert signed word in AX to signed double word

in DX:AX

DX = 11111111 11111111

AX = 11110000 11000111 (–3897 decimal)

3. Logical Instructions

i. AND destination, source

Destination operand may be register, memory location.

Source operand may be register, immediate data or memory location.

Result is stored in destination operand.

Follow the rules as given below:-

1 AND 1 = 1

1 AND 0 = 0

0 AND 1 = 0

0 AND 0 = 0

E.g. MOV AX, 3F0FH // AX=3F0FH

MOV BX, 0008H // BX=0008H

AND AX, BX // AX=0008H

ii. OR destination, source

Destination operand may be register, memory location.

Source operand may be register, immediate data or memory location.

Result is stored in destination operand.


1 OR 1 = 1

1 OR 0 = 1

0 OR 1 = 1

0 OR 0 = 0

E.g. MOV AX, 3F0FH // AX=3F0FH

MOV BX, 0098H // BX=0098H

OR AX, BX // AX=3F9FH

iii. NOT operand;

Operand may be register, memory location.

This instruction inverts (complements) the contents of given operand.

Result is stored in Accumulator (AX).


1 NOT = 0

0 NOT = 1

E.g. MOV AX, 0200FH // AX=200FH

NOT AX // AX=DFF0H

iv. TEST destination, source



Both operands may be register, memory location or immediate data.

This instruction ANDs the contents of a source byte or word with the contents of specified

destination word.

Flags are updated but neither operand is changed .

TEST instruction is often used to set flags.

Depends on the 0th

bit of result ZF will be set or reset and based on the sign bit of result SF will be

set or reset

Examples:

TEST AL, BH; AND BH with AL. no result is stored. SF, ZF

4. Rotate and shift instruction

i. RCR destination, source

Also known as Rotate Right through Carry.

Each binary bit of the destination is rotated towards right position through Carry flag by the count

specified in the source operand.

Least Significant Bit (LSB) is placed in the Carry flag.

Then carry flag bit is placed in the Most Significant Bit (MSB) position.

Example:

RCR BX, 1; Word in BX is rotated by 1 bit towards right and CF will contain LSB bit and

content of CF will moved to MSB bit of BX.

ii. RCL

Also known as Rotate Left through Carry.

RCL instruction rotates the bits in the operand specified by destination operand towards left by the

count specified in source operand.

The operation is circular, the MSB of operand is rotated into a carry flag and the bit in the CF is

rotated around into the LSB of operand.

Example:

RCL AX, 1 ; save higher-order bit(MSB) of AX in CF



iii. ROL – ROL Destination, Count

Rotates all the bits in a specified word or byte to the left some number of bit positions.

The data bit rotated out of MSB is circled back into the LSB. It is also copied into CF.

If you to want rotate the operand by one bit position, you can specify this by putting 1 in the count

position in the instruction.

ROL AX, 1 Rotate the word in AX 1 bit position left, MSB to LSB and CF

iv. ROR – ROR Destination, Count

Rotates all the bits in a specified word or byte some number of bit positions to right.

The data bit moved out of the LSB is also copied into CF.

If you want to rotate the operand by one bit position, you can specify this by putting 1 in the count

position in the instruction.

Ex: ROR BL, 1 Rotate all bits in BL right 1 bit position LSB to MSB and to CF.

v. SAL Destination, Count

SHL Destination, Count

SAL and SHL are two mnemonics for the same instruction.

This instruction shifts each bit in the specified destination some number of bit positions to the left.

As a bit is shifted out of the LSB operation, a 0 is put in the LSB position. The MSB will be shifted

into CF.

Flags are affected as follow: CF contains the bit most recently shifted out from MSB. For a count of

one, OF will be 1 if CF and the current MSB are not the same. SF and ZF will be updated to reflect

the condition of the destination. PF will have meaning only for an operand in AL.

SAL BX, 1 Shift word in BX 1 bit position left, 0 in LSB

vi. SHR Destination, Count

This instruction shifts each bit in the specified destination some number of bit positions to the right.

As a bit is shifted out of the MSB position, a 0 is put in its place.

The bit shifted out of the LSB position goes to CF.

The flags are affected by SHR as follow:

CF contains the bit most recently shifted out from LSB.

For a count of one, OF will be 1 if the two MSBs are not both 0’s.

SF and ZF will be updated to show the condition of the destination.

PF will have meaning only for an 8-bit destination.

Ex: SHR BP, 1 Shift word in BP one bit position right ,0 in MSB



vii. SAR Destination, Count

This instruction shifts each bit in the specified destination some number of bit positions to the right.

As a bit is shifted out of the MSB position, a copy of the old MSB is put in the MSB position.

The LSB will be shifted into CF.

The flags are affected as follow:

CF contains the bit most recently shifted in from LSB.

For a count of one, OF will be 1 if the two MSBs are not the same.

After a multi-bit SAR, OF will be 0.

SF and ZF will be updated to show the condition of the destination.

PF will have meaning only for an 8- bit destination

5. String Manipulation Instructions

i. MOVS

It causes moving of byte or word from one string to another.

In this instruction, the source string is in Data Segment and destination string is in Extra Segment.

SI and DI store the offset values for source and destination index.

There are following sub types,

MOVSB

MOVSW

ii. CMPS

Also known as Compare String.

String values remain unaffected. Only flags affected. Basically it performs the subtraction

The source string is in Data Segment and destination string is in Extra Segment.SI and DI store the

offset values for source and destination index.

If both the byte and word are equal then zero flag will be set (i.e. ZF=1) otherwise it will be reset

(i.e. ZF=0).


i. CMPSB:- Compare String Byte.

ii. CMPSW:- Compare String Word.

iii. SCAS

Used for scanning a string in memory for a particular byte or word.

It compares contents of byte in AL or word in AX with byte or word at memory pointed by

ES.

Whenever a match to the specified operand is found in the string, execution stops and Z flag

is set

it does not change operands


SCASB

SCASW

iv. STOS

Instruction copies a byte from AL or a word from AX to a memory location in the extra segment.


Sub types are STOSB / STOSW



v. LODS

Copies a byte from a string location pointed to by DS to AL, or a word from a string location

pointed to by DS to AX.


Sub types are LODSB / LODSW

6. Branching Instructions i. CALL

Also known as unconditional call.

This Instruction is used to transfer execution to a subprogram or procedure. Independent of any

status or condition.


i. NEAR CALL:- is a call to a procedure which is in the same code segment as the CALL

instruction

ii. FAR CALL:- is a call to a procedure which is in a different from that which contains the

CALL instruction .

ii. JMP Des

Unconditional jump.

Under unconditional jump, the execution control is transferred to the specified location using 8-bit

or 16-bit displacement.

Example: JMP Label-Name

iii. .Jxx Des

Conditional Jump

All the conditional jumps follow some conditional statements or any instruction that affects the

flag.

iii. Loop Des:

This is a looping instruction.

The number of times looping is required is placed in the CX register.



With each iteration, the contents of CX are decremented.

ZF is checked whether to loop again or not.

If CX is not 0, execution will jump to a destination specified by a label in the instruction. If CX = 0

after the auto decrement, execution will simply go on to the next instruction after LOOP.

Subtypes are, LOOPE / LOOPZ (LOOP WHILE CX = 0 AND ZF = 1) ,

LOOPNE / LOOPNZ (LOOP WHILE CX ≠ 0 AND ZF = 0)

iv. RET

return execution from procedure to calling program

The RET instruction does not affect any flag.

7. Flag Manipulation Instructions

i. CMC

Also known as Complement Carry Flag.

It inverts contents of carry flag.

if CF = 1 then CF will be = 0.

if CF = 0 then CF will be = 1.

E.g. CMC

ii. STC

Also known as Set Carry Flag.

It makes carry flag in set condition.

After execution CF = 1.

E.g. STC

iii. CLI

Also known as Clear Interrupt Flag.

It makes interrupt flag in reset condition.

After execution IF = 0.

E.g. CLI

iv. CLD

Also known as Clear Direction Flag.

It makes direction flag in reset condition.

After execution DF = 0.

E.g. CLD

v. CLC (CLEAR CARRY FLAG)

This instruction resets the carry flag to 0.

It does not affect any other flag.

vi. STI (SET INTERRUPT FLAG)

Setting the interrupt flag to 1 enables the INTR interrupt input of the 8086.

The instruction will not take effect until the next instruction after STI.



vii. STD (SET DIRECTION FLAG)

This instruction sets the direction flag to 1.

It does not affect any other flag.

8. Machine Control Instructions

i. HLT

Also known as Halt

It makes the processor to be in stable (do nothing) condition.

E.g. HLT

ii. NOP

Also known as No Operation.

It tells about further there will be no operation to be performed.

E.g.NOP

iii. WAIT

wait for signal or interrupt signal

8086 enters an idle condition in which it is doing no processing.

The 8086 will stay in this idle state until the 8086 test input pin is made low or until an interrupt

signal is received on the INTR

iv. LOCK – ASSERT BUS LOCK SIGNAL

allows a microprocessor to make sure that another processor does not take control of the system bus

while it is in the middle of a critical instruction,

The LOCK prefix is put in front of the critical instruction.

V. ESC (ESCAPE)

This instruction is used to pass instructions to a coprocessor,

2.4 ASSEMBLER DIRECTIVES

Are types of hints that are given to the assembler by using some predefined alphabetical strings.

It helps the assembler to correctly understand the assembly language programs to prepare the codes.

1. SEGMENT

indicate the start of a logical segment.

The started segment is also assigned a name

2. ENDS (END SEGMENT)

used with the name of a segment to indicate the end of that logical segment.

Example : CODE SEGMENT : Start of logical segment

…………….some instructions…………….

CODE ENDS : End of segment named CODE

3. PROC (PROCEDURE)

• Used to identify the start of a procedure.

• The PROC directive follows the name of a procedure.

• After the PROC directive, the term near or far is used to specify the type of the procedure.

4. ENDP



• to indicate the end of the procedure

Ex:

DIVIDE PROC FAR, identifies the start of a procedure named DIVIDE and tells the assembler that the

procedure is far

…………………..

DIVIDE ENDP indicate the end of DIVIDE procedure

5. ASSUME

Used to tell the assembler, about the name of the logical segment it should use for a specified

segment.

Ex:

ASSUME CS: CODE: tells the assembler that the instructions for a program are in a logical segment

named CODE.

ASSUME DS: DATA: tells the assembler that for any program instruction, which refers to the data

segment, it should use the logical segment called DATA.

6. DB (DEFINE BYTE)

• Used to declare a byte or bytes of storage locations in memory.

Ex:

PRICES DB 49H, 98H, 29H Declare array of 3 bytes named PRICES and initialize them with specified

values.

7. DW (DEFINE WORD)

• Used to define a variable of type word or to reserve storage locations of type word in memory.

Ex:

WORDS DW 1234H, 3456H declare an array of 2 words and initialize them with the specified values.

6. DB (DEFINE BYTE)

• used to declare a byte or bytes of storage locations in memory.

Ex:

PRICES DB 49H, 98H, 29H Declare array of 3 bytes named PRICES and initialize them with specified

values.

7. DW (DEFINE WORD)

• used to define a variable of type word or to reserve storage locations of type word in memory.

Ex:

WORDS DW 1234H, 3456H Declare an array of 2 words and initialize them with the specified values.

10. DT (DEFINE TEN BYTES)

• used to declare a variable, which is 10 bytes in length or to reserve 10 bytes of storage in memory.

Ex:

PACKED DT 11223344556677889900 declare an array named PACKED, which is 10 bytes in length. It

will initialize the 10 bytes with the values 11, 22, 33, 44, 55, 66, 77, 88, 99, and 00 .

11. OFFSET

• which tells the assembler to determine the offset or displacement of a named data item (variable),

Ex:

MOV BX, OFFSET PRICES, determine the offset of the variable PRICES and move that value into BX

12. EQU (EQUATE)

• used to give a name to some value or symbol. Each time the assembler finds the given name in the

program, it replaces the name with the value or symbol you equated with that name.



Ex:

FACTOR EQU 03H

ADD AL, FACTOR. //ADD AL, 03H.

13. NAME

• used to assign a name to an assembly language program module

14. LENGTH

• This tells the assembler to determine the number of elements in some named data item, such as a

string or an array.

Ex:

MOV CX, LENGTH STRING1, determines the number of elements in STRING1 and load it into CX. If

the string was declared as a string of bytes, LENGTH will produce the

number of bytes in the string. If the string was declared as a word

string, LENGTH will produce the number of words in the string.

15. PTR (POINTER)

• used to assign a specific type to a variable or a label. The operator PTR is prefixed by either BYTE

or WORD.

Ex:

INC BYTE PTR [BX] increment the byte pointed to by BX.

INC WORD PTR [BX] increment the word pointed to by BX.

16. ORG (ORIGIN)

• it directs the assembler to start the memory allotment for the particular segment.

• The ORG directive allows you to set the location counter to a desired value at any point in the

program.

• If the ORG statement is not written in the program, the location counter is initialized to 0000

Ex: ORG 2000H set the location counter to 2000H,

17. LABEL

• is used to assign a name to the current content of the location counter.

• The type of the label must be specified, i.e. whether it is a NEAR or a FAR label, BYTE or WORD

label, etc.

• If the label is going to be used as the destination for a jump or a call, then the label must be

specified as type NEAR or FAR.

• If the label is going to be used to reference a data item, then the label must be specified as type byte,

type word, or type double word.

Ex:

ARRAY1 LABEL WORD

18. EXTRN

• is used to tell the assembler that the name or labels following the directive are in some other

assembly module.

• For a reference to externally named variable, you must specify the type of the variable,

Ex:

EXTRN DIVIDE: FAR tells the assembler that DIVIDE is a

label of type FAR in another module.

19. PUBLIC

• is used to tell the assembler that a specified name or label will be accessed from other modules.



Ex:

PUBLIC tx, sx , which makes the two variables tx and sx available to other assembly modules.

20. TYPE

• The assembler determines the number of bytes in the type of the variable.

• For a byte-type variable, the assembler will give a value of 1, for a word-type variable, 2, and for a

double word-type variable, 4.

Ex:

MOV AX, TYPE STRING moves the value 0002H in AX.

2.5 MACROS

The macros allows the programmer to write a named block of source statements, then use that name

in the source file to represent the group of statements.

During the assembly phase, the assembler automatically replaces each occurrence of the macro

name with the statements in the macro definition.

Macros are expanded on every occurrence of the macro name, so they can increase the length of the

executable file if used repeatedly.

Unlike procedures, macros should be defined above the code that uses it.

MACRO DEFINITION

Defining Macros is done as follows—

Label MACRO [optional arguments];

statements;

ENDM

Example:

MyMacro MACRO p1, p2, p3

MOV AX, p1

MOV BX, p2

MOV CX, p3

ENDM

2.6 STACK

Stack is implemented in the memory for temporary storage of information such as data or

addresses.

The stack is 64Kbytes long.

Stack is accessed by using SP and SS.

SP contains an offset value that points to a storage location in the current stack segment.



Two operations

1. PUSH: stack pointer (SP) decremented by two as we store a data word into the stack

2. POP: SP incremented by two as we retrieve a data word from the stack back to the CPU register.

Fig 2 push and pop operations

2.7 INTERRUPTS AND INTERRUPT PROCESSING

Interrupts provide a mechanism for quickly changing program environment.

An interrupt service routine (ISR) is a software routine that invokes in response to an interrupt.

ISRs examine an interrupt and determine how to handle it.

When a microprocessor receives an interrupt signal it stops executing current normal program, save

the status (or content) of various registers (IP, CS and flag registers) in stack and then the processor

executes a ISR in order to perform the specific task/work requested by the interrupt

There are 256 possible interrupt types available on 8086 with certain of these reserved for various

system purposes, and certain available for user-defined interrupt service routines.

8086 Interrupt Types

256 Interrupts Of 8086 Are Divided In To 3 Groups

1. Type 0 To Type 4 Interrupts: These are used for fixed operations and hence are called dedicated

interrupts

2. Type 5 To Type 31 Interrupts: Not used by 8086,reserved for higher processors like 80286 ,80386

etc

3. Type 32 To 255 Interrupts: Available for user, called user defined interrupts these can be H/W

interrupts and activated through intr line or can be S/W interrupts.

Sources of Interrupts in 8086

1. One source is from an external signal applied to NMI or INTR input pin of the processor. The

interrupts initiated by applying appropriate signals to these input pins are called hardware

interrupts.

2. A second source of an interrupt is execution of the interrupt instruction "INT n", where n is the type

number. The interrupts initiated by "INT n" instructions are called software interrupts.

3. The third source of an interrupt is from some condition produced in the 8086 by the execution of an

instruction. Such conditional interrupts are also known as exceptions.



Interrupt priority: In systems with more than one interrupt inputs, some interrupts have a higher

priority(internal interrupt) than other

External Interrupts

The external interrupt facility is used to alert the processor that a peripheral device requires the

CPU’s attention.

The 8086 microprocessor has two control lines INTR and NMI that can signal interrupts.

Maskable interrupts use the INTR signal line, and nonmaskable interrupts use the NMI signal line.

Nonmaskable interrupt (NMI)

• Initiated from external hardware by sending a 1 to the NMI input of the 8086.

• NMI causes the current flags, CS, and IP to be pushed onto the stack Interrupt enable flag is cleared

to disable all external hardware interrupts.

• It is for hardware events that must be responded to immediately (major system faults), eg detection

of power failure and detection of a memory read error.

Software interrupt

• During software interrupt, no external interrupt acknowledge bus cycles are initiated.

Internal interrupt and exceptions

• Internal interrupts are generated by the processor during execution time and exceptions are

generated by operations like division with zero,overflow etc

RESET

• Processor initialization or start up is accomplished with activation (HIGH) of the RESET pin

The Operation of an Interrupt sequence on the 8086 Microprocessor:

1. External interface sends an interrupt signal, to the Interrupt Request (INTR) pin, or an internal

interrupt occurs.

2. The CPU finishes the present instruction (for a hardware interrupt) and sends Interrupt

Acknowledge (INTA) to hardware interface.

3. The interrupt type N is sent to the Central Processor Unit (CPU) via the Data bus from the hardware

interface.

4. The contents of the flag registers are pushed onto the stack.

5. Both the interrupt (IF) and (TF) flags are cleared. This disables the INTR pin and the trap or single-

step feature.

7. The contents of the code segment register (CS) are pushed onto the Stack.

8. The contents of the instruction pointer (IP) are pushed onto the Stack.

9. The interrupt vector contents are fetched, and then placed into the IP and into the CS so that the

next instruction executes at the interrupt service procedure addressed by the interrupt vector.

10. While returning from the interrupt-service routine by the Interrupt Return (IRET) instruction, the

IP, CS and Flag registers are popped from the Stack and return to their state prior to the interrupt.



Interrupt Vector Table

Interrupt vector is used to determine the address of the ISR of the interrupting device.

Is a table of interrupt vectors that associates an interrupt handler.

Is located in the first 1024 bytes of memory at addresses 000000H–0003FFH.

module 2 instruction set

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