Modern VLSI Design 3e: Chapter 3 Partly from 2002 Prentice Hall PTRweek5-1

Lecture 14

CMOS Logic Gates

Feb. 5, 2003

Modern VLSI Design 3e: Chapter 3 Partly from 2002 Prentice Hall PTRweek5-2

Contents of the Course

ASIC FPGA Transistor and Layout Gate and Schematic Systems and VHDL/Verilog

Modern VLSI Design 3e: Chapter 3 Partly from 2002 Prentice Hall PTRweek5-3

Contents of the Course (cont’d)

2 ASIC labs 2 FPGA labs Transistor/Layout Gate and Schematic Systems/VHDL

(Cadence)

(Synopsys)

(XilinxFoundation)

Modern VLSI Design 3e: Chapter 3 Partly from 2002 Prentice Hall PTRweek5-4

Topics

Combinational logic functions. Static complementary logic gate structures.

Modern VLSI Design 3e: Chapter 3 Partly from 2002 Prentice Hall PTRweek5-5

Combinational logic expressions

Combinational logic: function value is a combination of function arguments.

A logic gate implements a particular logic function.

Both specification (logic equations) and implementation (logic gate networks) are written in Boolean logic.

Modern VLSI Design 3e: Chapter 3 Partly from 2002 Prentice Hall PTRweek5-6

Gate design

Why designing gates for logic functions is non-trivial:– may not have logic gates in the libray for all

logic expressions;– a logic expression may map into gates that

consume a lot of area, delay, or power.

Modern VLSI Design 3e: Chapter 3 Partly from 2002 Prentice Hall PTRweek5-7

Boolean algebra terminology

Function:f = a’b + ab’

a is a variable; a and a’ are literals. ab’ is a term. A function is irredundant if no literal can be

removed without changing its truth value.

Modern VLSI Design 3e: Chapter 3 Partly from 2002 Prentice Hall PTRweek5-8

Completeness

A set of functions f1, f2, ... is complete iff every Boolean function can be generated by a combination of the functions.

NAND is a complete set; NOR is a complete set; {AND, OR} is not complete.

Transmission gates are not complete. If your set of logic gates is not complete, you

can’t design arbitrary logic.

Modern VLSI Design 3e: Chapter 3 Partly from 2002 Prentice Hall PTRweek5-9

Static complementary gates

Complementary: have complementary pullup (p-type) and pulldown (n-type) networks.

Static: do not rely on stored charge. Simple, effective, reliable; hence

ubiquitous.

Modern VLSI Design 3e: Chapter 3 Partly from 2002 Prentice Hall PTRweek5-10

Static complementary gate structure

Pullup and pulldown networks:

pullupnetwork

pulldownnetwork

VDD

VSS

outinputs

Modern VLSI Design 3e: Chapter 3 Partly from 2002 Prentice Hall PTRweek5-11

Inverter

a out

+

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Inverter layout

(tubs notshown)a out

+

transistors

GND

VDD

a out

tub ties

Modern VLSI Design 3e: Chapter 3 Partly from 2002 Prentice Hall PTRweek5-13

NAND gate

+

ba

out

Modern VLSI Design 3e: Chapter 3 Partly from 2002 Prentice Hall PTRweek5-14

NAND layout

+

ba

out

b

a

out

VDD

GND

tubties

Modern VLSI Design 3e: Chapter 3 Partly from 2002 Prentice Hall PTRweek5-15

NOR gate

+

b

a

out

Modern VLSI Design 3e: Chapter 3 Partly from 2002 Prentice Hall PTRweek5-16

NOR layout

b

a

out

a

b

out

VDD

GND

tub ties

Modern VLSI Design 3e: Chapter 3 Partly from 2002 Prentice Hall PTRweek5-17

Pullup/pulldown network design

Pullup and pulldown networks are duals. To design one gate, first design one

network, then compute dual to get other network.

Example: design network which pulls down when output should be 0, then find dual to get pullup network.

Modern VLSI Design 3e: Chapter 3 Partly from 2002 Prentice Hall PTRweek5-18

Lectures 15

Transfer Characteristics

(Transfer Curve and Noise Margin)

Feb. 7, 2003

Modern VLSI Design 3e: Chapter 3 Partly from 2002 Prentice Hall PTRweek5-19

Topics

Electrical properties of static combinational gates:– Noise margin and transfer curve;– delay;– power.

Modern VLSI Design 3e: Chapter 3 Partly from 2002 Prentice Hall PTRweek5-20

Logic levels

Solid logic 0/1 defined by VSS/VDD.

Inner bounds of logic values VL/VH are not directly determined by circuit properties, as in some other logic families.

logic 1

logic 0

unknown

VDD

VSS

VH

VL

Modern VLSI Design 3e: Chapter 3 Partly from 2002 Prentice Hall PTRweek5-21

Logic level matching

Levels at output of one gate must be sufficient to drive next gate.

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Transfer characteristics

Transfer curve shows static input/output relationship—hold input voltage, measure output voltage.

Modern VLSI Design 3e: Chapter 3 Partly from 2002 Prentice Hall PTRweek5-23

Inverter transfer curve

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Logic thresholds

Choose threshold voltages at points where slope of transfer curve = -1.

Inverter has a high gain between VIL and VIH points, low gain at outer regions of transfer curve.

Note that logic 0 and 1 regions are not equal sized—in this case, high pullup resistance leads to smaller logic 1 range.

Modern VLSI Design 3e: Chapter 3 Partly from 2002 Prentice Hall PTRweek5-25

Noise margin

Noise margin = voltage difference between output of one gate and input of next. Noise must exceed noise margin to make second gate produce wrong output.

In static gates, t= voltages are VDD and VSS, so noise margins are VDD-VIH and VIL-VSS.

Modern VLSI Design 3e: Chapter 3 Partly from 2002 Prentice Hall PTRweek5-26

Example 1

Transfer curve and noise margin

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