modern physical design - ucsd vlsi cad...

ICCAD Tutorial, November 9, 2000

1

SC/ABK/MSICCAD Tutorial: November 9, 20001

Modern Physical Design:Algorithm

TechnologyMethodology

(Part IV)Stan Chow Ammocore

Andrew B. Kahng UCSD

Majid Sarrafzadeh UCLA


Crosstalk Induced Errors

l Transition on an adjoining signal causes unintendedlogic transition

l Symptom: chip fails (repeatably) on certain logicoperations

Aggressor net

Victim net

Wire R

Drive R Grounded C

Coupling C

Input Noise Tolerance


2


Crosstalk Induced Errors

l Timing dependence on crosstalkl timing depends on behavior of adjoining signals

l symptom: timing predictions inaccurate compared to silicon (effectcan be large: 3:1 on individual nets)

Other logic net(s)

Wire R

Grounded C Coupling C (multiplied by Miller effect)

Delay here and here depends on the behavior of other nets


Effects of Crosstalk:Delay Uncertainty

-4.00E-01

-2.00E-01

0.00E+00

2.00E-01

4.00E-01

6.00E-01

8.00E-01

1.00E+00

1.20E+00

1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61

Time (ps)

Vo

ltag

e (v

)

Series1

Series2

Series3

Series4

Series5

Series6

Series7

min nom max

unfriendly

friendly

nominal

Thresholds


3


Effects of Crosstalk:Delay Uncertainty

Relative Delay vs. Relative Risetimefor different coupling percentages

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0 1 2 3 4 5 6Risetime of interferer / Risetime of victim

Del

ayR

elat

ive

to n

o-c

ross

talk

cas

e

10% coupling - fast10% coupling - slow50% coupling - fast50%coupling - slow100% coupling - fast100% coupling - slow


Conventional FlowArchitectural/ Behavioral Design

RTL Design

Timing Optimization

Floor Planning

Extraction

Place and Route

Timing Verification

Logic Synthesis

Logical Design

Physical Design


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Performance Optimization Methodologyl Design Optimization

l global restructuring optimization -- logic optimization on layoutusing actual RC, noise peak values etc.

l localized optimization -- with no structural changes and leastlayout impact

l repeater/buffer insertion for global wires

l Physical optimizationl high fanout net synthesis (eg. for clock nets); buffer trees to meet

delay/skew and fanout requirementsl automatically determine network topology (# levels, #buffers, and

type of buffers)l wire sizing, spacing, shielding etc.

l Fixing timing violations automaticallyl fix setup/hold time violationsl fix maximum slew and fanout violations

Courtesy Hormoz/Muddu, ASIC99


Performance Optimization Methodology

l Static methods (when must we go / can we godynamic?)

l Filtering-Based methods - approximate analysesl Analysis Best Practices, Macromodelsl Incremental analysis backplane



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Performance Optimization Tool FlowArchitectural/ Behavioral Design

Extraction

Timing Analysis

Signal Integrity Analysis

RTL Design

Optimization

Floor Planning

Placement

Logic Synthesis

Global Routing Detailed Routing

Electrical Analysis/Estimation

EM Analysis

Power Analysis

ClockAnalysis



1

2

3

4

5

Electrical Optimization


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Objective: Minimize Congestion and Wire length withtiming

Traditional Approaches

NewApproach

Slack = -1

Slack = -1

Net 1

Net 2

Weight based approachesNet1 priority = Net2 Priority

Electrically Correct drivenNet1 lower priority, longer net

Net2 higher priority, shorter net

vs

Electrical Placement / Partitioning


D Q

Latch

CLK

==>

Physical … proximity of the signalTemporal … noise event occurs timing windowCritical … is the path importantElectrical … driver strength vs pin cap

Managing Glitch / Delay Uncertainty


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Managing Complexity

l Use fast models to reduce complexityl 1000,000 net design 1000 billion pairwise relationships

l Which signals are prone to coupling noise?l Net isolation techniques

l electricall critical

l logical - nodes cannot switch in same or opposite direction

l temporal

l Quickly focus on the problem netsl Identify significant aggressorsl Reduce time and space requirements to a manageable

size


Information vs. Control in PD Flow• Floor planning

– localize major functions of the chip– cluster critical nets

• Placement / Optimization– find legal location for all cells and pins– traditional objective - minimize wire length– gate sizing, buffer insertion, pin swap, etc.

• Global routing– resolve congestion– find best paths for critical nets

• Detail Routing– Create the net geometry


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• Placement phase– Don’t know adjacencies, layer assignment, or global route

– Do know net length, est. wire R/C, driver strength, signal slews

– Metrics tell if a net is likely to have problems

– Fixes (size driver, buffer signal) cause no convergence problems

• Global route phase– Don’t know adjacencies, only congestion figure

– Do know layer assignments, better R/C estimates

CwireRsource Rwire

Crosstalk Prevention


Performance Validation Integrated Flow

l Logic design too early for signal integrityproblems

l Placement/ Global routing best place to achievetiming convergence

l Placement/ Global routing best place to achievenoise immunization

l Detail routing is too late to fix all the signalintegrity problems


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Glitch/Delay Uncertainty Optimization

l Increase driver strengthl net’s glitch and delay uncertainty reduced

l victims of this net could adversely be affected

l area/power is increased

l Reduce aggressor strengthl victims of this net would benefit

l the net becomes more susceptible to noise

l area/power reduced

l Insert bufferl significantly reduces victim’s noise

l Reduce net length


Coupling Impact Analysis

l Accurate estimate of coupling capacitancel statistical model:

l coupling_per_length = f(congestion, layer)

l Efficient measure of impact on noise and delayl prune the net-pair space to a manageable sizel decouple nets for efficient delay compuation

l compute tight upper bounds on noise energy


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Wiring Methodologies

l Electrically connect pins on a netl 10 million nets per chip

l 3-4 pins per net

l 6-7 routing layers

l Average length of 160 um per net

l Constraints for Routerl maximum parallel run for the wire

l minimum spacing

l nets to be shielded


Block B

Density 100K Gates

Block A

Density 50K Gates

Early Wiring Estimation

l Routing Prototype Model (RPM)l considers routing congestion

l considers placement density

l considers wire length and fanouts (net pinouts)

l Pre-route prototype to Post-route within 5%

l Physical locations for all pinsl Global route

l congestionl Layer information


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Predictive Models of Net Length

HalfPerim

Star Spine MinSpan

Steiner

O(N) O(N) O(N) O(N^2logN)

O(N^2.logN)

Low Low Med Med High

where N is number of pins connected to the net


Crosstalk Prevention Strategies

l Placement phasel don’t know adjacencies, layer assignments, or global routesl do know net length, est. wire R/C, driver strength, signal slewsl establish metrics to tell if net is likely to have problemsl fixes include driver sizing, buffering

l Global route phasel don’t know adjacencies, but have idea of congestionl do know layer assignments, better R/C estimates

l Can apply timing windowsl only consider signals that can change at the same timel data comes from static timing analysis

l Detailed routing - detailed analysis and routing ECOsl N.B.: In any case, SI brings potential huge

infrastructure changes (e.g., statistical centering designw/distributions)


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SC/ABK/MSICCAD Tutorial: November 9, 200023Courtesy Hormoz/Muddu, ASIC99

Pre-Route Pruning

l Victim Pruningl sensitivity to coupling effects

l likelihood of being on a critical path (delay analysis only)

l Aggressor Pruningl drive strength and load

l Impact Pruningl victim-aggressor pairs

l physical proximity of net pairs

l relationship in the time domain


Post-Route Pruningl Geometric/Capacitive coupling

l depends on magnitude of coupling capacitance as compared tototal capacitance of net

l Typically less than 10% of nets have significant couplings andcouplings to only few nets are significant

l Structural Filteringl take into consideration the type of gate driving the netsl consider direction of signal propagation or location of driverl victim net with weak driver is more likely to have glitchl aggressor net with strong driver is more likely to cause glitch on

victim nets

l Temporal Pruningl switching windows between victim and aggressor nets is used

l Functional or Logical Pruningl eliminate signals/paths that can never be responsible for noise

l Finally, need detailed analysis after filtering stage


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Timing and Logic Dependence forGlitchl Structured filtering determines the potentially significant

couplingsl Need to tie in the timing or switching window information

to determine if indeed these are relevantl Coupled nets switching at non-overlapping intervals

l coupling capacitance can be converted to a groundedcapacitance

l Coupled nets switch simultaneously with overlappedintervalsl need to analyze both nets with their drivers simultaneouslyl coupling capacitance can be converted to a grounded

capacitance with worst-case switch factor


time

n1

n2

n3

n4


Reducing Conservatism

l Aggressor nets are not uncorrelatedl timing correlation: some nodes can not switch at the same time

l noise effect depends on switching windows of nets

l Logic correlation: some nodes can not switch inopposite direction and some nodes switch monotonicallyin one direction


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Integrated Flow for Crosstalk Avoidance

Placement

Optimization

Global Route Est

Routing

Extraction

Route constraints

CouplingImpact

Analysis

Detailed Noise

Analysis

Sensitive nets

ECO control

Violations


Criteria for Immunizing AgainstCrosstalkl Need models for noise estimation and delay uncertainty

computation with tight upper boundsl Need timing windows and logical transition between

coupled netsl Need physical information

l accurate estimation of RCs, congestion, density, pin location,and layer information in pre-routing stages

l Fidelity of models is important


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0 5 10 15 20-5-10-15-20

012

0040

016

0080

0

Golden Delta Metric (%error weighted by absolute error)

Num

ber

of C

ases


Delays with Coupling vs NominalDelays


Issues for Delay Uncertainty

l Parameters that effect victim net’s gate and interconnectdelaysl aggressor net(s) coupling capacitance

l fast slew time at aggressor nets and large aggressor net drivers

l slow slew time on victim net and small victim net driversl proximity of aggressor driver to victim net’s driver (same

direction vs opposite direction signal propagation)

l power bounce in victim driver/receiver gates

l Impact the following delay componentsl victim net driver gate delay

l victim net delayl victim net receiver gate delay


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Impact of Coupling on Delay

l Coupling adds delay ambiguity/uncertaintyl amount of coupling depends on the temporal relationship

between waveforms; coupling varies between nodes ofdistributed coupled RC networks

l Current timing tools employ a technique which convertcoupling caps. to grounded caps by multiplying with aswitch factor depending upon switching conditionsl reduces coupled RC networks to just uncoupled RC networks

l allows efficient interconnect delay analysis

l introduces error in delay computationl can it be applicable for worst-case analysis?


• Only consider signals that can change at the same time

• Data comes from static timing analysis

One clock cycle

A

B

C

D STATimingWindows

SI CrosstalkMagnitudes

Worst case occurs here, does not include signals A or D.


Timing Windows for Crosstalk


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A1

V

A2

Simple Worst Case Model

A1

V

A2Static Analysis Model


Crosstalk Analysis Approachesl Simple worst case model

l assume all aggressor nets are switching simultaneously in oppositedirection to victim net

l functional and timing information not considered

l yields pessimistic results

l Static Analysis Modell timing information is used but function information is ignored

l yields accurate results but might flag too many nets as problematic


A1

V

A2

Delay-Vector ModelCourtesy Hormoz/Muddu, ASIC99

Crosstalk Analysis Approachesl Zero-Delay Model

l temporal information is ignoredl search functional space to find input vectors causing maximum

noisel if both aggressor and victim nets switch in the same cycle then

assumes conservatively that transitions are correlated

l Delay-Vector Modell consider both timing and functional information completelyl not always possible to obtain exact vectors causing maximum noise


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A

B

A

Cc SF*Cc

B

SF*CcVA

VB


Switch Factor Methodologyl Switch factor for coupling cap. between pair of nets:

l 0 for nets switching in same direction (in phase)

l 1 when aggressor net is quiet and only victim net is switching

l 2 for nets switching in opposite direction (out of phase)l effective change in voltage, ∆Veff = VA - VB = 2Vdd

l Switch factor depends on slew times, relative offset ofwaveforms at both nodes: need accurate models,iterative methods for accurate SF


Standard Practice

l Use SF=2.0 for most coupling netsl coupled nets nets which are part of same logical bus

l coupled clock nets and regular nets coupling to clock nets

l pessimistic for some nets and could be optimistic?

l due to disparity between rise/fall slew times switch factor couldbe more than 2!


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1 2 N

Vh

Vref

VloTa Tv

Tv = N Ta

3C

2C

C


Effect of Slew Time on SwitchFactorl SF is in the range (0, 3)


Parameters Affecting Switch Factor

l All possible combinations of switch factorsl SFij = f (Aj, Vi, Tij, Xij)

l Aj represents event times for aggressor nets

l Vj represents event times for victim net

l Tjj is ratio of aggressor and victim slew timesl Xij is cross-coupling capacitances between aggressor and victim

nets

l SF’s depend on events and transition times and vice-versal Hence, requires iterative solution to find accurate SF’s


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IR Drop

l Voltage drop in supply lines from currents drawn by cellsl Symptom: chip malfunctions on certain vectorsl Biggest problem: what’s the worst-case vector?

Voltages depend on currentsof other cells

PadPower supplynetwork consistsof wires of varyingsizes; they must be bigenough, but too big wastes area

Currents depend on drivertype, loads, and how oftencell is switched

Allowablevoltagedrop at pin


IR Drop

l Analysisl model I/O P/G supply; C extraction must distinguish decoupling

cap between P/G and coupling cap between signals, P/G

l Prevention (good design)l P/G lines on same layer, close to each other; large decoupling

on chip; process solutions (e.g., DEC Alpha)


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Electromigration

l Power supply lines fail due to excessive currentl Symptom: chip eventually fails in the field when wire

breaks

Currents depend on currentsof other cells

PadPower supplynetwork consistsof wires of varyingsizes; they must be bigenough, but too big wastes area

Currents depend on drivertype, loads, and how oftencell is switched

Current limit depends on wire size


Electromigration

l Prevention: wire cross-section to current rulesl Maximum current density for particular material (via,

layer)l Modified Black’s equation; waveform modelsl Higher limits for short, thin wires due to grain effects

l Copper: 100x resistance to EM → not a problem anymore? (actually, 4-5x)


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Hot Electron Effectsl May also be called short channel effectl Caused by extremely high electric fields in the channel

l Occurs when voltages are not scaled as fast as dimensions

l Effect becomes worse as devices are turned on harderl Symptom: Thresholds shift over time until chip fails

N+ diffusion

Gate

Oxide and/or interfaceis damaged here

Electrons pick up speed in channel;‘hot’ electrons are the fastest of astatistically fast bunch

Impact ionization occurs here

+++

+++


Hot Electron Effect (cont)l Depends on how hard device is driven (input slew rate)l And on the size of the load

Vds

Vgs

Trajectory with large C, fast T in

Trajectory with small C, slow T in

Contours of constanthot electron flux


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Hot Electron Prevention Strategies

l Allowable region for input slew and output loadl Fluence per transition is function of input slew, output

loadl Set maximum allowed degradation over life of device

(estimate of total number of transitions) ≡ fluence limit

l Size device as neededl Output load vs. driver sizes


VerilogVHDL STA CTS

Route RCX DelayCalc

System Level Constraints

Activities

CrosstalkParasitics

CrosstalkDelay

NewLibraryData

Timing Windows

Problems fixed ateach step

PlacePBS

HotElectron

Sig Wire/Clk WireSelf Heat

Electro-migration

IR Drop

CrosstalkPreventionSig WireSelf Heat Clk Wire

Self Heat

SI Flow - Hot Electron


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VerilogVHDL STA CTS

Route RCX DelayCalc

System Level Constraints

Activities

CrosstalkParasitics

CrosstalkDelay

NewLibraryData

Timing Windows

Problems fixed ateach step

PlacePBS

HotElectron

Sig Wire/Clk WireSelf Heat

Electro-migration

IR Drop

CrosstalkPreventionSig WireSelf Heat Clk Wire

Self Heat

SI Flow - Hot Electron


• Allowable region for input slew and output load

Load Capacitance

Inp

ut

Tra

nsi

tio

n T

ime

Input rise time too long; causes too much short circuit current

Output rise time too long

Output load too big

Hot electrondegradation

Legal operatingarea Limit may

depend on operatingfrequency

New Design Rule for Hot ElectronEffects


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• Get raw process degradation

• Select cell EOL performance(5% timing loss over life)

• Use BTA BERT model tocompute total acceptable fluence

• Compute fluence per transitionas a function(load, slew)

• Compute Total fluence

• Replace Driver, as needed

TLF 4.0 File

slew

load

Damage/transition

Damage Limit/cell

Total fluence = fluence/transition * freq * lifetime

Hot Electron Characterization


Wire Self-Heat

l May also be called signal wire electromigrationl Wire heats above oxide temperature as pulses go

throughl Symptom: chip eventually fails when wire breaksl Depends on metal composition, signal frequency, wire

sizes, slew rates, and amount of capacitance drivenl Requires different data/formulas from power supply EM

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