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1)A high priority Interrupt has occurred while executing the third instruction. The processor jumps to the vector table location 0x0010 and from there jumps to the ISR and executes it. After completing the ISR, to which address the control would return to?

1000 MOV A, 20

1004 MOV B, 301008 MULT A, B, C100C MOV C, L1

a)0x0010b)0x0012c)0x100Cd)0x1008

Sorry, the correct answer is c. When the interrupt occurs while executing an ins

truction, it will complete the current instruction. So, after completing the ISR, the control would return to fourth instruction.

2)Which of the following task is not performed as part of the Kernel Startup?

a)Initialization of Memory Management systemb)System enters main and is ready to start C style functionc)Initialize task and inter task communication systemd)Initializes I/O sub systems

Sorry, the correct answer is b. At the end of C startup, the system is ready to

execute C style Functions. It calls the C function main() which in turn performsthe kernel startup

3)What is FALSE about HAL (Hardware Abstraction Layer)?

a)HAL helps to improve the system performanceb)It helps to port the software to different hardware.c)If HAL interfaces are defined, then concurrent development of the software andhardware design can be carried out.d)It helps to reduce the development cycle

Sorry, the correct answer is a. HAL is an abstraction layer implemented in software, between the physical hardware and the software. The wrapper code adds overhead to the underlying driver codes, making it easy from portability and usage angle, but not from performance point of view

4)What is the difference between bootloader and boot monitor?

a)Boot monitor actually performs diagnostic support in addition to boot loadingb)It can work as debug agentc)It can support in firmware upgrade.

d)All of the above.

Sorry, the correct answer is d. Boot monitor usually provides/supports all the t

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hree facilities: diagnostics,debug agent and firmware upgrade

5)DMA controller has a bus clock frequency operating at 100Mhz. It is able to do adata transfer of 4 byte data at the raising edge of the clock. How many bytes of data will be transferred by the controller in 0.5 sec?

a)400 Mbytesb)200 Mbytesc)100 Mbytesd)50 Mbytes

Sorry, the correct answer is b. The amount of data transferred in 1 sec is 4 * 100 * 10^6 and hence in 0.5 secs it is 200 Mbytes of data

6)What is False about DMA controller?

a)Is used to transfer data from one memory to another memory or from an I/O device to memoryb)It shares the system memory and bus with the CPU and has both bus master and slave capability.c)The DMA controller releases the system bus for the duration of the transfer, the process is referred as cycle stealingd)When CPU uses internal cache memory, the DMA controller can use the system memory parallely.

Sorry, the correct answer is c. The CPU actually releases the system bus for theduration of transfer, and hence it is referred as cycle stealing. All other statements are true about DMA.

7)What is not true about the block device drivers?

a)Most block devices have support for character device interfacesb)Block device classes can be used through UNIX style API's like fopen(), ioctl(), fclose()c)Block devices are those for which don't use buffer cached)All of the above

Sorry, the correct answer is c. Normally the block devices use buffer cache mechanism to improve performance.

8)Which of the following devices is preferred during the initial phase of development where there is volatility in the requirements?

a)FPGAb)ASICc)GALd)All of the above

Sorry, the correct answer is a. The manufactures normally prefer Field programma

ble Gate array during the early stage of the development because it can be reprogrammed to reflect any changes

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9)A 9600 bps serial communication link with asynchronous mode of transmission usesone start bit, seven data bits, one parity bit and one stop bit. How many characters can be transmitted per second ?

a)800

b)960c)1200d)1000

Sorry, the correct answer is b. Each character requires 10 bits (1 start bit + 7data bit + 1 parity bit + 1 stop bit) to be transmitted for each character. So, 960 characters can be transmitted over 9600 bps link.

10)A system has 8 MB of physical memory and 2048 physical pages. What will be thesize of the physical page and the virtual page?

a)2048 Bytes and 1024 Bytesb)2048 Bytes and 4096 Bytesc)1024 Bytes and 1024 bytesd)4096 Bytes and 4096 Bytes

Sorry, the correct answer is d. Physical page size = Physical memory/number of physical page = 4096 Bytes. The virtual page is same as that of physical page size

11)What is TRUE about the periodic timer?

a)In the periodic timer, count value becomes zero, it generates an interrupt tothe processor ONLY onceb)It is not possible to configure the timer as periodicc)Periodic timer can be used by the RTOS to carry out scheduling or software timer services.d)None of the above.

Sorry, the correct answer is c. In the periodic timer, when it because zero, thevalue is reloaded again and it is possible to configure the timer as oneshot orperiodic using the control registers

12)An Embedded system receives 4 signals through the 4 pins of an input port. Which of the following will be most suitable to analyze the input signals?

a)ICEb)Breakpointc)Logic Analyserd)Voltmeter

Sorry, the correct answer is c. Logic analyzer is used to track/analyze different signals simultaneously. Hence it can used to analyze 4 signals simultaneously

13)You are developing a cost effective embedded system where the LCD display is notavailable to display the error messages. Which approach you will take up to ide

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ntify the errors so that you can debug it easily?

a)Write error code in shared memory location and use those error codes for debugging.b)If file system is available, log the errors in a error_log.txt filec)Check the possibility of writing the errors in Non volatile memory

d)All of the above.

Sorry, the correct answer is d. You can write error codes in some shared memorylocation and interpret these codes to carry out debugging. If file system is available in the embedded system, you can write the error codes to a text file anduse that for debugging. You can also write it in the Non-volatile memory, so that after the system is switched OFF and powered ON you can read the error codes and perform debugging. The option can vary depending upon which is suitable/feasible for that system.

14)Identify the problem in the below code snippet. Task 1, Task2 and Task3 are of e

qual priority and the system has the time slice of 5msec. Identify the problemssee with respect to Task1,2 and 3? Assume that task 1 starts running 1st.

int write_count = 0;Task_func1 (){

Acquire write_Lock1Write to the file1Release write_lock1Write_count++

}Task_func2 (){

Acquire write_lock2Write to file 2Release write_lock2Write_count++

}Task_func3(inputbuffer, size){

Acquire Read_lockif(size is 0)return INVALID

Memorycopy(tempbuffer, inputbuffer, size)Release read_lockreturn SUCCESS

}

a)Task_func1 and Task_func2 will enter deadlock conditionb)Task_func1 and Task_func2 will enter deadlock condition and Task_func3 synchronization is not handled properly.c)Task_func1 and Task_func2 will enters race conditiond)Task_func1 and Task_func2 will enters into a race condition and Task_func3 synchronization mechanism is not handled properly

Sorry, the correct answer is d. Task_func1 and Task_func2 are updating a global

variable Write_count++, which is outside the synchronization lock. The context switch can happen at any given point while executing Task_func1 and Task_func2 resulting in wrong updation of the variable WriteCount. In Task 3, sync mechanism

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is not handled properly, i.e. the semaphore Read_lock is not released after thesize 0 condition.

15)Which of the following is most important aspect of a RTOS?

a)Deterministic behaviourb)Support for latest chipsets/processorsc)Support for modern protocolsd)None of the above

Sorry, the correct answer is a. Deterministic or predictable behaviour is the most the important aspect of the real time system. Only then, it is possible to calculate the worst case response for time critical events.

16)Which of the following is CORRECT about the initialisation of a RTOS based embedded system?

a)Kernel initialization step initializes only the internal modules of the RTOS.b)Kernel initialization creates the various RTOS resources needed by the application.c)Application Initialization is done as part of the kernel initialization.d)Application Initialization will never do any hardware initializations.

Sorry, the correct answer is a. Kernel initialization step initializes all the internal modules of the RTOS so that the RTOS is ready to service all the API calls made by the application. It does not create any resources needed by the application. Application initialisation is done after kernel initialisation. It creates all the RTOS resources needed by the application by calling the appropriate c

reate APIs. Hardware initializations are done by the boot loader. Yet, the application initialisation can also reinitialize some of the hardware according to the requirements of the application. It can initialize some of the application specific hardware which was not initialized during the boot load operations.

17)Which of the following is NOT CORRECT?

a)A task is a RTOS object/resource created inside the RTOS by calling the appropriate APIs provided by the RTOS.b)A function becomes a task when it is made as an entry function of a task by passing it as an argument to the task create API provided by the RTOS.c)A function should have an infinite loop like a while(1) loop for it to be madeas a task.d)None of the above

Sorry, the correct answer is c. A task or any other RTOS resource is an object inside the RTOS. It is created by calling the appropriate APIs provided by the RTOS. To create a task, we have to write a function. This function should be passed as an entry function to the RTOS API. It is not necessary that the function must be implemented using a while(1) loop. If the function is implemented using aninfinite loop like a while(1) loop, then it becomes a continuous running task and it never finishes it exits explicitly or killed. If it does not have a while(1) loop then the task ends after the first execution. Typically, in an embedded

application, all tasks are created using infinite loops. During initialisation phase, a single execution task may be created and used.

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18)Which of the following is CORRECT when a task t2 preempts a task t1?

a)The current register contents of the CPU are saved into the stack of the outgoing task t1 and updated by the values already saved in the stack of task t2.b)The program counter of the processor is updated with the address of the next i

nstruction of task t2c)There is only one stack pointer available in the CPU and hence there cannot bedifferent stacks available for task t1 and t2.d)When preemption happens, the CPU changes its mode. Each mode has its own stackfrom which the registers have to be updated.

Sorry, the correct answer is a. Task t1 is being preempted. Hence the current register contents of CPU will be saved in the stack of t1. t2 is the new task which is getting scheduled. Hence the registers will be updated with the values already saved in t2 stack. Each task will have a task control block(TCB) in the RTOS. One of the elements of this structure is a stack pointer (a software pointer).This will be pointing to the stack allocated to that task. The hardware stack p

ointer register will be updated with this value. Thus each task will have a separate stack to store its context. There is no hardware mode change happens when atask is preempted by another task.

19)Device A and Device B can be treated as equal priority, while Device C has a higher priority.Which two devices can be connected to the same interrupt pin?

a)Device A and Device Cb)Device A and Device B

c)No two devices can be connected to the same interrupt pin.d)Both A. and B. are true

Sorry, the correct answer is b. "Multiple devices of the same priority alone canbe connected to the same interrupt pin. This allows for boards, where number ofdevices is greater than interrupt pins."

20)Watchdog timer in a processor is used for

a)Providing timing delay in software applicationsb)Used for debugging timersc)Countdown timer, which on expiry resets the processor.d)Timer used for providing clocks at a different frequency than the system clock.

Sorry, the correct answer is c. "Watchdog timers are used for detecting deadlocked , or starved tasks or infinite loops. It is a countdown timer, which on expiry will reset the processor. "

21)Assume memory size is 256 bytes. What needs to be the minimum width of the address bus to be able to access all the values in the memory?

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a)16 bitsb)32 bitsc)8 bitsd)4 bits

Sorry, the correct answer is c. "To address 256 bytes equal to 2 power 8, we need 8 address lines. Hence address bus width should be 8 bits."

22)What is TRUE of a fetch cycle of an instruction?

a)Whichever address is present in the PC, it fetches the instruction from that address, and stores the instruction in the Instruction Registerb)Whichever address is present in the instruction register, it fetches from thataddress, and stores the instruction in the PC.c)After fetching the instruction, address contained in the Instruction registeris incremented

d)PC holds the address of the current instruction, while the Instruction register holds the address of the next instruction.

Sorry, the correct answer is a. " PC always holds the address of the instructionto be fetched. And when the data from the address held in the PC is fetched, that data, which is nothing but the instruction opcode, is stored in the Instruction Register. After fetching the instruction, PC is incremented to hold the address of the next instruction to be fetched"

23)What is TRUE about a zero address machine?

a)A zero address machine has instructions which are stored in the CPU itself andhence no operand memory address is applicable to these instructionsb)A zero address machine fetches instructions only from stack memoryc)A zero address machine fetches operands only from stackd)A zero address machine will have zero memory

Sorry, the correct answer is c. " A zero address machine have instructions likeadd , move etc which do not specify any operand address. By default the operandsare pushed and popped from/to address stored in stack pointer register, i.e from/to stack."

24)In memory mapped I/O

a)It is possible for CPU to write data into a device register by writing into specific memory locationsb)It is possible for CPU to write data into a device register by directly accessing I/O portc)It is possible for CPU to write data into a device register only through special instructionsd)It is not possible for CPU to write into device registers

Sorry, the correct answer is a. " In memory mapped I/O, the I/O registers are mapped to specific memory locations. By writing into these memory locations, usingthe normal memory load and store operations, the data is transmitted from CPU t

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o device. "

25)When a DMA transfer is happening, which of the following statements is TRUE?

a)It is possible for a CPU to read instructions from memory.b)It is possible for a CPU to read and write data into memory.c)It is possible for a CPU to be in the execute stage of an instruction.d)Both a. and b.

Sorry, the correct answer is c. " When a DMA transfer is happening the memory bus connecting the CPU and the memory is occupied in the transfer. Hence the CPU cannot do any memory reads/writes. But it will be able to do register reads, or other operations involving other hardware units within the CPU. It can perform the execute stage of the instruction pipeline, even though a DMA transfer is happening at the same time. "

26)What is the advantage of a CISC machine over a RISC machine?

a)Because its instruction set is complex, the same C code produces more assemblycode lines than in a RISC machine.b)Results in lower memory footprint.c)Pipeline is more efficientd)Instruction lengths are equal

Sorry, the correct answer is b. "CISC machines reduces number of instructions ina program. Hence it results in lesser code and lesser memory footprint "

27)Which mechanism can be used to transfer data from a CPU register to I/O port?

a)DMAb)I/O mapped I/Oc)Memory mapped I/Od)Both b. and c.

Sorry, the correct answer is d. " Both I/O mapped I/O and Memory mapped I/O canbe used to transfer data from CPU register to I/O port. In the case of I/O mapped I/O, this can be done by a special instruction, which transfers the data fromthe register to the I/O port and in the case of memory mapped I/O, the I/O portsare mapped to specific memory locations. By writing into these memory locations, the data gets transferred from register to I/O port. However in DMA, the datais always transferred to/from devices and memory, but it doesnt reach the CPU "

28)What is the advantage of Von Neumann over Harvard?

a)Instruction set will only contain equal length instructions and hence efficien

t pipelineb)CPU and memory hardware will be more simpler and cheaperc)Self modifying code is possible only in Von Neumann

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d)Both b. and c.

Sorry, the correct answer is b. "Since Von Neumann has a common bus for both instruction and data memory transfers, the hardware to send and receive data to/from memory is common. However in Harvard, these buses are separate and the hardware is more complex and costlier"

29)Which of the following is triggered due to software instruction errors like Divide by zero?

a)Interrupt service routineb)Reset vectorc)Exception Handlerd)Error handler user function

Sorry, the correct answer is c. " An exception handler is not called like a function. It is automatically called whenever there are implicit instruction executi

on errors like Divide by zero. Interrupt service routines are also not called explicitly like functions, but are called when software and hardware triggered interrupts occur. Explicit error handler functions are called by user. Reset vector is also implicitly called whenever reset pin is asserted "

30)An RTOS based application requires the RTOS to provide scheduling time slice of2msecs and software timer services of 5msecs granularity. It has to provide realtime clock(RTC)feature. But the clock should not drift its accuracy more than 1sec per day. Assume that there is only one hardware timer and it is designed tobe clocked at 10Mhz frequency.We need to select the correct timer tick, correctcounter value that needs to be loaded to the timer and also the accuracy of theclock(ppm)needed to meet the RTC requirement. Which of the following options wil

l provide the best chance of meeting all the above criteria?

a)Timer tick = 1ms;HW timer load value=10000;clock ppm value

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ystem uses a double-buffer, what should be optimal size of each buffer without losing any data?

a)0 bytesb)10000 bytesc)2500 bytes

d)1000 bytes

Sorry, the correct answer is c. "Since the data is coming in bursts of 10 ms, and in10ms, 10000 * 10 m = 100 bytes can be processed by the consumer. There are four bursts in one second and 10000 bytes being produced. Hence, there are 10000/4 = 2500 bytes being produced in a burst. Hence the processing speed is not sufficient. Hence even though the data production and consumption rate is equal inthis case, we need to provide a buffer. The buffer should be capable of holdingat least one burst size, i.e 2500 bytes. For 2500 bytes the processing time willbe 2500/10000 = 250ms. Assuming that the 10ms bursts are equally(periodically)spaced, it is sufficient to hold one burst size in one buffer. By the time the third burst arrives ( at a time of 500ms, it can overwrite the first buffer, sinc

e it is already processed at the end of the first 260ms ) Note that a single buffer will not be sufficient in this case, because by the time the second burst arrives, the first burst is not yet consumed. "

32)In an RTOS based application, which of the following is FALSE?

a)Pipes are typically used for streaming audio and video data between tasks. Themessages posted to pipes cannot be prioritised.b)Message queues are typically used for exchanging command and control information between tasks. The messages in message queues can be prioritised.c)Usually, an Event occupies only one bit in an eventgroup. Hence a 32 bit eveng

roup supports 32 events that can be used for communication between various tasks.d)None of the above.

Sorry, the correct answer is d. Pipes are used for large chunks of data to be passed across tasks while message queues are used for exchanging commands and control information. Messages in pipes cannot be prioritised where as those in message queues can be prioritised. For using an RTOS event, an eventgroup has to be created and in that eventgroup, each bit represents individual events.

33)Which of the following is TRUE?

a)From an ISR, sending message to a message queue is allowed as long as it is not a blocking call.b)Sending an event from the ISR to a task is good option since it does not blockand is also faster.

c)We cannot wait for receiving messages or events in an ISR.d)All the options are correct.

Sorry, the correct answer is d. We can send messages from the ISR to some tasksbut we should not block if the message queue is full. We can send events from the ISRs. The event sending APIs do not have blocking options and hence there areno issues. Since interrupts are asynchronous and have to be completed faster, it

is not possible to be waiting to receive a message or event in an ISR.

34)

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Which of the following is TRUE

a)A Mutex is a type of binary semaphore used for protecting critical resources from simultaneous access by multiple threads of execution.

b)When a task which has obtained a mutex, tries to acquire the same mutex again,it will acquire it successfully without getting blocked.c)If a task has obtained a mutex and a different task tries to acquire that mutex, it will block on that mutex.d)All the above.

Sorry, the correct answer is d. A Mutex is a type of binary semaphore used for protecting critical resources from simultaneous access by multiple threads of execution. The mutex remembers the task which has already acquired it and if the same task tries to acquire it again, it keeps a count of the number of such requests and allows successful acquisition. When the mutex is being released, that task has to release it that many times so that the mutex will be available for acq

uisition by any other task. If a different task tries to acquire an already acquired mutex, it will immediately block

35)

Which of the following is TRUE about the characteristics of an RTOS and amonolithic OS like Linux?

a)In RTOS and Linux, kernel mode execution is preemptible.b)In RTOS and Linux preemption happens when the time slice is over.c)Linux and RTOS are monolithic operating systemsd)None of the above.

Sorry, the correct answer is d. In RTOS, kernel mode execution is preemptible where as in Linux Kernel mode execution is not preemptible. Linux uses round robin scheduling where preemption happens only when the time slice is over whereas in RTOS it also happens when a higher priority task becomes READY. Unlike Linux,a RTOS is not monolithic. Hence its components like file system, network stacketc can be removed to get smaller memory foot print.

36)

Which of the following is FALSE about calling the scheduler of an RTOS?

a)A periodic timer interrupt has to call the scheduler function.b)Scheduler has to be called by the RTOS API which is called by the applicationc)RTOS has to call the scheduler without any assistance from the application orthe timer interrupt.d)None of the above.

Sorry, the correct answer is c. The scheduler function of the RTOS does the scheduling of the various tasks. But who calls this scheduler function? The ISR ofa periodic timer interrupt calls the scheduler periodically. This period is called the time slice. Also it has to be called whenever the RTOS API is called bythe application. Once the API completes its functionality, it will call the scheduler at the end of the API. So, it is not that the RTOS has to call the schedu

ler without the assistance of the application or the interrupts

37)

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Assume that a RTOS based multitasking application has the following 3 tasks. Allthe 3 tasks have the same priority and hence will be scheduled in round robin fashion. The time slice is 1ms.

Assume that send and receive message APIs take negligible time.Assume that context switch time is negligible. Assume task A starts first at 0thms.

List out various tasks that will be running at 1ms intervalfrom 0th to 10th ms assuming task A starts at 0th ms.

task A{

Simulate_msg()//Simulate msg from task C for the first time this

task is scheduled.Takes negligible time.while(1){

receive(msg from task C);// blocks here to get a message (except for the f

irst time)process_msg();send(msg to task B);//takes 2ms till send completes.some_more_processing()// takes 1ms

}}

task B{

while(1){

receive(msg from task A);//blocks here to get a messageprocess_msg();

send(msg to task C);//takes 2ms till send completes.some_more_processing()// takes 1ms

}}

task C{

while(1){

receive(msg from task B);//blocks here to get a messageprocess_msg();send(msg to task A);//takes 2ms till send completes.some_more_processing()// takes 1ms

}}

a)A A B A B C B C C Cb)A B C A B C A B C Ac)A A B B C C C A B Bd)A A B B C A B C C A

39)

If a function uses global variables, which of the following is true regarding the reentrancy of the function?

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a)Protect the access to each of those global variables using one or more mutex inside that function.b)Make those global variables as part of a private control block which will be used only by one task.c)If the function will be called by only a single thread of execution, then it is safe to use the global variable without any mutex protection.

d)All the above.

Sorry, the correct answer is d. If a task uses a global variable and if that variable is shared with any other task, then it has to be protected by a mutex. Ifit is not a multi tasking environment and if there are no interrupts which aresharing that variable, then there is no need for protecting the variable using mutex. Similarly, if the global variable is stored in a private data structure used only by that task, then also it need not be protected by the mutex.

40)Which of the following is TRUE?

a)Task A and Task B are in race condition if their behaviour and hence the system behavior changes based on the order in which they are scheduled.b)Race condition can be avoided by sequencing the tasks by using semaphores or messages or events.c)Deadlock condition can be avoided by enforcing an order in which the semaphores can be obtained.d)All the above.

Sorry, the correct answer is d. Two tasks can race against each other and resultin an unexpected behavior based on the order of execution. This can be avoidedby sequencing their execution by using semaphores. When using multiple semaphores, we can enforce an order in which the semaphores have to be used. This will av

oid the deadlock conditions.

41)In a priority based preemptive system, which of the following is TRUE?

a)A task which runs without blocking has to be given the highest priority.b)A task which runs without blocking has to be given the lowest priority.c)Whether it blocks or not, does not impact the decision of its priority.d)None of the above.

Sorry, the correct answer is b. A task which continuously runs without blockinghas to be given the lowest priority. Otherwise it will not allow any other tasklower than its priority to be scheduled.

42)Which of the following is TRUE?

a)Round robin scheduling is first-in-first-out scheduling without time slice.b)Priority preemptive system does not preempt a task unless a higher priority task gets ready.c)When an interrupt occurs, the scheduler switches out the current running taskand schedules the ISR.

d)None of the above.

Sorry, the correct answer is d. Round robin scheduling is first in first out wit

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h time slice. Priority preemptive systems will follow round robin scheduling among tasks of equal priority. In such a case, the preemption happens when the time slice is over. When an interrupt occurs, the CPU directly takes the control tothe interrupt vector and then to the ISR. It is not scheduled by the scheduler.

43)

Consider the following set of tasks, with the time values given in msecs.

TaskName Burst Time Arrival Time PriorityA 2 2 P1B 4 0 P2C 3 4 P2D 1 3 P3

Each task prints the numbers starting from 1, 2, 3,...,incrementing the number by 1 for every 1 millisecond it is executed. The printed number is prefixed withcorresponding task id. The system uses priority based preemption scheduler with1ms time-slice. What would be the output for this

scenario?

Note: CPU Burst time is the time a task requires to complete execution when it executes alone and has all resources required. Arrival time is the first occurrence of task execution. Also note that priority P1 is the highest priority.

a)B1 B2 A1 A2 B3 C1 B4 C2 C3 D1b)B1 B2 A1 A2 C1 B3 C2 B4 C3 D1c)A1 A2 B1 B2 B3 C1 B4 C2 C3 D1d)B1 B2 A1 A2 B3 B4 C1 C2 C3 D1

Sorry, the correct answer is a. Task B arrives at time 0 and runs for 2 ms tillTask A arrives at 2nd msec. Task A runs for 2ms and completes. Then task B runs.But task C has already arrived at 4rd msec. But it is not scheduled and only task B is scheduled because task B got preempted by task A and got into the readyqueue at the 2nd msec itself. Task B and C have the same priority. So, as per round robin Task B gets scheduled again and runs for 1msec. Then task C runs for 1msec. Once task B and C complete, the lowest priority task D gets scheduled andruns for 1msec.

44)Consider an embedded system running 3 tasks shown below. The context switching time is negligible.

What is the approximate CPU utilization of each of these tasks if they are scheduled in a round-robin fashion, if the scheduler time-quantum is 2 ms?

send_task(){

while(1){

do_something();//takes 2 msecsend_io_data();//waits for 2msec for send to be completed by the i/o devic

e}

}

receive_task()

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{while(1){

do_something();//takes 2 msecrecv_io_data();//waits for 2msec for i/o device to fill recv buffer

}}

process_data_task(){

while(1){

process_data();//Takes 4msec every time called}

}

a)Send - 17% Rcv - 17% Process - 66%

b)Send - 25% Rcv - 25% Process - 50%c)Send - 33% Rcv - 33% Process - 33%d)None of the above.

Sorry, the correct answer is b. When a task is doing a I/O bound operation, theCPU is not loaded and the I/O device is busy doing sending or receiving of data.During this time, the CPU is not being utilised. Since it is round robin, eachtask gets a time slice of 2ms per cycle. Once all tasks get one time slice, again the next round starts Here, once the send and receive tasks spend 2ms each, they are into the I/O bound mode where the CPU is not used and the I/O device is busy. During this time the send and receive tasks do not use the time slice and hence the process task gets that time also. So,for every 4 time slices, send taskuses one time slice, receive task uses 1 time slice and the process task uses 2

times slices. So, send task uses 2 out of 8 msecs, receive task uses 2 out of 8msecs and process task uses 4 out of 8 msecs.

45)

In a priority preemption RTOS based system, assume the following 3 tasks t1, t2and t3 with priorities p1,p2 and p3 respectively where p1

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lock_m2();

do_job2();

release_m2();

release_m1();

}}int t3 (void){

while (1){

lock_m1();

lock_m2();

lock_m3();

do_job3();

release_m3();

release_m2();

release_m1();}

}Will there be deadlock caused by this code? If so how to fix it?

a)No deadlock and no fix needed.

b)Causes Deadlock. Make t1 code similar to t3c)Causes Deadlock. Make t1 code similar to t2d)Causes Deadlock. Make t1 and t2 code similar to t3.

Sorry, the correct answer is b. Take all mutexes in the same order and release them in the correct order to prevent dead lock. Task t1 has lower priority than task t3. Assume that it got preempted by task t3 after taking the mutex m3. Now task t3 takes m1 and m2 and tries to take m3 and it will block since m3 is already taken by task t1. So, task t1 will get scheduled and it will try to take m2. But m2 has already been taken by task t3 and hence task t1 also will block. Thisis a deadlock condition. To fix this, change the code of task t1 to take all mutexes in the same order in which task t3 is taking and release them in the correct order to prevent dead lock. This same order has to be maintained by any othertask which tries to take these mutexes. Then we can avoid the dead locks. Task t2 does not have to change the code like that of Task t1 since it does not use m3. It uses only m1 and m2 and it is being taken in the correct order as taken bythe task t3.