3012 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 11, NOVEMBER 2008

Modeling and Fabrication of ZnONanowire Transistors

Steve J. Pearton, Fellow, IEEE, David P. Norton, Li-Chia Tien, and Jing Guo

(Invited Paper)

Abstract—ZnO is attracting attention for application in trans-parent nanowire (NW) transistors because of the ease of syn-thesis of ZnO nanostructures, their good transport properties,the availability of heterostructures, and the possibility for op-toelectronic integration. A variety of both top and bottom gaten-type ZnO NW transistors have been reported, showing generallyhigh on/off ratios (104 − 107), subthreshold voltage swings of130–300 mV/dec, and excellent drain–current saturation. Muchhigher electron mobilities and improved device stability are foundwhen surface passivation is employed, pointing to the importanceof controlling surface charge density. Simulations show that de-fects such as grain boundaries lead to a decrease of drain current.While the dc characteristics of such devices are generally reason-able, there have been no reports of the RF or high-speed switch-ing performance. Additional work is needed on optimized gatedielectrics, reliability, and functionality of ZnO NW transistors.

Index Terms—Heterostructures, nanowires (NWs), ZnO.

I. INTRODUCTION

THERE has been significant interest recently in the devel-opment of ZnO-based UV/visible light-emitting diodes

(LEDs) and transparent thin-film transistors for display ap-plications [1]–[4]. In particular, low-cost ZnO LEDs couldbe used in traffic signals, outdoor displays, backlighting inelectronic displays, automobile brake lights, indicators on elec-tronic devices, biodetectors, and general lighting applications.ZnO has a number of material advantages over GaN, includ-ing a large exciton binding energy (60 meV compared with26 meV for GaN), exceptional resistant to radiation damage byhigh energy radiation, the commercial availability of large high-quality single-crystal wafers, and simplified device process-ing because wet chemical etching is possible, unlike GaN. Atunable bandgap can be realized by alloying ZnO with CdO,

Manuscript received January 17, 2008; revised July 28, 2008. Currentversion published October 30, 2008. This work was supported by the NASAHydrogen Research Grant NAG3-2930, by the Air Force Office of ScientificResearch under Grant F49620-03-1-0370, by the Army Research Office underGrant DAAD19-01-1-0603, and by the National Science Foundation (DMR0700416, Dr. L. Hess). The review of this paper was arranged by Editor M.J. Kumar.

S. J. Pearton, D. P. Norton, and L.-C. Tien are with the Department ofMaterials Science and Engineering, University of Florida, Gainesville, FL32611 USA (e-mail: spear@mse.ufl.edu; dnort@mse.ufl.edu; lctien@ufl.edu).

J. Guo is with the Department of Electrical and Computer Engineering,University of Florida, Gainesville, FL 32611 USA (e-mail: guoj@ufl.edu).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2008.2005157

MgO, or BeO. The bandgap can be changed from 3 to 4.0 eVin Zn1−xCdxO and MgxZn1−xO alloy films with small latticemismatch. This makes it possible to realize strain-free and high-quality multiple quantum well device structures. ZnO also hasa high breakdown electric field of ∼2 × 106 V/cm and a largesaturation velocity of 3.2 × 107 cm/s at room temperature.

ZnO is generally crystallized in the hexagonal wurtzite struc-ture although metastable zincblende can be observed in somecases. The lattice parameters of wurtzite ZnO are a = b =3.250 Å and c = 5.206 Å The specific gravity is 5.72 g/cm3,corresponding to 4.21 × 1022 molecules per cubic centimeters.The ionic radii on Zn2+ and O2− are 0.60 and 1.38 Å, respec-tively, corresponding to a Zn–O distance of 1.972 Å [2]. As-grown undoped ZnO films typically show nonstoichiometry andare usually n-type [2]. Typical values of the Hall mobility atroom temperature for single crystals and polycrystalline sam-ples are about 100–200 and 1–10 cm2/V · s, respectively [2].These properties make ZnO attractive for nanowires (NWs),which have been synthesized by a wide variety of methods thatgenerally yield single-crystal material.

The ease of synthesizing ZnO-based nanostructures [4],the good transport properties, and the transparency of theZnMgCdO system have made this a natural for exploring theperformance of ZnO NW field-effect transistors (FETs). In gen-eral, these have employed metal–oxide–semiconductor (MOS)gates because of the low Schottky barrier heights (typically< 1 eV) of metals on ZnO. Both bottom and top gate geometrieshave been reported, and initial reports of simple logic circuitshave appeared [5]. In this paper, we review recent progressin the synthesis, modeling, and device performance of ZnONW FETs [6]–[31]. The strong sensitivity of the NW deviceperformance to surface quality means that it is imperative todevelop optimized passivation approaches and low interfacedensity dielectrics. We also discuss the development of onesuch dielectric in this paper.

II. SYNTHESIS OF ZnO NWs

The group at UF has focused on the growth of ZnO NWs andNWs using catalyst-driven molecular beam epitaxy [32]. Theformer process is site specific, as single-crystal ZnO nanorodgrowth is realized via nucleation on Ag or Au films or is-lands that are deposited on a given substrate surface. Growthoccurs at relatively low substrate temperatures, on the order of300 ◦C–500 ◦C, making it amenable to integration on numerous

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PEARTON et al.: MODELING AND FABRICATION OF ZnO NANOWIRE TRANSISTORS 3013

Fig. 1. Transmission electron micrograph of a ZnMgO NW grown bycatalyst-driven molecular beam epitaxy.

device platforms. With this approach, nanorod placement canbe predefined via location of metal catalyst islands or parti-cles. The NWs are semiconducting [33], exhibit strong pho-toluminescence under ultraviolet illumination [34], and havebeen implemented in a number of sensor applications [35]. Byusing this technique, the synthesis of 1-D heteroepitaxial cored(Zn, Mg)O semiconductor NWs can also be realized [36]. Thestructures form spontaneously in a Zn, Mg, and O2/O3 flux,consisting of a single-crystal Zn-rich Zn1−xMgxO (x < 0.02)core encased by an epitaxial Zn1−yMgyO (y � 0.02) sheath.High-resolution Z-contrast scanning transmission electron mi-croscopy shows core diameters as small as 4 nm, as shown inFig. 1. The cored structure forms spontaneously under constantflux due to a bimodal growth mechanism in which the coreforms via bulklike vapor–liquid–solid growth, while the outersheath grows as a heteroepitaxial layer. The cored ZnO/ZnMgONW structures have the potential to serve as self-assembledFET heterostructures.

More generally, the synthesis of ZnO NWs and nanorodshas been demonstrated using a number of techniques, in-cluding chemical vapor deposition, vapor-phase transport, gasreactions, oxidation of metal in the pores of anodic aluminamembranes, and solution-based methods [37]–[39]. Chemi-cal vapor deposition has been used both with and withoutcatalyst metal. In the former case, growth proceeds via avapor–liquid–solid mechanism. The most typical metal catalysthas been gold. Alternatively, chemical vapor deposition growthcan be achieved without metal catalysts, with growth proceed-ing via a vapor–solid process. The latter has the advantageof avoiding any contamination issues with the metal catalyst.Metal-organic chemical vapor deposition has been used forthe growth of ZnO on a number of substrates and includesinteresting results for ZnO nanorod quantum wells [40]. Inaddition, one can also achieve the growth of ZnO NWs usinga catalyst-free pulsed laser deposition technique by employinghigh temperatures and high background pressures [41]. A num-ber of groups have also reported the growth of ZnO NWs fromaqueous solution [39]. For many of these techniques, the opticaland semiconducting properties of the resulting ZnO NWs areimpressive.

III. DEVICE DESIGN AND SIMULATION

Most device modeling and simulation work on NW FETshave been focusing on Si and Ge NWs, as a potential deviceoption to sustain the Moore’s law [42]. Quantum effects and3-D electrostatic effects, which become inevitably important forNW FETs, need to be modeled. The quantum transport equationhas been solved using the nonequilibrium Green’s function(NEGF) formalism at the ballistic limit and in the presenceof scattering self-consistently with a 3-D Poisson equationunder the effective mass approximation [43]. For NWs with adiameter larger than 5 nm, the effective mass approximationworks well. For NWs with even smaller diameters, atomisticdetails, however, can become important, and the effective massapproximation can break down [44]. Tight-binding atomisticsimulations have been reported to model atomistic scale fea-tures for silicon NW transistors [45]. Simulation of Si and GeNW FETs is beyond the scope of this paper, but it provides thecontext for discussing the simulation of ZnO NW FETs.

For ZnO NW FETs, simulations of the gate insulator ca-pacitance [11], diffusion transport [46], and the effect of grainboundaries [23] have been reported. In this section, we firstextend the NEGF simulation approach to model quantum trans-port and ballistic performance limits of ZnO NW FETs. Diffu-sive transport and the grain boundary (GB) effect are modelednext. As the channel length increases, the device performanceis limited by scattering and nonideal effects, such as grainboundaries.

The modeled device has an intrinsic ZnO NW channel witha diameter of 5 nm, and the source and drain extensions are n+

doped. The gate insulator thickness is 5 nm, and the dielectricconstant is κ = 10 [19]. An effective mass description (withan electron effective mass of m∗ = 0.318) is used. The carriertransport equation is numerically solved self-consistently witha 3-D Poisson equation. A mode space method is used toreduce the computational cost [47]. The mode space approachdecouples the 3-D carrier transport equation to a 2-D quantumconfinement problem in the cross section of the NW, whichis solved by a 2-D Schrödinger equation and a 1-D transportproblem along the NW axis [43]. For ballistic transport, the1-D transport equation is solved using the NEGF formalismfor each mode (subband). In the diffusive transport regime, thedrift-diffusion equation is solved for each subband.

Quantum confinement and quantum interference effects areobserved in the ballistic simulation results. Fig. 2(a) showsthe local density of states (LDOS) in the cross section of theNW for the lowest subband and the second lowest subband.For the lowest subband, the LDOS has the maximum valueat the center of the NW and decreases isotropically as theradius increases. The second mode is twofold degenerate, andits LDOS has two symmetric maximum values. Fig. 2(b), whichshows the LDOS along the transport direction, shows quantuminterference patterns between the injected electron wave (fromthe source or drain contact) and the wave reflected by thepotential barrier in the channel. The LDOS plot also showscarrier injection from multiple subbands, which indicates anenergy spacing of ∼100 meV between the lowest subband andthe second lowest subband for a simulated diameter value of

3014 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 11, NOVEMBER 2008

Fig. 2. (a) Quantummechanically confined electron modes in the cross sectionof the NW. (b) LDOS along the ZnO NW channel. The solid line shows the firstconduction subband edge as a function of the position. The channel length is25 nm in the range of 20 nm < x < 45 nm.

5.0 nm. Because the energy spacing is larger than the thermalenergy at room temperature, carrier transport is quasi-1-D.The energy spacing between the subbands decreases inverselyproportional to the NW diameter square. For a ZnO NW witha diameter larger than 10 nm, the energy spacing betweenthe subbands becomes comparable or smaller than the room-temperature thermal energy.

We next compare the different gate geometries of the ZnONW FET. Fig. 3(a) shows a coaxial gate geometry and a planargate geometry. The coaxial gate geometry is ideal for efficientgate electrostatic control and could be achieved by a verticalNW FET structure. On the other hand, a planar gate geometryis easier to be fabricated for a horizontal FET structure andhas been experimentally demonstrated for ZnO NW FETs [19].Fig. 3(b) shows the ballistic transfer characteristics of the coax-ial structure and the planar structure. A common off-current of∼1.0 nA is specified for a fair comparison, which is achievedby engineering the work function of the metal gate for each gategeometry. The subthreshold swing of the coaxially gated FET isslightly smaller than that of the NW FET with a planar gate, dueto better gate electrostatic control and suppressed short channeleffects. The advantage of the coaxial gate geometry is largerabove the threshold. The transconductance of the coaxial gatedevice is about a factor of two larger than that of the planargate device FET due to a larger gate capacitance. The coaxialgate geometry is preferred in terms of a larger transconductanceand a smaller subthreshold swing.

We next explore the effect of GBs in the diffusive transportregime. The GB is assumed to be in the cross section perpendic-ular to the NW with spatially uniformly distributed trap states,and a Gaussian distribution near the middle of the ZnO bandgap over the energy scale [23]. The states below the middlegap energy are assumed to be donorlike, and those above themiddle gap energy are acceptorlike. The trap states are filled

Fig. 3. Comparison of the gate geometries. (a) Schematic cross sections ofthe coaxially gated geometry and the planar top gate geometry. (b) Simulatedballistic ID versus VG characteristics for the ZnO NW FETs with (solid) thecoaxial gate and (dashed) the planar gate on (left) the log scale and (right) thelinear scale. The gate insulator thickness is 5 nm, and the dielectric constant isκ = 10. The channel length is 25 nm.

according to the quasi-Fermi level at each channel position.Fig. 4(a) compares the simulated ID versus VG characteristicsat VD = 0.5 V for a channel length of Lch = 1.0 μm withoutany GBs (the dashed line) and a channel with a single GB atthe middle of the channel (the solid line). The GB results ina decrease of the source–drain current and an increase of thethreshold voltage. Fig. 4(b), which compares the first subbandprofiles, shows voltage drops across the GB. The voltage droplowers the electric field in the rest part of the channel and thesource–drain current.

To explore the effect of multiple GBs, the current–voltage(I–V ) characteristics were simulated by varying the number ofequally spaced GBs in the channel. Both the on-current and theoff-current decrease as the number of the GBs nGB increases.As discussed earlier, the GBs increase the threshold voltage ofthe transistor. In order to separate this effect from other effectsdue to the GBs, we compared the ID versus VG characteristicsfor nGB = 0, 10, and 50 at a specified common off-current, asshown in Fig. 5(a), by shifting the ID−VG characteristics alongthe x-axis. Fig. 5(b), which shows the same characteristics ata linear scale, indicates that the on-current of the FET withnGB = 10 is approximately the same as that in the absence ofGBs if a common off-current is specified. The on-current of theFET with nGB = 50, however, is only about 60% of the value.The effective channel mobility, which can be extracted from theI–V characteristics above the threshold, remains approximatelyunchanged for nGB = 10 and decreases by about 40% fornGB = 50. For a small number of GBs, the effect of the GBs onthe I–V characteristics is essentially increasing the thresholdvoltage. As the number of the GBs increases, the GBs result in

PEARTON et al.: MODELING AND FABRICATION OF ZnO NANOWIRE TRANSISTORS 3015

Fig. 4. Effect of a single GB [23]. (a) ID versus VG at VD = 0.5 V. (b) First subband profile at VD = VG = 0.5 V for (the dashed lines) a single-crystal ZnONW channel and (the solid lines) a channel with one GB. A single GB with a trap density constant of NT0 = 8 × 1013/cm2 exists at the middle of the channel.The channel length is 1 μm.

Fig. 5. Effect of multiple grain boundaries [23]. The ID versus VG characteristics with the same VT specification (a) on the linear scale and (b) on the log scaleat VD = 0.5 V for a channel (the dashed line) without GBs, (the dash–dot line) with ten equally spaced GBs, and (the solid line) with 50 equally spaced GBs. Thechannel length is 1 μm. A common off-current is specified by adjusting the threshold voltage of each ZnO NW FET.

both the increase of the threshold voltage and the decrease ofthe effective channel mobility [23].

The modeling of ZnO NW FETs has evolved to a stagethat 3-D electrostatics, quantum effects, diffusive transport, andGB effects can be treated, and the dc device characteristicscan be modeled. Future work needs to address the followingissues. The surface and the interface, for example, betweenthe NW and the gate insulator, need to be better modeledand understood. The understanding, particularly at the atom-istic scale resolution, is useful for understanding the sensingmechanisms of the ZnO NW chemical and biological sensors.Bipolar transport characteristics and excitonic generation andrecombination need to be simulated and explored for ZnO NWoptoelectronic devices. The simulation of switching and RFcharacteristics is needed for understanding and optimizing thespeed of ZnO NW FETs. Measuring wavefunction modes inthe cross section of an NW is experimentally very challenging,and as a result, no such experiments have been reported sofar. Nevertheless, we note that our simulation conclusion ofthe low-dimensional effects, which become important as thediameter decreases to about 5 nm, can be readily tested in futureexperiments.

IV. DEVICE ISSUES AND PERFORMANCE

As described earlier, most publications on ZnO NWFETs have focused on the use of MOS gates, based onSiO2. We have found that a gate oxide of amorphous(Ce0.33Tb0.67)MgAl11O19 actually produced the lowest inter-face state density on undoped ZnO thin films, suggesting thatthey are also applicable to NWs for improved channel modu-lation. Since surface states are so important in NW transistors,

it is desirable to have low interface state density systems forthe gate dielectric. To establish the properties of this interface,the oxide with 200 nm thickness was deposited on undopedZnO films by pulsed laser deposition at 100 ◦C and a capacitorformed using Al contact (Fig. 6, top). Fig. 6 (center) showsthe hysteresis curve of the capacitance–voltage (C–V ) plots,indicating that there is little hysteresis effects in the MOSstructure. The dielectric constant for the amorphous CTMA wasdetermined to be ∼10, which is similar to that of Al2O3. Thebottom of Fig. 6 shows the leakage current density of CTMAas a function of applied voltage. A low leakage current of10−6 A/cm2 was obtained at the applied voltage of 5 V.

Fig. 7 shows the interface trap density of MIS diode between(Ce, Tb)MgAl11Ox and undoped ZnO thin films using theTerman method [48]. From the fact that interface traps donot respond to the ac voltage in high-frequency C–V mea-surements, high-frequency capacitance can be expressed asCHF = (CoxCs)/(Cox + Cs) because interface traps respond tothe varying dc gate bias. The interface trap density of MIS diodewas determined to be ∼1 × 1010 eV−1 · cm−2 near the conduc-tion band edge. This Terman method is generally considered tobe useful for underestimating interface trap density due to itslimitation of insufficient high frequencies.

By using this gate oxide, top-gate NW transistors werefabricated [19]. Fig. 8 shows scanning electron microscopy(SEM) micrographs of the completed devices, using NWs thatwere grown by molecular beam epitaxy and then dispersedonto Si substrates. The wire diameter was 30–50 nm, thechannel length was 2 μm, and both gate–source and gate–drainspacing was 2 μm. The dielectric thickness was 50 nm. Typicaldc characteristics are shown in Fig. 9 which displays thedrain-current–drain-voltage (ID−VDS) characteristics and the

3016 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 11, NOVEMBER 2008

Fig. 6. (Top) Schematic of MOS diode with top electrode diameter of200 μm, (center) 1-MHz C–V characteristics of MOS diode using undopedZnO as a semiconducting layer with electrode area of 3.14 × 10−4 cm2, and(bottom) I–V characteristics of same MOS diode.

Fig. 7. Interface trap density of MOS diode between (Ce0.33,Tb0.67)MgAl11O19 and undoped ZnO using Terman method.

transfer characteristics measured at room temperature under366-nm illumination. The use of illumination provides en-hanced carrier concentration in the channel and larger devicecurrent by a factor of roughly two in our case. The modulationof the channel conductance indicates that the operation of thedevice is an n-channel depletion mode. The gate leakage current

Fig. 8. SEM micrographs of ZnO NW FETs showing (top) contact pads and(bottom) close-up of active region.

Fig. 9. (Top) Transfer and (bottom) IDS−VDS characteristics of ZnO NWFET at room temperature measured with illumination from UV (366 nm) light.

is low, and the NW MOSFETs exhibit excellent saturationand pinch-off characteristics, indicating that the entire channelregion under the gate metal can be depleted of electrons. The

PEARTON et al.: MODELING AND FABRICATION OF ZnO NANOWIRE TRANSISTORS 3017

TABLE ISUMMARY OF DEVICE PERFORMANCE OF VARIOUS GEOMETRIES OF ZnO NW TRANSISTORS

threshold voltage is ∼3 V with a maximum transconductanceof ∼5 mS/mm. The on/off-current ratio at VD of 10 V wason the order of 125 [19]. The field-effect mobility μFE canbe determined from the transconductance using the relationIDS = (W/L)μFECOX(VGS − VT )VDS, where W is the chan-nel width, L is the channel, COX is the gate oxide capacitance,and VT is the threshold voltage. The extracted mobility was∼3 cm2/V · s. The carrier concentration in the channel isestimated to be ∼1016 cm−3.

Table I summarizes recent reports of the dc performanceof ZnO NW FETs. While MOSFETs are the most com-mon approach, there are a few reports of metal gate devices(MESFETs). The most common geometry is a bottom gateusing the SiO2 on an underlying Si wafer, although the topgate approach allows for individual addressing of devices. Theon/off ratios are generally above 106, and the subthreshold volt-age swing is in the range of a few hundred millivolts per decade.A noticeable feature is the wide variation in reported field-effect mobilities. A common theme is that higher mobilities areobtained on devices with surface passivation [13], usually SiO2

or in some cases polymers such as poly(methylmetahacrylate)[26]. Passivated devices show higher mobility and less varia-tion in threshold voltage than unpassivated devices, and thishas been ascribed to a reduction in surface traps [26]. Thesensitivity of the dc characteristics of the NW FETs to thepartial pressure of oxygen in the measurement ambient has beenused to advantage in fabricating oxygen sensors [18]. High off-currents and threshold slopes are often observed and ascribedto interface states at the ZnO/dielectric interface and incomplete

gating effects due to the cylindrical geometry of the NW and thequasi-planar nature of the gate contact [31]. Both enhancementand depletion mode operations have been demonstrated [9].ZnO NW FETs exhibit Hooge’s constants around 5−10−3

obtained from the gate dependence of noise amplitude, and thisis comparable to that obtained with CMOS Si [22]. The noisespectra have a classic 1/f dependence at room temperature [7],[22]. The devices show excellent radiation hardness to highenergy protons of the type encountered in low earth orbit andare promising for space-based applications [14]. It is commonfor reports of significant changes in threshold voltage andoff-current as a result of repeated measurement sweeps [12],indicating the role of trap states at the ZnO/gate oxide interface.Control of threshold voltage variation and minimal leakage cur-rents are, of course, the key requirements for integrated circuitapplication of NW transistors. At this stage, generalization andcomparisons of the existing literature about NW FETs are stilldifficult because of the different geometries, dielectrics, andabsence of many standard device parameters in the variousreports. This will improve as the science matures.

To date, there have been no reports of the RF or high-speed switching performance. This is important because it willestablish the effect of parasitic capacitances on the high-speedperformance of NW transistors. In other words, having a veryshort gate length is not the only parameter that determinesswitching speed, and it is also important to establish the ef-fect of contact pads on the maximum frequency of oscilla-tion and also determine the high field mobility in the devicechannel.

3018 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 11, NOVEMBER 2008

V. FUTURE WORK

The ability to grow NWs with techniques that are consid-erably less costly than conventional molecular beam epitaxyand metal-organic vapor deposition (the tools of choice forthin films) and at lower temperatures is one advantage, and ofcourse, the freedom to transfer the NWs to any other substrate,including cheap ones such as glass, is another advantage. Aclear advantage seems to reside in the low power require-ments of ZnO NW transistors, particularly when coupled toa simple fabrication scheme that involves contacting multipleNWs. There needs to be more emphasis on measuring thetype of routine transport properties (carrier density, mobil-ity, resistivity, and temperature dependence of resistivity) forNWs that are common for thin films. The measurement ofsurface recombination velocity and effects of various surfacetreatments is lacking. There is certainly room for investigatingcoaxial heterostructure NW FETs because of the natural carrierconfinement and surface passivation. The reproducibility ofmeasurements and the stability of NW properties as a functionof measurement current density are also largely absent to date.There is a paucity of data on higher levels of device integration,e.g., small-scale circuits involving a few dozen NW transistorsand on-chip resistors, capacitors, and inductors.

ACKNOWLEDGMENT

The authors would like to thank Prof. F. Ren, Y.-W. Kwon,and H. S. Kim for technical discussions.

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Steve J. Pearton (A’91–SM’93–F’01) received thePh.D. degree in physics from the University ofTasmania, Hobart, Australia.

He was a Postdoctoral Fellow with the Universityof California, Berkeley, prior to working at AT&TBell Laboratories, Murray Hill, NJ, from 1994 to2004. He is currently a Distinguished Professorand an Alumni Chair of the Department of Materi-als Science and Engineering, University of Florida,Gainesville. His research interests include the elec-tronic and optical properties of semiconductors.

Prof. Pearton is a Fellow of the AVS, ECS, TMS, and APS. He was therecipient of the 2007 J.J. Ebers Award from IEEE.

David P. Norton received the Ph.D. degree in elec-trical engineering from Louisiana State University,Baton Rouge, in 1989.

Since 2000, he has been with the University ofFlorida (UF), Gainesville, where he is currently aProfessor with the Department of Materials Scienceand Engineering and the Director of the Nanofabri-cation Facility. Prior to joining UF, he was with OakRidge National Laboratory for eight years, where hewon numerous awards. His research interests includeelectronic oxides and nanostructured materials and

devices.Prof. Norton is a Fellow of AVS and APS.

Li-Chia Tien was born in Taipei, Taiwan, R.O.C.,in 1976. He received the B.S. degree in chemistryand the M.S. degree in materials science and en-gineering from the National Tsing Hua University,Hsinchu, Taiwan, in 1999 and 2001, respectively. Heis currently working toward the Ph.D. degree in theDepartment of Materials Science and Engineering,University of Florida, Gainesville.

His research interests center on the synthesis of1-D semiconductor and fabrication of nanometer-scale devices.

Jing Guo received the Ph.D. degree in electricalengineering from Purdue University, West Lafayette,IN, 2004.

He is currently an Assistant Professor in electri-cal engineering with the Department of Electricaland Computer Engineering, University of Florida,Gainesville. His current research interests includemodeling and simulation of nanodevices, carbonnanotube and graphene electronics and optoelec-tronics, nanowire electronics, and device physicsof nanotransistors. He is the coauthor of the book

Nanoscale Transistors: Device Physics, Modeling, and Simulation (Springer-Verlag, 2006).

Dr. Guo has served in the technical program committees of the InternationalElectron Devices Meeting and the Device Research Conference.