Vidyabhushan Mohan

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Introduction Motivation Overview of FlashPower and FENCE NAND Flash Memory Primer FlashPower – Modeling and Validation FlashEnduraNCE – Modeling and analysis Conclusion Future Work

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Solid State Memory – Early 80s

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NAND

FLASH

Systems have different requirements

Power

Performance

Reliability

Need – Flash Modeling tools.

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5

Device level

System level

+ Device level characterizations. + Device level optimizations.

- Cannot be directly translated to system performance.

+ Use as one single value. + Device independent analysis.

- Cannot isolate the effect of device parameters

Architecture level

+ Abstract device-level details. + Explore design space. + Parameterizable. + Use with other simulators.

Power

Impacts capacity and performance

New hybrid memory systems

Endurance

Impacts the deployment of NAND Flash

Simplistic endurance estimates

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FlashPower

Model power consumption of a NAND Flash chip

Parameterized

Integrated with CACTI 5.3

FlashEnduraNCE (FENCE)

Stress and Recovery Model

Quantify the benefit that recovery can provide

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Introduction Motivation Overview of FlashPower and FENCE NAND Flash Memory Primer FlashPower – Modeling and Validation FlashEnduraNCE – Modeling and analysis Future Work Conclusion

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10 The threshold voltage of the FGT is small

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FN

Tunneling

Trapped

ChargesDissipate

Energy

Increases the threshold voltage of the FGT

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FN

Tunneling

Dissipate

Energy

Decreases the threshold voltage of the FGT

Flash Page Pass

transistors 13

Page

decoder

Flash String

SSL

GSL

SL

Block

Decoder

Block 1

Block

n-1

Block 0

Buffer

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Dies =>Planes + Buffer =>Block =>Pages

Introduction Motivation Overview of FlashPower and FENCE NAND Flash Memory Primer FlashPower – Modeling and Validation FlashEnduraNCE – Modeling and analysis Future Work Conclusion

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Powered Off

Pre-charge state

Erase state

Program state

Read state

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Page

decoder

Vpre Vpre Vpre

0V

0V

0V

Floating

0……………………………………….0

SSL

GSL

SL

Epre = Ebl,pre

18 +Ep-pre Eunselected-page,p+

Nloop*( Edec,p+ Ebuffer+ Eiopins+

0V Vcc 0V

Vcc

0V

Vcc

Vpgm

Vpass

Block

Decoder

Block 1

Block

n-1

Block 0

Buffer

GSL

SSL

SL

Eprogram=

Eselected-page,p+ Eblip,p+ Ebl,p+

Esl+ Everify-program )

Physical

Address

Page

decoder

Flash Memory Characterization – Grupp et al, MICRO 2009.

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Chip

Name

Capacity

(Gb)

Page

size (B)

Pages/

Block

Blocks/

plane

Planes

/die Dies

A2 2 2112 64 1024 2 1

A4 4 2112 64 4096 1 1

A8 8 2112 64 4096 2 1

B2 2 2112 64 2048 1 1

B4 4 2112 64 2048 2 1

0

0.5

1

1.5

2

A2 A4 A8 B2 B4

En

erg

y (u

J)

Chip Name

Energy per read operation

Measured

Modeled

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Error bars depict energy variation based on value of bits.

0

5

10

15

20

25

30

A2 A4 A8 B2 B4

En

erg

y (u

J)

Chip Name

Energy per program operation

Measured

Modeled-2 Partial

Program Cycles

Modeled-4 Partial

Program Cycles

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Error bars depict energy variation based on value of bits.

Energy dissipated for programming zeros Energy dissipated for programming ones

0

50

100

150

200

250

A2 A4 A8 B2 B4

En

erg

y (u

J)

Chip Name

Energy per erase operation

Measured

Modeled -

Tunneling on 50%

cells

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Error bars depict energy variation based on value of bits.

Introduction Motivation Overview of FlashPower and FENCE NAND Flash Memory Primer FlashPower – Modeling and Validation FlashEnduraNCE – Modeling and analysis Future Work Conclusion

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Stress Model Recovery Model When do the failures occur? Impact of detrapping on endurance Analysis of SSD level Endurance

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Stress Model

Program and Erase operations are stress events

Results in charges trapped in tunnel oxide.

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Initial State

During Programming

- -

- -

-

- -

- - - - - - - -

During Erasure

Programmed State

Erase State

- -

- -

- - TRAPPED

CHARGES

Recovery model

Quiescent period between stresses

Some charges get detrapped

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- - -

- -

- -

- -

Programmed State – After detrapping

- - -

- -

- -

- -

Programmed State – Before detrapping

- - -

During quiescent

period

- - -

Increase in threshold voltage due to stress -∆Vth,s = C1 * cycle0.62 + C2 * cycle0.30

Decrease in threshold voltage due to

recovery - ∆Vth,r = C3 * ln (∆Vth,s ) * ln (t)

Effective increase in threshold voltage - δVth = ∆Vth,s - ∆Vth,r

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Failure when δVth = ∆Vth

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∆Vth = 1.7V for SLC and 0.65V for MLC

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32 GB Enterprise SSD is modeled

Like Intel-X25E

Disksim –Storage System Simulator Enterprise workloads – from Microsoft

LM – Live Maps

RAD – Radius Authentication Server Workload

EXCH – Mail Exchange Server Workload

MSNFS – MSN File System Workload

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0

20000

40000

60000

80000

100000

120000

140000

160000

180000

LM RAD EXCH MSNFS

No of P/E Cycles per workload over a 5 year period

No of P/E Cycles

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0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

LM RAD EXCH MSNFS

δV

th(V

)

Workloads

Change in δVth over a 5 year period for different workloads

Change in δVth

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Contribution: Architecture level modeling tools FlashPower

Measure energy dissipated by NAND Flash chips

Results validated with 5 chips

Insights into relationship between value of bits and energy dissipation

FENCE Stress and recovery model

Quantify the impact of detrapping on Endurance

Analyze SSD-level Endurance

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FlashPower

Extension to support MLC flash memory

Validate FENCE with real chip measurements Analyze the impact of temperature on

endurance Comprehensive analysis of flash memory

reliability by studying

Bit Error rates

Data retention

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Vidyabhushan Mohan, Sudhanva Gurumurthi, Mircea R. Stan. FlashPower: A Detailed Power Model for NAND Flash Memory. Design Automation and Test in Europe (DATE) ’10.

Vidyabhushan Mohan, Taniya Siddiqua, Sudhanva Gurumurthi and Mircea R. Stan. How I Learned to Stop Worrying and Love Flash Endurance. HotStorage’10. Under Submission.

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Sudhanva Gurumurthi Mircea R. Stan Taniya Siddiqua Joe E. Brewer – University of Florida Koji Sakui – Intel, Tohoku University Laura Grupp – University of California, San

Diego Steve Swanson – University of California, San

Diego

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Increase in threshold voltage due to stress -∆Vth,s

∆Vth,s = (∆Nit + ∆Nit) * q/ Cox

∆Nit = 0.08 * cycle0.62

∆Not = 5 * cycle0.30

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Decrease in threshold voltage due to recovery - ∆Vth,r

∆Vth,r = 0.6 * ln (∆Vth,s ) * ln (t)

FENCE – Endurance Model

δVth = ∆Vth,s - ∆Vth,r

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Page

decoder

Block

address

Page

address Vpre Vpre Vpre

Vread

Vread

0V

0V

Vread

100………………..0..…………1

Block

Decoder

Block 1

Block

n-1

Block 0

Buffer

SSL

GSL

SL

Eread= Edec,r+ Eselected-page,r+ Eunselected-page,r+ Esl+ Ebl-1,r+ Ebuffer+ Eiopins+ Er-pre

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Page

decoder

Block

address

β * Vera

Vera - Vbi

0V

Block

Decoder

Block 1

Block

n-1

Block 0

Buffer

GSL

SSL

SL β * Vera

Vera - Vbi Vera - Vbi Vera - Vbi

Eerase= Edec,erase+ Esl+ Ewell+ Ebl,e+ Nbits-0* Etunnel,mc+

Everify-erase + Er-pre

Bias voltages for read, program and erase

Doping level of NAND block P-well and N-well

Number of partial program cycles Capacitance of I/O pins – 5pF

Reference: J.E. Brewer and M. Gill, editors. Nonvolatile

Memory Technologies with Emphasis on Flash. IEEE Press,

2008. 45

Required Inputs – represents micro-architecture of a Flash chip

Feature size of FGTs

Page size – data area + spare area

Pages per block

Blocks per plane – can be 2 dimensional

Operating voltage of the chip

Optional Inputs

Read, program and erase and pre-charge voltages

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Controller

+ FTL

DRAM ECC

NAND

Flash

Memory

Array

NAND Flash Chip

Decoders

Dec

od

ers

Address

bus

Page

buffer

1. Get

Erase

address Data

bus

2. Send addr

Status

register

4. Send command

3