144

Modeling and Simulation

SEM of the Si Field Emitter tip. (Courtesy of S. D. Senturia and A. I. Akinwande)

145

Modeling and Simulation

• Modeling of Advanced Device Structures

• MOSFET Scaling and Device Design for Low Temperature Operation

• First-Order CMOS Device Model

• Efficient 3-D Interconnect Analysis

• Numerical Techniques for Integral Equations

• Modeling the Effect of Interconnect Variation on Circuit Performance

• Simulation Algorithms for RF Circuits

• Software Tools for Process-Sensitive Reliability Assessments of IC Designs

• Modeling of Grain Growth in Thin Films

• Modeling of Interconnect Reliability

• Simulation of Electromigration-Induced Failure of IC Interconnects

• Electric Field Simulations for Field Emission Devices

• Simulation Tools for Micromachined Device Design

146

continued

As MOSFET dimensions are reduced to the submicronlevel, the electrical performance is critically dependenton the two-dimensional (2D) distribution of dopantconcentrations in the semiconductor. In order toaccurately characterize, predict, and control the devicetopology, and therefore the device behavior, it isessential to obtain an accurate description of the 2Ddoping profile. Moreover, knowledge of an accurate 2Ddistribution enables one to calibrate transport andmobility models, making possible accurate devicesimulations.

However, the lack of a mature 2D doping profilingtechnique has been an obstacle in achieving such goals.Here, we have demonstrated a modern, comprehensivetechnique for the extraction of 2D profiles in submicronMOSFETs: inverse modeling. The main advantages ofthis technique include: (1) the ability to extract 2Ddoping profiles (including effective channel length) ofvery small devices (down through sub-100 nm); (2)immunity to parasitics; (3) low dependence on mobilitymodel; (4) non-destructive measurement; and (5)simplicity of data preparation and ease of use. Datafrom subthreshold I-V characteristics is a strong func-tion of doping and can accurately determine a profile,especially near the channel. Data from Cgds-V curvespromises to provide more information (and thus moreaccurate and faster convergence) near the source/drainregions.

The approach of inverse modeling is flexible and can beused to engineer sub-100 nm devices. For instance, onemay specify various desired electrical properties (e.g.,high drive current, low DIBL, low off current) andgenerate a doping profile that will achieve these results.Hence, a set of “well-tempered” devices (those withdesirable characteristics) in the sub-100 nm regime arebeing created which will be used to compare advancedsimulation techniques and models. Also, the techniquehas been applied to a variety of device structures,including asymmetric designs.

We have applied the inverse modeling technique to theSuper-Steep Retrograde (SSR) devices fabricated at MIT.The extracted profile of a 0.1 um effective channel lengthdevice is shown in Figure 1. We have also demonstratedthe accurate device performance prediction capabilitythat is possible with this technique, once appropriatemobility models have been calibrated. Figure 2 shows acomparison between the measured and predicted I-Vcharacteristics of a 0.1 um channel length SSR device.The potential power of this method is apparent.

Modeling of Advanced Device Structures

PersonnelI. J. Djomehri, Z. Lee, M. B. McIlrath (D. A. Antoniadis)

SponsorshipSRC

Fig. 1: Extracted 2D doping profile of a SSR device havingsource/drain halo dopings. The device has Lgate = 0.1µm,tox = 50 A, and W = 10µm.

147

continued MOSFET Scaling and DeviceDesign for Low TemperatureOperation

PersonnelK. M. Jackson, A. Lochtefeld(D. Antoniadis)

SponsorshipDARPA, SRC

Lowering the operating temperature of a device has longbeen viewed as a way to extract the ultimate perfor-mance out of a given gate length device. This project isexploring the concept of using temperature as a scalingparameter to eliminate the ever more pressing tradeoffbetween device performance and leakage current (Ioff).In addition to describing a general device design space,this project is exploring the tradeoff between perfor-mance at lower operating temperatures and testability atroom temperature.

The traditional parameters for device design, channeldoping and oxide thickness, have little effect on theinverse subthreshold slope. Thus as the thresholdvoltage is scaled, the device’s off-current increases.However, since the inverse subthreshold slope is propor-tional to absolute temperature, scaling temperature bythe same factor as Vth will keep Ioff constant (Figure 3).

Fig.3: Schematic comparison of Ids-Vgs curves of an initial design to ascaled design (L & Vth) demonstrating the constant Ioff possible withlower operating temperatures.

Fig. 2: Comparison between measured and predicted I-V characteristics using calibrated mobility models. The device has a SSR channelprofile with L = 0.1 µm, tox = 50 A, and W = 10 µm. Simulated dataare denoted by symbols.

148

In order to map out the design space of Ioff

and perfor-mance, optimizations constrained by three differentscaling scenarios were used to create device designs forchannel lengths from 220 nm to 40 nm. The optimiza-tions used a set of analytical equations for short channeldevice characteristics which have been shown to matcha family of N-MOSFETs from Leff=5 mm to 100 nm, andthus model SCE and velocity saturation well.

Fig. 4A: Comparison of switching speed (FOM=I/CV) for the threedifferent scaling scenarios.

Fig. 4B: Corresponding Ioff of the worst case device (0.8Leff) for thescaling scenarios in Figure 4A.

The results of these optimizations are shown in Figure 4A&B with each point having a unique Vdd, tox, and Nbthat give the characteristics shown. The results showthat fixing Ioff (Vth does not decrease) yields a figure ofmerit (I/CV) that scales more slowly than 1/L, whilescaling Vth with Vdd (a constant field scaling like ap-proach) yields a FOM that grows at 1/L as would beexpected, but gives unacceptably high off-currents(Figure 4B). In the scaled temperature scenario, whereT, Nb, and Vbs (substrate bias) are free to be adjusted(Vdd and tox are the same as the scaled Vth case), boththe fixed Ioff and scaled Vth constraints can be met. Theresulting performance is up to 1.6x that of the scaled Vthscenario, because of the increased mobility and satura-tion velocity at lower temperatures.

To further investigate the design space for 50 nmchannel lengths, a set of simulations using the 2-Dnumerical device simulator MEDICI were performed.Device designs using a non-uniform channel dopingcreated with either Halos or a SSR profile were picked toachieve a low threshold voltage (Vth) at low tempera-ture (using a forward biased Vbs) as well as to a reason-able off-current at room temperature (using a reversebiased Vbs) which would allow room temperaturewafer-level tests and even burn-in of circuits.

The results of these simulations suggest a tradeoffbetween performance at low temperatures and off-current at room temperature (Figure 5). Devices withheavier sub-surface doping have a large back-bias (Vbs)control, which results in a greater ability to lower theoff-current at room temperature. However, thesedevices have significantly higher drain capacitances andslightly lower drive currents than devices with lowersub-surface doping, resulting in lower performance.

continued

continued

149

Fig. 5: Room temperature Ioff (with substrate bias) versus deviceperformance at 90K for 9 different 50nm devices, illustrating thetradeoff between low temp. performance and room temp. testability.

continued

CMOS device design is usually carried out using com-plex two- and three-dimensional device modeling tools.While these tools provide an accurate simulation envi-ronment, they require a complex grid managementsystem and a large number of input parameters, whichoften times, are not accurately known. There is a needfor a simple, first-order device model that can be used inroad map planning, sensitivity analysis, and microelec-tronics education.

In this project, we are constructing an analytical frame-work to form the basis for a compact and efficientphysics-based device simulation environment forCMOS. Over the years, a wealth of analytical modelshave been developed to describe a variety of MOSFETdevice physics aspects. The range of applicability ofthese models is often limited. As a consequence, it isessentially impossible to develop a simple analyticalformulation that can be reasonably accurate for anychoice of device parameters. To overcome this diffi-culty, our model is constructed to be reasonably accuratefor “well-designed” devices, since these are the onlyones that eventually reach the manufacturing stage. Awell-designed device is a device with sufficient electro-static integrity, that is, good isolation between theoutput and the input. The demand of good electrostaticintegrity substantially narrows down the range ofrequired models and simplifies their development.

Using only five input parameters: polysilicon gatelength, effective channel length, oxide thickness, junc-tion depth, and well doping level, we have demon-strated that an analytical first-order CMOS device modelhas the capability of predicting key device figures ofmerit for digital applications. The simplicity of themodel makes it easier to understand the role of impor-tant parameters in the design process and the trade-offsthat device designers face.

First-Order CMOS Device Model

PersonnelT. Payakapan (J. A. del Alamo)

SponsorshipSRC

continued

The design space evaluation and simulations done so farin this project demonstrate the viability of device designfor room temperature testing of 50 nm devices optimizedfor low temperature operation. Current efforts arefocused on fabricating a set of 50 nm devices to evaluatethe simulated results.

150

The accuracy of the model is tested by comparingagainst measurements from actual devices fabricated atMIT. Ongoing work is directed at improving the modelto better match device characteristics. Towards that end,source and drain resistance has been added to the model(see Figure 6). This has resulted in an improvement inthe predictive power of deep-submicron devices. Nextthe body effect, inversion-layer quantization, and a gate-induced drain lowering will be added to make themodel more accurate.

continued

We have developed multipole-accelerated algorithms forcomputing capacitances and inductances of complicated3-D geometries, and have implemented these algorithmsin the programs FASTCAP and FASTHENRY. Themethods are accelerations of the boundary-element ormethod-of-moments techniques for solving the integralequations associated with the multiconductor capaci-tance or inductance extraction problem. Boundary-element methods become slow when a large number ofelements are used because they lead to dense matrixproblems which are typically solved with some form ofGaussian elimination. This implies that the computationgrows as N cubed, where N is the number of panels ortiles needed to accurately discretize the conductorsurface charges. Our new algorithms, which use Krylovsubspace iterative algorithms with a multipole approxi-mation to compute the iterates, reduces the complexityso that accurate multiconductor capacitance and induc-tance calculations grow nearly as NM where M is thenumber of conductors. For practical problems whichrequire as many as 10,000 panels or filaments, FASTCAPand FASTHENRY are more than two orders of magni-tude faster than standard boundary-element basedprograms. Manuals and source code for FASTCAP andFASTHENRY are available from our web site(rle-vlsi.mit.edu).

In more recent work, we have been developing analternative to the fast-multipole approach to potentialcalculation. The new approach uses an approximaterepresentation of charge density by point charges lyingon a uniform grid instead of by multipole expansions.For engineering accuracies, the grid-charge representa-tion has been shown to be a more efficient chargerepresentation than the multipole expansions. Numericalexperiments on a variety of engineering examples arisingindicate that algorithms based on the resulting“precorrected-FFT” method are comparable in computa-tional efficiency to multipole-accelerated iterativeschemes, and superior in terms of memory utilization.

Efficient 3-D Interconnect Analysis

PersonnelI. Balk, M. Chou, J. Kanapka, F. Wang, J. F. Wang,J. Tausch (J. White)

SponsorshipDARPA, SRC, IBM, Harris Semiconductor, MAFETConsortium

continued

Fig. 6: Measurements and Model Predictions for Transconductancevs. Effective Gate Length for a supply voltage of 2V. The data is fromdevices fabricated at MIT.

151

The precorrected-FFT method has another significantadvantage over the multipole-based schemes, in that itcan be easily generalized to some other common kernels.Preliminary results indicate that the precorrected-FFTmethod can easily incorporate kernels arising from theproblem of capacitance extraction in layered media.More importantly, problems with a Helmholtz equationkernel have be solved at moderate frequencies with onlya modest increase in computational resources over thezero-frequency case. An algorithm based on theprecorrected-FFT method which efficiently solves theHelmholtz equation could form the basis for a rapid yetaccurate full-wave electromagnetic analysis tool.

Reduced-order modeling techniques are now commonlyused to efficiently simulate circuits combined withinterconnect. Generating reduced-order models fromrealistic 3-D structures, however has received lessattention. Recently we have been studying an accurateapproach to using the iterative method in the 3-Dmagnetoquasistatic analysis program FASTHENRY tocompute reduced-order models of frequency-dependentinductance matrices associated with complicated 3-Dstructures. This method, based on a Krylov-subspacetechnique, namely the Arnoldi iteration, reformulatesthe system of linear ODE’s resulting from theFASTHENRY equation into a state-space form anddirectly produces a reduced-order model in state-spaceform. The key advantage of this method is that it is nomore expensive than computing the inductance matrixat a single frequency. The method compares well withthe standard Pade approaches and may present someadvantages because in the Arnoldi-based algorithm,each set of iterations produces an entire column of theinductance matrix rather than a single entry, and ifmatrix-vector product costs dominate then the Arnoldi-based algorithm produces a better approximation for agiven amount of work. Finally, we have shown that theArnoldi method generates guaranteed stable reducedorder models, even for RLC problems.

Our recent work has focussed on fast techniques ofmodel reduction which generate low order models ofthe interconnect directly from the discretized Maxwell’sequations under the quasistatic assumption. Whencombined with fast potential solvers, the overall algo-rithm efficiently generates accurate models suitable forcoupled circuit-interconnect simulation.

The design of single chip mixed-signal systems whichcombine both analog and digital functional blocks on acommon substrate is now an active area of research,driven by the relentless quest for high-level integrationand cost reduction. A major challenge for mixed-signaldesign tools is the accurate modeling of the parasiticnoise coupling through the common substrate betweenthe high-speed digital and high-precision analog compo-nents. We are working on a sparsification method basedon eigendecomposition which handles edge effects moreaccurately than previously applied multipole expansiontechniques, and then combine the sparsification ap-proach with a multigrid iterative method which con-verges more rapidly than previously applied Krylov-subspace methods. Results on realistic examples demon-strate that the combined approach is up to an order ofmagnitude faster than the sparsification plus a Krylov-subspace method, and orders of magnitude faster thannot using sparsification at all.

continued

152

Finding computationally efficient numerical techniquesfor simulation of three dimensional structures has been animportant research topic in almost every engineeringdomain. Surprisingly, the most numerically intractableproblem across these various discplines can be reduced tothe problem of solving a three-dimensional potentialproblem with a problem-specific Greens function. Appli-cation examples include electrostatic analysis of sensorsand actuators; electro- and magneto- quasistatic analysisof integrated circuit interconnect and packaging; andpotential flow based analysis of wave-ocean structureinteraction.

Although the boundary element method is a popular toolto solve the integral formulation of many three-dimen-sional potential problems, the method become slow whena large number of elements are used. This is becauseboundary-element methods lead to dense matrix prob-lems which are typically solved with some form ofGaussian elimination. This implies that the computationgrows as cubically with the number of unknowns tilesneeded to accurately discretize the problem. Over the lastdecade, algorithms with grow linearly with problem sizehave been developed by combining iterative methodswith multipole approximations. Our work in this area hasbeen to develop precorrected-FFT techniques, which canwork for general Greens functions, and Wavelet basedtechniques, which generate extremely effectivepreconditioners which accelerate iterative method conver-gence.

The development of fast boundary-element based solvershas renewed interest in developing well-conditionedintegral formulations for a variety of engineering prob-lems. We have developed second-kind formulations forthe electrostatics problem that directly yeilds the surfacecharge distribution on conductors, and have developedtechniques which insure accuracy in the numericallycomputed capacitances given arbitrarily shaped dielectricmaterials of arbitrarily high permitivity.

Numerical Techniques for IntegralEquations

PersonnelT. Korsmeyer, J. Singer, J. Tausch, J. F. Wang (J. White)

SponsorhipSRC, DARPA, MURI

In order to study the impact of long range spatial andpattern dependent variation on circuit performance,CAD tools must be extended and integrated in innova-tive ways. In this work, we are developing the CADinfrastructure to study device and interconnect variationimpact on circuit performance.

In previous work, we developed a method to accuratelyextract a global path geometry that includes both nearbyinterconnect structures and accounts for variation in thethickness of interlevel dielectrics (ILD) as a function ofposition on the layout. Capacitance extraction (usingFastCap) was performed on this 3D geometry, followedby Spice analysis to study clock skew in a balanced H-bar distribution network.

A new methodology has been developed to overcometime and computation limitations in the previousapproach. In particular, the goal is to enable the studyof hundreds or thousands of global paths to understandthe impact of spatial variation. An IBM 1GHz micropro-cessor circuit design and layout was used as the casestudy. In our approach, a single circuit extraction isperformed for each net of interest, and key geometricinformation kept for nodes in that net. This information,combined with spatial variation information, enablesone to consider the incremental (linearized) change tocapacitance due to variation. The modified net under-goes timing analysis (rather than Spice simulation) toextract delay information. In this way, a distribution ofnet delay variations can be generated.

Modeling the Effect of InterconnectVariation on Circuit Performance

PersonnelV. Mehrotra(D. Boning and J. Chung)

SponsorshipDARPA, PDF Solutions, IBM

153

RF integrated circuit designers make extensive use ofsimulation tools which perform nonlinear periodicsteady-state analysis and its extensions. However, thecomputational costs of these simulation tools haverestricted users from examining the detailed behavior ofcomplete RF subsystems. Recent algorithmic develop-ments, based on matrix-implicit iterative methods, israpidly changing this situation and providing new fastertools which can easily analyze circuits with hundreds ofdevices. We have investigated how these new methodsby describing how they can be used to accelerate finite-difference, shooting-Newton, and harmonic-balancebased algorithms for periodic steady-state analysis.

Simulation Algorithms for RF Circuits

PersonnelO. Nastov (J. White)

SponsorshipCadence Design Systems, Motorola Semiconductor,Harris Semiconductor, MAFET Consortium

continued

154

Integrated circuits are currently designed using simpleand conservative ‘design rules’ to ensure that the result-ing circuits will meet reliability goals. This simplicityand conservatism leads to reduced performance for agiven circuit and metallization technology. There havebeen recent significant advances in the understanding ofthe dependence of integrated circuit interconnect reliabil-ity on interconnect geometries, circuit layout, andinterconnect processing. In addition, it is now knownthat many interconnect elements are immune toelectromigration-induced failure under the conditions oftheir actual use. Incorporation of these improvedunderstandings of interconnect reliability into the circuitdesign and layout process will lead to more accuratereliability assessments and to less overly conservativedesigns, allowing the design and layout of higher-performance circuits.

We are developing a TCAD tool, ERNI, which will allowprocess-sensitive and lay-out specific reliability estimatesfor fully laid out or partially laid out integrated circuits.We have developed a set of filtering algorithms whichallow identification of highly reliable or immortalinterconnect elements based on increasingly morecomplex analyses. By using these algorithms in ahierarchical analysis, we expect that large circuit-levelanalyses will be made computationally tractable. Theavailability of a tool such as ERNI will allow assessmentof the impact of materials, processes, circuit-design andcircuit-layout modifications on circuit reliability. Thiswill lead to the manufacture of higher performancecircuits with more accurately assessed reliabilities.

Software Tools for Process-SensitiveReliability Assessments of IC Designs

PersonnelY. Chery, S. Riege, W. Fayad, Y.-J. Park (D. Troxel andC.V. Thompson)

SponsorshipDARPA, SRC

We have developed computer simulations for normaland abnormal grain growth during deposition andsubsequent heat treatments of polycrystalline thin films.We have included the effects of grain boundary dragdue to surface grooving and due to the presence ofsolutes. The former leads to stagnation of normal graingrowth at a point where the grain sizes are lognormallydistributed and the average grain diameter is about threetimes the film thickness. This simulation result closelymatches experimental results in a wide variety of sys-tems. To account for observations of texture evolutionduring abnormal grain growth in thin films, we haveincluded the effects of surface, interface, and strainenergy anisotropy in our simulations of grain growth infilms. These simulations allow investigations of theeffect of energetic anisotropies on the evolution oftexture and grain orientation distributions, as well as onthe evolution of the average grain size and the distribu-tion of grain sizes. Predictive simulations of the evolu-tion of the distribution of grain sizes and orientations canbe made as a function of materials selection, film thick-ness, and processing conditions, in both continuous andpatterned films.

In the past year we have modified our grain growthsimulation tool to account for the effects of second phaseprecipitates and of rough interfaces for both continuousand patterned films. These features have been includedto account for experimental observations of grain growthmade during in situ heating of continuous and patternedfilms in a transmission electron microscope. In addition,we have studied the evolution of soap froths in 3Dvolumes in order to characterize grain structure evolu-tion in volumes in which 2 or more dimensions arecomparable to the average grain size. We are developinganalytic models which describe such evolution, andcomparing these models and results from froth studieswith fully-3D simulations of grain growth carried out atLos Alamos National Laboratory. Analytic models for

Modeling of Grain Growth inThin Films

PersonnelS. Seel, W. Fayad, S. Riege, H.J. Frost, G. Straub(C.V.Thompson)

SponsorshipNSF, SRC

continued

155

grain structures and grain structure evolution are beingincorporated into tools for simulation of stress evolutionand for analysis of the reliability of micrometer and na-nometer-scale materials in device and circuit structures.

continued

Recent research has demonstrated interconnect failuredue to electromigration effect to be strongly dependentnot only on current density but also on metal filmcrystal grain size distribution and geometries of inter-connect patterns. This type of failure is manifest as adepletion of interconnect metal forming a “void” (open-circuit) or an accumulation possibly forming a “short”to neighboring interconnect.

Our research work focuses on:

1. Developing abstract, physically-based, micro-structural interconnect failure models to moreaccurately predict electromigration inducedfailure.

2. Electromigration Reliability for NetworkInterconnect (ERNI), our prototype computer-aided design tool based on these abstractedmicrostructurally based models.

A release of ERNI 2.0 is expected soon with extensionssupporting hierarchical designs and utilizing higherperformance circuit simulation engines. This release willincorporate client and server programs implemented inJava. With this, multiple designers at different locationswill be able to cooperatively design integrated circuitrywhich incorporates electromigration reliability models.

Modeling of Interconnect Reliability

PersonnelY. Chery (C. V. Thompson and D. E. Troxel)

SponsorshipDARPA

continued

156

We have developed a software tool for structure-sensitivesimulation of electromigration and electromigration-induced failure of interconnects. A web-based version ofthis tool, MIT/EmSim, can be accessed atnirvana.mit.edu/emsim/. The tool generates grainstructures with known statistical variations as a functionof median grain size and line width, and predicts failurestatistics as a function of various failure criteria, and as afunction of the current density and of the temperature.The effects of wide-to-narrow transitions, junctions, andthermal history have also been included, and are nowbeing tested through comparisons with experiments.MIT/EmSim has been used to simulate electromigration-induced failure in pure Al and Al-Cu interconnects, andis currently being adapted for use in simulation ofelectromigration-induced failure in pure Cu an Cu alloyinterconnects. MIT/EmSim allows the user to studyfailures based on void nucleation, void growth, andcompressive failures. Future upgrades will incorporatethe effects of precipitate nucleation and growth, redistri-bution of alloy additions, and post-patterning grainstructure evolution.

In the conventional interconnect reliability assessmentmethodology, accelerated lifetime tests are carried out atelevated current densities and temperatures, and specificscaling behavior is assumed in predicting lifetimes at in-service current densities and temperatures. For example,it is assumed that lifetimes scale with the current densityj to the power –2 for void-nucleation-limited failure, andj to the power –1 for void-growth-limited failure. Usingsimulations we have shown that there can be a transitionin scaling behavior in going from to test to serviceconditions, leading substantial scaling errors when this isnot accounted for. Further, we have shown that shortlines can display conventional scaling behavior at testconditions but be immune to failure at service conditions.These simulation results are consistent with a growingbody of experimental results. This complex behaviormust be accounted for in order to make accurate reliabil-

Simulation of Electromigration-Induced Failure of IC Interconnects

PersonnelV. Andleigh, Y.-J. Park, C. Hau, S. Riege, W. Fayad (C.V. Thompson)

SponsorshipSRC, DARPA

ity projections, and in order to take advantage of thegreatly improved reliabilities of short lines. To catalogscaling behavior we have developed ‘failure-mechanismmaps’ which show the scaling behavior as a function ofcurrent density and line length. Such maps can be usedin reliability assessments and in developing optimumcircuit layout strategies. MIT/EmSim can be used togenerate these maps for different metallization materialsand processes.

157

The goal of this project is to develop a CAD tool forprediction of electron emission from field emitter tips,their trajectory to the phosphor screen and the resultingspot size on the screen for an array of field emitters. Thebasic structure studied is shown in Figure 8. It consists ofa a field emitter cone with a tip radius of 10 nm, a 0.2 µmthick gate with 1 µm aperture, a 0.5 µm thick focusingelectrode located 0.5 µm above the gate. The anode isabout 1 mm above the field emitter.

The project raises two key challenges: the very differentdimensional scales surrounding the emitter tip (10 nm),the gate (1 µm) and the anode (1 mm) and the the need toadapt boundary element based solvers for (Dirichlet andNeumann) mixed boundary conditions. The potentialgradient is calculated on surfaces with Dirichlet condi-tions and potential on surfaces with Neuman conditionsusing a Green’s Theorem kernel. A source formula isused to calculate an equivqlent pseudo-charge distribu-tion on all surfaces from which electric field is deter-mined at any point of interest is determined.

Using this approach, electric field at the tip surface isdetermined and the field emission current density iscalculated using the Fowler-Nordheim equation. Theelectron trajectories are obtained by integrating theLorentz equation from various points on the emission tipto the anode. The spot size and current distribution onthe phosphor screen for an array of field emitters can becalculated using superposition using the trajectoriesweighted by the emission surface areas and the currentdensities.

Figure 9 shows a typical Si FEA structure that wasfabricated and characterized. Figure 10 shows a compari-son of the experimental simulated current per tip asfunction of the gate voltage for a 60x60 Si tip FEA. Theonly adjustable parameter is the radius of curvature. Theradius of curvature that matched the simulation is 8.4 nmwhile the experimentally measured radius is about10 nm.

Electric Field Simulations for Field Emission Devices

PersonnelY-J. Yang(S. D. Senturia in collaboration with A. I. Akinwande)

SponsorshipDARPA

Figure 11 shows a comparison between the spot sizemeasured for a phosphor screen which is biased at 5000V and is 1 cm away from the FEA. The experimentalspot size is about 2 mm while the simulated spot size is1.8 mm.

continued

Fig. 8: The Integrated Focus Electrode Field EmitterDisplay structure.

158

Fig. 10: Comparison between the experimental and simulated currentdensity for a Si field emitter array. The only adjustable parameter wasthe tip radius.

Fig. 11: Experimental and simulated spot size on phosphor screenfor a 60x60 4µm-pitch FEA with the phosphor screen biased at 5000V at a distance of 1 cm from the FEA.

continued

Fig. 9: SEM of the Si Field Emitter tip.

1.E-16

1.E-15

1.E-14

1.E-13

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

20 40 60 80 100 120

Ia (

A)

r = 8.2 nm

measured

r = 8.6 nm

159

Micromachining technology has enabled the fabricationof several novel microsensors and microactuators.Because of the specialized processing involved, the costof prototyping even simple microsensors, microvalves,and microactuators is enormous. In order to reduce thenumber of prototype failures, designers of these devicesneed to make frequent use of simulation tools. Toefficiently predict the performance of micro-electro-mechanical systems these simultion tools need to ac-count for the interaction between electrical, mechanical,and fluidic forces. Simulating this coupled problem ismade more difficult by the fact that most MEMS devicesare innately three-dimensional and geometricallycomplicated. It is possible to simulate efficiently thesedevices using domain-specific solvers, provided thecoupling between domains can be handled effectively. Inthis work we have developed several new approachesand tools for efficient computer aided design andanalysis of MEMS.

One of our recent efforts in this area has been in develop-ing algorithms for coupled-domain mixed regimesimulation. We developed a matrix-implicit multi-levelNewton methods for coupled domain simulation whichhas much more robust convergence properties than justiterating between domain-specific analysis programs, butstill allows one to treat the domain analysis programs asblack boxes. In addition, we developed another approachto accelerating coupled-domain simulation by allowingphysical simplifications where appropriate. We refer tothis as mixed regime simulation. For example, self-consistent coupled electromechanical simulation ofMEMS devices face a bottleneck in the finite elementbased nonlinear elastostatic solver. Replacing a stiffstructural element by a rigid body approximation whichhas only 6 variables, all variables associated with theinternal and surface nodes of the element are eliminatedwhich are now a function of the rigid body parameters.Using our coupled domain approach has made it pos-sible to perform coupled electromechanical analysis of anentire comb drive accelerometer in less than 15 minutes.

Simulation Tools for Micromachined Device Design

PersonnelX. Wang, W. Ye, Y. Massoud, D. Ramaswamy (J. White)

SponsorshipDARPA, SRC

Analysis of the resonance behavior of micromachineddevices packaged in air or fluid requires that fluiddamping be considered. Since the spatial scales aresmall and resonance analyses are typically done assum-ing a small amplitude excitation, fluid velocities canoften be analyzed by ignoring convective and inertialterms and then using the steady Stokes equation. Forhigher frequency applications, the convective term maystill be small, but the inertial term rises linearly withfrequency. Therefore, analyzing higher frequencyresonances requires the unsteady Stokes equations,though the small amplitudes involved make it possibleto use frequency domain techniques. We have devel-oped a fast Stokes solver, FastStokes, based on theprecorrected-FFT accelerated boundary-elment tech-niques. The program can solve the steady Stokesequation or the frequency domain unsteady Stokesequation in extremely complicated geometries. Forproblems discretized using more than 50,000 un-knowns, our accelerated solver is more than threeorders of magnitude faster than direct methods.

continued