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1 CADENCE DESIGN SYSTEMS, INC. FDIP Workshop, EPEP 2006
Modeling and Analysis Challenges for Complex Digital Systems-in-Package Designs
Zhen MuCadence Design Systems, Inc.
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2 FDIP Workshop, EPEP 2006
Note
• The content of this presentation is the collected effort of the entire SiP team in SPB division at Cadence.
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3 FDIP Workshop, EPEP 2006
Topics
• SiP Overview
– What is SiP?
– Why is SiP Important?
– SiP applications
• SiP Design Challenges
• Requirements of EDA tools for SiP design and analysi s
– Co-Design methodologies
– Design management
– SI and PI analysis
• Summary
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4 FDIP Workshop, EPEP 2006
Topics
• SiP Overview
– What is SiP?
– Why is SiP Important?
– SiP applications
• SiP Design Challenges
• Requirements of EDA tools for SiP design and analysi s
– Co-Design methodologies
– Design management
– SI and PI analysis
• Summary
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5 FDIP Workshop, EPEP 2006
What is SiP?
• SiP (System-in-Package)
– Single package that combines all of the electronic components (digital ICs, analog ICs, RF ICs, passive components or other elements) needed to provide a system or sub-system.
• Applications
– Cellular
– Bluetooth
– 802.11 WLAN
– CMOS Sensors
Courtesy of Philips
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6 FDIP Workshop, EPEP 2006
Why is SiP important?
• Increased functional density– Miniaturization due to fewer packages and
3D stacked die– Multiple technologies in a SiP
• Reduced time-to-new product concepts– Faster design cycles (over SoC)– Reduce system board complexity and layer
count
• Performance through interconnect elimination
– Low power– High speed
• Optimization of complexity, cost, and time to market
Courtesy of ASAT
Source: Renesas
37%
26%
13%
12%
12%
Miniaturization
EMI Noise Reduction
Low Power
Cost Reduction
High-Speed Bussimplification
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7 FDIP Workshop, EPEP 2006
SiP applications in wireless devices
SiP Functions
RF/IF(WLAN, Bluetooth, GPS)
Camera(A-FEP,DSP,VDr)
Baseband(DSP,memory)
Application(GPU,CPU,memory)
Camera
Voice
Video
Music
PersonalProductivity
Games
GPS
WLAN
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8 FDIP Workshop, EPEP 2006
SiP and Stacked-package designs increase 21% yearlyDesigns move from experts to majority of designers
(Source: Electronic Trend Publications )
Multi-Die package forecast
Courtesy of ASAT
Courtesy of Cannon
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9 FDIP Workshop, EPEP 2006
Topics
• SiP Overview
– What is SiP?
– Why is SiP Important?
– SiP applications
• SiP Design Challenges
• Requirements of EDA tools for SiP design and analysi s
– Co-Design methodologies
– Design management
– SI and PI analysis
• Summary
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10 FDIP Workshop, EPEP 2006
Multiple die connections
Die stackingPackage-on-package
3D IC RF module
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11 FDIP Workshop, EPEP 2006
Complex die stack design
3D StackDesign
3D StackViewer
Actual Stack Design
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12 FDIP Workshop, EPEP 2006
Complex die stack design
• Interposer
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13 FDIP Workshop, EPEP 2006
PCB to PCB
Pin on chip
package
Systems interconnect
Driving I/O
bufferon chip
C4 Bump
Receiving I/O bufferon chip
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14 FDIP Workshop, EPEP 2006
Topics
• SiP Overview
– What is SiP?
– Why is SiP Important?
– SiP applications
• SiP Design Challenges
• Requirements of EDA tools for SiP design and analysi s
– Co-Design environment
– Design management
– SI and PI analysis
• Summary
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15 FDIP Workshop, EPEP 2006
Modeling and analysis challenges
• Optimization requires design automation
• Recongnicing the differences between SiP design and classic single package and PCB designs
• Issues
– Multiple stacked dies are placed vertically or horizontally
– Connection between multiple dies are realized by wirebonding, interposer, interconnect, or flip-chip technology
– IC design needs to consider package design, while package designneeds to consider IC requirements
– How to make die information available to package designers, and how to pass package models back to IO designers to simulate entire signal path
– Data passing and property mapping
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16 FDIP Workshop, EPEP 2006
Modeling and analysis challenges
• Fundamental requirements for SiP tools
– An environment with IC/package/board co-design and co-simulationcapabilities
– To provide engineers with Signal Integrity (SI) and Power Integrity (PI) solutions
– Concurrent pre-route analysis and post-route verification
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17 FDIP Workshop, EPEP 2006
Current methodologies must change
• Isolated IC, Package, and PCB design tools increases costs and design cycle times
– Many problems not discovered until integration (costly iterations)
• New methodology requires full system interconnect planning
– IC package interconnect and its influence must be fully understood and modeled
– Must arbitrate connection scheme across chip, package and board
• Timing, signal integrity and power delivery intertwined
– Full analysis of system interconnect from buffer to buffer required
• Constraints have to be established based on accurate pre-route analysis
ICIC PackagePackage PCBPCB
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18 FDIP Workshop, EPEP 2006
Opening Up the Solution Space
IC
Design Space
Board
Design Space
I/O Pad to Package Pin Physical Design
and Modeling
I/O Pad � Bump Array Placement and Optimization
RDL Routing
I/O Pad to Bump Delays
System Level I/O Buffer Characterization
Package Footprint Creation
Schematic Symbol Creation
I/O Pad to Package Pin Delays
Package Pin Optimization
Package
Design Space
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19 FDIP Workshop, EPEP 2006
Topics
• SiP Overview
– What is SiP?
– Why is SiP Important?
– SiP applications
• SiP Design Challenges
• Requirements of EDA tools for SiP design and analysi s
– Co-Design methodologies
– Design management
– SI and PI analysis
• Summary
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20 FDIP Workshop, EPEP 2006
SiP digital design flow
• Concurrent designs & independent teams
• Unique IC processes
• Design chain geographically diverse
System
Sub
U1U2
M1,2
System Design Hierarchy
U3U1 U2 U3
M1
M23DIC
SiP
Resulting SiP Complex 3D Structures & Technologies
– U1: flip chip, 90nm digital
– 3DIC:– U2: wire bond 130nm
– M1 & M2: wire bond 90nm memory
– U3: fixed die, flip chip 130nm digital
Sub-assembly is the SiP
PCB
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21 FDIP Workshop, EPEP 2006
Architect
Layout
SI/PI
SiP digital design methodology
*
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22 FDIP Workshop, EPEP 2006
Digital SiP connectivity hierarchy
Board
FA,B,C FD
SiP (SoC, FB)
Balls Int
SiP (FD)
Balls Int
SoCBlock
FunctionB
Block
SiP (SoC, FB) Logical Interface
SoC Function B
BumpsBumps IntInt
FunctionD
Block
SiP Logical Interface
Function D
Bumps Int
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23 FDIP Workshop, EPEP 2006
Co-design dies
• IC tool based die abstract editor
• Co-design die are hierarchical design elements on substrate
• Die abstracts management
• Data Import/Export
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24 FDIP Workshop, EPEP 2006
Concurrent design to enable optimizationof DIE abstracts
Flip chip with drivers, RDL and
Bumps
Flip chip (standard)
Wire bond chip (standard)
SIP IO PlannerCo-design DIE
SiP Substrate Editor
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25 FDIP Workshop, EPEP 2006
• Flip Chip or Wirebond Attachment
– Automatic optimization strategies via node swapping
• Based on Package Pin Assignment
• Flip Chip Escape Patterns
• Feasibility Routing for RDL
– IOP mask ready RDL routing
– I/O Buffer to Bump/Die Pad in IOP
• IC-Pkg routability analysis
– All angle, Orthogonal, Diagonal
– Support for Differential Signaling
– Materials and Standard Package trade-offs
– Full mask ready substrate routing
Route feasibility analysis: IC-RDL and SiP substrate
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26 FDIP Workshop, EPEP 2006
Package Physical Layout
• Automatic Bond Shell Creation
• Net assignment based on Routability of Package
• All angle auto-routing
• Unique routers for wire-bond and flip-chip routing styles
– DRC correct
– Electrical constraints and Physical rules
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27 FDIP Workshop, EPEP 2006
3D Visualization
• Support for Die Stacks
• Bond Wire Clearance Checking
– Reverse Bonding
• Micro-Via Checking
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28 FDIP Workshop, EPEP 2006
Topics
• SiP Overview
– What is SiP?
– Why is SiP Important?
– SiP applications
• SiP Design Challenges
• Requirements of EDA tools for SiP design and analysi s
– Co-Design methodologies
– Design management
– SI and PI analysis
• Summary
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29 FDIP Workshop, EPEP 2006
Co-design methodologies in high-speed design
• Problem1: Signal path from silicon to board through package
– Reflections, xtalk, timing
The interconnect from Package to Board and IO buffersare modeled
The interconnect from Package to Board and IO buffersare modeled
SiliconSilicon
PackagePackage
Board(s)Board(s)
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30 FDIP Workshop, EPEP 2006
Co-design methodologies in high-speed design (cont’)
• Problem 2: Power delivery path from board to silicon through package
Power is delivered from PCB to Siliconthrough Package
Power is delivered from PCB to Siliconthrough Package
SiliconSilicon
PackagePackage
Board(s)Board(s)
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31 FDIP Workshop, EPEP 2006
Co-design methodologies in high-speed design (cont’)
• Problem 3: Effects between signal and power supply
Silicon Package Board
Problem 1: signal
Problem 2: power
Problem 3: Interference of signal and power
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32 FDIP Workshop, EPEP 2006
Signal analysis: Establishing constraints
• Early exploration on multi-die connection
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33 FDIP Workshop, EPEP 2006
Signal analysis: Establishing constraints
• Early exploration on multi-die connection
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34 FDIP Workshop, EPEP 2006
Signal analysis: Establishing constraints
• Extracted circuit for space simulation
Three dies
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35 FDIP Workshop, EPEP 2006
Signal analysis: interconnect modeling
• Detailed interconnect modeling
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36 FDIP Workshop, EPEP 2006
Signal analysis: assistant to analysis
• 3D view
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37 FDIP Workshop, EPEP 2006
Signal analysis: wirebond constraints
• Perform what/if analysis by changing wirebond profiles
– Work with existing design and/or start new design
– Edit the parameters
– Update (or extract) constraints
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38 FDIP Workshop, EPEP 2006
Signal analysis: stackup design
• Crossection details
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39 FDIP Workshop, EPEP 2006
Signal analysis: wirebond modeling
• Interested wirebonds
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40 FDIP Workshop, EPEP 2006
Signal analysis: wirebond model re-use
• Extracting models from existing design
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41 FDIP Workshop, EPEP 2006
Signal analysis: wirebond model re-use
• The corresponding design with only wirebonds
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42 FDIP Workshop, EPEP 2006
Signal analysis: wirebond model re-use
• 3D view of the multi-die design
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43 FDIP Workshop, EPEP 2006
Signal analysis: wirebond model reuse
• View geometry mesh
– Original net (in full)
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44 FDIP Workshop, EPEP 2006
Signal analysis: reflections, crosstalks, timing
• Building simulation circuits
– 3D modeling
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45 FDIP Workshop, EPEP 2006
Signal analysis: reflections, crosstalks, timing
• Simulation circuit
Two dies
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46 FDIP Workshop, EPEP 2006
Power analysis: power delivery
• Power delivery to multiple dies
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47 FDIP Workshop, EPEP 2006
Power analysis: power delivery
• Power delivery to multiple dies
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48 FDIP Workshop, EPEP 2006
Power analysis: power delivery
• Power delivery to multiple dies
– Decoupling capacitor selection and placement
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49 FDIP Workshop, EPEP 2006
Power analysis: IR-Drop analysis at IC level with package effects included (cont’)
• Voltagestorm output using multi-port DC net model of package
With N-port DC net model in package
Worst IR-drop : 253mV
Without package effects
Worst IR-drop : 155mV
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50 FDIP Workshop, EPEP 2006
Power analysis: stability study
• Estimate SSO/SSN impacts at early design stage
– This methodology helps decide the ratio of signal I/O pads to power & ground pads before starting chip design
Data preparation
I/O Pad Ratio Setting
SSO Simulation
Pass?
Adding capacitors
No
Yes
Start to design chip’s floor-plan and export design spec. to package house
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51 FDIP Workshop, EPEP 2006
Co-simulation in SiP: final verification
• Final verification for solutions 1-3
– Consider entire signal path
– Silicon to board through package
– Examine signal quality and timing budget
– Consider power stability
– Key is SSN analysis
Silicon Package Board
Problem 1: signal
Problem 2: power
Problem 3: Interference of signal and power
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52 FDIP Workshop, EPEP 2006
Co-simulation in SiP: final verification
• Design example: finished package design
– Many diff. pairs
– Multi-GHz signaling
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53 FDIP Workshop, EPEP 2006
Co-simulation in SiP: final verification
• Design example
– Finished package design
– Wideband model extraction
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54 FDIP Workshop, EPEP 2006
Co-simulation in SiP: final verification
• Design example
– Mesh view of a pair of critical differential signals
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55 FDIP Workshop, EPEP 2006
Co-simulation in SiP: final verification
• Design example– Driver/receiver
model
– Transistor level model wrapped in Spectre format
– Macromodel
– Long trace representing board
– Run Spectre directly in SiPenvironment
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56 FDIP Workshop, EPEP 2006
Co-simulation in SiP: final verification
• Large package model
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57 FDIP Workshop, EPEP 2006
Co-simulation in SiP: final verification
• Assign package model and power/ground buses
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58 FDIP Workshop, EPEP 2006
Co-simulation in SiP: final verification
• Results of detailed Spectresimulation
– 8 Lane SSO analysis results
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59 FDIP Workshop, EPEP 2006
Summary
• System-in-Package is the right integration solution for wireless and consumer products– It posts great challenges to designs and analyses (differences between
single package and PCB designs)
• Design tools are evolving to meet the needs of designers– IC-Package-Board co-design and co-simulation enable designs to be
optimized to meet design requirements
• SiP Digital tool– Providing a co-design environment for SiP interconnect including embedded
ICs and the target printed circuit board
– Including integrated signal integrity, parasitic extraction/modeling and substrate interconnect editing, power delivery, and signal/powerinterference analyses
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60 FDIP Workshop, EPEP 2006
Thank you