model 6750 brtu-93 with tellabs tcs532l - oracle … · interface and test cards) figure 1-2 model...

Application Guide for Model LAB-532 with Tellabs TCS532L

Spirent Communication Rev. A

Application Guide for Model 6750 BRTU-93 with Tellabs TCS532L

Revision Author Approval Date

A Victor Afable 11/11/06



Table of Contents

1.0 BRTU-93 and DCS Introduction and Preparation --------------------------------------------------------- 3

1.1 Objective ----------------------------------------------------------------------------------------------------- 4

1.2 Description ---------------------------------------------------------------------------------------------------- 4

1.2 Equipment Drawings and Cable Running List ----------------------------------------------------- 5-8

2.0 BRTU-93 and TCS532 Set Up --------------------------------------------------------------------------------- 9

3.0 Circuit Access Test --------------------------------------------------------------------------------------------- 15

4.0 REACT TEST RESOURCE Example ---------------------------------------------------------------------- 22

5.0 REACT TEST E1 and Fractional E1 ------------------------------------------------------------------------ 25



Section 1.0

BRTU-93 and DCS Introduction and Preparation



1.0 Objective

This document is made to use as an application guide for setting up the Model 6750 BRTU-93 and REACT for accessing Fractional E1 circuit using BRTU E1 FAD Interface card from Tellabs 532L DCS This document does not cover the overall acceptance/verification and focused only in configurations of Spirent Model 6750 BRTU-93 and REACT to access Fractional E1 circuits from Tellabs TCS532 DCS. Additional information may be obtained in the following documents for the purpose of troubleshooting, maintenance, operation requirements, etc.

HKMN-6700-085 6750 Acceptance Test Procedure

HKMN-6750-101 6750 Application Drawings.

1.1 Description

This document consist of six sections

Section 1 Introduction and Preparation

Section 2 Model 6750 BRTU

Section 3 Circuit Access Test

Section 4 React Test Resource Example

Section 5 Testing E1 and Fractional E1 using REACT



1.2 Equipment Drawings

Figure 1-1 Model 6750 BRTU-93 Front View (Drawing shows with E1, E3, DS1 Interface and test cards)

Figure 1-2 Model 6750 BRTU-93 Rear View



Note: BRTU-93 Relay Rack Configuration.

Figure 1-3 Typical Rack Elevation (7’ X 1” X 23”) of 6750 BRTU-93

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BRTU-99

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Figure 1-4 Model 6750 BRTU-93

Typical BRTU (TSC Mode) driving TCS532L via Async TSC Communication

6705-93

BRTU

J83

TB1

TB2-48Vdc

DSX1 Panel

J46

IP

NETWORK

Ethernet Hub

Tellabs

TCS532L

Tellabs

TCS532L

DSX1 Panel

X-Connect to BRTU-93 E1 FAD

E1 TAP Signal

REACT

REACT Comm.

E1 FAD E1 FAD

J39

ASYNC

PORT

7110-20A

TSC

Comm.

E1 Test Bus Cable



Cable Running List

Run No.

Cable Type

Code From Equipment

To Equipment

Remarks

EQPT PWR

1 20AWG Red/Black

BRTU-93 Connectors TB1 (Black) TB2 (Red)

-48V Fuse Panel -48VDC Power Supply

COMM/ TEST BUS

2 7121-66P BRTU-93 J46

Ethernet Hub IP Communication to REACT

3 Test Bus TCS532 TAP PORT

BRTU J83 E1 Tap Connection

Refer to Figure 1.4 for more information



2.0 Model 6750 BRTU-93 Shelf Configuration: Pull the 6750 SCU card and ENABLE the battery backup by placing the BLUE JUMPER to pin 1 and pin 2 of J1 connector. If the BRTU is equipped with eSCU the battery backup is jumper is J3 enable the battery by placing the BLUE jumper in pin 1 and pin 2.

VBATT EN 1-2

VBATT DIS 2-3 Ba

ttery

1 2 3J3

Set up a VDT (VT100) or a laptop PC for direct connection to the fixed port at 9600 bps, 8 data bits, no parity, and 1 stop bit (9600, 8, N, 1).

Using the 9-pin male/ female Straight Cable, connect the PC to the craft port at the front of the BRTU-93 unit.

2.1 Login to the BRTU-93

Enter Command: ACT-USER::SUPER:CTAG::SUPER;

2.2 Edit Date and Time

Enter Command: ED-DAT:::CTAG::050906,101500;

YRMMDD,HHMMSS 2.3 Edit Site Identifier (SID)

Enter command: ED-SID:HEKIMIAN-6700::CTAG::LABBRTU;

OLD/CURRENT SID NEW SID



2.4. Edit BRTU-93 Equipment Table

Enter Command: ED-ATTR-EQPT:::CTAG::TSC=ON;

Enter Command: ED-ATTR-EQPT:::CTAG::TMO=5000;

Enter Command: ED-ATTR-EQPT:::CTAG::SHELF=93;

2.5. Retrieve the Equipment table and response should be as shown below:

Enter command: RTRV-ATTR-EQPT:::CTAG;

Response:

LABBRTU01 05-04-12 09:42:39 M CTAG COMPLD "SHELF=93 TSC=ON REPORT=FULL EQLR=0 TMO=5000SECS LEV=REL" "IDLE=TC CYCLETEST=OFF DS1DS3=OFF"

2.6 Retrieve the BRTU-93 firmware version

Enter Command: RTRV-VRSN-EQPT:::CTAG; LABBRTU01 05-04-12 09:42:45 M D COMPLD /*CARD APPL/PGM1 BOOT/PGM2 DSP HW ASSY / " E1U-01-03: RC02.80 RE03.30 6700-1280-02 REV G4 OPT " " E1U-01-04: RC02.80 RE03.30 6700-1280-02 REV G4 OPT " " DAT-01-05: RC02.30 RF03.30 6700-1740-03 REV B1 OPT " " DAT-01-06: RC02.30 RF03.30 6700-1740-03 REV B1 OPT " " FPU-01-07: RA02.20 RA02.20 6700-1657-02 REV A1 OPT " " SCU-01-20: RH13.70 RH13.30 6700-1652-01 REV B8 OPT " " PSU-01-21: 3500-1624-11 REV F7 OPT " Results shown above are the latest firmware version of the BRTU-93. The eSCU firmware should be at least version 13.70 or higher.

2.7 Edit the BRTU-93 IP address as required.

Enter Command: ED-ATTR-IP::J46:CTAG::ADDR= 172.30.26.14; --- IP Address

Enter Command: ED-ATTR-IP::J46:CTAG::MASK=255.255.255.0; --- Subnet Mask

Enter Command: ED-ATTR-IP::J46:CTAG::GATEWAY= 172.30.26.254; --- Gateway

NOTE: Changes to the TCP/IP parameters will take effect only after the BRTU-93 has been rebooted. You need to issue the INIT-SYS:::CTAG::4; command for the TCP/IP changes to take effect.



2.8 Edit the BRTU-93 Async Link Table Note: Per our example drawn in figure 1-4 Async port J39 is used as the TSC communication port to

the TCS532 hence the J39 pot of the BRTU-93 has to be set to match with the TCS532 Async port.

Enter Command: ED-ATTR-LINK::J39:CTAG::ECHO=OFF;

Enter Command: ED-ATTR-LINK::J39:CTAG::96008N1;

Enter Command: ED-ATTR-LINK::J39:CTAG::SLAVE=ON; 2.9 Retrieve the BRTU-93 Async Link configuration

Enter Command: RTRV-ATTR-LINK:::CTAG;

Response:

LABBRTU01 05-04-12 09:42:45 M D COMPLD /* JID TADR UART ECHO FLOW RAW BROAD SLAVE LOGIN DTR */ " J32 SCU-14-01 12008N1 ON ON OFF ON OFF OFF " " J33 SCU-14-00 12008N1 ON ON OFF ON OFF ON DTR FIXED" " J39 SCU-14-03 96008N1 OFF ON OFF ON OFF ON DTR " " J40 SCU-14-02 12008N1 ON ON OFF ON OFF OFF "

Note: Ensure that the J39 port is configured as shown in the shown above



2.10 Edit the BRTU-93 TAU 2.10.2 TAU table set up for the Tellabs TCS532 DCS: Note: The TAU configuration that is used in this example based on the example drawings shown in

figure 1-4 TID used in this step are examples only, refer to REACT Administrator for the assigned TID.

Enter Command: ED-DB-TAU::E-LAB532L:CTAG::TYPE=TCS532,JID=J39;

E-LAB532L = is the given Test Identifier for the DCS. This should match with the TID in REACT test resource set for that DCS and BRTU-93. TYPE = Access Type enter TCS532 for Tellabs TCS532 JID = J39 as the TSC port (async as shown in figure 1-4) Note: If the TCS532 uses TCPIP connection, the BRTU-93 can use that connection for its TSC connection to the DCS. Shown below is an example of TAU table with TCPIP used for TSC communication between the BRTU-93 and the TCS532 DCS. Enter Command: ED-DB-TAU::LAB-32:CTAG::TYPE=TCS532,JID=J46,ADDRESS=10.22.33.44- 23, CTYPE=TELNET,PERSIST=YES; Note: TCPIP shown in this command is example only. Please refer to the REACT Administrator for the correct IP address of the DCS.

2.11 Retrieve the TAU Table: Enter Command: RTRV-DB-TAU::ALL:CTAG;

LAB-HEKIMIAN 05-11-08 06:28:38 M D COMPLD /* TID TYPE REVISION AIDFMT ROUTE */ /* JID ADDRESS CTYPE PERSIST MAXCONN */ /* UID PID LOGIN */ " E-LAB532L TCS532 00.00 322 0 J39 0 0 YES 1 0 0 Y " LAB-HEKIMIAN 05-11-08 06:28:38 M D COMPLD /* TID TYPE REVISION AIDFMT ROUTE */ /* JID ADDRESS CTYPE PERSIST MAXCONN */ /* UID PID LOGIN */ " E-LAB532L TCS532 00.00 322 0 J46 10.22.33.44-23 TELNET YES 1 0 0 Y "

Note In the event that entry in the TAU table that needs to be removed, the following command can be used to remove it:

ED-DB-TAU::E-LAB532L:CTAG::DELETE;

ASYNC TSC PORT

TCPIP TSC PORT



2.11 TAP Table Set Up

Edit the BRTU TAP table FAD+ card installed in slot 7 of the BRTU-93. For the FAD that is installed in slot 7 of the BRTU-93 the assigned TAP number for its slot is TAP 1, 2, 3. Please not since that FAD+ is used only first 2 TAP can be assigned. Low speed interface can be installed in slot 7 and slot 12. Please refer to the drawing shown below for more information on TAP assignments per slots of the BRTU-93.

BRTU-93 TAPID assignment

Enter Command: ED-DB-TAP::1:CTAG::TID=E-LAB532L,TAPID=101,FR=F,LC=H,

TPA=FFFFFFFFFFFFFFF,TCA=TTTTTTTTTTTTTTT;

Enter Command: ED-DB-TAP::2:CTAG::TID=E-LAB532L,TAPID=103,FR=F,LC=H, TPA=FFFFFFFFFFFFFFF,TCA=TTTTTTTTTTTTTTT;

TAPID=101/103 – This is the TACC number (1-999 odd) of the first FAD). FR=F - Framing is set as F for MF24 other Framing option is shown below:

FRAMING (FR) Framing for a TAD interface (DS1, E1, or DS3) or FR B indicates MF16 and CRC-4 (BRTU and ITU-T DRTU only) M indicates MF16 (BRTU and ITU-T DRTU only) C indicates MF2 and CRC-4 4 (BRTU and ITUT DRTU only) F indicates MF24 (BRTU and ITU-T DRTU only) SF indicates superframe (BRTU and DRTU only) ESF indicates superframe (BRTU and DRTU) M23 indicates M23 DS3 framing (BRTU DS3 only) CBP indicates CBP DS3 framing (BRTU DS3 only)

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BRTU-93 Main Shelf (ED-ATTR-EQPT:::CTAG::SHELF=93;)

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(8) Test Bus Max. per side (8) Test Bus Max. per side

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BRTU-93 Main Shelf (ED-ATTR-EQPT:::CTAG::SHELF=93;)

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LC = H - Line Code is set to H for HDB3 other line code option is shown below:

LINECODE (LC) Line code for a TAD interface (DS1, E1, or DS3) or LC

H indicates high density bipolar 3 (BRTU and ITU-T DRTU only) AMI or A indicates alternate mark inversion B8ZS indicates bipolar eight zero substitution (BRTU and DRTU only) B3ZS indicates bipolar three substitutions (BRTU DS3 only)

2.12 Retrieve the TAP table: Enter Command: RTRV-DB-TAP::ALL:CTAG;

LAB-HEKIMIAN 05-11-08 06:28:43 M D COMPLD /* TPID TID STATUS TAPID TAPID2 */ /* TYPE FR LC EQ TPA TCA */ /* CONCAID ACCESSRATE TAPTYPE TIMING S-TRACE */ /* OPTIONS " 1 E-LAB532L F 101 0 TCS532 0 0 1 FFFFFFFFFFFFFFF TTTTTTTTTTTTTTT 1 0 0 0 01 “ 2 E-LAB532L F 103 0 TCS532 0 0 1 FFFFFFFFFFFFFFF TTTTTTTTTTTTTTT 1 0 0 0 01



3.00 E1 Circuit Access Test

This section provides test procedures for E1 testing. It is assumed that the configurations in steps 1 and 2 of this procedure are complete and that the DCS ports and test circuits are configured and available.

3.1 E1 Testing Through Hardwire Loops

E1 testing through hardwire loops will use installed 6716-71 E1 test card(s) to generate E1 signal on the transmission path through the loop and return to itself. Install hardwire loops on the circuit under test.

Figure 3-1 Install jumpers on the Circuit Under test

NOTE: TID and SID should not be the same name tid = Target system identification (CLLI and system number) sid = Site identifier or name of the BRTU-93

3.1.1 Establish the access by entering the following command:

Enter command: CONN-TACC-E1:E-LAB532L:1011:CTAG:999:SPLTF;

Response:

E-LAB532L 06-10-24 10:49:50

M CTAG COMPLD

U-U

NTD=A

3.1.2 CHG-TSTSIG-E1

Enter command: CHG-TSTSIG-E1::999:CTAG:QRS,M,H;

Response:

E-LAB532L 06-10-24 10:50:50

M CTAG COMPLD

BRTU

E1 FAD+

TELLABS

TCS532 DCS

F E

A Z

BRTU

E1 FAD+

TELLABS

TCS532 DCS

F E

A Z



3.1.3 MEAS-SIG-E1

Enter command: MEAS-SIG-E1::999:CTAG:1,15,QRS,M,H;

NOTE: The process will display an update test result screen in every 15 sec. interval until it reaches one minute.

Response: (Last test result screen)

E-LAB532L 06-10-24 10:51:16

M CTAG COMPLD

1-0, 0, , 0, 0,

QRS ES=0, TE=0

BPV ES=0, TE=0

MF TE=0

MFAS ALM=0, RMT MFAS ALM=0

SES=0, FS=NA

PSL=0, PSLS=0.0

FSL=0, FSLS=0.0

UAS=0, %AS=100.000

DGRM=0, %DGRM=0.000

%EFS=100.000, BITS=1.229e+08

TEST COMPLETED

;

NOTE: Ensure that there are no errors in a one minute test.

3.1.4 Change test direction from facility to equipment side

Enter command: CHG-ACCMD-E1::999:CTAG:SPLTE;

Response:

E-LAB532L 06-10-24 10:52:18

M CTAG COMPLD



3.1.5 MEAS-SIG-E1

Command string: MEAS-SIG-E1::<tsn>:<ctag>:<dur>,<ri>, <tstsig>,<fr>,<lncd>;

Enter command: MEAS-SIG-E1::999:CTAG:1,15,QRS,M,H;

NOTE: The process will display an update test result screen in every 15 sec. interval until it reaches one minute.

Response: (Last test result screen)

E-LAB532L 06-10-24 10:53:36

M CTAG COMPLD

1-0, 0, , 0, 0,

QRS ES=0, TE=0

BPV ES=0, TE=0

MF TE=0

MFAS ALM=0, RMT MFAS ALM=0

SES=0, FS=NA

PSL=0, PSLS=0.0

FSL=0, FSLS=0.0

UAS=0, %AS=100.000

DGRM=0, %DGRM=0.000

%EFS=100.000, BITS=1.229e+08

TEST COMPLETED

;

NOTE: Ensure that there are no errors in a one minute test.

3.1.6 DISC-TACC

Command string: DISC-TACC::<tsn>:<ctag>;

Enter command: DISC-TACC::999:CTAG;

Response:

CONCERT-LAB-532 00-10-12 10:53:53

M CTAG COMPLD

At this point, the first E1 access between the BRTU and TCS532 is tested and is working properly.



3.2 Fractional E1 Access Test (Access up to 30 time slot).

Use an E1 test set as an external E1 signal source to generate E1 to feed circuit under test. Install a hardwire loop at the Equipment side of the circuit and Portable test set at the Facility side of the circuit as shown in the example below.

3.2.1 Connect Test Access Fractional E1 up to 30 time slots:

Ensure that the Framing is set up properly in the BRTU TAP table, DCS TAP and the circuit under test. The Framing can be set to either MF24 or MF2

Enter command: CONN-TACC-E0E30:E-LAB532L:02-1&&-30:CTAG:999:N;

Response: E-LAB532L 97-03-12 15:49:27 M 0 COMPLD /* Note: Access rate is greater than test rate */

NOTE:

The last three characters of the command code (E0y) define the speed of the circuit test: • E0A indicates 2.4 kbps • E0B indicates 4.8 kbps • E0C indicates 9.6 kbps • E0D indicates 56 kbps • E0Dn indicates Nx56 kbps (56k fractional E1) • E0E indicates 64 kbps • E0En indicates Nx64 kbps (64k fractional E1) When initiated with this command, a test session that is derived from an E1 FAD always brings up the access in dual FAD mode. In this configuration, two data cards are allocated to the test session since the E1 FAD only routes full E1 signals.

BRTU

E1 FAD+

TELLABS

TCS532 DCS

F E

A Z

Portable

Test

Equipment

BRTU

E1 FAD+

TELLABS

TCS532 DCS

F E

A Z

BRTU

E1 FAD+

TELLABS

TCS532 DCS

F E

A Z

Portable

Test

Equipment



For fractional E1, the addresses of the time slots must be entered in the <aid> field in the form 021-06&&-12 for consecutive time slots and in the form 021-06&-08&-10&-12 for distributed time slots. In addition, both grouped time slots and distributed time slots can be included in one command. For example, 021-06&&-10&-12&-14 indicates time slots 06 through 10 and 12 and 14.

3.2.2 Change the access from monitor access to split mode.

Enter command: CHG-SPLT-DDS::999:CTAG; Response: E-LAB532L 97-03-12 15:49:36 M CTAG COMPLD

3.2.3 Test Straightaway on Equipment Direction (Hardwire Loop as shown in the drawing shown in step 3.2.:

Enter command: TST-STRHTY-DDS::999:CTAG:E,B,QRS,Y,1,0,15;

Response: E-LAB532L 97-03-12 15:49:1652 M CTAG COMPLD BE=6, ES=1, 1-0 BER=1.536e-06 SES=0 PSL=0, PSLS=0.0, PSLEB=0.000e+00 FSL=0, FSLS=0.0 UAS=0, %AS=100.000 DGRM=1, %DGRM=100.000 %EFS=98.333, BITS=3.840e+06 TEST COMPLETED ; NOTE: Y = YES, inserts 6 bit errors in a test. Therefore, ensure that the test result reads 6 bit errors. Other

option is N for no bit error insertion. 3.2.4 Release the access by entering the following command: Enter Command: DISC-TACC::999:CTAG;

E-LAB532L 97-03-12 15:49:1652 M CTAG COMPLD



3.2.5 Fractional E1 test on the Facility Direction Connect the test set to the Equipment direction and hardwire loop at the Facility as shown in the drawing below: 3.2.1 Connect Test Access Fractional E1 up to 30 time slots.

Enter command: CONN-TACC-E0E30:E-LAB532L:02-1&&-30:CTAG:999:N;

Response: E-LAB532L 97-03-12 15:49:27 M 0 COMPLD

3.2.2 Change the access from monitor access to split mode.

Enter command: CHG-SPLT-DDS::999:CTAG; Response: E-LAB532L 97-03-12 15:49:36 M CTAG COMPLD

BRTU

E1 FAD+

TELLABS

TCS532 DCS

F E

A Z

Portable

Test

Equipment

BRTU

E1 FAD+

TELLABS

TCS532 DCS

F E

A Z

BRTU

E1 FAD+

TELLABS

TCS532 DCS

F E

A Z

Portable

Test

Equipment



3.2.3 Test Straightaway on Equipment Direction (Hardwire Loop as shown in the drawing shown in step 3.2.:

Enter command: TST-STRHTY-DDS::999:CTAG:F,B,QRS,Y,1,0,15;

Response: E-LAB532L 97-03-12 15:49:1652 M CTAG COMPLD BE=6, ES=1, 1-0 BER=1.536e-06 SES=0 PSL=0, PSLS=0.0, PSLEB=0.000e+00 FSL=0, FSLS=0.0 UAS=0, %AS=100.000 DGRM=1, %DGRM=100.000 %EFS=98.333, BITS=3.840e+06 TEST COMPLETED ; NOTE: Y = YES, inserts 6 bit errors in a test. Therefore, ensure that the test results reads 6 bit errors.

3.2.4 Release the access by entering the following command: Enter Command: DISC-TACC::999:CTAG;

E-LAB532L 97-03-12 15:49:1652 M CTAG COMPLD



4.0 REACT TEST RESOURCE CONFIGURATION FOR BRTU E1 and E0 ACCESS WITH THE TELLABS TCS532 DCS. 4.1 Set the Telnet Database to include the address of the BRTU

%*LABB 878 TCPIP_172.30.26.14_7010 IP address for BRTU

Note: Address and ports used are examples only; refer to REACT admin for the assigned address. Enter COM-LINK Direct/Modem/Remote/PAD X28 (D/M/R/P): R

6439 module, DATS, SUPER DCS, HLI CONC, DC/B, DCS, none (6439/DATS/SD/C/D/A/N): N Enter ABILITY: ANALOG,CHANNELIZE,PERFORMANCE,ANALOG/CHANNELIZE,DDS, TA200PM,PBX,DS3/E3,ISDN,DCS LOOP,DSLAM,ICON ATM SW,ADSL RTR,IP TPUT,FR SW,STM,PON,STS1,STS3C,STS12C,VC3,STM1,STM4,IP_N (A/C/P/(A/C)/DDS/T/X/3/I/DCSL/D/ICON/SW/R/IP/F/M/PON/S1/S3/S12 /VC3/STM1/STM4/IP_TLS/IP_VPN): P Is this a TR834 , natively supported , or foreign site (T/N/F): T Enter Modem number: %*LABB Enter name (15 chars. max): E-LAB532L Is this a CEPT device(Y/N)?: Y Is this a Hekimian BRTU (Y/N)?: Y Is this resource a 6750 RTU or 6750 TSC? (R/T): T Enter FAD/TAD hardware number, 0 disables FAD locking (00-99)?: 0 Is this a STSx TAD or other access(T/O)?: O Is this an E3 FAD or other access(F/O)?: O Individual DCS port, 6439 port (I/C): I Enter type of DCS: WECO, TDAX, RDX, TELL, DSXpert, ERICCSON MV-36, OTHER (W,X,R,T,P,V,O): O See note below: Enter DCS port: Enter DCS link number, 0 to ignore: 0 Enter digroup/fad for test set: 1 Do you have a Remote controlled Reset Box for this resource (Y/N): N Enter REACT 2001 primary test server host: HOST Enter REACT 2001 secondary test server host: HOST Enter REACT 2001 RTU Label: RTU SAVE THE EDIT



REACT Test resource for DDS Test: Enter COM-LINK Direct/Modem/Remote/PAD X28 (D/M/R/P): R

6439 module, DATS, SUPER DCS, HLI CONC, DC/B, DCS, none (6439/DATS/SD/C/D/A/N): N Enter ABILITY: ANALOG,CHANNELIZE,PERFORMANCE,ANALOG/CHANNELIZE,DDS, TA200PM,PBX,DS3/E3,ISDN,DCS LOOP,DSLAM,ICON ATM SW,ADSL RTR,IP TPUT,FR SW,STM,PON,STS1,STS3C,STS12C,VC3,STM1,STM4,IP_N (A/C/P/(A/C)/DDS/T/X/3/I/DCSL/D/ICON/SW/R/IP/F/M/PON/S1/S3/S12 /VC3/STM1/STM4/IP_TLS/IP_VPN): DDS Enter Modem number: %*LABB Equipped with PVS (Y/N)?: N Enter name (15 chars. max): E-LAB532L Is this a CEPT device(Y/N)?: Y Is this a Hekimian BRTU (Y/N)?: Y Is this resource a 6750 RTU or 6750 TSC? (R/T): T Enter FAD/TAD hardware number, 0 disables FAD locking (00-99)?: 0 Is this a STSx TAD or other access(T/O)?: O Is this an E3 FAD or other access(F/O)?: O Individual DCS port, 6439 port (I/C): I Individual DCS port, 6439 port (I/C): I Enter type of DCS: WECO, TELLABS, MATRIX SWITCH, RDX, TDAX, TDAX NB, OTHER (W,T,M,R,X,B,O): T Enter DCS link number, 0 to ignore: 0 Enter test port: 1 Enter TAD framing MF16+CRC4, MF16, MF2+CRC4, or MF2 (B/M/C/F): F Enter TAD line coding AMI or HDB3 (A/H): H Do you have a Remote controlled Reset Box for this resource (Y/N): N Enter REACT 2001 primary test server host: HOST Enter REACT 2001 primary test server host: HOST Enter REACT 2001 secondary test server host: HOST Enter REACT 2001 RTU Label: RTU Display only this position? (y/n): Y SAVE THE EDIT Note: Prior to REACT version 3.800 the maximum Fractional E1 access with TCS532 is 15 timeslot. Therefore for DCS type selection you need not to select Tellabs for your DCS type. Since that we are configured in TSC mode not selecting Tellabs will not make effect with the access command sent to the BRTU.



TEST RESOURCE STATUS

TYPE LONG TERM POS. TP/SIDE ABILITY LINK DEV. 3965 3705 MODEM/PORT1 PORT2 PASSWORD DCS/LNK D-PORT STATUS TEST NAME

---------------------------------------------------------------------------------------------------------- ----------------------- 186 001/- E1 REMOTE ---- TSC %*LABB TA/E1 -----/00 OUT FREE ELAB532L 187 001/- DDS REMOTE ---- TSC %*LABB TA/DDSE ----/00 OUT FREE E-LAB532L

4.3 Contact REACT Administrator and establish the access using the REACT and verify a successful access from the REACT.



5.0 Testing E1 and Fractional E1 using REACT 5.1 This section provides test procedures for E1 testing using the REACT. It is assumed that the configuration in steps 1 and 2 of this procedure is complete and that the DCS ports and test circuits are configured and available.

5.1.1 E1 testing through hardwire loops will use installed 6716-71 E1 test card(s) to generate E1 signal on the transmission path through the loop and return to itself. Install hardwire loops on the circuit under test.

Figure 5-1 Install jumpers on the Circuit Under test

5.1.2 Login to the REACT by entering your user name and password followed by the OK button

BRTU

E1 FAD+

TELLABS

TCS532 DCS

F E

A Z

BRTU

E1 FAD+

TELLABS

TCS532 DCS

F E

A Z



5.1.3 At the REACT testing manager dialog select DS1/E1 testing as shown in the example below. 5.1.4 DS1/E1 Test circuit as shown below should appear. Click on the E1-DCS box to start the E1 test.



5.1.5 Enter the Test Identifier and the Access Identifier as shown the example below followed by the OK button. Note: TID and the AID used in this step are examples only. 5.1.6 Verify the access is established as shown in the example below.



5.1.7 Click on the SPLIT button – the split dialog box should appear. Select the direction of the circuit to test and click on box to check for the hardwire loop followed by the OK button. 5.1.8 Verify the circuit is split and that since hardwire loop is installed in both direction of the circuit Loopback detected should report in the test results window as shown in the example below. Click on the BERT button to continue.



5.1.9 Bit Error Test (BERT) window should appear. Select the direction of the test and click on the Internal Timing. Select the signal and set the time duration to 2.15 minutes test followed by the OK button.

5.1.10 Live Results will appear – verify a clean test as shown in the example below. Click on the OK button to continue.



5.1.11 REACT test window should appear verify that the results on the result window should display with no error. While the test is running click on the Inject Errors button.

5.1.12 Inject Errors window should appear. Click on the Bit Errors and enter the number of errors to inject followed by the OK button. As an example below 25 bit errors is injected to the circuit under test.



5.1.13 Verify that 25 bit error shows in the test results. Click on the OK button to continue.

5.1.14 Verify that 25 bit error shows in the test results. When the test is over (2.15 minutes after) click on the Chg Direction button to switch the test direction from the Z direction to the A direction.



5.1.15 Verify that the direction of the test is now changed to A (Facility) direction by checking the orange line now facing the A direction. Click on the BERT button to continue.

5.1.16 Bit Error Test (BERT) window should appear. Select the direction of the test this time will be the A (Facility) direction and click on the Internal Timing. Select the signal and set the time duration to 2.15 minutes test followed by the OK button.



5.1.19 Inject Errors window should appear. Click on the Bit Errors and enter the number of errors to inject followed by the OK button. This time as an example below 50 bit errors is injected to the circuit under test.




5.1.21 Verify that 50 bit error shows in the test results. When the test is over click on the release button to release the access. 5.1.22 Verify that the circuit is release as shown in the example below. Click on file and quit to exit out the E1 test window.



5.2 This section provides test procedures for Fractional E1 testing using the REACT. It is assumed that the configuration in steps 1 and 2 of this procedure is complete and that the DCS ports and test circuits are configured and available.

5.2.1 Use an E1 test set as an external E1 signal source to generate E1 to feed circuit under test. Install a hardwire loop at the Equipment side of the circuit and Portable test set at the Facility side of the circuit as shown in the example below.

Ensure that the Framing is set up properly in the BRTU TAP table, DCS TAP and the circuit under test. The Framing can be set to either MF24 or MF2

BRTU

E1 FAD+

TELLABS

TCS532 DCS

F E

A Z

Portable

Test

Equipment

BRTU

E1 FAD+

TELLABS

TCS532 DCS

F E

A Z

BRTU

E1 FAD+

TELLABS

TCS532 DCS

F E

A Z

Portable

Test

Equipment



5.2.2 At the REACT testing manager dialog select DS1/E1 testing as shown in the example below. 5.2.3 DDS Test circuit as shown below should appear. Click on the E1-DCS box to start the DDS test.



5.2.4 Enter the Test Identifier and the Access Identifier as shown the example below followed by the OK button.

Note:

1. For fractional E1, the addresses of the time slots must be entered in the <aid> field in the form 021-06&&-12 for consecutive time slots and in the form 021-06&-08&-10&-12 for distributed time slots. In addition, both grouped time slots and distributed time slots can be included in one command. For example, 021-06&&-10&-12&-14 indicates time slots 06 through 10 and 12 and 14. 2. For accessing 30 Factional E1 make sure that the data rate is set to 64 and the Framing is set to MF2.

3. Note: TID and the AID used in this step are examples only.



5.2.5 Verify the access is established as shown in the example below. 5.2.6 Click on the SPLIT button – the split dialog box should appear. Select the direction of the circuit to test and click on box to check for the hardwire loop followed by the OK button.



5.2.7 Verify the circuit is split as shown in the example below. Click on the Primary Channels button to continue. 5.2.8 DDS Primary Channel test window should appear. Select the direction of the test and select the signal and set the time duration to 1.15 minutes test (or more) followed by the OK button.



5.2.11 The DDS Inject Errors window should appear. Click on the Bit Errors and enter the number of errors to inject followed by the OK button. As an example below 6 bit errors is injected to the circuit under test.




5.2.13 Verify that 6 bit error shows in the test results. When the test is over (1.15 minutes after) click on the Split button to switch the test direction from the Z direction to the A direction. 5.2.14 Select the direction to test followed by the OK button.



5.2.15 Verify that the direction of the test is now changed to A (Facility) direction by checking the orange line now facing the A direction.

5.2.16 Connect the test set to the Equipment direction and hardwire loop at the Facility as shown in the drawing below: Then click on the Primary Channel button.

BRTU

E1 FAD+

TELLABS

TCS532 DCS

F E

A Z

Portable

Test

Equipment

BRTU

E1 FAD+

TELLABS

TCS532 DCS

F E

A Z

BRTU

E1 FAD+

TELLABS

TCS532 DCS

F E

A Z

Portable

Test

Equipment



5.2.17 DDS Primary Channel test window should appear. Select the direction of the test and select the signal and set the time duration to 1.15 minutes test (or more) followed by the OK button.





5.2.20 The DDS Inject Errors window should appear. Click on the Bit Errors and enter the number of errors to inject followed by the OK button. As an example below 20 bit errors is injected to the circuit under test.




5.2.22 Verify that 20 bit error shows in the test results. When the test is over (1.15 minutes after) release button to release the access.



5.2.23 Verify that the circuit is release as shown in the example below. Click on file and quit to exit out the DDS test window.



5.2.24 Exit out of REACT by clicking on the File followed by Quit as shown below. 5.2.25 Click on Yes to continue exit off the REACT 5.2.26 Remove the Portable test set and the hardwire loop connected in the circuit under test.

END

model 6750 brtu-93 with tellabs tcs532l - oracle … · interface and test cards) figure 1-2 model...

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