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Mobile TV Integrated Circuits
Design of a Low-Voltage Multi-Standard Sigma-Delta Modulator
Carlos André Faria Calisto
Dissertation submitted for obtaining the degree of
Master in Electrical and Computer Engineering
Jury
Supervisor: Prof. Carlos Leme
Co-Supervisor: Prof. João Vaz
President: Prof. Marcelino Santos
Members: Prof. Jorge Fernandes
January 2009
i
Acknowledgments
First, I would like to thank the board of Chipidea, for giving me the opportunity to develop my master
thesis in a state-of-the-art industrial environment and for the excellent working conditions that were
given.
I would like to acknowledge my advisor, Professor Carlos Leme, for his guidance and support. I also
want to thank Marco Oliveira for his invaluable assistance and advice on issues related to the design
of sigma-delta modulators and Tiago Patrão for his knowledge and insights in analog design.
I would like to thank all my colleagues at Chipidea for their friendship and all their help, Diogo Calado,
André Teixeira, André Carvalho, Hélder, José Brito, José Jesus, Proença, Rodrigo Duarte, Angelo,
Alexandre, Luis, Pedro Acabado, David Lousada, just to name a few.
I would also like to thank all my colleagues at Instituto Superior Técnico for the conversations and
coffee breaks, Ricardo Preguiça, David Copeto, Tiago Gaspar, Sérgio Brás, Sérgio Paiva, Ruben,
José Guerra, Gabriel, Miguel Barros, Sara, Guilherme, Hugo Varandas, Vasco Andrade e Silva and
Rui Francisco, among others.
I would like to express my gratitude to my personal friends that supported me over the last few years,
Rui Pascoal, Luis João, Renato Sousa, Joana Sismeiro, João Monteiro, André Sousa, Nuno Moita
and Miguel Marques.
Finally I would like to thank my parents, my brother and my sister for their love and encouragement. I
admire my parents’ determination and sacrifice to put me through college.
ii
Abstract
Mobile Television integrates two of the most popular consumer products ever: television and mobile
phone. Moreover, the co-existence of numerous standards defined for wireless communication
increases the need for interoperability between various technologies. Therefore, the integration of
several radio interfaces into programmable and reconfigurable hardware supporting multiple standards
and multiple frequency bands becomes extremely important.
This thesis describes the design of a programmable bandwidth, low-voltage and low-power Sigma-
Delta Modulator in an 80nm CMOS technology. First the system is modeled and validated in Matlab
environment with use of behavioral models. Then the electrical design is optimized for low-power and
robustness.
The 3rd
order, 12 levels architecture supports the standards GSM, CDMA2000, UMTS and DVB-H.
The Sigma-Delta Modulator designed in a 1V supply technology, achieves a peak SNR of 64dB for
GSM (100kHz signal band) and 57dB for DVB-H (4MHz signal band) consuming between 2.6 and
6mA.
Keywords
Mobile Television, programmable, multiple standards, Sigma-Delta Modulator, low-voltage, low-power.
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Resumo
Televisão móvel integra dois dos produtos mais populares de sempre: a televisão e o telefone móvel.
Além disso, a co-existência de vários standards para comunicação sem fios aumenta a necessidade
de interoperabilidade entre várias tecnologias. Desta forma, a integração de várias interfaces de rádio
em hardware reconfigurável e programável capaz de suportar múltiplos standards e múltiplas bandas
de sinal, torna-se muito importante.
Esta tese descreve o desenho de um modulador Sigma-Delta de baixo consumo e de baixa tensão de
alimentação com largura de banda programável, numa tecnologia CMOS de 80nm. Primeiro, o
sistema é modelado e validado no ambiente Matlab com o apoio de modelos comportamentais. De
seguida, o desenho eléctrico é optimizado para consumo reduzido e robustez.
A arquitectura de 3ª ordem e de 12 níveis suporta os standards GSM, CDMA2000, UMTS e DVB-H. O
modulador Sigma-Delta alimentado a 1V, atinge SNR máximo de 64dB para GSM (banda de sinal de
100kHz) e um SNR máximo de 57dB para DVB-H (banda de sinal de 4MHz).
Palavras-chave
Televisão móvel, programável, múltiplos standards, modulador Sigma-Delta, baixo consumo, tensão
de alimentação baixa
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Table of Contents
ACKNOWLEDGMENTS ..................................................................................................................................... I
ABSTRACT ..................................................................................................................................................... II
RESUMO ....................................................................................................................................................... III
TABLE OF CONTENTS .................................................................................................................................... IV
LIST OF FIGURES ......................................................................................................................................... VIII
LIST OF ACRONYMS ...................................................................................................................................... XI
LIST OF SYMBOLS ....................................................................................................................................... XIII
CHAPTER 1 INTRODUCTION ........................................................................................................................ 1
1.1 OVERVIEW .................................................................................................................................................. 1
1.2 MOTIVATION ............................................................................................................................................... 2
1.3 THESIS ORGANIZATION .................................................................................................................................. 3
CHAPTER 2 THE ΣΣΣΣ−−−−∆∆∆∆ ADC IN WIRELESS COMMUNICATIONS SYSTEMS ........................................................ 5
2.1 IDEAL TRANSCEIVER ...................................................................................................................................... 5
2.2 WIRELESS TRANSCEIVER GENERAL ARCHITECTURE ............................................................................................... 6
2.3 THE Σ-∆ ADC ............................................................................................................................................. 6
2.4 SIGNAL-TO-NOISE RATIO AND DYNAMIC RANGE ................................................................................................... 7
2.5 SYSTEM SPECIFICATIONS ................................................................................................................................ 7
CHAPTER 3 THE ΣΣΣΣ−−−−∆∆∆∆ ADC ........................................................................................................................... 9
3.1 ANALOG TO DIGITAL CONVERSION ................................................................................................................... 9
3.1.1 Sampling and the Anti-Aliasing filter ............................................................................................... 9
3.1.2 Ideal A/D Conversion ..................................................................................................................... 11
3.1.3 Quantization noise ......................................................................................................................... 12
3.2 NYQUIST-RATE ADC ................................................................................................................................... 14
3.3 LIMITATIONS OF NYQUIST-RATE ADCS ........................................................................................................... 15
3.4 OVERSAMPLING ......................................................................................................................................... 16
3.5 NOISE SHAPING .......................................................................................................................................... 17
v
3.6 THE Σ−∆ MODULATOR ............................................................................................................................... 19
3.6.1 Single-stage Single-bit Σ−∆ Modulator ......................................................................................... 19
3.6.2 Single-Stage Multi-Bit Σ−∆ Modulator .......................................................................................... 23
3.6.3 Multi-Stage Σ−∆ Modulator .......................................................................................................... 23
3.6.4 Feedforward Σ−∆ Modulator ........................................................................................................ 25
3.6.5 Summary ........................................................................................................................................ 26
CHAPTER 4 SYSTEM SPECIFICATIONS ........................................................................................................ 27
4.1 NOISE POWER SPECIFICATION ....................................................................................................................... 27
4.2 THE Σ−∆ MODULATOR ............................................................................................................................... 28
4.2.1 Power consumption ....................................................................................................................... 29
4.2.2 Architecture ................................................................................................................................... 29
4.3 SYSTEM MODELING ..................................................................................................................................... 30
4.3.1 Integrators’ Gains .......................................................................................................................... 31
4.3.2 Non-idealities ................................................................................................................................. 32
4.4 FUNCTIONAL SIMULATION ............................................................................................................................ 41
4.5 SIMULATION RESULTS .................................................................................................................................. 42
4.5.1 Ideal Modulator ............................................................................................................................. 42
4.5.2 Real Modulator .............................................................................................................................. 43
CHAPTER 5 CIRCUIT DESIGN ..................................................................................................................... 46
5.1 INTEGRATORS ............................................................................................................................................ 46
5.1.1 Capacitors Design .......................................................................................................................... 46
5.1.2 Switches Design ............................................................................................................................. 52
5.1.3 Multi-Standard Adaptability .......................................................................................................... 53
5.1.4 Operational Amplifier Specifications ............................................................................................. 54
5.2 PROGRAMMABLE AMPLIFIER DESIGN .............................................................................................................. 56
5.2.1 Topology ........................................................................................................................................ 56
5.2.2 Frequency response ....................................................................................................................... 57
5.2.3 Noise .............................................................................................................................................. 60
vi
5.2.4 Offset voltage ................................................................................................................................ 61
5.2.5 Slew-rate ........................................................................................................................................ 62
5.2.6 Distortion ....................................................................................................................................... 62
5.2.7 Project ............................................................................................................................................ 63
5.2.8 Common-mode feedback circuit .................................................................................................... 64
5.2.9 Bias Circuit ..................................................................................................................................... 65
5.3 INTERNAL A/D CONVERTER .......................................................................................................................... 66
5.3.1 Resolution ...................................................................................................................................... 67
5.3.2 Comparator.................................................................................................................................... 68
5.3.3 Resistors String .............................................................................................................................. 69
5.4 DWA DAC ............................................................................................................................................... 70
5.5 CLOCK GENERATOR ..................................................................................................................................... 71
CHAPTER 6 RESULTS ................................................................................................................................. 73
6.1 1ST
INTEGRATOR ......................................................................................................................................... 74
6.2 Σ−∆ MODULATOR .................................................................................................................................... 79
CHAPTER 7 CONCLUSIONS ........................................................................................................................ 82
7.1 RESULTS ANALYSIS ...................................................................................................................................... 82
7.2 FUTURE WORK .......................................................................................................................................... 82
APPENDIX1 NOISE ..................................................................................................................................... 84
A1.1 CMOS INHERENT NOISE .............................................................................................................................. 84
A1.1.1 Thermal noise ................................................................................................................................ 84
A1.1.2 1/f noise ......................................................................................................................................... 85
A1.2 NOISY DEVICES ........................................................................................................................................... 85
A1.2.1 Resistors ......................................................................................................................................... 85
A1.2.2 MOS transistor ............................................................................................................................... 86
A1.3 BASIC BLOCKS ............................................................................................................................................ 87
A1.3.1 Switched-Capacitor ........................................................................................................................ 87
A1.3.2 Operational Amplifier .................................................................................................................... 88
A1.4 NOISE IN SWITCHED-CAPACITOR INTEGRATORS ................................................................................................ 90
vii
REFERENCES ................................................................................................................................................. 93
viii
List of Figures
Figure 1.1. DTV complementing the existing mobile phone technologies [TI2005]. ............................... 2
Figure 2.1. Ideal integrated transceiver block diagram. .......................................................................... 5
Figure 2.2. Block diagram of a general transceiver. ............................................................................... 6
Figure 2.3. Block diagram of a Sigma-Delta ADC. .................................................................................. 7
Figure 3.1. Block diagram of an ADC. ..................................................................................................... 9
Figure 3.2. Analog input signal (a) and its spectrum (b). ...................................................................... 10
Figure 3.3. Sampling signal ∆T(t) (a) and its frequency spectrum (b). .................................................. 11
Figure 3.4. Discrete-time signal x(n) (a) and its frequency spectrum (b). ............................................. 11
Figure 3.5. Quantized signal as a function of the input signal. ............................................................. 12
Figure 3.6. Quantizer block (a) and its linear model (b). ....................................................................... 12
Figure 3.7. Quantization error as a function of the input signal. ........................................................... 12
Figure 3.8. Power Spectral Density of quantization noise (blue). ......................................................... 13
Figure 3.9. Nyquist-rate sampled signal spectrum (a) and the respective anti-aliasing filter response
(b). ......................................................................................................................................................... 15
Figure 3.10. Block diagram of an Oversampled A/D converter. ............................................................ 16
Figure 3.11. Oversampled signal spectrum (a) and respective anti-aliasinf filter response (b). ........... 16
Figure 3.12. Spectrum of the quantization error at Nyquist-rate (fs1) and Oversampled (fs2). ............... 17
Figure 3.13. First Order Σ−∆ M block diagram (a) and its linear z-domain model (b). .......................... 18
Figure 3.14. Loop filter H(f), signal transfer function STF(f) and noise transfer NTF(f) functions of a
Σ−∆ Modulator. ...................................................................................................................................... 19
Figure 3.15. Single-stage Σ−∆ modulator block diagram. ..................................................................... 20
Figure 3.16. Ideal noise transfer functions for different order Σ−∆Ms with OSR=32. ............................ 21
Figure 3.17. Block diagram of the n-th order single-loop Σ−∆M with coefficients. ................................ 22
Figure 3.18. Block diagram of a 2-2 cascade Σ∆ Modulator. ................................................................ 24
Figure 3.19. Block diagram of a full feedforward Σ−∆ Modulator. ......................................................... 25
Figure 4.1. Sigma-delta ADC system architecture block diagram, including the most important noise
sources. ................................................................................................................................................. 27
Figure 4.2. Lth order N-bit Σ−∆M block diagram. ................................................................................... 28
ix
Figure 4.3. 3rd
Order Σ−∆ modulator block diagram with an Overload Detector for the 3rd
stage and
Dynamic Element Matching (DWA). ...................................................................................................... 30
Figure 4.4. 3rd
Order Σ−∆ modulator. .................................................................................................... 31
Figure 4.5. 3rd
Order Σ−∆ modulator with the integrators output balanced. .......................................... 31
Figure 4.6. 3rd
Order Σ−∆ modulator with the integrators output and power consumption balanced. ... 31
Figure 4.7. Model of an ideal integrator. ............................................................................................... 32
Figure 4.8. Switched-capacitor integrator model. ................................................................................. 33
Figure 4.9. Model of a leaky integrator. ................................................................................................. 34
Figure 4.10. Behavioral model of a integrator with finite DC gain and settling non-idealities. .............. 35
Figure 4.11. Model of the switched-capacitor integrator noise. ............................................................ 37
Figure 4.12. Switch On-Resistance as a function of the input voltage [Khoo1998]. ............................. 37
Figure 4.13. Behavioral model of the internal ADC ............................................................................... 39
Figure 4.14. Behavioral model of the Σ−∆ modulator. ........................................................................... 41
Figure 4.15. First Integrator behavioral model. ..................................................................................... 42
Figure 4.16. Second and third Integrator behavioral models. ............................................................... 42
Figure 4.17. Power Spectral Density of the modulator output for Mode 1 – GSM and Mode 4 – DVB-H.
.............................................................................................................................................................. 43
Figure 4.18. Power Spectral Density of the modulator’s output for Mode 1 - GSM. ............................. 44
Figure 4.19. Power Spectral Density of the modulator’s output for Mode 4 – DVB-H. ......................... 44
Figure 4.20. Outputs of the integrators and modulator for Mode 1 - GSM. ........................................... 45
Figure 4.21. Outputs of the integrators and modulator for Mode 4 – DVB-H. ....................................... 45
Figure 5.1. 1st Integrator simplified electrical schematic. ...................................................................... 47
Figure 5.2. 2nd
Integrator simplified electrical schematic. ..................................................................... 49
Figure 5.3. 3rd
integrator simplified electrical schematic. ...................................................................... 51
Figure 5.4. Two-stage cascode compensated operational amplifier with folded first-stage. ................. 56
Figure 5.5. Small-signal equivalent model for weak signals. ................................................................ 57
Figure 5.6. Common-Mode Feedback circuit for the operational amplifier. .......................................... 65
Figure 5.7. OpAmp bias circuit. ............................................................................................................. 66
Figure 5.8. Simplified schematic of the internal Flash A/D converter. .................................................. 67
Figure 5.9. Simplified electrical schematic of the latched-comparator. ................................................. 68
x
Figure 5.10. Simplified electrical schematic of the latched-comparator. ............................................... 69
Figure 5.11. Time diagram of the clock signals. ................................................................................... 71
Figure 5.12. Electrical schematic of the clock generator circuit. ........................................................... 72
Figure 6.1. Bode diagram of the 1st integrator, Mode 1 – GSM. ........................................................... 74
Figure 6.2. Bode diagram of the 1st integrator, Mode 2 – CDMA2000. ................................................. 74
Figure 6.3. Impulsive response of the 1st integrator for Mode 1 –GSM and Mode 2 – CDMA2000. ..... 75
Figure 6.4. Bode diagram of the 1st integrator, Mode 3 – UMTS. ......................................................... 76
Figure 6.5. Bode diagram of the 1st integrator, Mode 4 – DVB-H. ........................................................ 76
Figure 6.6. Impulsive response of the 1st integrator for Mode 3 – UMTS and Mode 4 – DVB-H .......... 77
Figure 6.7. Input signal and output signals of all three integrators for GSM and DVB-H. ..................... 79
Figure 6.8. Output of the Σ−∆ Modulator for Mode 1 – GSM and Mode 4 – DVB-H. ............................ 80
Figure 6.9. Frequency spectrum of the output signal of the Σ−∆ Modulator. ........................................ 80
Figure A1.1. Resistor noise model (R* stands for noiseless R). ........................................................... 85
Figure A1.2. MOS transistor noise model (M* stands for noiseless M). ............................................... 87
Figure A1.3. Switched-capacitor equivalent noise model ..................................................................... 88
Figure A1.4. Equivalent noise model of the operational amplifier. ........................................................ 88
Figure A1.5. Equivalent noise model of a switched-capacitor integrator. ............................................. 90
Figure A1.6. Typical switched-capacitors integrator. ............................................................................ 92
xi
List of Acronyms
AC – Alternating current
A/D - Analog-to-Digital
ADC - Analog-to-Digital Converter
A-GPS – Assisted GPS
CDMA2000 – American CDMA standard
CMFB – Common-mode Feedback
CMOS - Complementary Metal-Oxide-Semiconductor
D/A – Digital-to-Analog
DAC - Digital-to-Analog Converter
DC – Direct Current
DDF - Digital Decimator Filter
DEM – Dynamic Element Matching
DR – Dynamic Range
DSP - Digital Signal Processor
DTV - Digital Television
DVB-H - Digital Video Broadcast-Handheld
DWA – Data Weighted Averaging
EDGE – Enhanced Data rates for GSM Evolutions
ENOB - Effective Number Of Bits
GBW – Gain-Bandwidth Product
GPRS – General Packet Radio Service
GSM – Global System for Mobile Communications
HDTV - High Definition TV
IC - Integrated Circuit
IF – Intermediate-Frequency
ILA – Individual Level Averaging
ISDB-T - Integrated Services Digital Broadcast-Terrestrial
LPAAF - Low-Pass Anti-Aliasing Filter
LSB - Least Significant Bit
MASH – Multi-Stage Noise Shaping
MOS – Metal-Oxide Semiconductor
NTF - Noise Transfer Function
OP – Operating Point
OpAmp – Operational Amplifier
OSR – Oversampling Ratio
PDF - Probability Density Function
PSD - Power Spectral Density
xii
RON – ON Resistance of the switch
R/F – Radio Frequency
ΣΣΣΣ-∆∆∆∆ − Sigma-Delta
SNR – Signal-to-Noise Ratio
SNRp – Peak Signal-to-Noise Ratio
SQNR – Signal-to-Quantization Noise Ratio
SR – Slew Rate
STF - Signal Transfer Function
T-DMB – Terrestrial Digital Multimedia Broadcasting
TV – Television
UMTS – Universal Mobile Telecommunication System
UWB – Ultra wide-band
xiii
List of Symbols
∆∆∆∆ - Quantization Step.
e – Quantization Error.
Vref - Reference Voltage of an ADC.
es2 – Input Signal Power.
fs – Sampling Frequency.
fb – Signal Bandwidth.
N - Number of Bits.
fN – Nyquist-rate.
Ts – Sampling Time.
L – Order of the converter.
k – Boltzmann constant
T – Absolute Temperature
ADC – Low-Frequency Gain
RON – ON resistance
1
Chapter 1
Introduction
1.1 Overview
Television (TV) has changed since the first black-and-white broadcasts of the 1940s. There have been
innovations in quality with color and digital broadcasts, as well as improvements in the delivery
methods, including cable, satellite and High Definition Television (HDTV). Each of these technology
advances has increased the popularity of TV and brought more content and programming to
consumers. Now the TV is taking a step further towards digital broadcasting to mobile phones.
People are already experiencing Digital Television (DTV) services on mobile phones, mostly known as
streaming TV over the cellular network, similar as streaming video over the Internet. There is a
downside to the streamed DTV services over the network as it uses the voice bandwidth, thus
lowering the overall capacity of the network for all users.
With the broadcast mobile DTV services, the consumer experience will be similar to having digital
cable or satellite quality programming on a mobile phone, using a DTV broadcasting standard over a
separate air interface. Users will be able to watch live television programs, traffic reports, movie clips
and music videos as well as listen to digital music and view a variety of entertainment and content
options.
As with cellular phones, different standards for TV broadcast exist, such as [TI2005]:
Terrestrial-Digital Multimedia Broadcasting (T-DMB) – Is a digital terrestrial radio
transmission system for sending multimedia (radio, TV, and data) to mobile devices. DMB
services are commercially deployed in Korea and trialing in Europe and in other parts of
Asia.
Integrated Services Digital Broadcast-Terrestrial (ISDB-T) – The digital TV standard for
Japan delivers DTV services to the home, allowing greater economies of scale for
providers, with minimal interruption for consumers.
Digital Video Broadcast-Handheld (DVB-H) – Derived from the DVB standard is used in
Europe for cable, satellite and terrestrial TV services. DVB-H reduces power consumption
through time-slicing and has been designed around small screen and antenna sizes to give
reliable, high-speed reception.
In Table 1.1, several characteristics of the above referred standards are presented. The standard with
the most market acceptance and support around the world is the DVB-H one according to [TI2006].
2
Hundreds of companies are developing services, devices, hardware and software for the standard.
More detailed information about the DVB-H standard can be found, for example, in [ETSI2004]
Table 1.1. DTV Handset Standards [TI2005].
System T-DMB ISDB-T DVB-H
Region/Country of deployment Korea Japan Europe, US
Channel Frequency/Max bps 6 MHz
9.2 Mbps
6 MHz
23 Mbps
8 MHz
31 Mbps
Optimized Power Reduction for Handset None Mobile use 1 seg.only Time slicing
The mobile broadcast DTV integrates two of the most popular consumer products ever: television and
the mobile phone. Moreover, the co-existence of numerous standards defined for wireless
communication increases the need for interoperability between various technologies. Figure 1.1 shows
modern technologies like Wi-Fi, Bluetooth, A-GPS (Assisted GPS), UWB (Ultra wide-band) and more
recently the DTV complementing the existing phone technologies: GSM (Global System for Mobile
Communications), GPRS (General Packet Radio Service), EDGE (Enhanced Data rates for GSM
Evolution), UMTS (Universal Mobile Telecommunication System), CDMA2000 (American CDMA
standard).. Therefore, the integration of several radio interfaces into programmable and reconfigurable
hardware supporting multiple standards and multiple frequency bands becomes extremely important.
Figure 1.1. DTV complementing the existing mobile phone technologies [TI2005].
It is because of this rising market need of reconfigurable hardware capable of supporting multiple
standards that the Sigma Delta AD converter plays an important role.
1.2 Motivation
With the advances in CMOS (Complementary Metal-Oxide-Semiconductor) technologies there is a
trend to move the signal processing functions to the digital domain through the use of DSPs (Digital
3
Signal Processor), speeding up the design cycle and bringing more flexibility and programmability.
The speed, density increase, the area, size and power reduction of modern digital integrated circuits
(ICs) also enhances the predominance of digital methods in almost every area of communication and
consumer products. For analog circuits the evolution of technologies is not as beneficial as it is for
digital circuits. The reduction of the intrinsic gain of the transistor, the difficulties in modeling the
operation of the transistor, the use of low voltages that reduce the signal swing; all of these constraints
make the analog design challenging and more difficult [Yao2006].
The real world remains analog and so, there is and always will be a great need of data converters to
interface the DSP with the real world. The improvements in speed and capability of the DSPs require
an increase of speed and accuracy of the associated data converters, making the Analog-to-Digital
Converter (ADC) and the Digital-to-Analog Converter (DAC) fundamental building blocks of a mixed-
signal integrated system.
Among different ADCs, the Sigma-Delta (Σ−∆) ADC features high resolution and medium-to-high-
speed conversion without the requirement of high-precision devices; this is a desirable characteristic
when choosing high-precision ADCs in common CMOS technologies. Several designs of Σ−∆ A/D
(Analog-to-Digital) converters for wideband communications have been reported proving the
advantages of Σ−∆ converters for high-speed and high resolution applications, [Gomez2002],
[Altun2005], [Chiang2004] and [Farahani2004].
Taking in consideration the advantages of supporting several standards in the same integrated
system, the focus of this thesis is the development of a programmable bandwidth, low-voltage and
low-power Σ−∆ Modulator for a Σ−∆ ADC, supporting the wireless standards GSM, UMTS,
CDMA2000 and DVB-H.
1.3 Thesis Organization
This thesis is organized in 7 chapters.
Chapter 2 introduces the role played by the ADC in a wireless communication system presenting the
specifications for the programmable bandwidth Σ−∆ ADC.
Chapter 3 shows the basic principles of the ADC, its operation and possible implementations with their
pros and cons.
Chapter 4 is dedicated to the analysis of the non-idealities that affect the performance of Σ−∆
modulators. System considerations, behavioral models and mathematical formulas are obtained. The
specifications for the Σ−∆ modulator blocks are presented.
Chapter 5 treats the design of the system at circuit-level. Implementations of the blocks of the
modulator are shown. In this chapter a single-stage third-order twelve-level switched-capacitor Σ−∆
modulator implemented in a standard digital 80-nm CMOS technology is demonstrated.
4
Chapter 6 presents the results that validate the design and the implementation of the Σ−∆ modulator.
Chapter 7 summarizes and concludes the thesis.
5
Chapter 2
The ΣΣΣΣ−−−−∆∆∆∆ ADC in Wireless
Communications Systems
This chapter gives an overview of the wireless communications systems and introduces the role of the
Σ−∆ ADC in a general transceiver.
First, the ideal transceiver is presented and then the general structure of a receiver is described.
Finally, the multi-standard Σ−∆ ADC and Σ−∆ Modulator specifications are introduced.
2.1 Ideal Transceiver
In the ideal world, a fully integrated transceiver would be constituted by an antenna, an A/D and a
Digital-to-Analog (D/A) interface next to the antenna, a DSP and another A/D and D/A interface right
before the destination and source transducers (speakers, displays, microphones, cameras, etc).
Figure 2.1 presents the block diagram of an ideal integrated transceiver, where the only non-
integrated components are the antenna and the destination and source transducers.
Figure 2.1. Ideal integrated transceiver block diagram.
The signal processing is nowadays totally performed in the digital domain due to its flexibility and
adaptability to multiple standard communications. However, the received signal from the antenna has
to be converted by a high-resolution ADC at a frequency near the radio-frequency (RF) carrier’s, which
is unrealizable with the available technologies.
6
The impossibility of directly converting the antenna’s signal, as well the need for low-power
consumption devices, makes it necessary to spread the chain of the signal processing between the
analog and digital domains.
2.2 Wireless Transceiver General Architecture
A general integrated transceiver for mobile communications is constituted by 3 fundamental blocks:
the front-end processes the input analog signal modulated in RF and in Intermediate-Frequency (IF)
(filtering, amplification, frequency conversion); the back-end processes the analog and digital signal in
base-band (filtering, amplification, modulation, demodulation, A/D and D/A conversions); and the
user-end implements the interface with the user (A/D and D/A conversions, signal conditioning).
Figure 2.2 shows the block diagram of a typical integrated transceiver for mobile communications.
Figure 2.2. Block diagram of a general transceiver.
The choice of the transceiver architecture, in particular the receiver and transmitter, has
consequences in the consumption, integration and adaptability to multiple standards, which is out of
the scope of this thesis. More information about different transceiver architectures can be found at
[Khoo1998] and [Razavi2001].
2.3 The ΣΣΣΣ-∆∆∆∆ ADC
The ADC is a fundamental building block in mixed-signal integrated systems and plays a major role in
today’s radio communication systems. In the back-end block of a typical transceiver, Figure 2.2, the
ADC is the bridge between the real world and the digital one, and therefore it is one of the bottlenecks
of the system, converting the analog signal into its digital representation to be processed by the DSP.
The Σ−∆ ADC has three fundamental blocks, a Low-Pass Anti-Aliasing Filter (LPAAF), a Σ−∆
Modulator and a Digital Decimation Filter (DDF), as shown in Figure 2.3.
7
Figure 2.3. Block diagram of a Sigma-Delta ADC.
2.4 Signal-to-noise ratio and dynamic range
In A/D conversion, sometimes the concepts of signal-to-noise ratio and dynamic range are used
indistinctively, like synonyms, what is not always true:
Signal-to-Noise Ratio (SNR) of an ADC is the ratio between signal power and noise power at
its output. In this case, noise means any kind of unwanted signal;
Dynamic Range (DR) of an ADC is the ratio between the maximum input signal power and
the minimum detectable input signal power that can be applied without compromising the
functioning of the system.
If the noise power is independent of the signal power, the dynamic-range is equal to the full-scale
signal-to-noise-ratio. However, sometimes the noise power increases with the signal power, and in
these situations, the maximum SNR is lower than the dynamic range – this is the case of the A/D
converters employing Σ−∆ modulation.
2.5 System Specifications
The projected system consists in a Σ−∆ modulator for a Σ−∆ ADC. The specifications for the Σ−∆ ADC
and for the Σ−∆ Modulator are listed in Table 2.1.
8
Table 2.1. ΣΣΣΣ−−−−∆∆∆∆ ADC specifications.
Parameter Conditions Min. Typ. Max. Units
Technology - TSMC 80nm G, 1P5M
Core Area - A 0.6 mm2
Junction Temperature - T Working temperature -40 50 +125 ºC
Supply Voltage - VDD 0.95 1 1.05 V
Signal Bandwidth - fb
Mode 1: GSM
Mode 2: CDMA2000
Mode 3: UMTS
Mode 4: DVB-H
0.1
0.6
2
4
MHz
Current Consumption - IDD
Mode 1
Mode 2
Mode 3
Mode 4
2.5
3
5
6
mA
Input Signal Amplitude 50% Full-Scale 1 Vpp
SNR
Mode 1: Bandwidth: 100kHz
Mode 2: Bandwidth: 600kHz
Mode 3: Bandwidth: 2 MHz
Mode 4: Bandwidth: 4MHz
64
62
55
54
dB
9
Chapter 3
The ΣΣΣΣ−−−−∆∆∆∆ ADC
This chapter firstly presents the A/D conversion principles. The theory of sampling is discussed and
then the behavior of the ideal converter is described, presenting the inherent quantization error. A
detailed description of data conversion can be found in [Norsw1997]. The concepts of oversampling
and noise shaping are introduced. Finally, the Σ−∆ modulator is presented and several architectures
are described with some detail.
3.1 Analog to Digital Conversion
The A/D converter, depicted in Figure 3.1, operates in three fundamental steps with the intent to
convert a continuous in time and amplitude signal into a discrete-time and discrete-amplitude signal.
The anti-alias filter is used to limit the input analog signal xa(t) bandwidth so that the sampling process
does not alias unwanted noise or signal components in the actual signal band. Then xa(t) is sampled
at uniform intervals fs=1/Ts (The sampling frequency is the inverse of the sampling time), and
quantized into its digital representation xd(n).
Figure 3.1. Block diagram of an ADC.
3.1.1 Sampling and the Anti-Aliasing filter
In general, signals can be divided according to its amplitude and time domain. In the amplitude
domain, there are discrete-amplitude and continuous-amplitude values; in the time domain there are
the discrete-time and continuous-time values. The analog signal is a continuous-time and continuous-
amplitude signal while the digital signal is a discrete-amplitude and discrete-time signal. The sampling
process converts a continuous-time signal xa(t), shown in Figure 3.2, into a discrete-time signal
x(n)=xa(nTs).
10
Figure 3.2. Analog input signal (a) and its spectrum (b).
The sampling signal, also known as an impulse train or a Dirac comb is a Periodic Schwartz
Distribution constructed from Dirac delta functions, e.g. [Spanier1987], as seen in Figure 3.3,
( ) ( )
( ) ( )
,
, 01
0,
T
k
t t kT
twhere t and x dx
elsewhere
δ
δ δ
∞
=−∞
∞
−∞
∆ = −
+∞ = = =
∑
∫ (3.1)
Being a periodic function with period Ts=1/fs, ( )st nTδ − can be represented by a Fourier Series
( ) 21sj nt T
s
ns
t nT eT
πδ∞
=−∞
− = ∑ (3.2)
Thus the signal x(n) can be represented as
( ) ( ) ( ) ( ) ( )( 2 ) 21 1
s sj nt T j ntf
a s a a
n n ns s
x n x t t nT x t e x t eT T
π πδ∞ ∞ ∞
=−∞ =−∞ =−∞
= − = =∑ ∑ ∑
(3.3)
Equation (3.3) states that sampling is equivalent to modulating the input signal by carrier signals at
multiples of fs (fs, 2fs, 3fs, 4fs ...), as shown in Figure 3.4.
The sampling theorem states that by sampling a signal with a sampling frequency equal to the
Nyquist-frequency, fN=2fb, that is twice the signal bandwidth, the signal can be perfectly reconstructed,
[Nyqui1928] and [Shann1949]. However, the signal bandwidth is not completely limited and
frequencies outside the signal band exist; after sampling, the signal bands overlap and hence add
distortion to the sampled signal, phenomenon called aliasing. To avoid this, the signal is firstly filtered
through an anti-aliasing filter. This filter has always a limited steepness and that is why most of the
Nyquist-rate converters operate at a somewhat higher frequency than the Nyquist-frequency.
11
Figure 3.3. Sampling signal ∆∆∆∆T(t) (a) and its frequency spectrum (b).
Figure 3.4. Discrete-time signal x(n) (a) and its frequency spectrum (b).
3.1.2 Ideal A/D Conversion
An ideal digital-to-analog (D/A) conversion can be mathematically expressed by:
( )1 2
1 22 2 2 ,N
out ref NV V b b b− − −= ⋅ ⋅ + ⋅ + + ⋅ K
(3.4)
From expression (3.4) it is clear that the output voltage, Vout, is perfectly constructed in a way that
every bit, bi, contributes with a scaled version of the reference voltage, Vref. The least significant bit
(LSB) voltage, VLSB, is given by Vref and by the number of bits, N. The maximum output voltage
achievable is Vref – VLSB.
ref
LSB N
VV =
2 (3.5)
Although the output value in a D/A converter is perfectly defined, this is not the case in the A/D
converter. The output is here described by [Pla1994]:
( )1 2
1 22 2 2 ,N
ref N in xV b b b V V− − −⋅ ⋅ + ⋅ + + ⋅ = ± K (3.6)
2 2LSB x LSBV V V− ≤ ≤ + (3.7)
From equation (3.6) it is clear that now a range of valid input values Vin±Vx are producing the same
digital world. This is called a quantification error which is inherent to every ADC and is discussed in
the next section.
12
3.1.3 Quantization noise
The quantized signal, q(n), depicted in Figure 3.5, can be described as the sum of the correct signal
x(n) and the quantization error e(n), as shown in the linear model, e.g. [Johns1997], of Figure 3.6.
Here ∆ is equal to VLSB.
( ) ( ) ( )q n x n e n= +
(3.8)
Figure 3.5. Quantized signal as a function of the input signal.
Figure 3.6. Quantizer block (a) and its linear model (b).
Expressing the quantization error as a function of the correct signal, a more useful equation is
obtained and the quantization error is shown in Figure 3.7.
( ) ( ) ( )ne q n x n= −
(3.9)
Figure 3.7. Quantization error as a function of the input signal.
13
Assuming the quantization error to be described as white noise, which means its Probability Density
Function (PDF) is uniform between ±∆/2, the noise power is given by
( )/ 2 2
2 2
/ 2
1
12qe e deσ
∆
−∆
∆= ⋅ =
∆ ∫
(3.10)
In Figure 3.8 is shown that the Power Spectral Density (PSD) of the quantization noise, Se(f) is white
and within ±fs/2. The power spectral density of the sampled noise and its amplitude are given
respectively by
( )( )2 2
2 12 2E
s s
eS f
f f
σ ∆= =
(3.11)
2 1
12e
s
hf
∆=
(3.12)
As an error source, the quantization noise degrades the quality of the signal. This can be expressed
by using the SNR, or by the so often called SQNR (Signal to Quantization Noise Ratio), defined as the
ratio between the maximum signal input power and the noise power, illustrated by expression (3.13).
max10 log 10 log s
dB
e
Psignal powerSNR
noise power P
= =
(3.13)
Figure 3.8. Power Spectral Density of quantization noise (blue).
Assuming an input signal to be sinusoidal with amplitude A, the signal power is given by:
22
2 2 2
ref
s
VAP
= =
(3.14)
Thus, the peak SNR (SNRp) of an ideal N-bit ADC with 2N quantization levels can be calculated as:
14
( )
2
2
2
10 log
2 210 log
2
12
310 log 2 6.02 1.76 ]
2
sp
e
ref
N
ref
N
PSNR
P
V
V
N dB
= =
=
= = + [
(3.15)
Therefore, expression (3.15) gives the best possible SNR for an N-bit ADC and it is clear that the SNR
determines the ENOB (Effective Number Of Bits) that the ADC can resolve, given by:
1.76
6.02
dBSNRENOB
−=
(3.16)
Equation (3.16) shows that by increasing the number of bits the SNR can be increased by 6dB/bit.
3.2 Nyquist-Rate ADC
The operation of a Nyquist ADC is illustrated in Figure 3.1 and has already been presented with detail
in the beginning of the chapter. Nyquist-rate ADCs are usually classified depending on the number of
clock cycles required to complete a single conversion. Some of these converters are flash, sub-
ranging, successive approximation and pipelined, e.g. [Johns1997] and [Razavi1995].
The Flash ADC is the fastest in converting an analog signal to a digital one as they only need one
clock cycle to perform the conversion, making use of 2N comparators, where N is the number of bits. It
is extremely suitable for applications requiring very large bandwidths, however due to the matching
and accuracy requirements of the analog components (resistors and capacitors), it is limited in
resolution. Moreover, the complexity of the implementation grows exponentially with the number of
bits, making the flash ADC practical in high-speed applications with a relatively small resolution,
typically 10-bit or less.
Several architectures have been proposed to overcome some of these limitations. The essential idea
is to divide the quantization process over several cycles. For example, in a sub-ranging ADC, the
conversion is performed in two cycles: in the first step, N/2 bits are resolved using an N/2 flash ADC;
in the second step, the digital signal obtained in the first step is converted back to the analog domain,
subtracted from the input signal and then converted to resolve the remaining N/2 bits. This
architecture uses only 2(N/2)+1
comparators while the latency time is increased by two.
Architectures such as pipelined also use the technique of dividing the quantization process over
several cycles. The major differences are the latency time to perform a single conversion and the
number of bits that are resolved by several stages. In addition, some of these architectures require
15
digital correction and calibration techniques to improve resolution. The successive approximation ADC
uses a binary search algorithm to determine the closest digital representation of the input signal; one
bit is resolved per clock cycle using a single comparator; from the most significant bit (MSB) to the
LSB, each bit is determined through a comparison with the previous cycle analog result; to complete
an N-bit conversion, N clock cycles are required.
3.3 Limitations of Nyquist-Rate ADCs
The two major limitations of the Nyquist-rate converters are the anti-aliasing filter and the quantization
noise. Concerning the anti-aliasing filter, at first glance, its requirements are fairly straightforward: the
pass-band must accurately pass the desired signals and the stop-band must attenuate any interferer
outside the pass-band, as shown in Figure 3.9. This attenuation must be sufficient enough so the
residue will not damage the system performance when aliased into the pass-band after sampling. The
actual design of anti-aliasing filters can be very challenging. If the out-of-band interferers are strong
and very near the pass frequency of the desired signal, the requirements for the filter stop-band and
narrowness of the transition band can be quite harsh. These requirements need high-order filters but
unfortunately the topologies having such characteristics, such as Chebychev, typically place costly
requirements on component matching and tend to introduce phase distortion at the edge of the pass-
band, threatening the signal recovery. In addition the pass-band distortion of the analog anti-alias filter
should be at least as good as the ADC since any out-of-band harmonics introduced will be aliased.
Nyquist-rate converters use the minimal required sampling frequency determined by the Nyquist
criteria, allowing for a maximal quantization error as stated by equation (3.10. In real designs,
quantization is done by comparing the sampled signals with generated reference voltages. Reference
voltages are generated using passive elements such as resistors and capacitors, and for high-
resolution designs, typically greater than 12-bit, these reference voltages are in the order of microvolt.
With today’s technology it is very difficult to implement such matching and tolerance in the
components, limiting the resolution of Nyquist converters.
Figure 3.9. Nyquist-rate sampled signal spectrum (a) and the respective anti-aliasing filter response (b).
16
3.4 Oversampling
By sampling the input signal at a higher frequency than that of the Nyquist-rate, advantages including
the anti-alias filter requirements and quantization noise reduction can be obtained over Nyquist-rate
converters. But consequently, a decimation filter is necessary at the output to filter and downsample
the digital stream, as shown in Figure 3.10.
Figure 3.10. Block diagram of an Oversampled A/D converter.
Figure 3.11. Oversampled signal spectrum (a) and respective anti-aliasinf filter response (b).
From Figure 3.11a) it is clear that the images of the oversampled signal band are not so close to one
another and hence the anti-aliasing filter specifications can be relaxed, Figure 3.11b).
Considering a signal sampled at the Nyquist-rate fN=2fb and a signal sampled with a sampling
frequency OSR (Oversampling Ratio) times the Nyquist frequency fs=OSR.fN, it is possible to define
the ratio between the sampling rate and the Nyquist frequency:
2
s s
b N
f fOSR
f f= =
(3.17)
The power of the quantization noise is evenly distributed between ±fs/2 and as the sampling frequency
increases, the amplitude of the spectral density decreases, while the quantization noise power
remains the same, as seen in Figure 3.12.
Therefore, by using an oversampling technique, the quantization noise power of an ADC can be
reduced by a factor of OSR, and so, the SNR can be effectively increased, hence the resolution of the
ADC.
17
( ) ( )/ 2 2
2
/2
1
12
fs
e e
fs
P S f H f dfOSR
−
∆ = =
∫
(3.18)
The SNRp of an oversampled system is:
( )10log 6.02 1.76 10log [ ]s
p
e
PSNR N OSR dB
P= = + +
(3.19)
From expression (3.19) it is clear that the peak SNR can be increased by 3dB by doubling fs, i.e., the
resolution of the ADC increases by 0.5bit/octave. This is a way to exchange the speed and the
resolution of an ADC system, as long as the quantization noise is the major noise of the system.
Figure 3.12. Spectrum of the quantization error at Nyquist-rate (fs1) and Oversampled (fs2).
3.5 Noise shaping
Using the oversampling technique alone is not that effective and additional techniques have to be
used. By applying a loop filter before the quantizer and introducing feedback, as shown in Figure
3.13a), a Σ−∆ modulator is constructed. An analysis to the z-domain linear model of the Figure 3.13b)
shows that the output of the modulator is given by
( ) ( ) ( ) ( ) ( )Y z X z STF z E z NTF z= + (3.20)
Where STF(z) represents the Signal Transfer Function (STF), NTF(z) represents the Noise Transfer
Function (NTF) and can by calculated as
( )
( )( )1
H zSTF z
H z=
+
(3.21)
( )
( )1
1NTF z
H z=
+
(3.22)
18
By properly choosing H(z), it is possible to obtain the desired signal and noise transfer function within
a certain band of interest. If H(z) is chosen to have a very large gain inside the band of interest and a
small gain outside this same band, the STF and NTF become:
( ) 1
1
STF z
z
=
→
(3.23)
( )
( )1
11
NTF zH z
= <<+
(3.24)
From expressions (3.23) and (3.24), the signal can pass the Σ−∆ modulator directly and the noise is
greatly reduced inside the band of interest. This is called noise shaping.
By choosing an integrator as the loop filter H(z) with the transfer function
( )
1
11
zH z
z
−
−=
−
(3.25)
the signal and noise transfer functions of the Σ−∆M become
( ) 1STF z z
−= (3.26)
( ) 11NTF z z−= − (3.27)
Figure 3.13. First Order ΣΣΣΣ−−−−∆∆∆∆ M block diagram (a) and its linear z-domain model (b).
The loop filter transfer function, signal and noise transfer functions of the Σ−∆ modulator are shown in
Figure 3.14. It is seen that the output contains a delayed, but otherwise unchanged replica of the
analog input signal. The quantization noise is suppressed at low frequencies, shifting a large amount
of noise to higher frequencies, behaving like a first-order high-pass filter. Combined with
oversampling, the SNR of the ADC can be greatly improved.
19
Figure 3.14. Loop filter H(f), signal transfer function STF(f) and noise transfer NTF(f) functions of a ΣΣΣΣ−−−−∆∆∆∆ Modulator.
3.6 The ΣΣΣΣ−−−−∆∆∆∆ Modulator
The previous section introduced the first-order Σ−∆ Modulator, namely its block diagram in Figure 3.13
and the frequency response of its STF and NTF in Figure 3.14.
In the time-domain, the integrator integrates the difference between the input signal and the feedback
output signal and then the result is fed to the quantizer. The negative feedback tries to minimize the
difference between the input and the output signals of the Σ−∆M and as a result, the average of the
output signal tracks the input signal. The discussion has been constrained to low-pass
Σ−∆ Modulators, but depending on the frequency band of interest, a band-pass Σ−∆ Modulator can
also be used in a wide range of wireless transceivers. By applying several loop filters and more
stages, different noise shaping transfer functions can be obtained.
The next subsections present several Σ−∆ Modulator architectures.
3.6.1 Single-stage ΣΣΣΣ−−−−∆∆∆∆ Modulator
The single-stage Σ−∆ converter is defined as there being only one single Σ−∆ loop in the entire
converter; the forward path consists of a series of integrators, as seen in Figure 3.15.
Each integrator input is the difference between the previous integrator output and the DAC output. The
number of integrators in the forward path defines the order (L) of a sigma-delta modulator. The ADC
and the DAC provide N bits of resolution.
20
Figure 3.15. Single-stage ΣΣΣΣ−−−−∆∆∆∆ modulator block diagram.
Considering that each integrator has the transfer function like expression (3.25), the ADC is modeled
as an additive error source E(z), shown in Figure 3.6, and that the DAC can be modeled also as an
additive error source EDAC(z), the signal and noise transfer functions are now expressed as:
( ) LSTF z z
−= (3.28)
( ) ( )11
L
NTF z z−= −
(3.29)
and the output of the modulator is
( ) ( ) ( ) ( ) ( )11
LL
DACY z z X z z E z E z− −= + − −
(3.30)
Equation (3.30) indicates that errors in the DAC add directly at the input of the sigma-delta loop,
implying that the D/A converter has to be linear to the full resolution of the modulator to avoid any
degradation in the performance. One way to ensure this linearity is to use a single bit-quantizer and a
two-level DAC that is inherently linear [Will1993]. Multi-bit DACs can also be used, but require digital
correction or dynamic matching techniques [Candy1992].
Considering the DAC as a unity gain buffer, and the quantization noise power e of expression (3.10),
the total quantization noise power inside the signal band is given by
( ) ( )
( )
/ 2 222 1
/ 2
2 2 12 2
112
2 1
12 2 3 2 1
b
b
b
b
ffsL
e e
sfs f
L Lf
s sf
P S f H f df z dff
j fdf
f f L OSR
π π
π
−
− −
+
−
∆= = −
∆ ∆ = =
+
∫ ∫
∫
(3.31)
It is now possible to calculate the SNRp of the L-th order N-bit Σ−∆ modulator as:
( ) ( )
( )( )
( )
2 12
2
2 10 10
2 1 2 1
1 26.02 log 10 log 20 log 2 1 [ ]
2 3 2 1
L
Nsp
e
LN
P OSRSNR L
P
L OSR dBL
π
π
π
+3
= = − + = 2
= + − + − +
(3.32)
21
Equation (3.32) shows the SNR as a strong function of the oversampling ratio and the order of the
loop, implying that the designer can tradeoff between order and oversampling ratio to meet a given
SNR specification. This is the theoretical performance of an ideal Lth order N-bit single-stage
Σ−∆ modulator.
Figure 3.16 shows the ideal NTF for different order Σ−∆M that become steeper in the signal band for
higher-order Σ−∆M and hence improving the noise shaping ability in comparison with the first-order
Σ−∆M.
The discussion of the Σ−∆M has so far neglected stability issues. Modulators of order L > 2 are
conditionally stable [Candy1992] and the reason is that the higher loop-gain of the higher-order loop
filter causes the overload of the quantizer.
Figure 3.16. Ideal noise transfer functions for different order ΣΣΣΣ−−−−∆∆∆∆Ms with OSR=32.
To stabilize a higher-order loop, the use of loop coefficients might be required. Coefficients a1, a2,…,aL
are the loop coefficients of the corresponding first, second, and L-th stage, as seen in Figure 3.17.
Now, the noise transfer function is
( ) 1
1
11
1,
11
L iLL
j
i j i
NTF zz
k az
− +−
−= −
=
+ −
∑∏
(3.33)
where k represents the quantization gain.
The amplitude of the NTF can be approximated as:
( )1
1
1L
L
i
i
zNTF z
k a
−
=
−=
∑ (3.34)
22
Then the SNR of the Σ−∆M can be calculated as:
( )
2
1
L
p ip ideal
i
SNR SNR k a=
=
∏ (3.35)
The quantization gain k is not determined in a single-bit quantizer, since it only responds to the polarity
of the input signal and as a result, the gain of the last integrator is irrelevant to the operation of the Σ−∆
modulator. In other words, the last loop coefficient can have any value without affecting the
performance of the Σ−∆M. For a single-bit Σ−∆M, the quantization gain k can be combined with the last
integrator gain.
Figure 3.17. Block diagram of the n-th order single-loop ΣΣΣΣ−−−−∆∆∆∆M with coefficients.
Normally the product of all coefficients is smaller than unity to reach stability. From expression (3.35)
the SNR degrades due to the introduction of the loop coefficients, compared to the ideal the Σ−∆M. By
properly choosing all coefficients, the high-order the Σ−∆M can be made stable in the whole input
range, but the steepness of the noise transfer function becomes gentler and hence the noise shaping
ability is degraded.
The noise shaping ability of the Σ−∆M strongly depends strongly of the following factors: oversampling
ratio, order of the noise shaping, number of bits of the quantizer and loop coefficients, as seen in
expressions (3.32) and (3.35).
The SNR of a Σ−∆M can be increased by (2L+1).3 dB, or L+0.5 bits by doubling the OSR, where L is
the loop filter order. It is tempting to raise the oversampling ratio to increase the SNR. However, it is
restricted by the speed limit of the circuit and the power consumption, which means that in practice, for
the same performance, it is preferred to lower the OSR. The increase in the signal bandwidth
requirements also drives the lowering of the OSR.
Increasing the loop filter order L increases the SNR of the converter, but just ideally, as the stability
problem becomes a major concern. Therefore, smaller loop coefficients are introduced to ensure
stability and hence the noise shaping ability degrades. Moreover, to expand the loop filter order, more
circuitry is required. In practice, the order of the loop filter is kept below the fifth-order.
The introduction of loop coefficients to stabilize the Σ−∆M degrades its SNR. The larger coefficients,
the better noise shaping, but higher is the risk of getting instability. A compromise has to be made
23
between the stability and the SNR. Optimized loop coefficients have been developed for high
performance Σ−∆ modulators in [Mar1998b].
3.6.2 Single-Stage Multi-Bit ΣΣΣΣ−−−−∆∆∆∆ Modulator
Many Σ−∆ ADCs utilize a single-bit quantizer and a single-bit DAC in the feedback loop because of its
intrinsic linearity. However, increasing the number of bits in the quantizer increases the SNR
significantly; for each additional bit, the SNR is increased by 6 dB. Moreover, the loop stability is also
improved and loop coefficients can be greater, thus obtaining a better noise shaping.
Multi-bit quantizers architectures can achieve resolutions comparable with to those with single-bit
quantizers at lower OSR and therefore, for wideband Σ−∆ modulators is advantageous to choose a
multi-bit topology to lower the OSR. The use of multi-bit quantizers also improves the stability in
higher-order modulators [Norsw1997].
There are however some drawbacks with the use of multi-bit quantizers in Σ−∆Ms. A multi-bit
quantizer requires a multi-bit DAC in the feedback loop increasing the complexity of both the analog
and digital circuitry. The most significant problem with multi-bit designs is the DAC linearity and
mismatch which degrades the performance. In order to reduce the error, some techniques such as
digital correction [Cat1989], [SN1993] and Dynamic Element Matching (DEM), [Pla1976], [Pla1979],
[Car1989], [Gee2001], [Gee2002], are used, increasing the area and power of the design. The
dynamic element matching is an effective technique to increase the linearity of the DAC and it is
widely used on multi-bit Σ−∆ converters, without the requirement of additional trimming.
3.6.3 Multi-Stage ΣΣΣΣ−−−−∆∆∆∆ Modulator
One efficient way of easing the stability problems associated with high-order modulators without the
need of loop coefficients is to use the cascade modulator, also known as multi-stage or MASH (Multi-
Stage Noise-Shaping) modulators.
Cascade architectures use combinations of inherently stable first and second-order Σ−∆ modulators to
achieve higher-order noise-shaping. Since the stability criteria is relaxed as compared to the higher-
order loops, the cascade modulators approach the SNR bound in equation (3.32) closely than higher-
order single-stage implementations. As an example, a 2-2 cascade architecture is shown in Figure
3.18. In this architecture, the second modulator estimates the quantization error of the first modulator
with the overall result being obtained by an appropriate digital combination of the outputs. If the digital
combination is done correctly, a fourth-order noise-shaping is the result.
24
Figure 3.18. Block diagram of a 2-2 cascade ΣΣΣΣ∆∆∆∆ Modulator.
The digital recombining network, based on the prediction of the gain g, tries to eliminate the
quantization noise of every stage, except the last one.
Considering the transfer function of a second-order single-stage modulator, including delays in the
loop and neglecting any DAC linearity errors, the transfer function of the first second-order stage is
obtained in equation (3.36) and the transfer function of the second second-order stage in equation
(3.37):
( ) ( ) ( ) ( )
22 1
1 11Y z z X z z E z− −= + −
(3.36)
( ) ( ) ( ) ( )
22 1
2 1 21Y z z gE z z E z− − = + −
(3.37)
To cancel the first stage quantization error, the appropriate digital recombining network is
( ) ( ) ( ) ( )
22 1
1 2
11
x
Y z z Y z z Y zg
− −= − − (3.38)
Combining the results of equations (3.36), (3.37) and (3.38), gives the overall fourth-order NTF of the
2-2 cascade architecture:
( ) ( ) ( ) ( )( )
41
4 2 1
1
11 1
x x
zgY z z X z z z E z
g g
−
− − −−
= + − − −
(3.39)
The combination of the cascade architecture with multi-bit DAC improves the SNR even further. Note
that since the quantization error of the first-stage does not appear directly at the output of the
modulator, the use of a multi-bit DAC in the first-stage will not improve the SNR of the cascaded
modulator.
One of the main drawbacks of the cascaded Σ−∆ modulator is the severe requirement of the building
blocks. A quantization noise component from the previous converter leaks to the output of the entire
modulator if the matching is not controlled. [Rib1991], [Yin1994b]. As the non-idealities like the
mismatch of loop coefficient, finite DC (Direct Current) gain and settling error of the integrator are
becoming even more critical in nanometer CMOS technologies, the higher sensitivity to the non-
idealities of the building blocks makes the real circuit implementation even more difficult.
25
3.6.4 Feedforward ΣΣΣΣ−−−−∆∆∆∆ Modulator
Feedforward is the complement of feedback in a control system. If the input signal is fully feedforward
to the quantizer, a new Σ−∆ Modulator topology is obtained and shown in Figure 3.19.
Figure 3.19. Block diagram of a full feedforward ΣΣΣΣ−−−−∆∆∆∆ Modulator.
The STF and NTF are:
( ) 1STF z = (3.40)
( )
( )1
1NTF z
H z=
+
(3.41)
Compared to the traditional Σ−∆ Modulator, shown in Figure 3.13, the quantization noise transfer
function remains the same, while the signal transfer function is ideally unity in the full feedforward.
This unity STF suggests that the harmonic distortion due to non-idealities in the modulator’s loop filter
can be significantly reduced. In the traditional Σ−∆ M, the input seen by the first integrator is the error
signal u between the input x and the output y. Since the output is a delayed version of x in the time-
domain, the delay introduced by the signal transfer function causes the signal u to contain a high-pass
filtered version of the input signal x, which is restored to its full amplitude by the integrators [Sil2001],
resulting in a high swing inside the loop filter. From equation (3.20), the input signal Ut(z) of the loop
filter is:
( ) ( ) ( ) ( )( ) ( ) ( ) ( )1tU z X z Y z STF z X z NTF z E z= − = − − (3.42)
It is clear from equation (3.42) that for the traditional Σ−∆ Modulator, the input signal of the loop filter is
not only the quantization noise, but also a high-pass filtered input signal x. In a full feedforward
Σ−∆ Modulator, the output signal is not delayed and therefore, the only signal passing through the loop
filter is the quantization noise, much smaller than the input signal. The loop filter transfer function Uf(z)
is now:
( ) ( ) ( )fU z NTF z E z= − (3.43)
Since the input signal does not pass through the loop filter, its non-linearity will not disturb the signal.
Moreover, the quantization noise is smaller in amplitude than the input signal. This reduction of the
26
internal signal swings also relaxes the output swing requirements for the building blocks, which is a
tough requirement in low-voltage designs in modern CMOS technologies.
3.6.5 Summary
Generally speaking, the multi-bit modulators offer the best performance in SNR, but suffer from the
nonlinearity problem of the feedback DAC. The cascaded modulator offers good performance and an
increase on stability but it requires high-performance building blocks. The single-stage single-bit is the
worst one in terms of performance; however it is insensitive to the non-idealities of the building blocks.
The feedforward modulator reduces the harmonic distortion and relaxes the requirements of the
building blocks.
27
Chapter 4
System Specifications
In recent years, the Σ−∆ architecture has become the choice for A/D conversion in wireless receivers.
First, as shown in section 3.4, the quantization noise is modulated by a high-pass transfer function so
that most of its energy is located out of the band of interest; secondly, as illustrated in section 3.4, the
oversampling of the signal allows the relaxation of the analog filter specifications; thirdly, the Σ−∆
modulators are highly immune to analog components imprecision.
The power consumption remains a key aspect in the design of mobile communications systems. Less
power turns into increasing mobility and autonomy. Therefore, besides the necessity of complying all
the protocol specifications (SNR and signal bandwidth), efforts must be done to minimize the power
dissipation.
4.1 Noise Power Specification
The total noise power (all the blocks contributions) integrated in the signal band must be low enough
to ensure the SNR specification is achieved. In this context noise means any unwanted signal that
degrades the SNR and can be usually represented by an additive source. In Figure 4.1 the sigma-
delta ADC system architecture is presented where the noise of each block is summed at its input. The
design of the LPAAF is out of the scope of this work and therefore will not be discussed with detail.
Figure 4.1. Sigma-delta ADC system architecture block diagram, including the most important noise sources.
The noise of the main blocks (LPAAF and Σ−∆ modulator) contributes to the total noise in a similar
manner and therefore has to be taken into account. The main noise source of the Σ−∆ modulator is the
1st integrator’s, as the noise contributions of the 2
nd and 3
rd integrators are small when referred to the
modulator’s input in comparison to the 1st integrator (each of them has high gain >20dB inside the
band of interest). The noise of the LPAAF block will not be taken into account.
∫ ∫ ∫
28
The SNR of the system at its input with all the noise sources input-referred is given by:
, ,
,
2
10 10
, , 10 10
10
10
1210 log 10 log
10 10
110 log
10
AAF in in
in
in
s
SNR SNR
e AAF in in
SNR
V
PSNR
P N N Σ∆
Σ∆
− −Σ∆
−
= = = = +
+
=
(4.1)
where Vin represents the input signal’s amplitude (in V), Nx,in represents the input-referred noise power
generated by the block “x” (in V2) and SNRx,in represents the signal-to-noise ratio of the block “x” (in
dB).
According to Table 2.1 the worst case specification for SNR is 64dB (for an input signal of 50% of full-
scale) which defines the maximum allowed noise for each block. The input-referred noise of the
LPAAF is not considered in this work thus the major noise source is the 1st integrator of the Σ−∆
modulator (eint1) which must comply with the modulator’s 64 dB specification (eΣ∆,in), Figure 4.1.
With this topology, the maximum allowed signal input is 50% full-scale, which is the maximum
amplitude that can be applied without degradation in the Σ−∆ modulator behavior. For higher input
amplitudes the modulator saturates and the modulation effect of the quantization noise decreases
rapidly worsening the SNR of the Σ−∆M.
4.2 The ΣΣΣΣ−−−−∆∆∆∆ Modulator
The Σ−∆ modulator is the most important block in an ADC. Its theoretical functioning has already been
explained in Chapter 3. In Figure 4.2 is illustrated an Lth order N-bit Σ−∆ modulator block diagram.
Figure 4.2. Lth
order N-bit ΣΣΣΣ−−−−∆∆∆∆M block diagram.
The essential defining parameters of a Σ−∆ modulator are the order L (defined as the number of
integrators), the oversampling ratio (OSR) and the quantization N bits of the internal ADC and DAC.
∫ ∫
29
In specialized literature [Feld1997] and [Norsw1997] several topologies for Σ−∆M are discussed but
none presents a clear advantage above the others and thus other factors must be taken into account
when choosing the most adequate topology. These factors can be available area, technology, power
consumption, signal bandwidth, SNR, etc.
4.2.1 Power consumption
In Σ−∆ modulators the power consumption depends essentially on the thermal noise level and on the
frequency of operation.
In a switched-capacitor implementation, the minimum power achievable is determined by the
necessity of charging and discharging capacitors with a certain resolution, and in a limited time period
given by the sampling frequency; this is referred as the dynamic power limit. In practice, most
switched-capacitor circuits are implemented using amplifiers which require static bias currents and
therefore burn significantly more power than the dynamic limit; this is referred as the static power limit.
A more detailed overview of these power limits and limitations can be consulted in [Feld1997].
It can be seen from Appendix1 that the input referred signal-to-thermal noise ratio of a switched-
capacitor integrator as a function of the integration capacitor CO and the compensation capacitor CC of
the operational amplifier, is given by,
( ) ( )
s ,
2 22 22
3
ignal diff
i f i f
O C
PSNR
kT kTg g m g g
C OSR C OSRβ
=
+ + +
(4.2)
where k is the Boltzmann constant, T is the absolute temperature, gf is the internal DAC feedback
gain, gi is the input sampling gain and OSR is the oversampling ratio.
If the noise tolerance is higher, smaller capacitors can be used and therefore reduce the power
consumption for the same settling time specification (parasitic capacitances must be considered when
its value approaches the nominal value of the capacitors). If the thermal noise is the dominant noise
source in the circuit, a low power solution is achieved [Feld1997].
4.2.2 Architecture
The implemented Σ−∆ modulator is a single-stage, 3rd
order topology with a 12 level quantification.
Depending on the standard, different oversampling ratios and bandwidths are used. The block
diagram of the modulator is presented in Figure 4.3 and Table 4.1 presents this architecture’s SQNR.
The SQNR does not limit the SNR performance and therefore it is possible to implement a Σ−∆
modulator with its SNR limited by thermal noise, which is an optimum power solution.
30
Figure 4.3. 3rd
Order ΣΣΣΣ−−−−∆∆∆∆ modulator block diagram with an Overload Detector for the 3rd
stage and Dynamic Element Matching (DWA).
Table 4.1. SQNR and the specified SNR for the implemented modes.
- Mode 1 Mode 2 Mode 3 Mode 4
SQNR 77 72 60 60
SNR 64 62 55 54
It is shown in [He1988] that if the resolution of the internal ADC (in bit) is at least equal of the
modulator order, the modulator is potentially stable. The projected modulator has a 12 level ADC
which is equivalent to a resolution of a little more than 3 bit.
Although a multibit quantization is used, the system becomes potentially unstable when the input
signal approaches its full-scale. In order to prevent the saturation of the modulator, from which it might
never recover, an overload detector is implemented.
The internal DAC must have at least linearity equal to the converter resolution thus utilizing one of the
dynamic element matching techniques, in this case, DWA (Data Weight Averaging).
4.3 System modeling
This section presents a system-level modeling of the Σ−∆ modulator and its functional blocks:
integrators, internal ADC and DWA DAC. The main non-idealities and their Matlab/Simulink models
are presented.
Table 4.2 summarizes the most important specifications for the implemented Σ−∆ modulator.
Table 4.2. ΣΣΣΣ−−−−∆∆∆∆ modulator specifications.
Mode L Nlevels SNR fs [MHz] fb [MHz] OSR
1 – GSM 3 12 64 3 0,1 15
2 – CDMA2000 3 12 62 15 0,6 12,5
3 – UMTS 3 12 55 33,8 2 8,438
4 – DVB-H 3 12 54 67,5 4 8,438
31
4.3.1 Integrators’ Gains
In order to avoid the saturation of the integrators’ outputs, each integrator is scaled with a gain. Figure
4.4 shows the simplified block diagram of a 3rd
order Σ−∆ modulator with particular emphasis on the
integrators gains.
Figure 4.4. 3rd
Order ΣΣΣΣ−−−−∆∆∆∆ modulator.
The gains of the first implementation are not optimized considering the output swing of each
integrator, as the first two have an output swing three times greater than the 3rd
integrator one. All the
signals in the circuit must be within a certain supply voltage thus it is required to scale these gains in
order for this to happen. In Figure 4.5 the Σ−∆ modulator is presented with scaled gains so that the
outputs are balanced and within the allowed voltage range.
Figure 4.5. 3rd
Order ΣΣΣΣ−−−−∆∆∆∆ modulator with the integrators output balanced.
The gains of the 3rd
integrator are relatively high which implies higher power consumption in
comparison with the first integrators. One solution is to decrease the gains of the 3rd
integrator and
consequently increase the noise without affecting the performance of the modulator. The gains of the
2nd
stage are also reduced to decrease power consumption without concerns over the noise increase.
The final architecture is shown in Figure 4.6.
Figure 4.6. 3rd
Order ΣΣΣΣ−−−−∆∆∆∆ modulator with the integrators output and power consumption balanced.
32
Table 4.3 summarizes the gains of the integrators.
Table 4.3. Summary of the integrators’ gains.
Symbol Parameter Value
gi1 1st integrator input signal gain 0,35
gf1 1st integrator voltage reference gain 0,3
gi2 2nd
integrator input signal gain 0,67
gf2 2nd
integrator voltage reference gain 0,6
gi3 3rd
integrator input signal gain 1,5
gf3 3rd
integrator voltage reference gain 0,9
4.3.2 Non-idealities
In real systems, there are several non-idealities that affect the functioning and performance of the
modulator. These aspects become critical in high-resolution applications and affect particularly the
design of the 1st integrator, given that the other integrators’ errors are high-pass modulated just like
the quantization noise. Actually, the performance of the system is limited by these non-idealities and
not by the quantization noise.
System modeling allows a good estimation on the performance of switched-capacitors Σ−∆ modulator.
In this section the main non-idealities are introduced and its behavioral model blocks are presented.
With the use of these blocks, several circuit parameters can be derived.
The fundamental block in a switched-capacitor Σ−∆ modulator is the integrator. The ideal switched-
capacitor integrator with unity coefficients can be modeled with the transfer function of the expression
(3.25), which is repeated here for convenience
( )
1
11
zH z
z
−
−=
−
(4.3)
The correspondent model of the ideal integrator is presented in Figure 4.7.
Figure 4.7. Model of an ideal integrator.
The switched-capacitor integrator is modeled as an operational amplifier (OpAmp) and the sampling
capacitance and the integration capacitance, like is shown in Figure 4.8.
33
Figure 4.8. Switched-capacitor integrator model.
One of the major causes of the degradation in the performance of Σ−∆ modulators is the incomplete
charge transfer, also known as leakage in the switched-capacitors integrators due to the operational
amplifier non-idealities, namely finite gain, bandwidth, slew-rate and saturation voltages.
DC gain
The transfer function of the integrator is given by [Yao2006],
( )1
2
12
1
1
i
o
C zH z
Cz
ρρ
ρ
−
−
=
− (4.4)
Where ρ1 and ρ2 are the closed-loop static errors determined by the following expressions,
1
1
11
DC dc
DC dc
A f
A fρ =
+ (4.5)
2
2
21
DC dc
DC dc
A f
A fρ =
+
(4.6)
Where ADC is the OpAmp DC gain and fdc1 and fdc2 are the DC feedback factors during the sampling
and integration phases respectively. Factors fdc1 and fdc2 are given by the following expressions
1 1dcf = (4.7)
2o
dc
o i
Cf
C C=
+ (4.8)
Adding these factors to the behavioral model of the integrator gives a relationship between the OpAmp
DC gain and the SNR of the Σ−∆ modulator. The new model of the integrator is shown in Figure 4.9.
34
Figure 4.9. Model of a leaky integrator.
Incomplete and non-linear settling
In a switched-capacitor circuit, in each clock phase transition there is a charge transfer between two or
more capacitors. Thus, in each switching time instant there is an impulse in the output voltage of each
integrator. Moreover, given the fact that the bandwidth of the OpAmp is finite, it is necessary a finite
time for this impulse to be corrected at the output voltage.
Switched-capacitor circuits are discrete time systems by definition. The output voltages are only
observed at sampled times; therefore it is only required to assure that the output voltage at the
sampled time is at the final value minus an error. This statement is only correct if the signal variation is
smaller than the slew-rate (SR) of the amplifier.
If the signal evolution is dominated by the OpAmp’s slew-rate then the settling is considered to be
voltage dependent, i.e. non-linear, resulting in harmonic distortion. In practice this slewing is tolerated
if it happens only during a small part of the available settling time (Ts/2).
Considering the settling is completely linear, the error in the transfer function of the integrator is given
by
( ) ( )1
11
1
i
o
C zH z
C zε
−
−= −
− (4.9)
Considering the OpAmp has a first order impulsive response (dominant pole frequency response), the
time response to a step with amplitude Ve is given by
( ) [ ]
t
o e ev t V V e Vτ
−
= − (4.10)
where τ is the OpAmp time constant.
The slope of this curve reaches its maximum value when t=0, resulting in
( )max
eo
Vdv t
dt τ= (4.11)
Two separate cases have to be considered now [Malco2003]:
35
1) When the value specified by equation (4.11) is lower than the slew-rate of the OpAmp, no slewing
occurs and the evolution of the output is described by ((4.10) during the whole clock period (until
t=Ts/2);
2) When the value specified by equation ((4.11) is larger than the slew-rate of the OpAmp, the
amplifier is slewing and therefore the first part of the transient of vo(t-t0) is linear with slope SR.
0t t< ( )o ev t V t= + SR (4.12)
0t t< ( ) ( )
0
1
t t
o e ev t V V e τ
− = + − −
0SRt
(4.13)
where t0 is given by
0eV
tSR
τ= − (4.14)
If t0 is greater than the available settling time, the amplifier is always in SR and only equation (4.12)
holds.
Adding the settling non-ideality to the finite DC gain one, a new behavioral model for the integrator is
constructed, shown in Figure 4.10.
Figure 4.10. Behavioral model of a integrator with finite DC gain and settling non-idealities.
The SR of an amplifier is given by
eq
V ISR
t C
∆= =
∆ (4.15)
Where Ceq is the equivalent switching capacitor and I is the available current from the amplifier to
charge or discharge this charge.
According to [Johns1997] a properly compensated amplifier is approximate to a first order system with
a time constant given by
[ ]
1
2s
GBWτ
π β= 4.16
36
where β is the circuit feedback factor and GBW is the product gain-bandwidth of the amplifier.
For a given resolution of N bit, the maximum settling error in the available settling time must be inferior
to half a LSB
( )[ ]max 1
2 1%
2
e o s
N
e
V v t T
Vε
+
− == = (4.17)
This settling error can be defined in number of time constants (nτ) that fit in half clock period
( )1
max 1
1ln 2
2
n N
Ne nτ
τε − +
+= = ⇔ = (4.18)
The use of the behavioral model shown in Figure 4.10 allows the generation of relations between the
resolution of the modulator and the GBW and SR of the amplifier.
Electronic noise
The maximum SNR a system can achieve depends on two factors: the quantification noise and the
thermal noise level. The quantification error is settled by the choice of architecture and so it is the
thermal noise that limits the SNR.
The main noise sources in a switched-capacitor integrator are the switched-capacitor networks and
the operational amplifier. From Appendix 1, the thermal noise power stored in the integration capacitor
of a switched-capacitor is given by
( )
22
2 2
, 21 1 1 1
2
3
M P M P
Ai Aj Ai AjN T INT
i j i jO C
kT mV C C C C V
C OSR C
β
= = = =
= + + + ∑ ∑ ∑ ∑ (4.19)
where k is the Boltzmann constant, T represents the absolute temperature, OSR is the oversampling
ratio, CO is the integration capacitor, CAi represents one or more capacitors that sample the input
signal in one clock phase, CAj represents one or more capacitors that sample the input signal in the
complementary clock phase, m is a factor representing the contribution of the OpAmp’s noise
normalized to the differential pair transistor noise, β is the feedback factor of the circuit and CC is the
compensation capacitor.
The SNR at the input of the Σ−∆ modulator is given by
(4.20)
where Psignal,diff stands for the differential input signal, VN(T),INT1,diff,input2 represents the input referred
thermal noise of the first integrator differential output and gi represents the signal gain.
37
It is also possible to relate the specified SNR with the correspondent maximum thermal noise power
( ),2 2
, 1, ,
10
input
signal diff
N T INT diff input SNR
PV V =
10
(4.21)
Figure 4.11 shows the behavioral model for the thermal noise of the switched-capacitors and of the
operational amplifier [Malco2003].
Figure 4.11. Model of the switched-capacitor integrator noise.
The expression Thermal Noise in Figure 4.11 represents the thermal noise voltage and is given by
( ) [ ]2
, 1, ,N T INT diff inputThermalNoise V V=
(4.22)
MOS Switches
The requirements for MOS (Metal-Oxide-Semiconductor) switches for switched-capacitor circuits are
that they have a very high OFF resistance (so little charge leakage occurs) and a relatively low ON
resistance (so that the circuit can settle in the available settling time).
Linearity is an important factor in the design of the switches. Figure 4.12 shows the ON-resistance as
a function of the input voltage for the three types of MOS switches, NMOS, PMOS and CMOS. It is
desirable to select a region of operation where the ON resistance of the switch is independent of the
input voltage.
Figure 4.12. Switch On-Resistance as a function of the input voltage [Khoo1998].
38
The ON resistance (RON) of a NMOS or PMOS switch is given by,
( )[ ],
1 1ON MOS
dgs th ds
ds
RI W
K V V VLV
= = Ω∂
− −∂
(4.23)
where K=µCOX is a technology parameter (in A/V2), µ is the carriers mobility (cm
2/V/s), COX is the gate
oxide capacity density (F/m2), Id is the drain current (in A), Vgs is the voltage difference between gate
and source (in V), Vds is the voltage difference between drain and source (in V), W and L are the
transistor’s dimensions (in m) and Vth is the threshold voltage (in V).
After a small transient between cut and conduction, when the switch is in moderate conduction and
with Vds=0, equation (4.23) becomes
( )[ ],
1ON MOS
gs th
RW
K V VL
= Ω
−
(4.24)
From expression (4.24), the voltage applied to the switch must always be superior to Vth for the
channel resistance to be small and independent of the Vgs value. Consequently, if the applied signal
has a high amplitude range, CMOS switches must be used.
A CMOS switch is constituted by a PMOS and a NMOS switch in parallel, as shown in Figure 4.12.
The effective resistance of a CMOS switch is given by,
( ) ( )[ ],
, , , ,
1ON CMOS
N gs N th N P sg P th P
N P
RW W
K V V K V VL L
= Ω
− + −
(4.25)
The CMOS switch should be designed for equal impedance, this meaning that the PMOS should be
made larger than the NMOS by a factor equal to the ratio of µN/µP
NP
P
W
L
W
L
µ
µ
=
(4.26)
The OFF resistance of a switch is not infinite, but with proper design it can have values between MΩ
and GΩ, depending on the polarization, which is more than enough for most applications. Some
technologies present as an option, low threshold MOS transistors that can have lower OFF
resistances (KΩ), thus its use must be carefully analyzed.
When the switch turns OFF, the charge stored in the transistor’s channel is distributed by the drain
and source, which represents an addition of unwanted charge to sampling capacitor. This effect is
called charge-injection and is sometimes referred to as clock feed-through [Johns1997].
39
The CMOS switches should be designed for a first-order cancellation of charge injection errors. This
error is given by [Khoo1998],
( ) ( )
( ) ( )( ), ,
1 1
2 2
1
2
chan chanN POUT
s s
OXN N DD IN th N P P IN th P
s
Q QV
C C
CW L V V V W L V V
C
∆ = − + =
= − − − − −
(4.27)
where Qchan is the charge stored in the channel, COX is the gate oxide capacity density (F/m2), Cs is the
sampling capacitor (e.g. capacitor Cf3 of Figure 5.3), W and L are the transistor’s dimensions (in m),
Vth,N/P is the threshold voltage in V (P for PMOS, N for NMOS), VDD is the supply voltage (in V) and VIN
is the input voltage of the switch (in V).
For a partial cancellation of charge-injection error, the NMOS and PMOS should be designed to have
equal sizes
N N P PW L W L= (4.28)
Both the use of delayed clock phases and the fully-differential configuration of the integrator mitigate
the effects of signal-dependent charge injection [Johns1997].
Internal ADC non-linearity
The non-linearity of the internal A/D converter, mainly due to the mismatch in quantification levels and
to electronic noise, is highly attenuated by the high gain of the preceding stages. The quantification
noise is also highly attenuated by the integrators gain thus its effect in the resolution of the converter is
not that important [Norsw1997].
In conventional CMOS technologies it is relatively simple to project and design comparators with the
desired resolution. The behavioral model of the internal ADC is shown in Figure 4.13, with a quantizer
with 12 levels of quantification (to emulate the 12 level flash internal ADC) and where the only non-
ideality included is the saturation voltage of the circuit.
Figure 4.13. Behavioral model of the internal ADC
40
Internal DAC non-linearity
The main problem with multi-bit quantification is the fact that the internal DAC linearity can limit the
performance of the system. Any error in the DAC appears directly at the output without any
modulation, implying it must have the same resolution of the modulator.
A 1 bit DAC is intrinsically linear while a multibit DAC requires high precision components. This is
especially critical in digital CMOS technologies, forcing the use of linearization techniques. In current
technologies it is not possible to realize DAC with elements having a mismatch error below 0.1%,
which corresponds to 10 bit linearity.
There are two ways of correcting the DAC’s non-linearity: digital self-calibration and dynamic element
matching. The first translates in an increase of the complexity of the system [Baird1995]. The basic
principle with DEM technique is the alternately choice of the DAC elements so the output medium
value tracks the ideal medium value. As a result, the introduced distortion is modulated to high-
frequencies and can be eliminated by the digital filter at the output of the Σ−∆ modulator, just like the
quantification noise.
In specialized literature [Baird1995] several DEM algorithms are described with more detail, but here
some techniques are presented:
Randomization - The number of used elements is based on the input digital word and they are
selected randomly. The distortion appears as white noise uniformly distributed in all
frequencies, implying an increase in linearity.
Clocked Averaging – A pointer is used to indicate the first element to be chosen. This index is
incremented at the clock frequency and each element is used at a minimum rate of fs/N, where
N represents the number of elements. The noise appears at multiple frequencies of this rate
and is uniformly spread in the frequency spectrum.
Individual Level Averaging (ILA) – Each DAC level has a start index that registers the
elements used in the last time this level was utilized. This means that after some utilizations of
a certain level, all the elements would have been used and the medium error of that level
approaches zero. This algorithm conserves the noise modulation effect of the ideal modulator.
Data Weighted Averaging – The great advantage of this technique results from the fact that
the DAC elements are used at the maximum rate possible. This is done selecting sequentially
the elements of a vector where the first selected element is the one next to the last utilized
(there is only one index for all levels). As a result, the elements’ error tends rapidly to zero and
the distortion is moved to high frequencies.
From the techniques described, according to results published in literature [Cini1999], the DWA is the
one that best keeps the noise modulation effect and consequently the best linearization algorithm for
D/A converters.
41
4.4 Functional Simulation
The high-level design of the Σ−∆ modulator is validate through functional simulations using the
Matlab/Simulink environment. This simulation validates the solutions chosen.
The behavioral model of the Σ−∆ modulator is presented in Figure 4.14. To make this behavioral
model closer to the real model, non-idealities are included and saturation blocks are added:
- Saturation: limits the output swing of the integrators to the voltage supply level (±VDD=±1V);
- DC gain of the amplifier: models the charge and discharge leakage;
- GBW and SR of the amplifier: models the incomplete and non-linear settling;
- Thermal Noise: models the thermal noise of switched-capacitors and the thermal noise of the
amplifier.
Figure 4.14. Behavioral model of the ΣΣΣΣ−−−−∆∆∆∆ modulator.
Only the first integrator has all these non-idealities modeled as seen in Figure 4.15. In 2nd
and 3rd
integrators, shown in Figure 4.16, the model for thermal noise is not included as it does not limit the
performance of the system. Table 4.4 summarizes the parameters of some of the non-idealities for the
behavioral simulation.
Table 4.4. Parameters for the non-idealities used in the behavioral simulation
Symbol Parameter 1st
Int. 2nd
Int. 3rd
Int. Units
Vsat Saturation Voltage ±VDD ±VDD ±VDD V
ADC DC Gain 40 40 40 dB
nττττ Number of taus 5 5 5 s
SNR Signal-to-noise-ratio 67 - - dB
42
Figure 4.15. First Integrator behavioral model.
Figure 4.16. Second and third Integrator behavioral models.
4.5 Simulation Results
In order to assess the function and performance of the circuit, several simulations are realized. First,
an evaluation of the maximum achievable SNR of the ideal modulator (SQNR) is performed and then
the non-idealities are introduced to validate the performance of the real system.
4.5.1 Ideal Modulator
This simulation pretends to evaluate the behavior of the ideal Σ−∆ modulator. The blocks of the system
do not introduce any kind of noise or non-ideality. Only the intrinsic quantization noise is assessed.
Table 4.5 shows the characteristics of the input signal and summarizes the results of the simulation
Table 4.5. Summary of the simulation setup and results.
Specifications Input
Results
Mode SNR [dB]
ENOB [bit]
Fs [MHz]
F [MHz]
A [%FS]
OSR SQNR [dB]
ENOB [bit]
GSM 64 10,3 3,0 0,1 0,5 15 74 12,0
CDMA2000 62 10,0 15,0 0,6 0,5 12,5 70 11,3
UMTS 55 8,8 33,8 2,0 0,5 8,4 56 9,0
DVB-H 54 8,7 67,5 4,0 0,5 8,4 56 9,0
Figure 4.17 presents the power spectral densities of the ideal Σ−∆ modulator output for the worst case
modes: Mode 1 - GSM (best SNR) and Mode 4 – DVB-H (higher signal bandwidth). The maximum
43
SQNR of the system is between 3 and 4 dB below the architecture’s SQNR (Table 4.1) mainly due to
the fact the input signal is 50% full-scale, which corresponds to a decrease of 3dB in theoretical signal
power, and to the gains of the integrators.
Figure 4.17. Power Spectral Density of the modulator output for Mode 1 – GSM and Mode 4 – DVB-H.
4.5.2 Real Modulator
This simulation pretends to evaluate the behavior of the real Σ−∆ modulator. Several non-idealities are
introduced, namely the finite gain of the amplifiers, the incomplete and non-linear settling, and the
thermal noise. First, the system is simulated with all non-idealities except thermal noise and then all
the non-idealities are simulated. The input signal characteristics used are the ones showed in Table
4.5. The performance results are summarized in Table 4.6.
Figure 4.18 and Figure 4.19 present the modulator’s output Power Spectral Density for mode 1 and
mode 4 respectively (worst cases). When the finite gain and incomplente and non-linear settling non-
idealities are introduced, the SNR obtained decreases about 1 dB from the simulated SQNR. When
the thermal noise non-ideality is introduced in the system, there is decrease in the SNR. The SNR of
the system becomes limited by the Thermal Noise.
Table 4.6. Summary of the performance results of the real modulator.
Specifications
Results (ADC +
Settling)
Results (ADC + Settling +
Thermal Noise)
Mode SNR [dB]
ENOB [bit]
fs [MHz]
fb
[MHz] OSR
SNR [dB]
ENOB [bit]
SNR [dB]
ENOB [bit]
GSM 64 10,3 3,0 0,1 15 73 11,9 67 10,9
CDMA2000 62 10,0 15,0 0,6 12,5 68 11,0 65 10,5
UMTS 55 8,8 33,8 2 8,4 56 9,0 56 9,0
DVB-H 54 8,7 67,5 4 8,4 56 9,0 55 8,9
44
Figure 4.18. Power Spectral Density of the modulator’s output for Mode 1 - GSM.
Figure 4.19. Power Spectral Density of the modulator’s output for Mode 4 – DVB-H.
To assess the behavior of the system, it is important to check the amplitudes of the integrator’s output.
The integrator’s and modulator’s outputs for mode 1 and mode 4 are presented in Figure 4.20 and
Figure 4.21 respectively. From the observation of these figures, it is noticeable that all the outputs
exhibit a sinusoidal aspect but with different oscillations.
45
Figure 4.20. Outputs of the integrators and modulator for Mode 1 - GSM.
Figure 4.21. Outputs of the integrators and modulator for Mode 4 – DVB-H.
46
Chapter 5
Circuit Design
This chapter describes the circuit design of the system. First, the design of the integrators is presented
and then some possible design options for the internal ADC and DAC are introduced.
5.1 Integrators
There are two ways of implementing the basic building block of Σ−∆ modulators, the integrator. It can
be implemented using a switched-capacitors or active RC topology. For this work, the topology chosen
is switched-capacitors as it presents several advantages over active RC:
The operational amplifiers’ loads are purely capacitive and therefore do not require low
impedance outputs;
The transfer functions are established by relations between capacitors which are very precise;
The signals are only sampled in a given time instant thus the outputs of the amplifiers only
need to present at that instance a certain error determined by required resolution.
Each integrator realizes three basic functions: sampling of the input signal, D/A conversion of the
modulator’s output signal and subtraction of both of these signals. In each stage there are two
switched-capacitors branches: one samples the input, the other the voltage reference; the difference
between them is then integrated in a capacitor and available at the integrator’s output.
5.1.1 Capacitors Design
Given the fact that the system has feedback, the non-idealities – such as noise and distortion in the
signal band – of the integrators beyond the first one, when input referred, are attenuated by the low-
frequency gain of the first integrator. Therefore, the first integrator has the most demanding
specifications in terms of resolution and the whole performance of the Σ−∆ modulators depends on the
performance of the first stage.
1st integrator
Figure 5.1 presents the simplified non-differential electrical schematic of the first integrator.
Two capacitors (Ci1a and Ci1b) are used sample the input signal in complementary clock phases. With
this technique the input signal is sampled with an effective sampling frequency of 2fs, although the
47
capacitors are still switched at frequency fs. This double sampling technique implements a low-pass
anti-aliasing filtering function with zeros in every odd multiple of fs [Tavares2002].
Although the integrators are implemented in fully-differential topologies, to simplify the analysis, only
half of the fully-differential integrator is considered. This can be easily extrapolated for a fully-
differential topology, considering the noise power contributions are the double while the signal power
is four times superior.
Figure 5.1. 1st
Integrator simplified electrical schematic.
From section A1.4, the total thermal noise power stored in the first integrator integration capacitor of
the integrator from Figure 5.1, is given by
( ) ( )
( )2
2
1 1 11 1 12 2 2
, 1 , 12 2
1 1
2 i a f i bi a i b f
N T INT N T OA
O O
C C CC C CkTV V V
OSR C C
+ ++ + = +
(5.1)
where k is the Boltzmann constant, T represents the absolute temperature (in K), OSR is the
oversampling ratio, CO is the integration capacitor, Ci1a and Ci1b are the input signal sampling
capacitors, Cf1 is the DAC feedback sampling capacitor and VN(T),OA2 is the operational amplifier’s
thermal noise referred to its input (equation (A1.19)) .
Recalling the 1st integrator gains from Table 4.3 and analyzing the charge transfer of Figure 5.1,
11 1
1 1
1 1
0,35 , 0,3fi a i b
i f
O O
CC Cg g
C C
+= = = =
(5.2)
and dividing expression (5.1) by signal power gain (gi12), it is possible to obtain the total thermal noise
power referred to the input of the integrator (non-fully-differential)
48
( ) ( )
( )
( )
22
1 1 11 12 2
, 1, , 12 2 2
1 1 1 1
1 1 2 2
, 1,2
1 1
2
2
i a f i bi f
N T INT input N T OA
O i O i
i f
N T OA input
O i
C C Cg gkTV V
OSRC g C g
g gkTV V
OSRC g
+ ++ = + =
+ = +
(5.3)
where VN(T),OA,input2 represents the thermal noise power of the OpAmp referred to the input of the
integrator.
The signal-to-thermal noise ratio of the fully-differential integrator is given by,
( )
[ ],
1 2
, 1,2
signal diff
INT
N T INT input
PSNR d
V= Β (5.4)
The input-referred thermal noise contribution of the OpAmp is given by,
( ) 1
,2 2
, 1,
1010OA
signal diff
N T OA input SNR
PV V = (5.5)
where SNROA1 represents the OpAmp’s respective signal-to-thermal noise ratio.
As displayed in Table 4.2, the worst SNR specification is 64dB for Mode 1 - GSM. To have some
margin to account with non-idealities not accounted, 3dB are added to the SNR specification which is
now 67dB. Replacing expression (5.5) in expression (5.3), and this result in (5.4) and solving it in
order to CO, results in CO1>220fF. Considering that after the implementation in silicon, the capacity
value can vary within some extent, the chosen value is CO1=500fF. From expressions (5.2) the
remaining capacitor values can be determined and are presented in Table 5.1.
Table 5.1. 1st
integrator capacitors values.
Symbol Parameter Value Units
Ci1a Input sampling capacitor in phase 1 87,5 fF
Ci1b Input sampling capacitor in phase 2 87,5 fF
Cf1 Voltage reference sampling capacitor 150 fF
CO1 Integration capacitor 500 fF
The capacitors must be well matched for the gains to be very precise. For that to happen, each
capacitor is implemented by a group of unit capacitors (Cunit1) connected in parallel. On the other hand,
the feedback capacitor (Cf1) is in fact constituted by 12 identical branches that sample the reference
signal simultaneously. In each integration phase Φ2, the number of branches connected to the
integration capacitor is controlled by the 12 feedback signal lines (VDAC) and consequently, the
feedback gain gf can vary between 0 and 12xCunit1/CO1. To guarantee precision and match between
49
these capacitors, Cunit1 must be as big as possible. The value of Cf1 in Table 5.1 represents the sum of
the 12 feedback capacitors, thus the unit capacitor must be Cunit1=12,5fF.
The relative mismatch error between capacitors can be measure as a variance according to,
[ ]%CC
C WLσ
Α∆ =
(5.6)
where AC is a characteristic technology parameter.
2nd integrator
Figure 5.2 shows the non-fully-differential simplified electrical schematic of the 2nd
integrator.
Figure 5.2. 2nd
Integrator simplified electrical schematic.
Just like for the 1st integrator, the total noise power stored in the integration capacitor of the 2
nd
integrator is given by,
( ) ( )
2 2
2 2 2 22 2 2
, 2 , 22 2
2 2
2 i f i f
N T INT N T OA
O O
C C C CkTV V V
OSR C C
+ + = +
(5.7)
where k is the Boltzmann constant, T is the absolute temperature (in K), OSR is the oversampling
ratio, CO2 is the integration capacitor, Ci2 is the input signal sampling capacitor, Cf2 is the voltage
reference sampling capacitor and VN(T),OA2 represents the thermal noise of the amplifier referred to its
input. The above expressions (5.4) and (5.5) can be applied to the 2nd
integrator with the change of
the index 1 to 2 in every variable.
Recalling the 2nd
integrator gains from Table 4.3 and analyzing the charge transfer of Figure 5.2,
22
2 2
2 2
2, 0, 6
3
fii f
O O
CCg g
C C
= = = =
(5.8)
50
and dividing equation (5.7) by the signal power gain (gi22), it is possible to obtain the total thermal
noise power referred at the input of the integrator (non-fully-differential)
( ) ( )
( )
2 2
2 2 2 22 2
, 2, 2 , 22 2 2
2 2 2 2
2 2 2 2
, 2, 22
2 2
2
2
i f i f
N T INT input N T OA
O i O i
i f
N T OA input
O i
g g C CkTV V
OSRC g C g
g gkTV V
OSRC g
+ + = + =
+ = +
(5.9)
where VN(T),OA,input22 represents the thermal noise power of the OpAmp referred to the input of the
integrator.
The thermal noise specification for the 2nd
integrator is more relaxed comparing to the fist integrator.
For the 2nd
integrator the SNR specification is 66dB for both the switched-capacitors and the OpAmp’s
thermal noise, which gives a 64,5 dB specification for the 2nd
integrator at its input (input voltage=0,6
Vdiff).
Replacing equation (5.5) in equation (5.9) and its result in equation (5.4) and solving it in order to CO2,
results in CO2=61,4fF. Once again, considering that after the implementation the capacitor value can
change within some extent, the chosen value is CO2=160fF. From equation (5.8) the remaining
capacitor values can be determined and are presented in Table 5.2.
Table 5.2. 2nd
integrator capacitor values.
Symbol Parameter Value Units
Ci2 Input sampling capacitor 106,7 fF
Cf2 Voltage reference sampling capacitor 96,0 fF
CO2 Integration capacitor 160 fF
Like for the 1st integrator, to maximize the match precision between capacitors, Cunit2=Cf2/12, which
becomes Cunit2=8fF.
3rd integrator
Figure 5.3 shows the simplified non-fully-differential electrical schematic of the 3rd
integrator.
The 3rd
integrator topology is similar to the 2nd
integrator one. Just like for the 2nd
integrator, the total
noise power stored in the integration capacitor of the 3rd
integrator is given by,
(5.10)
where k is the Boltzmann constant, T is the absolute temperature (in K), OSR is the oversampling
ratio, CO2 is the integration capacitor, Ci2 is the input signal sampling capacitor, Cf2 is the voltage
reference sampling capacitor and VN(T),OA2 represents the thermal noise of the amplifier referred to its
51
input. The above equations (5.4) and (5.5) can be applied to the 3rd
integrator with the change of the
index 1 to 3 in every variable.
Figure 5.3. 3rd
integrator simplified electrical schematic.
Recalling the 3rd
integrator gains from Table 4.3 and analyzing the charge transfer of Figure 5.3,
33
3 3
3 3
1,5 , 0,9fi
i f
O O
CCg g
C C
= = = =
(5.11)
and dividing equation (5.10) by the signal power gain (gi32), it is possible to obtain the total thermal
noise power referred at the input of the integrator (non-fully-differential)
( ) ( )
( )
2 2
3 3 3 32 2
, 3, 3 , 32 2 2
3 3 3 3
3 3 2 2
, 3, 32
3 3
2
2
i f i f
N T INT input N T OA
O i O i
i f
N T OA input
O i
g g C CkTV V
OSRC g C g
g gkTV V
OSRC g
+ + = + =
+ = +
(5.12)
where VN(T),OA,input32 represents the thermal noise power of the OpAmp referred to the input of the
integrator.
The thermal noise specification for the 3rd
integrator is more relaxed compared to the 2nd
integrator
one. For the 3rd
integrator the SNR specification is 62dB for both the switched-capacitors and the
OpAmp’s thermal noise, which gives a 58 dB specification for the 3rd
integrator at its input (input
voltage = 0,45 Vdiff).
Replacing equation (5.5) in equation (5.12) and its result in equation (5.4) and solving it in order to
CO3, results in CO3=36,7fF.Once again, considering that after the implementation the capacitor value
can change within some extent, the chosen value is CO3=106,7fF. From equation (5.8) the remaining
capacitor values can be determined and are presented in Table 5.3
52
Table 5.3. 3rd
integrator capacitor values.
Symbol Parameter Value Units
Ci3 Input sampling capacitor 160 fF
Cf3 Voltage reference sampling capacitor 96,0 fF
CO3 Integration capacitor 106,7 fF
Like for the 1st integrator, to maximize the match precision between capacitors, Cunit2=Cf2/12, which
becomes Cunit2=8fF.
5.1.2 Switches Design
Taking into account all the considerations about MOS switches presented in section 4.3.2, the
switched-capacitor networks need to be designed to have enough bandwidth so that the capacitors
voltage can settle in the available settling time with a given resolution. The charging and discharging
time of the capacitors is limited by the ON resistance of the switch RON.
Defining the time constant of the switch-capacitor group like
ONR Cτ = (5.13)
It can be shown in [Tavares2002] that is possible to obtain a relationship between the resolution of the
modulator and the ON switch-resistance using a similar analysis,
( )1
1 1
2 2 ln 2ON N
s s
Rf n C f Cτ
+= = (5.14)
In sub-micron technologies like the one used in this system, it is possible to make nτ,SW>5nτ,OA, (where
nτ,SW and nτ,OA represent the number of time constants of the switches and operational amplifier
respectively, Table 4.2) with relatively small transistors. This way, the switches do not limit the
dynamic performance of the integrators.
Recalling equation (4.24) and considering equation (5.15), an expression can be obtained in order to
W (the channel width) for an NMOS or PMOS switch,
(5.15)
where fs is the sampling frequency, C is the switched-capacitor, nτ is the number of time constants of
the switch, L is the switch’s channel length, K is a technology parameter (A/V2), Vgs and Vth are the
gate-to-source and threshold voltages respectively. L is chosen to be the technology minimum.
In terms of charge injection and ON resistance, the most critical switches are the ones who sample the
input signal. To minimize these effects, the switches that transmit the signal are realized by CMOS
53
switches commanded by delayed clock phases. Therefore, the input switches are turned OFF little
after the ones connected to the amplifier’s virtual ground. This way, in that instant, there is no
conductive path between the positive terminal and the capacitor and so, there is no charge-injection
dependent of the input signal in the capacitor by the input switches, which would cause distortion.
5.1.3 Multi-Standard Adaptability
One of the requirements of this Σ−∆ Modulator is the adaptability to multiple RF standards. This
modulator is designed for GSM, CDMA2000, UMTS and DVB-H. Table 5.4 summarizes the system
specifications for every mode.
Table 5.4. System specifications for the ΣΣΣΣ−−−−∆∆∆∆ Modulator.
Mode SNR fs [MHz] fb [MHz] OSR ENOB
1 – GSM 64 3 0,1 15 10,3
2 – CDMA2000 62 15 0,6 12,5 10,0
3 – UMTS 55 33,8 2 8,438 8,8
4 – DVB-H 54 67,5 4 8,438 8,7
Each mode has a different input signal bandwidth, sampling frequency and thus a different
oversampling ratio. Also the SNR specification is different, which means the noise power level
acceptable for each mode is different.
One solution could be to use an operational amplifier with the hardest specifications, namely sufficient
DC gain and gain-bandwidth product to comply with DVB-H specifications and also a thermal noise
power level to comply with GSM SNR specification. This implies a high-bandwidth, low-noise amplifier,
which can be realized with a high current consumption. Having in mind that a GBW increase signifies
a gm of the differential pair increase and/or a compensation capacitor decrease, a gm increase implies
a power increase, a compensation capacitor decrease implies a noise increase. To decrease the
noise level, the compensation capacitor must be increased, which implies a decrease in GBW, but
also an increase in area and power.
Other solution could be to use different operational amplifier for different modes, where only one is
active in each mode of operation, but in this case there is an area and power-down consumption
increase.
The solution adopted is to design a programmable operational amplifier, where for each mode, the
performance of the OpAmp changes according to the desired mode specifications, just like a different
OpAmp for each mode realized by the same structure.
54
5.1.4 Operational Amplifier Specifications
The key to the multi-standard adaptability is the use of a programmable operational amplifier;
therefore, the design of the 1st integrator’s operational amplifier is the real bottleneck of the system.
This section presents the formulation of the 1st integrator’s operational amplifier specifications.
DC Gain
According to [Norsw1997], in a 2nd
order modulator, the noise increment inside the signal band is less
than 1dB when the integrator’s gain is comparable to the oversampling ratio. In higher-order modulator
this effect is even less important as there are more integrators in series in the action loop; therefore
lower gains are tolerated. The highest OSR is for Mode 1 – GSM thus ADC,min=15. In logarithmic units,
this value corresponds to 23,5dB. Different modes imply different ADC. A moderate gain of 40 dB
should be sufficient for a 10bit resolution.
Gain-Bandwidth product (GBW) and Settling
In a switched-capacitors integrator, the signals are not observed continuously and consequently, it is
only necessary to guarantee that in the end of the sampling period, the signal stored in the capacitor is
below the ideal value with an error determined by the resolution requirement.
Recalling equations (4.16) and ((4.18), the gain-bandwidth product of the operational amplifier is
related to the allowed settling time and the required resolution and is given by,
( )[ ]
1ln 2N
sfGBW Hzβ
π
+
=
(5.16)
where N is the required resolution (in bit), β is the feedback factor of the circuit, fs is the sampling
frequency (in Hz) and GBW is the gain-bandwidth product of the amplifier (in Hz). From Table 5.4,
different modes have a different resolution and sampling frequency specifications thus a different
GBW specification is generated by equation (5.16.
Phase Margin
The most frequent measure of the relative stability of a feedback system is the phase margin (PM).
However a high PM is not a guaranty of proper system performance and it is necessary to observe the
frequency response and check there is no over-elevation that can degrade the impulsive response of
the system. Also, pole-zero pairs can exist, and although sometimes not visible in the frequency
response, can degrade the time response. The minimum specified phase margin is PMmin=60º for all
modes.
55
Slew-Rate
The settling analysis realized in the previous section is only valid if the output settling is linear, i.e. as
long as its variation rate is lower than the maximum variation rate of the operational amplifier’s output
voltage (slew-rate). Nevertheless, if the amplifier evolves non-linearly only for a fragment of the
available settling time (half clock period) and linearly for the rest of the settling time, the distortion
introduced is despicable, [Feld1997].
The slew-rate specification for a class A output stage operational amplifier, when loaded with a
switched-capacitor can be defined as the time average of the output voltage. This means the ration
between the maximum voltage transition of the output (∆vO,max) and the available time for this
transition, which can be defined as one fifth of the settling time, thus one tenth of the clock period. This
results in,
[ ],max10 s OSR f v V s= ∆ (5.17)
From Table 5.4, different modes have different sampling frequencies, thus a different slew-rate
specification. The maximum output voltage variation is 0,6V.
Noise
From section 5.1.1, the thermal noise power of the 1st integrator’s operational amplifier (fully-
differential) referred to the input of the 1st integrator is given by,
( )
( )2
2
1 1 12 2
, 1, 2 2
1 1
22
3
i a f i b
N T OA input
C O i
C C CkTV m V
C OSR C gβ + + =
(5.18)
The OpAmp’s thermal noise level must comply with the specification of 70dB for GSM standard, 68dB
for the CDMA2000 standard, 61dB for the UMTS standard and 59dB for the DVB-H standard.
Summary
From the above expressions and specifications from Table 5.4 is possible to write the specifications
for the operational amplifier, summarized in Table 5.5.
Table 5.5. Summary of the 1st
integrator’s operational amplifier’s specifications.
Symbol Parameter GSM CDMA2000 UMTS DVB-H Units
ADC DC Gain 45 45 40 40 dB
ββββGBW Equivalent βGBW 5,9 28 61 120 MHz
SNRVN(T) Signal-to-thermal-noise ratio 70 68 65 65 dB
VN(T),INT,input2
Thermal Noise Power 12,5 19,8 39,5 39,5 nV2
SR Slew-Rate 18 90 203 405 V/µs
56
Conceptually, the three integrators are identical; only the specifications differ. The specifications for
the 2nd
and 3rd
integrators are more relaxed, as the corresponding non-idealities when referred at the
input of the modulator appear attenuated by the gains of the preceding stages; consequently, the
specifications for the corresponding operational amplifiers are also relaxed.
5.2 Programmable Amplifier Design
This section describes the design of the operational amplifier for the first integrator. The design
methodology can be extended to the design of the 2nd
and 3rd
integrator OpAmps with the difference
being the relaxation of the specifications.
5.2.1 Topology
The selected topology for the operational amplifier is a two-stage amplifier with cascode compensation
[Ahuja1983], as shown in Figure 5.4. For a matter of simplicity, bias and common-mode feedback
circuits are not included. The input-stage is a folded cascode with a PMOS differential pair while the
output-stage is a class-A common source.
Figure 5.4. Two-stage cascode compensated operational amplifier with folded first-stage.
Some form of compensation is necessary to maintain stability in a two-stage amplifier. The standard
Miller compensation [Johns1997] places a pole-splitting capacitor between the output of the amplifier
and the output of the first stage (between the drains of M11 and M5, Figure 5.4). This technique creates
a dominant low-frequency pole and moves the second pole to a higher frequency which ensures
amplifier stability. On the other hand the cascode compensation technique places a compensation
capacitor between the amplifier output and the first stage cascode node, Figure 5.4, creating a
dominant pole and two complex poles at higher frequencies. This also ensures amplifier stability with
the advantage of increasing the speed compared to Miller compensation. Higher speed amplifier
topologies achieve low power dissipation under a fixed settling constraint, thus the cascode
compensation technique is preferred.
57
5.2.2 Frequency response
To analyze the open-loop frequency response of the operational amplifier, the small-signal equivalent
model for weak signals valid for small variations around the bias point is elaborated, represented in
Figure 5.5., where gmi is the incremental transconductance of the transistor Mi (Figure 5.4), rn e cn
represent the total incremental resistance and capacitance respectively at nodes n, rnp represents the
total incremental resistance between nodes n and p and CC is the compensation capacitor.
The behavior of the circuit is described by the equation system
( )( )( ) ( )
( )( )
5 1 12 1 1 12 2 1
5 12 1 12 2 2 2
1 11 2
0
0
C C out in
C out out C out
gm g g s c C v g v sC v gm v
gm g v g g sc v
sC v gm v g s C C v
+ + + + − − = −
− + + + + =
− + + + + =
(5.19)
where conductances gn are used instead of resistances rn to ease the writing.
Figure 5.5. Small-signal equivalent model for weak signals.
Comparing the circuits of Figure 5.4 and Figure 5.5, it is possible to give a physical meaning to the
conductances gn and capacities cn,
1 1 3
12 5
2
7 7 9
11 13
1 1 5
2 5 7 11
11 13
1
out
out L
g gds gds
g gds
ggm rds rds
g gds gds
c cgd cgs
c cgd cgd cgs
c cgd cgd C
= +
=
=
= + = + = + +
= + +
(5.20)
where gdsi represents the incremental channel conductance of transistor Mi, rdsi represent the
incremental channel resistance of transistor Mi, cgsi and cgdi represent respectively the gate-to-source
58
and gate-to-drain capacitances of the transistor Mi and CL represents the load capacity of the
operational amplifier.
Solving the equation system (5.19), the circuit presents a frequency response with a low-frequency
dominant pole, two off-axis complex poles and two high-frequency symmetric zeros [Hurst2004].
DC Gain
From Figure 5.5, the low-frequency gain1 of the operational amplifier is given by
( )( )( )
1 11 5 12
5 12 1 2 1 12
DC
out
gm gm gm gA
g gm g g g g g
+=
+ + +(5.21)
Considering that the conductances g12 and g1 are small compared to gm5 and that g1g12 is small
compared to gm5gm2, the simplified expression is
1 11
2
DC
out
gm gmA
g g= (5.22)
In the expression (5.22) the gain contributions of the first and second stage of the operational amplifier
are clearly identifiable. The gain of the first stage is given by the differential pair incremental
transconductance gm1 divided by the first-stage output conductange g2. The gain of the second stage
is given by the incremental transconductance of the gain transistor of the second stage (M11), divided
by the output conductance gout.
Gain-bandwidth product
The approximate expression for the gain-bandwidth product of a properly compensated two-stage
operational amplifier with a compensation capacitor CC is given by [Johns1997],
11
C
gmGBW rad s
C
− = ⋅ (5.23)
Dominant pole
Considering the definition of the gain-bandwidth product, the approximate expression for the dominant
pole of the amplifier can be obtained through expressions (5.22) and (5.23) and is given by
(5.24)
High frequency poles and zeros
For the high-frequency poles and zeros, the exact solutions require a mathematical complexity that
does not allow taking conclusions over the dominant factors, and so some simplifications are made, 1 Frequency range before the dominant-pole, where the circuit presents an approximate flat response.
59
[Feld1997] and [Tavares2002]. Therefore, in high-frequencies, the incremental channel conductances
(gds) of the transistors are considered despicable compared to the capacitors’ susceptance (sC).
The non-dominant complex poles pair is given by
2 1
, 1 ,P ND n nw j rad sξϖ ξ ϖ − ≅ ± − ⋅ (5.25)
with damping factor ξ and natural frequency ϖn.
( )5 2
11 1
15 11
2 1
1
2
out C
out CC
out C
n
out C
out C
gm c c C
c Cgm C c
c C
gm gmrad s
c Cc c
c C
ξ
ϖ −
+ ≅
+ +
≅ ⋅ +
+
(5.26)
It is interesting to note that the real part of the complex poles ξϖn only depends on the cascode
transistor transconductance and can be written as:
5
12
n
out C
out C
gm
c Cc
c C
ξϖ =
+ +
(5.27)
Solving the equations system (5.26) in order to gm5 and gm11 the project equations relating the
incremental transconductances of the transistors M5 and M11 with the non-dominant poles location,
can be obtained.
5 1
11
2
11
out Cn
out C
n out
c Cgm c
c C
cgm
ξϖ
ϖ
ξ
= +
+
= +
(5.28)
The expression for the real symmetric zeros pair is given by
(5.29)
Replacing expression (5.28) in (5.29, a new expression for the symmetrical real zeros pair is obtained,
which is independent from the transconductances gm5 and gm11
60
1
1
1 outout
C
z n
C
cc c
Crad s
Cω ω −
+ +
= ± ⋅
(5.30)
If it is assumed that the compensation capacitor CC and the output capacitance cout are of the same
order of magnitude and that the capacitor c1 is despicable when compared to the prior ones, then a
simplified expression for the symmetrical zeros pair is given by
1out
z n
C
crad s
Cω ω − ≅ ± ⋅
(5.31)
Note that once the values for gm5 and gm11 are defined, the symmetrical zeros pair frequency
depends only of the specifications (ωn, cout and CC). Consequently, it can be concluded that the
symmetrical zeros pair frequency ωz and the natural frequency of the complex non-dominant poles
pair ωn are of the same order of magnitude, whenever the previous assumptions are valid.
Once the project equations relating circuit parameters and poles and zeros frequencies are deduced,
it is necessary to define their location.
In switched-capacitors circuits the settling time of the operational amplifier must be minimized and it is
closely related to its impulsive response. It is important to define the non-dominant poles and zeros
location on the complex plane.
A proper analysis of the settling time in 3rd
order systems [Mar1998a], allows a decision about the
location of the zeros and non-dominant poles to minimize the settling time,
1 2
0,9
2,4
2
n d
z z d
ξ
ω ω
ω ω ω
=
= = − =
(5.32)
where ωd is the closed-loop dominant-pole frequency, which is equal to GBWβ, where β is the circuit
feedback factor.
From the GBW specification, and for a given β, determined by the circuit topology, it is possible to
obtain the transconductances for the cascode transistor M5 and for the second-stage gain transistor
M11 for optimal impulsive response.
5.2.3 Noise
From Figure 5.4, the devices that contribute to the noise of the operational amplifier are transistors M1,
M3, M9, M6, M5 M13 and M11 (half of fully-differential circuit), but the contributions of the last two when
61
referred to the input of the OpAmp, are attenuated by the output-stage gain, thus being considered
despicable. It is also considered that, as referred in Appendix1, within certain limits, Flicker noise can
be made as small as it is wanted, and therefore is not included in this analysis.
Considering each MOS transistor thermal noise, expression (A1.7, and applying the superposition
theorem, the power sum of the several noise contributions is obtained, and the PSD of the OpAmp’s
thermal noise referred to its input is given by,
( ) 2
( ),
1
8 1
3VN T OAS f kT m V Hz
gm =
(5.33)
where m is
3 9 5 7
1 1 1 1
1gm gm gm gm
mgm gm gm gm
= + + + +
(5.34)
This factor m represents the same factor of the expressions (A1.22) and (A1.23) and it represents the
noise contribution of the transistors others than the differential pair one. To make the OpAmp’s noise
dominated by the differential pair, it is necessary to make gm3, gm9, gm5 and gm7 a few times smaller
than gm1. To reduce the factor m, the transconductances of transistors M3 and M9 must be decreased
by maximizing their overdrive voltages 2and the differential pair transconductance gm1 must be
increased by minimizing its overdrive voltage, by placing it in the weak inversion region (between
40mV and 80mV).
The minimum value for the compensation capacitor of the operational amplifier (half of a fully-
differential) for a given specification can be calculated from the expression (A1.26) which is repeated
here for convenience:
( )
2 2
2 2
, , 2
2
3
i f
N T OA INT
C i
g gkTV m V
C OSR gβ +
=
(5.35)
5.2.4 Offset voltage
The offset voltage analysis of an operational amplifier is similar to the one performed for the noise,
given the fact that the offset voltage can be considered as continuous noise (with zero frequency), as
its value does not change over time.
The differential offset voltage referred to the input of the operational amplifier, measured as a standard
deviation is given by
(5.36)
2 It represents the strength of the channel and is usually given by VOD=VGS-VTH.
62
where σ(∆VTHk) represents the threshold standard deviation of the MOS transistor Mk, which can be
related to its physical dimensions
( ) [ ]1
VTTH
AV V
WLσ ∆ = (5.37)
where AVT is a technology parameter for MOS devices.
From the observation of the expression (5.36), if the transconductance of the transistor M3 is a few
times smaller than the transconductance of transistor M1, the OpAmp’s offset voltage is dominated by
the contribution of the differential pair, thus its area must be properly chosen.
5.2.5 Slew-rate
The amount of current an amplifier with a class-A output stage can supply to a load is limited by the
polarization of the output stage. In switched-capacitors circuits the load is predominantly capacitive
and this, there is a limit for the output voltage variation. This limit is called slew-rate, it comes from the
equation that relates the instantaneous values of current and voltage on a capacitor (iC=C.dVC/dT) and
can occur in the output node as well as in internal ones.
The slew-rate specification determines the minimum value for the bias current of the output stage.
Assuming a fully-differential amplifier is loaded at each single output with a capacitance CL3, the non-
differential slew-rate is given by
[ ]2
L
ISR V s
C= (5.38)
where I2 represents the bias current of the output stage of the operational amplifier. In addition, some
attention has to be paid to the slew-rate at the output of the first-stage of the amplifier (drain of
transistor M6), as there is also an equivalent capacitor due to CC.
5.2.6 Distortion
In linear circuits, the non-linear distortion effect is caused generally by the relative current variation in
transistors. To analyze the distortion in an OpAmp it is necessary to analyze the transistors that have
the highest relative bias current variation, which normally occur at the output stage.
To ensure the desired distortion level, it is necessary to design properly (i) the relative output-stage
bias current variation and (ii) the amplifier’s gain at the maximum signal frequency (GBW design).
3 Equivalent to a differential load capacitance 2CL.
63
5.2.7 Project
Usually, the project of an operational amplifier is an iterative process supported in a Spice like
simulation tool. However, this process tens to be slow and inefficient in terms of the quality of the
project when the designer does not make a critical analysis.
This section describes the project flow that allows the initial project of a programmable two-stage
operational amplifier with cascode compensation, used in the integrators of the Σ−∆ modulator.
Compensation capacitor
From expression (5.35) the minimum value for the compensation capacitor CC can be calculated to
guarantee the noise specification of the operational amplifier, assuming m=3 (to have some margin
during the design). If the capacitor value is too small (smaller than 100fF for instance) it is convenient
to use a higher value so the frequency compensation does not become too dependent of the parasitic
capacitances (badly controlled).
The tightest noise specification is for the GSM standard – 70dB – and in order to ensure that the
operational amplifier complies with this specification, the compensation capacitor value is chosen
according to this specification.
First-stage
With the obtained value for the compensation capacitor CC, it is possible to calculate the differential
pair transconductance (gm1) that satisfies the gain-bandwidth product (GBW) specification, or in
particular the circuit one (GBWβ).
From the tightest GBWβ specification, which corresponds to the DVB-H standard, the value for gm1 is
calculated. From this value it is possible to calculate the input stage bias current. Considering that
different GBWβ specifications generate different gm1 and consequently different input stage bias
current, it is possible to change the transconductance gm1 according to each mode specification. This
is done by creating a programmable bias circuit, which depending on the active mode, generates
different bias current for the input-stage.
From the consumption point of view, it is better to bias the differential pair in weak inversion region
because that is where the maximum transconductance value can be obtained for the same bias
current. From the noise and offset voltage point of view it is also beneficial to bias the differential pair
in the weak inversion region to minimize the quotient gm3/gm1, making those parameters dominated
by the differential pair. For higher frequencies sometimes it is not possible to bias the differential pair
in the weak inversion region, as the transition frequency4 (fT) is minimal.
It is also important to note that, placing an input differential pair transistor biased in the saturation with
a fixed bias current in the weak inversion region corresponds to increasing the W/L relation. For a
fixed L this corresponds to increasing the parameter W, thus increasing the input parasitic capacitance
4 Frequency at which the transistor yields unity gain.
64
of the operational amplifier. This parasitic capacitance tents do decrease the circuit feedback factor
(β), which has to be compensated with an increase in the GBW, resulting in a consumption increase.
A compromise must be achieved between maximum transconductance for a given bias current (weak
inversion) and the minimum input parasitic capacitance (strong inversion).
The cascode transistor conductance gm5 determines the real part of the complex non-dominant poles
pair. Once established their optimum location, from expression (5.27) it is possible to obtain gm5. It is
also best to bias this cascode transistor in the weak inversion region to obtain the maximum
transconductance for the same bias current, which increases its noise contribution.
The transistors functioning as current sources (M3 and M9) must be biased with the maximum possible
overdrive voltage, in order to minimize the mirroring errors. This value is only limited by the voltage
swing in each node, so that none of the involved transistors enter the triode region.
Second-stage
The bias current of the second-stage is the maximum between three values: (i) the minimum current
that satisfies the slew-rate specification (given by expression (5.38)), (ii) the minimum current that
generates enough transconductance to place the non-dominant poles at a frequency sufficiently
higher than the GBW and therefore ensure the phase margin specification (continuous circuits) or
settling time (sampled circuits) (given by expression (5.28)) and (iii) the minimum current required to
guarantee the distortion specification. Normally in continuous time circuits the current is dominated by
second or third factor, while in switched-capacitors circuits any of the factors can dominate.
To ensure the correct location of the non-dominant poles for each mode, it is possible to change the
transconductance gm11 depending on the active mode. This way, the consumption is also optimized
for each mode. This is done with a programmable bias circuit, just like the one used for the input-
stage. To maximize both the output signal swing and the maximum transconductance for the same
bias current it is best to use low overdrive voltages.
5.2.8 Common-mode feedback circuit
Being a fully-differential operational amplifier, it requires a common-mode feedback circuit that
controls the common-mode voltage of the outputs, normally half of the supply voltage. This circuit is
usually referred to as the common-mode feedback (CMFB) circuit.
There are two typical ways to design CMFB circuits: continuous-time and switched-capacitors circuits,
[Johns1997]. The former approach is frequently the limiting factor on maximizing signal swings, and if
nonlinear, may even introduce common-mode signals. The latter approach is usually only used in
switched-capacitors circuits, since in continuous-time applications it introduces clock-feedthrough
glitches.
The CMFB circuit used is a switch-capacitors implementation, Figure 5.6. The capacitors CC generate
the average of the output voltages. The DC voltage across CC is determined by capacitors CS, which
65
are switched between the desired common-mode voltage and being in parallel with CC. During phase
Φ2d, the switched capacitors CS define the proper voltage on the sense capacitors. It is necessary to
use a negative gain amplifier, as the CMFB circuit output voltage (VBNS) actuates on the NMOS current
source transistors M3 and M4 (Figure 5.4) - an increase in the ouput common-mode voltage must be
compensate with a decrease in bias voltage of the transistors M3 and M4.
Figure 5.6. Common-Mode Feedback circuit for the operational amplifier.
The common-mode feedback circuit must have sufficient GBW and ADC to ensure the proper
functioning of the OpAmp.
5.2.9 Bias Circuit
The bias circuit used for the operational amplifier is show in Figure 5.7. For proper biasing, high-swing
cascode biasing is used. Detailed information about biasing circuits, namely the high-swing cascode,
can be consulted in e.g. [Johns1997].
As referred in section 5.2.7, both input-stage and output-stage bias current depends on the active
mode. The programming of the amplifier is done by the bias current selection vector IB<1:0> that
selects more or less current to the bias circuitry (IIN), according to the selected mode, Table 5.6.. Note
that the bias voltages for the differential pair bias transistor M15 (VBPS) is the same bias voltage for the
folded-cascode PMOS current-sources transistors M9 and M10 (VBPL). The power-down transistors are
not presented in Figure 5.7, for a matter of simplicity.
Each operational amplifier used in the integrators has a similar biasing circuit. The difference is in the
specifications, and therefore, different transconductance values are generated.
66
Figure 5.7. OpAmp bias circuit.
Table 5.6. Bias current programming.
Mode IB<1:0> IIN
1 - GSM 11 0,4
2 – CDMA2000 10 0,5
3 – UMTS 01 0,75
4 – DVB-H 00 1
5.3 Internal A/D Converter
The block referred to as internal A/D converter is responsible for the internal quantification process of
the Σ−∆ modulator. The converter chosen is the flash ADC, since this topology has the highest
conversion ratio and is conceptually the simplest to implement. All digital signals are generated
simultaneously, thus its latency is very low (being limited essentially by the dynamic characteristics of
the comparators). For this work, the flash ADC block does not present problems in terms of project
effort and area occupation, given the reduced number of implemented quantification levels (12).
In this work, for simulation purposes, it was used an already designed 12-level flash ADC (it does not
limit the performance of the system). Nevertheless, this section presents the main constraints in the
design of a flash converter, show in Figure 5.8. A complete design procedure for the flash ADC can be
consulted in [Tavares2002].
From Figure 5.8, a string of resistor divides the differential reference voltage (VREF=VREF,P – VREF,N) in a
set of 12 transition voltages that define the 12 quantification levels of the converter. The input signal is
compared, in parallel, with these transition voltages, through the use of 12 identical comparators, that
generate a thermometer coded output. The comparators are implemented in a switched-capacitors
topology, using the clock phases of the Σ−∆ modulator. The circuit is fully-differential, i.e. each
67
comparator compares the differential input signal (inp-inn) with a differential voltage (lkp-lkn, where k
can be any value between 1 and 6).
Figure 5.8. Simplified schematic of the internal Flash A/D converter.
5.3.1 Resolution
The resolution of the converter is limited, mainly by the precision of the transition voltages. The non-
ideal factors that can degrade the references values are: (i) static precision, (ii) dynamic
characteristics of the resistors string and (iii) the performance of the comparators.
To prevent comparison errors, the absolute error of the differential voltage has to be lower than half
the amplitude of a LSB:
max
142
2LSBV mVε = = (5.39)
68
5.3.2 Comparator
Figure 5.9 presents a simplified electrical schematic of the comparator. The circuit is constituted by a
switched-capacitor (C1p(n)) that alternatively connects to a reference voltage and to the input signal
through a latched-comparator with a pre-amplifier employing the auto-zero technique [Moreno1996].
During clock phase Φ1d the capacitor stores a charge that at its terminal the voltage is equal to vrefp(n)
In the next clock phase Φ2d, the capacitor’s voltage is subtracted to the input signal and the result is
amplified by the pre-amplifier and then is applied to the latched-comparator that generates the
correspondent logic level at the output.
Figure 5.9. Simplified electrical schematic of the latched-comparator.
If the comparator did not have the pre-amplifier, the offset input voltage of the latched-comparator (can
easily reach 100mV) is higher than the maximum error allowed (42mV). Also, the parasitic input
capacitance of the comparator (some dozens of fF) creates a capacitive divider that attenuates
considerably the input signal amplitude, making it necessary an increase in the comparator’s
resolution specification.
The pre-amplifier before the latched-comparator using an auto-zero technique, minimizes its offset
voltage, and the offset voltage of the comparator when referred to the input of the pre-amplifier,
appears attenuated by the pre-amplifier gain. The pre-amplifier is also used to amplify the input signal.
The input differential voltage of the latched-comparator is
( ) ( ) 1
1
V
par
Cincp incn vinp vinn vrefp vrefn A
C C − = − + − +
(5.40)
Where C1 is the sampling capacitance, Cpar is the pre-amplifier input parasitic capacitance and AV is
the voltage gain of the pre-amplifier (normally between 4 and 10, although it may simply be a unity-
gain buffer).
The value chosen for C1 is about 20fF. This is a sufficiently low value, so minimum dimension switches
can be used to switch C1 without introducing high value parasitic capacitances, and allows the
implementation of a resistor divider with a sufficiently high value, so its consumption is not significant.
69
Pre-Amplifier
The project and design of the pre-amplifier does not bring any particular difficulties. It can be easily
implement with a one-stage amplifier with an input differential pair and NMOS transistors as active
load. [Johns1997].
Latched-Comparator
Figure 5.10 presents the simplified electrical schematic of the latched-comparator. The dynamic
characteristics of the comparator are very important, since the available time for the output signal to
be defined is lower than half of clock period5.
The design of the latch and of the inverters is not problematic. In specialized literature, [Baker2008],
several design options are shown. The switches can be realized with the minimum dimensions.
Figure 5.10. Simplified electrical schematic of the latched-comparator.
5.3.3 Resistors String
The design of the resistors that constitute the flash ADC resistive divider results from a compromise
between two factors: (i) the settling error of the transition voltages and (ii) the power consumption of
the voltage references generator (VREF,P and VREF,N).
To avoid comparison errors, it must be assured that at the instant the reference voltages are observed
(at the end of the clock phase Φ1d), their values are well settled (with an error), thus the RC time
constant must be properly designed.
The switched-capacitors of each of the 12 comparators are connected to the resistors divider
simultaneously. Being fully-differential, each comparator has two outputs connected to each transition
voltage. This means that in the sampling instant of the reference voltages, there are two capacitors
connected to the reference node at the same time, and so a rigorous analysis of the equivalent circuit
5 Taking into account the delays between delayed and non-delayed phases (ph1 and ph1d; ph2 and ph2d) and
the superposition times between phases (ph1 and ph2; ph1d and ph2d), the effect time interval in which each phase is active is less than half clock period.
70
is not trivial and it must be considered as a distributed circuit. From this analysis, which is not on the
scope of this thesis, the value of the total resistance (Rtotal) can be calculated.
The expressions that define the resistors value, as functions of the reference voltages and transition
voltages are
0
, ,
1
, ,
,
6
, ,
, 1, 2,3, 4,5
ktotal
REF P REF N
k kk total
REF P REF N
REF P k
total
REF P REF N
lR R
V V
l lR R k
V V
V lR R
V V
+
=
− −
= =−
− =
−
(5.41)
where lk represents the value of the transition k voltage.
5.4 DWA DAC
The output signal of the Σ−∆ modulator is obtained through the internal 12-level flash ADC (about 3,5
bit) that quantifies the output of the 3rd
integrator. This signal is then applied to an internal feedback
DAC that assures the closing of the loop of the modulator.
The DAC is implemented by a matrix of unity capacitor in each integrator. The mismatch between the
several capacitors represent distortion directly added at the output of the modulator, thus the linearity
of the internal DAC limits the resolution of the entire system.
In current technologies it is possible to obtain a mismatch between capacitors of about 0,5% to
capacitor values as low as a one hundred fF. This value corresponds to about 6,5 bit of linearity, which
is not sufficient to guarantee the worst mode SNR specification of 64dB.
The use of a DWA dynamic element matching technique improves the linearity of the DAC. As
referred in section 4.3.2, the DWA is the most adequate solution to the linearization of D/A converters
for Σ−∆ modulator.
In this work, for simulation purposes, a DWA already implemented in Verilog was used. Nevertheless,
this section presents the principles of the DWA operation.
The principle behind DWA is the assumption that the errors of the unity elements that constitute the
DAC matrix are randomly distributed. Therefore, if the unity elements are activated in a sequence
determined by the digital word to be converted, the non-linearity error depends only of the average of
the error along the matrix. This effect corresponds to a 1st order high-pass error modulation, which for
the worst mode SNR specification with an OSR of 15, represents an increase in linearity of about
52dB (8,4bit).
71
5.5 Clock Generator
Switched-capacitor circuits require the generation of two-phase non-overlapping clocks with delayed
clocks to reduce signal-dependent charge injection.
The clock generator circuit is a sequential circuit that from a clock reference signal generates several
clock signals with the same frequency, but with different characteristics.
From this circuit it is possible to obtain:
Two opposite-phase and non-overlapping clock signals (Φ1 and Φ2) that implement the
switched-capacitors structures;
Two delayed clocks (Φ1d and Φ2d) that are used to minimize the clock feedthrough
phenomenon associated with the opening of the MOS switches;
Complementary versions of some of the above signals, whenever necessary.
Figure 5.11 shows the time diagram of the input and outputs of the clock generator circuit.
Figure 5.11. Time diagram of the clock signals.
The clock phases generator circuit is no more than a SR (Set-Reset) type bistable circuit, in which the
inputs S and R are excited, respectively, by the clock reference and by the respective complement,
resulting in a D (Data) type bistable circuit. Several delay blocks are added in the respective feedback
loop, allowing the extension of the non-overlapping time (tno) of the resulting clock phases (Φ1 and Φ2).
The delay introduced by these blocks, implemented as slow inverters, should be designed to
guarantee that every switch commanded by a given phase (e.g Φ1) is completely deactivated
(transistors in the cut region) before the next phase (eg. Φ2) is activated. With this condition, it is
assured that the switched nodes are never simultaneously connected to two different voltage sources,
which would cause the circuit to work improperly.
Figure 5.12 shows the electrical schematic of the clock generator circuit implemented.
72
Figure 5.12. Electrical schematic of the clock generator circuit.
The circuit is implemented in CMOS technology, thus the power consumption of the circuit is
associated with the charge and discharge of the internal parasitic capacitances and load of the circuit.
From the design point view, the transistor dimensions must be made as small as possible, but they
must guarantee the delay, transition and non-overlapping times specified.
From the simulation point of view, it should be verified that the circuit works for every temperature,
supply voltage and technology parameters and with the equivalent switches capacitances and
respects the following parameters:
Minimum non-overlapping interval between active phases (tno);
Maximum transition time in each phase (rise time and fall time);
Minimum/maximum delay between phases for the purpose of cancelation of the clock
feedthrough.
73
Chapter 6
Results
This chapter present the most important results obtained through electrical simulation of the designed
system, in the HSpice environment.
The design of the system is validated through electrical simulation in every functioning conditions
(temperature and voltage supply) and considering the process variations specified by TSMC (MOS
transistors, resistances and capacitances). A Montecarlo6 statistic simulation with 30 iterations
7 and
Gaussian distribution functions is performed for blocks where their performance depends on a good
match between transistors.
To validate the performance of the system (SNR), only the results for the worst-case SNR mode
(Mode 1 – GSM) and worst-case signal bandwidth and OSR mode (Mode 4 – DVB-H) are presented.
Table 6.1 presents the types of electrical simulations performed to evaluate the system. Depending on
the complexity and specifications of each block, all or some simulations are performed.
Table 6.1. Types of electrical simulations performed
Code Type of Simulation Conditions Results
OP Operating point closed-loop analysis
MOS, Rpoly and Cpoly variations;
T ∈ [-40;125] ºC;
VDD ∈ [0,95;1,05] V
Monte Carlo simulation with 30 iterations
Voltages and currents of the transistors;
Saturation margin:
AC_OLOOP Open-loop frequency analysis
DC Gain;
GBW;
PM.
AC_NOISE Closed-loop noise analysis Noise Power (Thermal+Flicker)
AC_PSR Power-Supply Rejection analysis PSSR
TR_SETT Transient settling analysis MOS, Rpoly and Cpoly variations;
T ∈ [-40;125] ºC;
Vdd ∈ [0,95;1,05] V
nτ
TR_SNR SNR analysis SNR
6 The Montecarlo simulation principle is based on a random number generator that creates random distributions
of parameters (Gaussian, uniform or limited) for electrical simulation. 7 According to the HSpice manual, if the circuit functions properly for all the 30 iterations, there is a 99%
probability that it will work for, at least, 80% of the possible parameters values.
74
6.1 1st Integrator
The loop feedbacks are different in each phase and therefore, both phases of functioning must be
analyzed.
The bode diagrams of the 1st integrator for both phases of Mode 1 – GSM are shown in Figure 6.1.
Figure 6.1. Bode diagram of the 1st
integrator, Mode 1 – GSM.
The bode diagrams of the 1st integrator for both phases of Mode 2 – CDMA20000 are shown in Figure
6.2.
Figure 6.2. Bode diagram of the 1st
integrator, Mode 2 – CDMA2000.
75
The impulsive responses of the 1st integrator for Mode 1 – GSM and Mode 2 – CDMA2000 are
presented in Figure 6.3.
Figure 6.3. Impulsive response of the 1st
integrator for Mode 1 –GSM and Mode 2 – CDMA2000.
Table 6.2 summarizes the results of OP, AC_OLOOP and TR_SETT simulations for Mode 1 – GSM
and Mode 2 – CDMA2000.
Table 6.2. Results of Operating Point, AC and Settling simulations for the 1
st integrator for GSM and
CDMA2000.
Mode 1 Mode 2
Differential Amplifier GSM CDMA2000
Operating Point Min. Typ. Max. Min. Typ. Max. Units
VOS,dif Output differential Offset voltage < 24,6 < 24,3 mV
IDD Current consumption 0,568 0,704 0,894 0,788 0,972 1,190 mA
ADC DC Gain 44,7 61,6 67,5 46,5 61,9 67,7 dB
AC Analysis
GBW Open-loop Gain-bandwidth product
- Phase F1 - Phase F2
67,0
66,4
102,0
100,0
153,0
151,0
89,9
89,1
137,0
135,0
207,0
203,0
MHz
PM Phase Margin
- Phase F1 - Phase F2
62,9
63,7
64,9
65,7
70,3
71,3
62,4
63,2
64,5
65,3
70,1
71,1
º
Settling Analysis
nττττ 1st order settling time constants > 8,8 > 10 τ
76
The bode diagrams of the 1st integrator for both phases of Mode 3 – UMTS are shown in Figure 6.4
Figure 6.4. Bode diagram of the 1st
integrator, Mode 3 – UMTS.
The bode diagrams of the 1st integrator for both phases of the Mode 4 – DVB-H are shown in Figure
6.5.
Figure 6.5. Bode diagram of the 1st
integrator, Mode 4 – DVB-H.
The impulsive responses of the 1st integrator for Mode 3 – UMTS and Mode 4 – DVB-H are presented
in Figure 6.6.
Table 6.3 summarizes the results of OP, AC_OLOOP and TR_SETT simulations for Mode 3 – UMTS
and Mode 4 – DVB-H.
77
Figure 6.6. Impulsive response of the 1st
integrator for Mode 3 – UMTS and Mode 4 – DVB-H
Table 6.3. Results of Operating Point, AC and Settling simulations for the 1st
integrator for UMTS and DVB-H.
Mode 3 Mode 4
Differential Amplifier UMTS DVB-H
Operating Point Min. Typ. Max. Min. Typ. Max. Units
VOS,di Output differential Offset voltage <23,8 <23,1 mV
IDD Current consumption 1,093 1,305 1,600 1,745 2,075 2,475 mA
ADC DC Gain 48,4 61,9 67,8 51,5 61,9 67,7 dB
AC Analysis
GBW Open-loop Gain-bandwidth product
- Phase F1 - Phase F2
119,0
117,0
178,0
175,0
272,0
268,0
177,0
174,0
261,0
257,0
270,0
265,0
MHz
PM Phase Margin
- Phase F1 - Phase F2
61,9
62,8
64,1
65,0
69,7
70,8
61,0
61,9
63,5
64,4
68,9
70,2
º
Settling Analysis
nττττ 1st order settling time constants > 7,5 > 5,6 τ
Results from Table 6.2 and Table 6.3 show that the 1st integrator presents stability greater than 60º in
any clock phase and for all modes. From Figure 6.3 and Figure 6.6 it is possible to verify that the time
response of the 1st integrator is very stable and with number of time constants nτ always greater than
5,6τ.
78
Operating Point and open loop AC simulations are also performed to verify the behavior of the CMFB
circuit, namely its stability. The results for Mode 1 – GSM and for Mode 2 – CDMA2000 are
summarized in Table 6.4 and results for Mode 3 – UMTS and Mode 4 – DVB-H are summarized in
Table 6.5.
Table 6.4. Results of Operating Point and AC simulation for the CMFB circuit for GSM and CDMA2000.
Mode 1 Mode 2
Common-Mode Amplifier GSM CDMA2000
Operating Point Min. Typ. Max. Min. Typ. Max. Units
VOS,c Output differential Offset voltage <28,2 <27,9 mV
ADC DC Gain 34,8 48,1 54,6 36,3 48,6 54,9 dB
AC Analysis
GBW Open-loop Gain-bandwidth product
- Phase F1 - Phase F2
14,3
12,5
19,2
16,9
29,3
24,7
18,9
16,6
25,1
22,1
38,0
31,8
MHz
PM Phase Margin
- Phase F1 - Phase F2
79,1
81,4
81,6
82,6
83,3
84,2
78,8
81,3
81,3
82,5
82,8
83,8
º
Table 6.5. Results of Operating Point and AC simulation for the CMFB circuit for UMTS and DVB-H.
Mode 3 Mode 4
Common-Mode Amplifier UMTS DVB-H
Operating Point Min. Typ. Max. Min. Typ. Max. Units
VOS,cm Output differential Offset voltage <28,0 <29,1 mV
ADC DC Gain 37,9 48,9 55,1 39,7 48,8 55,0 dB
AC Analysis
GBW Open-loop Gain-bandwidth product
- Phase F1 - Phase F2
24,4
21,4
32,1
28,0
49,0
41,1
34,9
30,1
46,2
39,1
69,4
57,5
MHz
PM Phase Margin
- Phase F1 - Phase F2
78,4
81,2
81,0
82,3
82,3
83,5
77,9
81,1
80,5
82,1
81,5
83,0
º
AC_NOISE and AC_PSR simulations are also performed to evaluate the noise power level at the input
of the 1st integrator, and to evaluate the power supply and ground noise. The results of the AC_NOISE
and AC_PSR simulations are summarized in Table 6.6.
79
Table 6.6. Results of Noise simulation for all modes.
Mode 1 Mode 2 Mode 3 Mode 4
1st
Integrator GSM CDMA2000 UMTS DVB-H
Noise Analysis Max. Max. Max. Max. Units
Vn2 Noise Power (1/f + thermal) < 4,24 < 4,87 < 6,88 < 6,54 nV
2
SNR SNR at 50% full-scale > 65,58 > 64,98 > 63,48 >63,69 dB
PSR Analysis
PSRR Noise Rejection
- Supply noise - Ground noise
< -21
< -17
< -22
< -16
< -22
< -16
< -22
< -17
dB
6.2 ΣΣΣΣ−−−−∆∆∆∆ Modulator
The performance of the complete Σ−∆ Modulator is also verified in HSpice. In the previous section, the
1st integrator was evaluated for the 4 implemented standards (GSM, CDMA2000, UMTS and DVB-H).
In this section, the complete Σ−∆ Modulator is evaluated only for the worst case SNR mode (GSM)
and worst case signal bandwidth mode (DVB-H).
The circuit is simulated for the typical conditions – Voltage supply = 1V; Temperature = 50º (323K).
The input signal is a differential sinusoid with 50% full-scale amplitude = 0.5V and with signal
frequency of 33kHz for GSM and 1.33MHz for DVB-H.
Figure 6.7 shows the input signal and the output waveforms of the three integrators.
Figure 6.7. Input signal and output signals of all three integrators for GSM and DVB-H.
80
The output signal of the Σ−∆ Modulator is codified as a thermometer code, thus is possible to build the
equivalent waveform through the sum of the 12 output bits of the internal flash ADC. The output signal
of the Σ−∆ Modulator for Mode 1 – GSM and Mode 4 – DVB-H are presented in Figure 6.8.
Figure 6.8. Output of the ΣΣΣΣ−−−−∆∆∆∆ Modulator for Mode 1 – GSM and Mode 4 – DVB-H.
To evaluate the SNR performance of the Σ−∆ Modulator it is necessary to apply an FFT to the output
signals of Figure 6.8. The result is shown in Figure 6.9.
Figure 6.9. Frequency spectrum of the output signal of the ΣΣΣΣ−−−−∆∆∆∆ Modulator.
The simulation takes about 100 signal periods, so a good in-band frequency resolution can be
achieved, in order to obtain a reasonable precision for the quantification noise in-band integration. The
approximate SNR obtained is 70,1dB for Mode 1 – GSM and 58,7dB for Mode 4 – DVB-H. This
81
simulation considers all the devices as non-noisy, thus this result only proves that the dynamic
performance of the Σ−∆ Modulator does not limit the system resolution.
Taking into account that the first integrator of the Σ−∆ Modulator achieves an SNR of 65,58 for GSM
and an SNR of 63,69 for DVB-H, Table 6.6, this set of results allows the validation of the project an
predicts an SNR of 64dB for GSM and an SNR of 57dB for DVB-H.
Note that the system was not implemented in silicon, and therefore the results are better than after
fabrication.
82
Chapter 7
Conclusions
7.1 Results Analysis
The main objective of this thesis was the design of a programmable bandwidth, low-voltage and low-
power Σ−∆ Modulator. This goal was accomplished through a system modeling and a careful design
methodology.
First, in Chapter 4, behavioral models were created for the several Σ−∆ Modulator blocks, which
included the most important non-idealities. A proper modeling of the system, speeds-up the design
process by predicting the “real” performance of the Σ−∆ Modulator, and here, the choice of the right
architecture plays a very important role.
Afterwards, in Chapter 5, the most important block of the Σ−∆ Modulator was designed: the first
integrator in the forward loop.
The low-voltage supply (1V) limited the maximum swing of the internal nodes voltages, making it hard
to place every transistor in the desired functioning region. The necessity of supporting several wireless
standards created several difficulties in terms of the design, namely the need for a programmable
operational amplifier. Here a compromise between power and speed was reached, in order to comply
with the system specifications.
The 3rd
order, 12 levels architecture supports the standards GSM, CDMA2000, UMTS and DVB-H.
The Sigma-Delta Modulator designed in a 1V supply technology, achieves a peak SNR of 64dB for
GSM (100kHz signal band) and 57dB for DVB-H (4MHz signal band) consuming between 2.6 and
6mA.
7.2 Future Work
Several optimizations can be realized over this project:
In a system modeling point of view, a behavioral model for the DWA DAC and Flash
ADC could be included, in order to make the expected performance closer to the real
one.
Concerning the Σ−∆ Modulator, namely from the architecture point of view, a
feedforward path from the input to the output of the first integrator could be added
[Yao2006]. This technique reduces the integrator’s gains and consequently the
83
voltage swings at the outputs of the integrators. This way, single-stage operational
amplifiers could be used, thus reducing power consumption and silicon area.
Furthermore, it could be beneficial to use offset voltage and flicker noise
compensation techniques in the first integrator.
In addition, other wireless standards could be added to the system, as the designed topology trades
performance for signal bandwidth, without a reasonable increase in area, serving as a good platform.
84
Appendix1
Noise
This appendix presents a detailed analysis on the noise of switched-capacitor integrators.
In electronic circuits there are two main types of noise: inherent noise and interference noise
[Johns1997]:
Interference Noise is the result of unwanted interaction between the circuit and the outside
world, e.g. power supply noise on ground wires (such as 50-Hz hum) or electromagnetic
interference between wires. It can be significantly reduced by careful circuit wiring or layout.
Inherent Noise refers to random noise signals due to fundamental properties of the circuits. It
can never be eliminated and is moderately affected by circuit wiring or layout. However it can
be significantly reduced through proper circuit design, such as changing the circuit
architecture or increasing the power consumption by changing components dimensions.
A1.1 CMOS inherent noise
The main types of inherent noise in CMOS integrated circuits are the thermal and the flicker noise
(also called 1/f noise).
A1.1.1 Thermal noise
This type of noise is due to the random motion of carriers in any conductor due to thermal excitation
(above absolute zero temperature). This is an equilibrium process independent of the current flow and
proportional to the absolute temperature. Thermal noise places fundamental limits on the dynamic
range achievable in electronic circuits.
Its spectral distribution is uniform and therefore it is also known as white noise. The spectral power
density of thermal noise, modeled by a noise voltage source SVN(T) in series with a conductor with
resistance R (in ohms), at the temperature T (in Kelvin) is given by,
(A1.1)
where k is the Boltzmann constant (1,38x10-23
J/K).
85
A1.1.2 1/f noise
This type of noise is present in any active CMOS device and occurs whenever a static current is
flowing. Flicker noise arises normally due to traps in the semiconductor, where carriers are held for
some time period and then released. Its name results from the fact that this effect is proportional to
1/fα, where α is between 0.8 and 1.3 [Johns1997].
The spectral power density of flicker noise, modeled by a noise voltage source SVN(F) in series,
generated in a generic active device is given by,
( )2F
VN T
KS V Hz
fα = (A1.2)
where KF is a device and technology constant.
A1.2 Noisy devices
The main noise sources in Σ−∆ modulator circuits are resistors and MOS transistors. Capacitors do
not generate noise for themselves.
A1.2.1 Resistors
All resistors or resistive conductors exhibit thermal noise. This noise can be represented by a series
noise voltage source and ideal R (i.e. Thévenin equivalent circuit) or by a shunt current noise source
and ideal R (i.e. Norton equivalent circuit), as shown in Figure A1.1.
Figure A1.1. Resistor noise model (R* stands for noiseless R).
The mean squares thermal noise voltage and current can be obtained through the integration of
((A1.1) in a band B, and are given respectively by,
( )
2 2
,4
N T RV kTRB V = (A1.3)
86
( )2 2
,
14
N T RI kT A
R = Β (A1.4)
To reduce the thermal noise due to resistors, one must either lower the temperature or use lower
resistance values.
A1.2.2 MOS transistor
The dominant noise sources in MOS transistors are thermal and flicker noise.
The flicker noise can be modeled as a voltage noise source in series with the gate, with a PSD given
by [Tavares2002],
( ) ( ) 2
, 2
af
f ds
VN F M ef
OX eff
K IS f V Hz
C L f =
(A1.5)
where Kf is a technology constant dependent on device characteristics, Ids is the drain-source current
(in A), af is the flicker noise exponent, COX and Leff represent the transistor’s gate capacitance per unit
area (F/m2) and the effective channel length respectively (m), f is the frequency (in Hz) and ef is the
flicker frequency exponent. It is important to note that the 1/f noise is inversely proportional to the
square of the effective channel length, Leff. In other words, larger devices have less flicker noise.
Flicker noise is extremely important in MOS circuits because it typically dominates at low frequencies.
Note also that p-channel transistors have less noise than n-channel transistors, since their carriers
(holes) are less likely to be trapped.
The thermal noise can be modeled as a noise current source between the drain and source terminal in
parallel with the transistor’s transconductance and with a PSD given by,
( ) ( ) 2
,
8
3mIN T M
S f kTg A Hz =
(A1.6)
or equivalently, modeled as a voltage noise source at the gate terminal, with PSD given by,
(A1.7)
where gm is the transistor’s transconductance (in S). This expression is valid for VDS=VGS-VTH and is
obtained through the calculus of the equivalent channel resistance for a saturated transistor, where
the channel cannot be considered homogeneous [Johns1997].
Figure A1.2 present the noise model for a MOS transistor.
87
Figure A1.2. MOS transistor noise model (M* stands for noiseless M).
The mean square voltage and current sources represented in Figure A1.2 are given by
( )2 2
, 2
af
f ds
N F M ef
OX effB
K IV df V
C L f = ∫
(A1.8)
( )2 2
,
8
3mN T M
B
I kTg df A = ∫
(A1.9)
( )2
,
8 1
3N T M
mB
V kT df Vg
= ∫
(A1.10)
where B stands for the noise integration band. Note that this simplified model assumes the gate
current is zero. This assumption is valid at low and moderate frequencies, but at higher frequencies an
appreciable current would flow through the gate-source capacitance, Cgs.
A1.3 Basic blocks
As already referred in this appendix, a capacitor does not generate noise for itself. However a
switched-capacitor samples and retains the noise associated to the MOS switch’s resistor.
A1.3.1 Switched-Capacitor
According to [Johns1997] the thermal noise power stored in a capacitor C, switched at frequency fs, at
temperature T, as shown in Figure A1.3, is independent of the conduction resistance of the switch, is
inversely proportional to the value of capacity and is given by equation (A1.11.
( )2 2
,2
N T SC
kTV V
C =
(A1.11)
88
Figure A1.3. Switched-capacitor equivalent noise model
where the factor 2 is due to the uncorrelated dual sampling for clock period (1/fs). Note that the noise
is generated by the resistor but the total power only depends of the value of the capacitor.
Furthermore, this is a sampled system and therefore the noise is considered to be uniformly
distributed in a band [0 to fs/2], thus the equivalent noise voltage source power PSD is given by,
( ) ( ) 2
,
4VN T SC
s
kTS f V Hz
f C =
(A1.12)
From ((A1.12) it is noticeable that this value is equal to the PSD produced by a resistor of value
1/(fsC), at temperature T. Note that when a capacitor is switched at frequency fs, it behaves as a
resistor with value 1/(fsC) for signals with frequency significantly lower than the sampling frequency fs.
In switched-capacitors there is no flicker noise given the fact it is associated with a continuous current
flux which does not happen in a switched-capacitor.
A1.3.2 Operational Amplifier
Generally speaking, the noise of an operational amplifier with a MOS differential pair at the input stage
is dominated by the differential pair, as the following stages’ noise when input referred, are attenuated
by the gain of the preceding stages. Therefore, the noise of an operational amplifier can be expressed
as the noise of a MOS transistor multiplied by a factor m, which counts the contribution of the stages
beyond the input one.
The equivalent noise model of an operational amplifier (half of a fully-differential OpAmp) is shown in
Figure A1.4 and consists of two noise voltage sources in series with the input of the amplifier.
Figure A1.4. Equivalent noise model of the operational amplifier.
89
The power spectral densities of the flicker SVN(F),AO and thermal SVN(T),AO noise voltage sources
generated by an operational amplifier (half of a fully-differential OpAmp) with an input CMOS
differential are given by
( ) ( ) 2
, 2
af
f ds
VN F AO ef
OX eff
K IS f m V Hz
C L f =
(A1.13)
( ) ( ) 2
,
8 1
3VN T OA
m
S f kT m V Hzg
=
(A1.14)
The factor m equal to 1 corresponds to the best situation, where only the differential pair contributes
with noise. With proper design, the factor m can be situated between 1 and 2.
In order to determine the total noise power referred to the OpAmp’s input it is necessary to integrate
equations ((A1.13) and ((A1.14) along the circuit equivalent noise band.
A properly compensated amplifier, when in a negative feedback, presents a -3dB cut-frequency given
by,
[ ], 3 , 3
2
mC dB C dB
C
gf GBW f Hz
Cβ β
π− −= ⇔ =
(A1.15)
where β represents the feedback factor, GBW is the product gain-bandwidth or unit-gain frequency of
the OpAmp, gm is the transconductance of one transistor of the differential pair and CC is the
compensation capacitor.
From [Johns1997], the equivalent noise band BN of a system with a first-order low-pass characteristic
is given by,
[ ], 3
2N C dBB f Hz
π−=
(A1.16)
Where fC,-3dB is the -3dB cut-frequency of the system.
Replacing equation ((A1.15) in equation ((A1.16), the equivalent noise bandwidth of an OpAmp with a
dominant-pole is given by
(A1.17)
Therefore, the mean square voltage of the flicker and thermal noise referred to the input of the OpAmp
are given respectively by
90
( )2 2
, 2 4
af
f ds m
N F AO ef
OX eff C
K I gV m V
C L f C
β =
(A1.18)
( )2 2
,
2
3N T OA
C
kTV m V
C
β =
(A1.19)
It is important to note that if the operational amplifier’s noise is dominated by the input differential pair
(m close to 1), then the thermal noise depends only on the values of the compensation capacitor and
of the feedback factor.
A1.4 Noise in Switched-Capacitor Integrators
In a switched-capacitor integrator there are two main noise sources: the operational amplifier and the
switched-capacitor network.
The noise analysis for the operational amplifier is only done for half of a fully-differential topology,
according to the Bisection Theorem. In a fully-differential topology, the noise power is two times
superior (the number of noise sources doubles and are not correlated) and the signal power is four
times superior to the single output equivalent circuit. This results in a 3dB gain in SNR.
Figure A1.5 shows the equivalent noise model of a switched-capacitor integrator with half of a fully-
differential OpAmp, equivalent noise models for the switched-capacitors and the equivalent noise
voltage source of the operational amplifier. CO represents the integration capacitor while CAi
represents the capacitors that sample the input during phase Φ1 while CAj represents the capacitors
that sample the input during phase Φ2. The phases Φ1 and Φ2 are complementary.
Figure A1.5. Equivalent noise model of a switched-capacitor integrator.
91
In most Σ−∆ modulators, there are typically two sampling capacitors: one samples the input signal
while the other, activated by the internal DAC, samples the reference voltage. Sometimes a double-
sample technique is used and another switched-capacitor branch is used.
As already referred in this section, the several noise contributions from the switched-capacitors are not
correlated and therefore the total noise power is the sum of all the noise power contributions. So,
through the analysis of the charge distribution, it can be demonstrated that the power spectral density
of the switched-capacitors thermal noise stored in the integration capacitor CO is given by
( ) ( ) 1 1 2
, , 2
4
M P
Ai Aj
i j
VN T SC TOT
s O
C CkT
S f V Hzf C C
= =
+
=
∑ ∑
(A1.20)
where M represents the number of sampling capacitor branches during phase Φ1 and P represents the
number of sampling capacitor branches during phase Φ2.
Σ−∆ modulators employ the oversampling technique. Considering an oversampling ratio OSR and
integrating equation ((A1.20) in the band of interest B=fs/(2OSR), the thermal noise power stored in
the integration capacitor CO due to the switched-capacitors is given by,
( )1 12 2
, , 2
2
M P
Ai Aj
i j
N T SC TOT
O
C CkT
V VOSR C
= =
+
=
∑ ∑
(A1.21)
The flicker noise of the OpAmp is not considered in this analysis as it does not present a limitation to
the system performance. The thermal noise of the OpAmp is sampled and transferred to the
integration capacitor with a gain given by the ratio between the sampling capacitors and the
integration one. As a consequence of being sampled at frequency fs, all the noise power expressed in
equation ((A1.19) is folded into the band [0:fs/2]. Just like for the switched-capacitors noise, the
thermal noise power of the OpAmp in the band of interest (fB=fs/(2OSR)) appears divided by a factor
OSR. Therefore, the thermal noise power of the operational amplifier, inside the band of interest,
stored in the integration capacitor is given by
(A1.22)
It is important to note that all the capacitors CAi (or CAj) sample the OpAmp’s noise at the same time
instant and as a consequence their noise contributions are summed in voltage. However, the noise
sampling in capacitors CAi and CAj is not correlated, as it is realized in different time instants, thus
being summed in power.
92
The total thermal noise power stored in the integration capacitor in a switched-capacitor integrator is
given by
( )
22
2 2
, 21 1 1 1
2
3
M P M P
Ai Aj Ai AjN T INT
i j i jO C
kT mV C C C C V
C OSR C
β
= = = =
= + + + ∑ ∑ ∑ ∑
(A1.23)
where k is the Boltzmann constant, T represents the absolute temperature (in K), OSR is the
oversampling ratio, CO is the integration capacitor, CAi represents one or more capacitors that sample
the input signal in one clock phase, CAj represents one or more capacitors that sample the input signal
in the complementary clock phase, m is a factor representing the contribution of the OpAmp’s noise
normalized to the differential pair transistor noise, β is the feedback factor of the circuit and CC is the
compensation capacitor.
Figure A1.6 shows the simplified schematic of a typical switched-capacitors integrator.
Figure A1.6. Typical switched-capacitors integrator.
Considering the typical integrator of Figure A1.6, expression (A1.23) becomes
( ) ( )2 2 2 2
, 2
2
3i f i fN T INT
O C
kT mV C C C C V
C OSR C
β = + + +
(A1.24)
Defining the signal gain (gi) and the DAC feedback gain (gf),
,
fii f
O O
CCg g
C C
= =
(A1.25)
It is possible to write expression ((A1.24) as
( ) ( ) ( )2 2 2 2
,
2 2
3i f i fN T INT
O C
kT kTV g g m g g V
C OSR C OSRβ = + + + (A1.26)
93
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