MOBILE CONTROLLED SMART PLC

Apu Sarmah1, Akshit Gairola2, RishabhKhurana3, Rajat mehta4

1Department of Electronics Engineering Bapurao Deshmukh College of Engineering

Wardha (Maharashtra , India) apusarmah2508@yahoo.co.in

2ABB Ltd, Faridabad , New Delhi akshit.gairola@in.abb.com

3, 4 Department of Electronics and communication Engineering Maharaja agrasen institute of technology(Indraprastha university)

Delhi, India 3rishabhkhuranaece@gmail.com , 4rajatmehta19@gmail.com

Abstract. PLC’s are the control hubs for a wide variety of automated systems and processes. Advanced control features, network connectivity and device interoperability are all capabilities increasingly demanded in a modern industrial application. To get in-depth knowledge of any system requires thorough studies of the system up to the designing level; this paper provides better vision for designing aspects of any basic PLC for the amateur(s) or experts already working with the system. This paper emphasizes on various aspects like designing issues related to PLC, designing algorithms and implementation of DTMF connectivity. The enhancement in approachability in PLC systems can be achieved by implementing the designed DTMF module into PLC, by virtue of which accessibility of the respective system can be achieved from any location of the world. The integral feature of any smart system, that is, password protection has also been framed in the designed algorithm. The performance is illustrated on a field test for fan control application.

Keywords- PLC, DTMF, CCITT, ISP, RS 485, Siemens S7-400 and WinCC.

1.

Introduction PROGRAMMABLE

LOGIC

CONTROLLER

are the control hubs for a wide variety of automated

systems and processes. Advanced control features, network connectivity and device Interoperability are all capabilities increasingly demanded in a modern industrial application. This paper gives a better understanding of the most basic fundamental concepts like PCM (Pulse Code Modulation), DTMF (Dual Tone Multiple Frequency) which assuage the complexities related to basic study of PLC for an amateur. The practical implementation of PLC has been done by using controller family P89C51RD2 having clock pulse of 11.92 MHz which decides the speed of the system in the form of 12 cycles and is found to be apt for getting results closer to expected results. By implying this idea a conclusion can be drawn that the same designed PLC can work much more efficiently when used with high speed controller families. Apart from this to augment accessibility of the designed PLC, DTMF module has also been implemented on the designed PLC.

Hardware implementation is not an autonomous process and requires drivers that drive a particular hardware. Designed PLC has been tested on a practical industrial task and the results obtained are closer to expected results. The DTMF module is also incorporated to a hi-tech industrial PLC series of Siemens i.e. S7-400 to obtain optimum accessibility and the respective results are monitored through the SCADA (Supervisory Control and Data Acquisition) system of Siemens i.e. WinCC (Windows Control Center) [8].

2.

Block Diagram The following block diagram represents the general diagram of any PLC system which mainly consist of one main

module i.e. CPU and further sub-modules like DI (Digital input), DO (Digital Output) by which the CPU .

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2011 International Conference on Circuits, System and Simulation IPCSIT vol.7 (2011) © (2011) IACSIT Press, Singapore

Fig1.Block diagram

collect the informative data for the compilation of user defines code to deal with the practical world I/O’s (Inputs/Outputs). The designed algorithm for the CPU uses the current status of the DI as the input for the processing and executes the user defined code and exchanges the executed data with DO using RS 485 Protocol. Apart from this system comprises of a DTMF mobile module (MM) by virtue of which user can directly provide commands needed by CPU to execute as per UDC (User Defined Code) by using mobile network.

3. Hardware Module

3.1. CPU For making any system potent, its brain i.e. CPU should be in capable of making decisions in appropriate

way, of-course good programmable skills is also one of the basic necessities of any system. For the same In-System Programming (ISP) technique has been used, it is a process whereby a blank device mounted on a circuit board can be programmed with the end-user code without the need of removing the device from the circuit board. Also, a previously programmed device can be erased and reprogrammed without removal from the circuit board [9]. CPU system uses the RS (Recommended Standards) 232 I/O interfacing standard (maximum length 50 feet at 19.2 Kbps and minimum length 19.2 Kbps for 50 feet) for programming the controller serially [13]. The designed CPU uses three 8 bit registers for data handling. Single network can be of 30 nodes maximum, Single node handles 24 I/O’s, total I/O’s handling capability of network is 720 (without using repeaters).

Fig.2. Complete interface of the designed PLC

(a)DI Module (b)CPU (c)DO Module

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3.2. DI DI is responsible for keeping check on PFS (Processed Field Status). Any change in PFS is sensed by DI

meticulously and in response a signal is sent to CPU by DI using RS 485 protocol via the same network that is shared by all the modules. In CPU, this signal gets compared to UDC (User Defined Code) and is processed accordingly to provide output. Algorithm design is a challenging intellectual activity that provides a rich source of observation and a test domain for a theory of problem solving behavior [15]. In general electric utility practice, protection and automation (control) are typically two separate disciplines. Normally, each discipline uses its own, separate devices for protection and automation [10]. Here, it is implemented within designed algorithm. The cut off point of any process is defined within DI, whenever cut off point approaches, designed algorithm bypass the USD and an abortion command is generated for all the DO modules to terminate the whole process via the same RS 485 network which is shared by all modules. The vital advantage of this technique is to avoid the time consumption required by CPU to respond for any change in PFS which depends on the

Fig.3. Protection and Automation Separation

Machine cycle of the CPU. Any small delay after reaching cut off point can result in malfunctioning of the process under going as well as the whole system.

3.3. DO The compiled results as per PFS and UDC are reflected on DO module where the actual field peripherals

whose operability are expected as per PFS, are connected. This particular respective module deals with the real world peripherals which have to be driven as per requirement of the process.

3.4. DTMF

The signalling service in telecommunications uses a frequency selection known as dual tone multi

frequency (DTMF) dialling, which is standardised by the CCIlT [1]. It is perhaps the most widely known method of Multi Frequency Shift Keying (MFSK) data transmission technique. The DTMF standards define the overlaying of two pure sinusoidal waves by additive combination.

TABLE 1 KEYPAD AND CORRESPONDING DTMF’S

Hz

1209

1336

1477

697 1 2 3

770

4 5

6

852

7

8

9

941

*

0

#

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x(t) = A cos (ϖ1t) +B cos (ϖht+ φ) (1) Where ϖ

l and ϖ

h are the low and high frequencies of the sine waves being used, A and B are the amplitude of

the signals and φ is the initial phase shifts [7]. In the DTMF signalling system, the combination of a high and a low-band frequency represents a specific digit or character, as is shown in Table 1. All DTMF frequencies have been carefully chosen to avoid the problems associated with harmonics and frequency distortion [6].

The MT8870, DTMF transceiver employs a CPU interface that allows precise control of transmitter and receiver functions. The receiver is a dual tone multi frequency module which receives a particular frequency and converts it into the corresponding 4-bit binary digit which is represented by the HIGH and LOW voltage. It consists of a bandsplit filter, which separates the high and low group tones, followed by a digital counter which verifies the frequency and duration of the received tones before passing the corresponding code to the output bus. Both these sections are incorporated in the form of an integrated circuit (IC) MT8870 [4]. The separation of the low-group and high group tones is achieved by applying the DTMF signal to the inputs of the sixth-order switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group frequencies.

Instructions are directly provided to CPU by the decoded respective codes as per DTMF table, by using that CPU accompanies PFS to perform the respective predefined jobs assigned by UDC. The biggest advantage of this technique is that the accessibility of the system can be achieved by any location of the world.

High and proficient production is one of the highest priorities in today’s industry. For the same it is mandatory to make today’s system much more capable of making decision power by their own even at the

higher rate of production. Determining the quality of the DTMF decoder can be accomplished by running a set of rigorous tests according to the typical specifications for a DTMF signal decoder such as those given in Table 2 [l, 11]. Further to make system more proficient to use the DTMF signal more efficiently for processing, neural networks and DSP processor for DTMF signals i.e. TMS320C30 [5] can be used. Multichannel DTMF decoding is performed by time multiplexing the channels in a digital signal processor (DSP) and a lowering of decoding time would mean that a larger number of DTMF channels can be decoded simultaneously [19]. The overall performance of the proposed DTMF decoder, as compared with the CCITT recommendations, is shown in Table 2 [3].

The above statistics have highlighted the fact that the neural DTMF decoder implemented on the TMS 320C30 using ANN (Artificial Neural Network) has a processing time equal to 27.00ms, which is lower than that recommended by the CCITT. The circuit designed above is a single ended input configuration, which may not work if the grounding is not done properly [17].

TABLE 2 COMPARISON OF CCITT STANDARDS AND NEURAL DECODER

PERFORMANCE

CCITT ANN

S/N >24 dB ≥14dB Twist <4 dB ≤4.6dB

Frequency distortion <1.5% ≤1.8% Dynamic Range >25 dBm 31 dBm

Silence time interval >45 ms >18.75 ms Required signal time duration 45ms<TS<55ms 18.75ms Processing time interval <100ms 27.00ms

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4. Software Module

4.1. Network One of the major concerns of designing of industrial data com systems is the most cost effective

implementation for multi dropped, medium speed and serial data communication. Apart from it, design trade off to obtain reliable data rates in relation to distance is another concern

in industrial applications. The various serial data com protocols range from RS 232 to gigabit Ethernet, and beyond. Though each

protocol suits a particular application so in all cases consideration of cost and performance of the physical layer is mandatory issue. RS 232 is a standard that originated as a communications guide for modems, printers and other PC peripherals. It provided a single ended channel with baud rates to 20 kbps, later enhanced to 1 Mbps. RS 232 systems are point to point and not multi droppable [13].

When a network needs to transfer small blocks of information over long distances, RS 485 is often the interface of choice [12]. It is a bidirectional, half duplex standard featuring multiple ‘bussed’ drivers and receivers, in which each driver can relinquish the bus. It has a higher receiver input impedance and large common mode range (-7v to +12v). The driver output voltage is ±1.5v minimum, ±5v maximum. The drive capacity is 32 unit loads, i.e. 32 12kΩ receivers in parallel. Any number of receivers can be connected to the bus, provide that combined (parallel) load presented to driver does not exceed 32 unit loads (375Ω). The main reason why RS 485 can extend so far is their use of balanced, or differential, signals.

4.2. RS 485 Conversion An RS-485 network can have up to 32 unit loads, with one unit load equivalent to an input impedance of

12k. By using high impedance receivers, one can have as many as 256 nodes [13].An RS-485 receiver must see a voltage difference of just 200 mV between A and B. If A is at least 200 mV greater than B, the receiver’s output is logic high. If B is at least 200 mV greater than A, the output is a logic low. For differences less than 200 mV, the output is undefined [5, 14]. Several vendors offer RS-485 transceivers with various combinations of features. Also, there are options for methods of terminating and biasing the line and controlling the driver enable inputs. Here, SN75176B differential bus transceiver is used for the conversion. It is designed for balanced transmission lines and meets ANSI Standards TIA/EIA-422-B and TIA/EIA-485-A and ITU Recommendations V.11 and X.27 [5]. Working of this transceiver can basically categorized into three modes

• Master Mode • Slave Mode

TABLE 3 COMPARISON OF RS 232 AND RS 485 PROTOCOL

Parameters RS 232 RS 485

Cabling Single ended Multi-ended Number of

Devices 1 Transmitter

1 Receiver 32 Transmitter

32 Receiver

Communication Mode

Full duplex Full duplex Half duplex

Max. Distance 50 feet at 19.2 Kbps 4000 feet at 100 Kbps

Min. Distance 19.2 Kbps for 50 feet 10 MBPS for 50 feet Signalling Unbalanced Balanced

Mark (data 1) -5 V min. -15 V max.

1.5 V min. (B>A) 5 V max. (B>A)

Space (data 0) 5 V min. 15 V max.

1.5 V min. (A>B) 5 V max. (A>B)

Input Level Min.

+/- 3 V .2V différence

Output Current 500 mA 250 mA

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• Master/Slave (Dual) Mode In master mode transceiver acts as a driver which only transmits the data after its conversion. It does not

accept any of data coming from network. In slave mode there is option of only receiving the data on a network whereas in dual mode the communication technique is half duplex [18].

In dual mode CPU acts as a transceiver. So while designing, the main point of consideration is that the same data will be received by CPU and it will also act as one of the 32 nodes (maximum number allowed in RS 485 protocol without repeaters). Since the driver differential outputs and the receiver differential inputs are connected internally to form differential input/output (I/O) bus ports that are designed to offer minimum loading to the bus when the driver is disabled or VCC = 0 [4]. Thus first two modes are advisable to use as user needs to consider the problem of the data handling in third mode while designing algorithm for the system.

5. Field Test The practical implementation of the designed PLC has been under taken on FCU (Fan Control Unit) in an

industrial environment and can be considered as field test. FCU is an integrated part in working of industrial units like reactors. The automation of FCU thus becomes mandatory to regulate the temperature conditions inside a reactor to avoid any devastating consequences. The required results have been obtained by implementing the designed PLC into FCU.

FCU includes the following tasks. I. When start input S0 is given then following should happen • Fan 1 and Fan 2 should come ON. • Mains contactor (K1) should CLOSE. • System on lamp (L1) should come ON. II. When Fan 1 or Fan 2 fails, the stand by fan FAN 3 should come ON. III. When two fans out of provided three fans fail then the following should happen • Mains contactor (K1) should drop.

Fig.4. Fan Control Unit

The results obtained by using the designed PLC in above field test are very close to the expected results. For the simulation of the task KIEL µVision3 is used. The Kiel µVision3 is a Windows-based software development platform that combines a robust editor, project manager, and all tools including the C compiler, macro assembler, linker/locator, HEX file generator and logic analyzer. Thus, the response time of the Task I can be depicted from simulation of designed algorithm for field test. In the designed algorithm each peripheral has been allotted a specific port shown in Fig. 5. Here Port 0 (out of four 8 bits ports) of DO is taken as an output port to handle the peripherals which will act as active HIGH.

Fig.5. Port Allocation

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Fig. 6. Simulated results of Task I

Now from the fig. 6 the response time can be observed. The Task I, start input S0 commences at

0.015429ms which is shown by logic 1 of P0.3 and the system takes 0.020857ms to complete the Task I. So, the response time of the designed algorithm for Task I is 0.005428ms which of course varies according to the designing pattern of algorithm. This response time also include the negligible time taken during data transfer from DI to CPU and after compilation from CPU to DO respectively from the shared data path. The data transfer rate in this case is 9600 kb/s. However this data transfer can come into consideration according to the variation in data transfer rate of the system and the increment in distance between data transferring units i.e. hardware modules.

Thus it can be depicted that by using P89C51RD2 whose operating frequency is 11.0592 MHz the field test having given specifications can be satisfied. For the CPU to execute an instruction takes certain numbers of clock cycles known as machine cycle (MC). In the 8051 family, the length of the machine cycle depends upon the frequency of the crystal oscillator connected to the system. In 8051, one machine cycle lasts for 12 oscillator periods. Therefore, to calculate the machine cycle we take 1/12 of the crystal frequency then take its inverse [16].

The following shows machine cycle for P89C51RD2 at different crystal frequency • 11.0592/12=921.6 kHz MC = 1\ 921.6 kHz = 1.085 µs. (2) • 16 MHz/ 12 = 1.333 MHz MC = 1/1.333 MHz = 0.75 µs (3) • 20 MHZ/12 = 1.66 MHz MC = 1/1.66 MHz = 0.60 µs (4)

From the above equations three different MC’s that varies as per crystal frequency of the crystal oscillator are shown which can be chosen as per requirement of the process. In fan control application PLC with MC 1.0852 µs is tested and results are found to be close to the expectation. The frequency of the crystal connected to the 8051 family can vary from 4 MHz to 30 MHz, depending on the chip rating and manufactures. For the same requirement of the data handling at higher data rates, choice of the controller family can also be considered as one of the point of designing issue.

6. Industrial Validation of DTMF Module The advantage of designed DTMF module lies in the fact that it can be implemented both in the designed

PLC as well as in several industrial PLC systems available. The validation of such DTMF module has been verified on a SIEMENS S7-400 PLC which is the most proficient PLC currently in use on industrial level in SIEMENS. S7-400 PLC is used in more complex applications that support a greater number of I/O points. Choosing S7-400 depends on the complexity of the task and possible future expansion. S7-400 having CPU 412-2DP has been used for the above mentioned validation of DTMF module having inbuilt DI/O module. The description of CPU 412-2DP can be illustrated as-Work memory 128kb code and 128kb of data;

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Fig.7. Validation setup for DTMF module

0.1ms/1000 instructions; 4kb DI/O; send and receive capability for direct data exchange; constant bus cycle time and clock editing; routing; multi-computing capable [8]. The 4-bit output of DTMF module is sensed by DI which is processed further in CPU according to designed algorithm. The algorithm is basically designed for generation of different frequencies for four different outputs in a DTMF module as shown in Table 4. The frequencies pertaining to different DTMF outputs are generated on pressing different digits on a keypad of mobile. The validation of generated frequencies has been validated by using WinCC which is a SCADA system of SIEMENS. The frequency response of the respective response is as per sequence shown in Table 4.

Fig.8. Validation of frequencies generated

(a)

2.5 Hz (b)

2 Hz

(c)

1.25 Hz (d)

1 Hz

The decreasing order of the frequency can be observed in the obtained pattern by using WinCC.

TABLE 4 FREQUENCY PERTAINING TO DTMF OUTPUT

Digit DTMF O/P Frequency Generated

1 0001 2.5 Hz

2 0010 2 Hz

3 0011 1.25 Hz

4 0100 1 Hz

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7. References [1] CCITT: ‘Yellow book‘, VI (vr. l), recommendation Q.23 (ITV)

[2] CHETTI,G.: ‘An oversampling-based DTMF generator’, IEEE Trans. Commun., 1991, COM-39, (8), pp. 1189-1191

[3] PDaponte, D.Grimaldi and L.Michaeli: “Neural network and DSP based decoder for DTMF”. Proceeding of IEEE ProcSci. Meas. Technol., Vol. 147, No. I, January 2000, pp. 34-40.

[4] Datasheets: MT8870, Zarlink Semiconductor, 89C51RD2, NXP (Phillips), SN75176B, Texas Instruments, 74AC14, Fairchild.

[5] ‘TMS320C3X user’s guide’ (Texas Instruments, 1994)

[6] REYES, A.H., SANCHEZ-SINENCIO, E., and DUQUE CARRILLO, J.F.: ‘A wireless volume control receiver for hearing aids’, IEEE Trans. Circuits Syst. 11, Analog Digit. Signal Process., 1995,42.

[7] Tho Nguyen, Linda G. Bushnell, “Feasibility Study of DTMF Communications for Robots”, UWEE Technical Report Number UWEETR-2004-0013, April 6, 2004

[8] Siemens manual P1.4 for WinCC V6.2 and S7-400.

[9] Navneet Tohan, Swati Mishra, Pankaj Bande and Rabinder Henry. “Mobile Controlled Smart Device for Multiple Device Regulation”, Proceeding of RAMPT09, Vol. 2, February 2009.

[10] Csper labuschagne, Izak van der merwe, “Programmability of Numerical Relays: A Busbar protection relay serves as a Traditional RTU”, Proceeding of SEL.

[11] OLEARLY, P., PAURITSCH, M., MALOBERTI, F., and RASCHETTI, G.: ‘An oversampling-based DTMF generator’, IEEE Trans. Commun., 1991, COM-39, (8), pp. 1189-1191.

[12] Jan Axelson, “Designing RS-485 Circuits” Feature article of The Computer Article Journal, Issue 107, 1999, pp 20-23.

[13] RS-422/485 Application Note, B & B Electronics Mfg. Co., Ottawa IL 61350 Revised October 1997.

[14] Maxim application note 3884, “How Far and How Fast Can You Go with RS-485”, July 25, 2006.

[15] Elaine Kant, “Understanding and Automating Algorithm Design”, IEEE Transaction on Software Engineering, VOL. SE-I1, NO. 11, November 1985, pp 1361-1374.

[16] Muhammad Ali Mazidi and Janice Gillispie Mazidi, “The 8051 Microcontroller and Embedded Systems”, Pearson Printed Hall, New Delhi, 2006.

[17] Tim Williams, “Circuit Designers Companion”, Newnes, 2005.

[18] Behrouz A. Forouzan,” Data Communication and Networks”, McGraw-Hill, New York, Third Edition, 1999.

[19] BAGCHI, S., and MITRA, S.K.: ‘An efficient algorithm for DTMF decoding using the sub band NDFT‘. Proceedings of IEEE symposium on Circuits.

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