mixed-signal system design and modeling ©2001 eric swanson lecture 6 fall semester 2002
TRANSCRIPT
Mixed-Signal System Design and Modeling
©2001 Eric Swanson
Lecture 6 Fall Semester 2002
2
Dynamic Range
• Before we can process real-world signals in the digital domain, we must quantize them
• Quantization to N bits takes the infinitely many voltage levels possible in the analog world and “rounds” them to a mere 2N levels
• The rounding error inherent in quantizing signals is called “quantization error”
3
Dynamic Range
• Analog-to-Digital Converters (ADCs) are quantizers that operate at the A/D interface– Suppose the ADC full scale input voltage range is VFS
– Then, the analog step size of an N-bit ADC is given by =VFS/2N
• If ADC analog input levels are large, and the input signal is “unrelated” to ADC sampling– Quantization error is essentially random
– Error is uniformly distributed between -/2 and +/2
4
Dynamic Range
• The mean-squared quantization error is:
• This error is commonly referred to as “quantization noise”
e2 = - /2
+ /2
x2 dx
=2
12
5
Dynamic Range
• The dynamic range of an ADC for sinusoidal inputs is the ratio of the rms value of biggest sinewave we can put into the ADC without overload to the rms value of the quantization noise:
DR (dB) = 20 log10
VFS/2/2
/12= 20 log10
VFS/2/2
VFS/2N/12
6
Dynamic Range
• Dynamic range for an ADC with sinusoidal input is often just called its “dynamic range”
• Finite DR is an inevitable consequence of “rounding” a continuous analog input to one of 2N discrete values
DR (dB) = 20 log10
VFS/2/2
VFS/2N/12= 20 log10 2N 3
2= 6.021N + 1.761
7
Dynamic Range
• 6.02N+1.76dB is the best case DR for an ideal N-bit ADC (or 2N-level quantizer)– Real ADCs add other noise sources in addition
to their quantization noise– Thermal noise typically dominates quantization
noise in commercial ADCs
• Digital signal processing of real-world signals is impossible without at least one ADC’s quantization noise
8
Dynamic Range
• Note that rounding a 32-bit accumulator value down to 16-bits for storage in a 16-bit register also adds 16b quantization noise– Best-case 16b dynamic range is 98.1dB – Changes in datapath word widths in digital
filters must be carefully evaluated for their dynamic range impact
• Let’s look briefly at real-world ADCs…
9
ADC Dynamic Range
• DR’s for the best standalone ADCs in the world in 2000 are plotted in the figure
• Dynamic range decreases as converter bandwidth increases
ADC Sampling Frequency (Hz)
104 106 108
40
80
60
120
140
100
20
Dyn
amic
Ran
ge
(dB
)
10
ADC Dynamic Range
• From 1975-1995, ADC performance at any sampling frequency improved by 2dB/year
• Since then, the “performance line” has stayed almost stationary
ADC Sampling Frequency (Hz)
104 106 108
40
80
60
120
140
100
20
Dyn
amic
Ran
ge
(dB
)
11
ADC Dynamic Range
• ADCs embedded in IC “Systems on a Chip” (SoCs) have less DR than the best standalone ADCs
• The embedded ADC performance level is shown in red
ADC Sampling Frequency (Hz)
104 106 108
40
80
60
120
140
100
20
Dyn
amic
Ran
ge
(dB
)embedded ADCs
12
ADC Dynamic Range
• Analog-digital crosstalk and design risk issues limit embedded ADC DR to about 100dB
• 1 GHz, 30dB DR levels are much more forgiving and the performance gap narrows
ADC Sampling Frequency (Hz)
104 106 108
40
80
60
120
140
100
20
Dyn
amic
Ran
ge
(dB
)embedded ADCs
13
ADC Dynamic Range
• Minimization of analog signal processing is a key goal of mixed-signal IC microarchitecture
• However, analog signal processing is almost unavoidable “above the red line”
ADC Sampling Frequency (Hz)
104 106 108
40
80
60
120
140
100
20
Dyn
amic
Ran
ge
(dB
)
14
Analog vs. Digital DR
• It’s much less expensive to add dynamic range to digital circuits than analog circuits
• To double the dynamic range of a digital datapath, we need to add only a bit to an already-wide datapath:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 016
+6dB DR