mixed-signal ic design notes set 1: quick summary of device …€¦ · power supply resonances;...

ECE194J /594J notes, M. Rodwell, copyrighted 2011

Mixed-Signal IC Design Notes set 1:

Quick Summary of Device Models

Mark RodwellUniversity of California, Santa Barbara

[email protected] 805-893-3244, 805-893-3262 fax


Background / Review

notes. online ECE145a therefer to please required, is detailgreater If

parametersport -2 modelsct Interconne

models Transistor n.informatiokey review Quickly

ECE145Ain covered wasmaterial This


Transmission Lines


Transmission Lines for On-Wafer Wiring

H

W microstrip line

0V

+V

geometry voltages currents

I

I

ADS use how to learn :ipsrelationsh eapproximat are These

light. of speed theis where

: velocitynpropagatio

and 377 where

:impedance sticcharacteri

0

0

c

cv

WHHZ

r

ro

ε

ηε

η

=

Ω≈

+≅


Transmission Lines: Waves, Voltage, Current

Ldz

LZCdzgenV

sZ

velocitynpropagatio /1

and impedance sticcharacteri /

where

currents wavereverse and forward)/()/(),(

voltages wavereverse and forward )/()/(),(

LCv

CLZ

ZvztV

ZvztVtzI

vztVvztVtzV

o

oo

=

=

+−

−=

++−=−+

−+


Reflections

( )( )

( )( )

tcoefficien ion transmisssource and

tcoefficien reflection source 11 where

:line of beginningAt

tcoefficien reflection load 11 where

:line of endAt

so

os

os

ossgenss

ol

olll

ZZZT

ZZZZVTVV

ZZZZVV

+=

+−

=Γ+Γ=

+−

=ΓΓ=

−+

+−

LZgenV

sZ


Pulse Reflections on Transmission Lines


Relating Lumped and Distributed Circuits

00 / , ZCZL ττ ==

model eApproximat

charging.circuit RCinductorneglect

)||()/(

→→

<<+ CRRRRL sLsL


Short Tramission Lines Can Be Modeled as L's and C's

00 / , ZCZL ττ ==

inductor anely approximat. small , large

:line -High 0

→CL

Z

capacitor.a ely approximat. small , large

:line -Low 0

→LC

Z


Skin effect loss

periphery. carrying-current effective theis P where,)1(1

lengthunit per resistance series added has Line

ty.conductivi theis where2/

depth skin oneby conductor thepenetratesCurrent

δσ

σωµσδ

jP

Zsurface+

=

=

H

W

~W +2H


package resonanceand grounding


What is Ground Bounce ?

ADC digitalsections

inputbuffer

ground returncurrents

Lground

∆Vingroundbouncenoise

"Ground" simply means a reference potential shared between many circuit paths.

To the extent that it has nonzero impedance, circuits will couple in unexpected ways

RFI, resonance, oscillation, frequently result from poor ground systems


Ground Bounce on an IC: break in a ground plane

signal line

signal line

ground plane

line 1

“ground”

line 2

“ground”

common-lead inductance

coupling / EMI due to poor ground system integrity is common in high-frequency systemswhether on PC boards...or on ICs.


Ground Bounce: IC Packaging with Top-Surface-Only Ground

Bond wire inductance aggravates the effect: resonates with through-wafer capacitance at 5-20 GHz

Peripheral grounding allows parallel plate mode resonancedie dimensions must be <0.4mm at 100GHz

IC: parallel-plane transmission line

peripheralbond inductances

peripheralbond inductances


power-supply resonance


Power Supply Resonance

onbondCLf π2/1=


Power Supply Resonances; Power Supply Damping

0

10

20

30

40

50

60

70

80

0 20 40 60 80 100

pow

er s

uppl

y im

peda

nce,

Ohm

s

Frequency (GHz)

90 GHz--local resonance between power supply capacitance and supply lead inductance

~N*5GHz resonances--global standing wave on power supply bus

Power supply is certain to resonate: we must model, simulate, and add dampling during design.


Standard cell showing power buses


Interconnects:Summary,

Design Strategy


fewer breaks in ground plane than CPW

IC Interconnects -- Thin-Film Microstrip

narrow line spacing → IC density

... but ground breaks at device placements

still have problem with package grounding

thin dielectrics → narrow lines→ high line losses→ low current capability→ no high-Zo lines

H

W

+ HWHZ

r

oo 2/1~

εη

...need to flip-chip bond

no substrate radiation, no substrate losses

InP mm-wave PA (Rockwell)


No breaks in ground plane

IC Interconnects -- Inverted Thin-Film Microstrip


... no ground breaks at device placements




Some substrate radiation / substrate losses

InP 150 GHz master-slave latch

InP 8 GHz clock rate delta-sigma ADC


VLSI Interconnects with Ground Integrity & Controlled Zo

negligible breaks in ground plane


negligible ground breaks @ device placements




no substrate radiation, no substrate losses


No clean ground return ? → interconnects can't be modeled !

35 GHz static dividerinterconnects have no clear local ground returninterconnect inductance is non-localinterconnect inductance has no compact model

InP 8 GHz clock rate delta-sigma ADC

8 GHz clock-rate delta-sigma ADCthin-film microstrip wiringevery interconnect can be modeled as microstripsome interconnects are terminated in their Zosome interconnects are not terminated...but ALL are precisely modeled


Active Devices: Bipolar Transistors


HBT Physical Structure


Physical structure, symbolic

baseBC gradecollector

N+ sub collector

semi-insulating InP substrate

emitter

emittercontact

base contact

cT

b,contWeWebW

underWN- drift collector

base contact

collector contact

bT

cW

EB grade

drawing lar toperpendicu LengthStripe Device EL=


0

5

10

15

20

0 1 2 3 4V

ce

mA

/µm

2

Bipolar Transistor: DC characteristics: common-emitter

Vbr,ceo

bc II β=

10-12

10-10

10-8

10-6

10-4

10-2

0 0.25 0.5 0.75 1

I c , I

b (A)

Vbe

(V)

Ic

Ib

satceV ,

maxJ

ion.documentatproject design in ninformatio More

density.power Maximumeffect,Kirk :byset is This.density current operating maximuma have HBTs maxJ


HBT hybrid-Pi equivalent-circuit model

cbf τ+τ=τ

Ccbi

Ccbx

Rbe

RbbB C

ERex

Rc

Vbe

CjeCbe,diff =gmτ f

gmVbee-jωτc

mobe gR /β=

)exp( cmom jgg ωτ−=

C

nkTqIg cmo /=

( )( ) ./1 toproportion in vary ,,,

, toproportion in vary ,, : lengthemitter of fingers HBT Given

max, Efingerccexbb

Efingercbxcbije

Efinger

LNIRRRLNCCC

LN


Active Devices: MOSFETs


MOSFETS

N+ source N+ drain

source contact (silicide) drain contact (silicide)

N+ polygate

gate metal(silicide) dielectric

sidewall

gate oxide

P substrate

S D S D S D S

G

G

Wg

Cross-Section Layout (multi-finger)

P substrate

gatedielectric

N+polysilicongate

inversionlayer


MOSFET DC Characteristics

ID

VDS

increasingVGS

gthgsgoxD LVVWcI 2/)(current limitedmobility

2, −=

−

µµ

)(current limitedvelocity

, thgssatgoxvD VVvWcI −=−

1

Expression dGeneralize

,

2

,

=

+

µD

D

vD

D

II

II

Id

VgsVth

mobility-limited

velocity-limited

: voltageknee thenlarger tha voltagesdrainFor


Knee Voltage: Mobility-Limited Case

VGD=Vth

regionscurrent -constant and Ohmic the betweenboundary thedefines voltageknee The

ID

VDS

increasingVGS

Ohm

ic constant-current

thgsdsdg VVVV −=−= whenoccurs curve in knee the

regime, limited-mobility theIn

IDRDVGD=Vth

IDRS

s.resistance drain & source parasitic theacross drops by voltage increasedfurther is Voltage KneeThe


Knee Voltage: Velocity-Limited Case

µ/ whenoccurs curve in knee theregime, limitedvelocity theIn

gsatds LvV =

s.resistance drain & source parasitic theacross drops by voltage

increasedfurther is Voltage Knee theAgain,

VDS=vsatLg/µ

IDRD

VDS=vsatLg/µ

IDRS


MOSFET Transconductance

gthgsgoxGS

Dm

gthgsgoxD

LVVWcVIg

LVVWcI

/)(

2/)( limitedmobility

2,

−=∂∂

=→

−=

−

µ

µµ

satgoxGS

Dm

thgssatgoxvD

vWcVIg

VVvWcI

=∂∂

=→

−=−

)( limitedvelocity

,

Id

VgsVth

∆V

gm

VgsVth

∆V

mobility-limited

velocity-limited


Linear vs. Square-Law Characteristics: 90 nm


90 nm MOSFET DC Characteristics

3V~1/ V 6.0||mm/S 7.0μm/mS 7.0/

channel-P

3V~1/ V 6.0mm/S 4.1μm/mS 4.1/

channel-N

λ

λ

=

===

=

===

th

satoxgm

th

satoxgm

VvcWg

VvcWg


Device Structure and Model

( ) ( )( )

( )

mi

gds

ggd

ggeq

gs

thgsgeq

geffeq

m

gRNWGNWC

NWLT

C

VVNWT

NWvT

g

/1~

~

or ~

∝

∝

−

ε

µεε

gdb

gsb

gs

gd

endg

g

sg

NWCNWC

NWRNWR

NR

NW

LR

∝

∝

∝

∝

+

/1/1

212~ ρ

CgdRg

Ri

Cgs Vg’s’

gmVg’s’ Gds

Rs

RdG

D

S

Csb

Cdb

CgdRg

Ri

Cgs Vg’s’

gmVg’s’ Gds

Rs

G

D

S

Csb

Cdb

S D S D S D S

G

G

Wg

contacts substrate ample -fingers gateshort -

using Increase maxf

widthgate fingers, gate # == gWN


CgdRin

Cgsx Vg’s’

gmxVg’s’ GdsxG

D

S

Cdb

Csb

Oversimplified Model

igsin

sm

dsdsx

sm

gsgsx

sm

mmx

RRRRRg

GG

RgC

C

Rggg

+++

+

+

~

1

~

1~

1~

etc analysis, hand roughFor CgdRg

Ri

Cgs Vg’s’

gmVg’s’ Gds

Rs

G

D

S

Csb

Cdb

gdgdsigs

gddsmgdmgs

CRGRRRff

CRRgCgCf

π

π

τ

τ

2)(2~

)(//~2/1sfrequencie cutoff eApproximat

max +++

+++


End

mixed-signal ic design notes set 1: quick summary of device …€¦ · power supply resonances;...

Documents