Mismatch in Circuit Design

V.M. Brea PhD Course2005-2007

Dept. of Electronics and Computer ScienceUniversity of Santiago de Compostela

Santiago de CompostelaSpain

Outline

IntroductionMismatch- definitionMismatch- modelsPelgrom ModelFinal Remarks

Introduction (I)

Hardware approach to problems like:Numerical Computation

ModelingVision Computing, Image ProcessingData baseCommunication …

Data AcquisitionSensors and Actuators

Introduction (II)

Buy- off-the-shelf general purpose solutionsSupercomputersPCsDSPsFPGAsPLDsMicrocontrollers …

Introduction (III)

Build- chip design, Application SpecificIC (ASIC)

VHDLVHDL-AMSStandard cellsMixed-SignalAnalog

Introduction (IV)

Hierarchy of IC Requirements and Choices

Overall CircuitsRequirementsand Choices

Overall MOSFETRequirementsand Choices

MOSFET Scalingand Design

Choices

ProcessIntegration

Choices

1.- Chip Power2.- Chip Speed3.- FunctionalDensity4.- Chip Cost5.- ArchitectureEtc.

1.- Vdd2.- MOSFET LeaKage3.- MOSFET DriveCurrent4.- Parasitic Series Resistance5.- Transistor Size6.- Vt Control7.- Reliability

1.- Tox, Lg, xj, Rs2.- ChannelEngineering3.- Oxynitride orHigh K Gates4.- Classical PlanarOr Non-ClassicalCMOS StructuresEtc.

1.- ThermalProcessing2.- OverallProcess Flow3.- ProcessModules4.- MaterialProperties5.- BoronPenetration

Introduction (V)

Top-down Design Flow of an ASIC

Natural Language-Description of theapplication

-Initial Specifications

Computing SoftwareStage-High-level LanguageC, C++, Matlab …

-Additional Constraints

Specific Software-Toos suited to the Hard

ware Model or Architecture

Hardware-LevelDesign

Introduction (VI)

Errors in Circuit Design (I)System-level- misconceptions, ill-posed problems…Hardware-level

ModelingVHDLRTLSPICE, Spectre, Eldo Models …

Introduction (VII)

Errors in Circuit Design (II)Hardware-level

Systematic ErrorsWrong Technology and/or Operating ConditionsLow CMRR, Fan-out, PSRR …OffsetFinite Output ImpedanceGainBandwidthHarmonic Distortion- linearityPost-layout SimulationsEtc.

Introduction (VIII)

Errors in Circuit Design (III)Random Errors

NoiseMismatch

Layout Errors- designManufacturing Errors- catastrophic failures

Manufacturing and Random errors dropyield in a technology process

Mismatch- Definition (I)

Mismatch is the process that causes time-independent random variations in physicalquantities of identically designed devicesImportance-

AnalogDigitalMixed-Signal

Key- Mismatch Modeling

Mismatch- Definition (II)

AnalogOffset in OACurrent mirrors- dc errorsFilters- cutt-off frequency

Mixed-SignalD/A and A/D ConvertersSense Amplifiers in DRAM cells

DigitalTransient Errors- Frequency

Mismatch- Definition (III)

Mismatch- types ofLot-to-lotWafer to waferInter-die (die to die)Intra-die (device to device)

Mismatch is either characterized with in-housemethods (time consuming- user or foundry), or with a mathematical model

Mismatch Models (I)

Circuit-basedFew parameters (2-3)Many parameters (5-7)

Many of them correlated, difficult to use in hand-analysis

Device-basedMany parameters, more precise, not usable in hand-analysis, only in computersimulations

Mismatch Models (II)

Circuit-based

Pelgrom and extensions- 3 parametersLovett- narrow devices show more mismatch

Seville- 5 parametersDrennan- Motorola, 7 parameters

Process gradients are dealt with layout styleslike common-centroid, symmetry, and/or use of dummy devices. Their effect is that ofsystematic errors; not random

Pelgrom Model (I)

Parameters

Equations

βγ ,,0TV

( )

( )

( ) 2222

222

2

220

20

02

DSWLA

DSWLA

DSWLAV VT

VTT

ββ

γγ

ββσ

γσ

σ

+=⎟⎟⎠

⎞⎜⎜⎝

⎛ ∆

+=∆

+=∆

Pelgrom Model (II)Goal- to have expressions for rapid hand-analysis and trade-offsevaluationAssumptions

Closely spaced devices

In today technologies, for the two former parameters to be comparable, D should be around 1mm. The above assumption isreasonable

No substrate effect. If there is any, an extra mismatch degradationterm must be added

WLADS

222 <<

( ) 00 =∆⇒= γσBSV

Pelgrom Model (III)Remark- For independent and normally distributed deviations in x and y, the standard deviation of a function Z=f(x,y) is:

Then for two functions Z (one subtracting from the other), we can write:

( ) ( ) ( )yyfx

xfZ 2

22

22 σσσ ⎟⎟

⎠

⎞⎜⎜⎝

⎛∂∂

+⎟⎠⎞

⎜⎝⎛∂∂

=

( ) ( ) ( )

( ) ( )ZZ

yyfx

xfZ

yyfx

xfZZZ

σσ

σσσ

2

22

22

2

21

=∆

∆⎟⎟⎠

⎞⎜⎜⎝

⎛∂∂

+∆⎟⎠⎞

⎜⎝⎛∂∂

=∆

∆∂∂

+∆∂∂

=−=∆

Pelgrom Model (IV)

Across-regions equations (square-law):

( ) ( ) ( )

( ) ( )( )

( ) 2

2022

2222

/1

⎟⎟⎠

⎞⎜⎜⎝

⎛ ∆+∆=∆

∆⎟⎠⎞

⎜⎝⎛+⎟⎟

⎠

⎞⎜⎜⎝

⎛ ∆=⎟⎟

⎠

⎞⎜⎜⎝

⎛ ∆

ββσσσ

σββσσ

IgVV

VI

gI

I

mTGS

Tm

DS

DS

Pelgrom Model (V)

Mismatch in strong inversion:

( ) ( ) ( )( )

( ) ( ) ( ) ( ) 22

022

20

222

4

4

⎟⎟⎠

⎞⎜⎜⎝

⎛−+=∆

−+⎟⎟

⎠

⎞⎜⎜⎝

⎛=⎟⎟

⎠

⎞⎜⎜⎝

⎛ ∆

ββσσσ

σββσσ

TGSTGS

TGS

T

DS

DS

VVVV

VVV

II

Pelgrom Model (VI)

The former equations can be approximated(see table I and plot) by:

( ) ( )( ) ( )

( )WLAV

VVWLA

VVV

II

VTGS

TGS

VT

TGS

T

DS

DS

202

2

20

20

2244

≈∆

−=

−≈⎟⎟

⎠

⎞⎜⎜⎝

⎛ ∆

σ

σσ

Pelgrom Model (VII)Table I

Pelgrom Model (VIII)

Pelgrom Model (IX)Mismatch on the design of elementarystages- Current Mirror (I)

Design- trade-offThree parameters- area, speed and powerPerformance- combination of the three parameters above

( ) ( )( )( )

( )os

inRMSrel

DDB

oxTGS

B

GSGS

IIAcc

VIAPWLCVVA

ICC

gmBW

σ

ππ

3

112

32 21

1

=

+=−+

=+

=

Pelgrom Model (X)Mismatch on the design of elementarystages- Current Mirror (II)

We define the performance equation (PE):

To calculate the errors in Ios (Accrel), we first go through theerrors in the currents of M1 and M2 (current mirror transistors, in and out, respectively). For M1, we can write:

PBWAcc

PowerAccuracySpeedPE rel

22.==

( )( ) WLVV

AIITGS

VTBUNIT −

= 022

1σ

Pelgrom Model (XI)Mismatch on the design of elementarystages- Current Mirror (III)

For the standard deviation of the current of M2, we formulate:

And as the standard deviation is referred to the input current, thestandard deviation of the input offset current is as follows:

( ) ( )UNITOUT IAI σσ =

( ) ( ) ( )

( ) AA

WLVVAI

IAII

TGS

VTB

UNITOUT

OS

12 0

22

2

+−

=+= σσσ

Pelgrom Model (XII)Mismatch on the design of elementarystages- Current Mirror (IV)

With this, and assuming a typical bias modulation index of ½, Accrel and PE become:

For large gains A, we would have:

( )

( )( )32

0

20

196

112

+−

==

+−

=

AA

VACVV

PBWAccPE

AA

AVVWLAcc

DDVTox

TGSrel

VT

TGSrel

π

( )DDVTox

TGSrel

VACVV

PBWAccGain

20

22

96π−

=

Pelgrom Model (XIII)Mismatch on the design of elementarystages- Current Mirror (V)

Conclusions

Total performance (PE) depends on technology constants and on thechosen bias point. It is independent of the transistor sizes

The best total performance comes with large (VGS-VT) values. Concern-(VGS-VT) usually upper bounded by Vdd/2

Larger (VGS-VT) values lead to better accuracy numbers at the cost oflower speeds. In order to increase speed, higher IB must be used, resulting in higher power dissipation. The trade-off in the design of a current mirror is quite clear

Finite output impedances and noise are additional concerns in currentmirror design

Pelgrom Model (XIV)Mismatch on the design of elementarystages- One Transistor Voltage Ampl. (I)

Goal- As in the current mirror, the goal is to find the best total performance (PE)

For the figure displayed on the blackboard we can write:

( ) ( )( ) ( )

( ) ( )( )

( ) oxTGS

B

GS

GS

GSin

out

WLCVVIBW

CgmBWCgmsR

RsA

CgmsgmRgmR

RR

VVsA

−=

≈

⎟⎟⎠

⎞⎜⎜⎝

⎛+

−≈

⎟⎟⎠

⎞⎜⎜⎝

⎛++

−−==

π

π

232/

//11

///11/11

1

2

1

2

1

2

Pelgrom Model (XV)Mismatch on the design of elementarystages- One Transistor Voltage Ampl. (II)

For the power dissipation and the relative accuracy the nextequations hold:

Combining the three former equations we achieve:

( ) GainAWLV

VVAcc

IVP

VT

DD

OS

inRMSrel

BDD

0263==

=

σ

( ) oxVTTGS

DDrel

CAVVV

PBWAccGain

20

22

24 −=

π

Pelgrom Model (XVI)Mismatch on the design of elementarystages- Differential Pair Voltage Ampl. (I)

Similarly to the One Transistor Voltage amplifier, the next equations hold:

This equation is esentially the same as that of a single transistor amplifier

( )

( ) oxVTTGS

DDrel

VT

DDrel

DD

GS

CAVVV

PBWAccGain

GainAWLVAcc

IVPCgmBW

20

220

96

26

22/

−=

=

==

π

π

Pelgrom Model (XVII)Mismatch on the design of elementarystages- Load Compensated OTA (I)

Input stage in OAsGoal- to find the best total performanceNew Constraint- to achieve safe phase and gain margins

The second pole plays a role in the gain-bandwidth (GBW) product

GBW must be made Kstab times smaller than the second pole in order to ensure stability with feedback configurations, thus:

( ) ( )22222

22 4

32 TGSox

B

bGSaGS VVLWCI

CCgmf

−=

+=

ππ

( )222

2

43

TGSoxstab

B

stab VVLWCKI

KfGBW

−==

π

Pelgrom Model (XVIII)Mismatch on the design of elementarystages- Load Compensated OTA (II)

As for the Accrel:

Where Ain is the internal gain of the amplifier from thedifferential input to the upper current mirror:

( )

( ) ( ) ( )

( )20

202

222

22

20

11

20

2

0201

22

22

22

1

263

pVTnVTinin

pVTnVT

in

TTOS

VTPVTN

DDin

OS

inRMSrel

AAALWALW

ALW

A

AVVV

AAGain

LWVAV

VAcc

+=+

=⎟⎟⎠

⎞⎜⎜⎝

⎛+=

+==

σσσ

σ

( )( ) 2

1

1

2

2

1

WW

VVVV

ggA

TGS

TGS

m

min =

−−

==

Pelgrom Model (XIX)Mismatch on the design of elementarystages- Load Compensated OTA (III)

Now, with the power dissipation, we have an expression for thetotal performance of the OTA:

Using GBW=Gain.BW we reach the final PE:

( ) ( ) ⎟⎟⎠

⎞⎜⎜⎝

⎛−+

=

=

12

02

0

22

.192

2

TGS

in

pVTnVToxstab

DDrel

DDB

VVA

AACKV

PGBWAccGain

VIP

π

( ) ( ) ⎟⎟⎠

⎞⎜⎜⎝

⎛−+

==1

20

20

23

.192 TGS

in

pVTnVToxstab

DDrel

VVA

AACKV

PBWAccGainPE

π

Pelgrom Model (XX)Mismatch on the design of elementarystages- Load Compensated OTA (IV)

Conclusions

Total performance (PE) depends on technologyconstants and on the chosen bias point

The best total performance comes with low (VGS-VT) values in the transistors operating in voltagemode (the differential pair), and with large (VGS-VT) values in the current mirror

Stability brings in more constraints leading tohigher power dissipation values

Pelgrom Model (XXI)Mismatch on the design of elementarystages- Feedback syst. & OTA Design (I)

Goal- to find PE for a general OA with feedback

With Cd being the capacitor associated with the dominant pole of theopen-loop transfer function of the OTA and gmin being thetransconductance of the input stage

( )( )TGSDDdCLCL

mINTGS

BDDB

d

mINCLCL

VVVCBWAP

gVV

IVIP

CgBWAGBW

−=

=−

=

==

π

π2,

2

Pelgrom Model (XXII)Mismatch on the design of elementarystages- Feedback syst. & OTA Design (II)

As in former analysis we have:

( )⎟⎟⎠

⎞⎜⎜⎝

⎛−=

=

in

drelCLCLVTox

DD

TGS

VToxCL

inDDrel

CCAccBWAAC

VVVP

ACACVAcc

2320

20

2

22

48

48

π

Pelgrom Model (XXIII)Mismatch on the design of elementarystages- Feedback sys. & OTA Design (III)

Conclusions

The minimal power consumption is limited by thetechnology, i.e. effect of mismatch. Likewise, PE is mainlylimited by the input transistor

To optimize PE in a voltage processing system, the inputstages have to be biased with low (VGS-VT) values; even in weak inversion

Differently from open loop stages, in which the powerconsupmtion is proportional to the square of the Gain, nowthere is a cubic dependence on the Gain. This is caused by another constraint in a feedback system, that is, the stabilityrequirements

Pelgrom Model (XXIV)Mismatch on the design of elementarystages- Gen. multi-stage volt. design (I)

In this case, the relative accuracy of the total system is determinedby the input signal RMS and the equivalent input referred offsetvoltage as follows:

The former expression is dominated by the offset in the first stage. The designer has to come up with the largest possible gain in thefirst stage A1

( ) ( ) ( ) ( ) ...2

21

3

2

1

21

2 +⎟⎟⎠

⎞⎜⎜⎝

⎛+⎟⎟

⎠

⎞⎜⎜⎝

⎛+=

AAV

AVVV OSOS

OSOSeqσσσσ

Pelgrom Model (XXV)Mismatch on the design of elementarystages- Gen. multi-stage volt. design (II)

If the offset is dominated by that of the first stage, the next equation willhold:

The source resistance Rs and the input capacitance C1 set the upperboundary for the system speed:

( ) ( )13 OS

inRMS

OSeq

inRMSrel V

VV

VAccσσ

≈=

( )

( )

20

lim 6 VToxsrel ACR

Accfπ

≈2

2

1lim2

20

1

202

1

21,

3

2,

32

inRMS

sOSeq

VTox

VTOSox

V

CRf

VACC

WLAVWLCC

πσ

σ

==

==

Pelgrom Model (XXVI)Mismatch on the design of elementarystages- Gen. multi-stage volt. design (III)

Conclusions

The best possible matching has to be achieved in the firststage (input) where the signal levels are the smallest. Thelargest possible amplification has to be done as soon as possible

Accuracy and speed are interdependent, and their relation isfixed by the technology process

Pelgrom Model (XXVII)Mismatch on the design of elementarystages- Circuit Design Guidelines

Current Processing Stages

Design with as large a (VGS-VT) as possible. Limited by other specifications like signal swing and power supplyvoltage

Voltage Processing Stages

Design with as low a (VGS-VT) as possible. Limited by therequired speed

Pelgrom Model (XXVIII)Mismatch on the design of elementarystages- Mismatch vs. Noise (I)

Currently, the power dissipation is the main concernin high performance circuit design, e.g. uPs

Mismatch and noise impose a minimum powerconsumption for a circuit to work at a certainfrequency

Mismatch is caused by technology parameters, whereas noise is caused by physical constants. Whichis the most important factor in the power dissipationof a system?

Pelgrom Model (XXIX)Mismatch on the design of elementarystages- Mismatch vs. Noise (II)

Analysis of Power/cycle in a class B system with a sourceresistance R driving a load capacitor C:

And as the accuracy of a system is related to the inputcapacitance, we can write:

Due to the effect of mismatch, an analog system consumes atleast this power to perform a signal processing operation at a frequency f with an accuracy or dynamic range DR

( )OS

sRMSsRMS V

VDRfCVPσ3

,8 2 ==

( )22

0

2

20

1

24

3

fDRACP

VACC

VTox

OS

VTox

eq

=

≈σ

Pelgrom Model (XXX)Mismatch on the design of elementarystages- Mismatch vs. Noise (III)

The limit imposed by noise is given by:

The mismatch limit (technology dependent) is dominant over thatof noise (see plot)

2

2

8kTfDRPCkTVnRMS

=

=

Pelgrom Model (XXXI)Mismatch on the design of elementarystages- Mismatch vs. Noise (IV)

Pelgrom Model (XXXII)Mismatch on the design of elem. stages-Techniques to reduce impact of mismatch

Auto-zero

Chopping

Trimming

Pelgrom Model (XXXIII)Scaling (I)

AVT is mainly determined by fluctuations of dopantatoms under the gate. Tox also plays a role. Thetrend is to have a decreasing standard deviation onAVT with shrinking technologies (see plots)

Beta is mainly determined by fluctuations in themobility factor. No consistent theory has been foundyet. The trend of the standard deviation on Beta withshrinking technologies is not that clear, although itmight look like the same as that of AVT (see plots)

Pelgrom Model (XXXIV)Scaling (II)

Pelgrom Model (XXXV)Scaling (III)

Final Remarks (I)

Matching of devices proportional toarea, and thus capacitanceAccuracy requirements- minimal circuitarea and capacitancePower to get a given bandwidthincreases with the circuit capacitanceBandwidth-accuracy-power- technologydependent

Final Remarks (II)

MOS current processing circuits- high(VGS-VT) and low gm/I valuesMOS voltage processing circuits- low(VGS-VT) and high gm/I valuesFor a given bandwidth and accuracy, the limit imposed by mismatch isdominant over noise