mips® architecture for programmers volume ii-a: the mips32® … · 2020. 9. 10. · document...

Document Number: MD00086Revision 5.04

December 11, 2013

MIPS® Architecture For ProgrammersVolume II-A: The MIPS32® Instruction

Set

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3 MIPS® Architecture For Programmers Volume II-A: The MIPS32® Instruction Set, Revision 5.04

MIPS® Architecture For Programmers Volume II-A: The MIPS32® Instruction Set, Revision 5.04 4

Contents

Chapter 1: About This Book ................................................................................................................ 141.1: Typographical Conventions ....................................................................................................................... 14

1.1.1: Italic Text.......................................................................................................................................... 151.1.2: Bold Text .......................................................................................................................................... 151.1.3: Courier Text ..................................................................................................................................... 15

1.2: UNPREDICTABLE and UNDEFINED ....................................................................................................... 151.2.1: UNPREDICTABLE........................................................................................................................... 151.2.2: UNDEFINED .................................................................................................................................... 161.2.3: UNSTABLE ...................................................................................................................................... 16

1.3: Special Symbols in Pseudocode Notation................................................................................................. 161.4: For More Information ................................................................................................................................. 19

Chapter 2: Guide to the Instruction Set .............................................................................................. 202.1: Understanding the Instruction Fields ......................................................................................................... 20

2.1.1: Instruction Fields .............................................................................................................................. 212.1.2: Instruction Descriptive Name and Mnemonic................................................................................... 222.1.3: Format Field ..................................................................................................................................... 222.1.4: Purpose Field ................................................................................................................................... 232.1.5: Description Field .............................................................................................................................. 232.1.6: Restrictions Field.............................................................................................................................. 232.1.7: Operation Field................................................................................................................................. 242.1.8: Exceptions Field............................................................................................................................... 242.1.9: Programming Notes and Implementation Notes Fields.................................................................... 25

2.2: Operation Section Notation and Functions................................................................................................ 252.2.1: Instruction Execution Ordering......................................................................................................... 252.2.2: Pseudocode Functions..................................................................................................................... 25

2.3: Op and Function Subfield Notation............................................................................................................ 342.4: FPU Instructions ........................................................................................................................................ 34

Chapter 3: The MIPS32® Instruction Set ............................................................................................ 363.1: Compliance and Subsetting....................................................................................................................... 363.2: Alphabetical List of Instructions ................................................................................................................. 37ABS.fmt ............................................................................................................................................................ 46ADD .................................................................................................................................................................. 47ADD.fmt ............................................................................................................................................................ 48ADDI ................................................................................................................................................................. 49ADDIU .............................................................................................................................................................. 50ADDU ............................................................................................................................................................... 51ALNV.PS .......................................................................................................................................................... 52AND .................................................................................................................................................................. 54ANDI ................................................................................................................................................................. 55B ....................................................................................................................................................................... 56BAL................................................................................................................................................................... 57BC1F ................................................................................................................................................................ 58BC1FL .............................................................................................................................................................. 60BC1T ................................................................................................................................................................ 62BC1TL .............................................................................................................................................................. 64


BC2F ................................................................................................................................................................ 66BC2FL .............................................................................................................................................................. 67BC2T ................................................................................................................................................................ 68BC2TL .............................................................................................................................................................. 69BEQ .................................................................................................................................................................. 70BEQL ................................................................................................................................................................ 71BGEZ................................................................................................................................................................ 72BGEZAL ........................................................................................................................................................... 73BGEZALL ......................................................................................................................................................... 74BGEZL.............................................................................................................................................................. 76BGTZ ................................................................................................................................................................ 77BGTZL .............................................................................................................................................................. 78BLEZ................................................................................................................................................................. 79BLEZL............................................................................................................................................................... 80BLTZ................................................................................................................................................................. 81BLTZAL ............................................................................................................................................................ 82BLTZALL .......................................................................................................................................................... 83BLTZL............................................................................................................................................................... 85BNE .................................................................................................................................................................. 86BNEL ................................................................................................................................................................ 87BREAK ............................................................................................................................................................. 88C.cond.fmt ........................................................................................................................................................ 89CACHE ............................................................................................................................................................. 94CACHEE......................................................................................................................................................... 100CEIL.L.fmt....................................................................................................................................................... 107CEIL.W.fmt ..................................................................................................................................................... 108CFC1 .............................................................................................................................................................. 109CFC2 .............................................................................................................................................................. 111CLO ................................................................................................................................................................ 112CLZ................................................................................................................................................................. 113COP2.............................................................................................................................................................. 114CTC1 .............................................................................................................................................................. 115CTC2 .............................................................................................................................................................. 117CVT.D.fmt....................................................................................................................................................... 118CVT.L.fmt ....................................................................................................................................................... 119CVT.PS.S ....................................................................................................................................................... 120CVT.S.fmt ....................................................................................................................................................... 121CVT.S.PL........................................................................................................................................................ 122CVT.S.PU ....................................................................................................................................................... 123CVT.W.fmt ...................................................................................................................................................... 124DERET ........................................................................................................................................................... 125DI .................................................................................................................................................................... 126DIV.................................................................................................................................................................. 127DIV.fmt............................................................................................................................................................ 129DIVU ............................................................................................................................................................... 130EHB ................................................................................................................................................................ 131EI .................................................................................................................................................................... 132ERET .............................................................................................................................................................. 133ERETNC......................................................................................................................................................... 134EXT................................................................................................................................................................. 136FLOOR.L.fmt .................................................................................................................................................. 138FLOOR.W.fmt................................................................................................................................................. 139INS.................................................................................................................................................................. 140


J...................................................................................................................................................................... 142JAL ................................................................................................................................................................. 143JALR............................................................................................................................................................... 144JALR.HB......................................................................................................................................................... 146JALX ............................................................................................................................................................... 150JR ................................................................................................................................................................... 151JR.HB ............................................................................................................................................................. 153LB ................................................................................................................................................................... 155LBE................................................................................................................................................................. 156LBU................................................................................................................................................................. 157LBUE .............................................................................................................................................................. 158LDC1 .............................................................................................................................................................. 159LDC2 .............................................................................................................................................................. 160LDXC1 ............................................................................................................................................................ 161LH ................................................................................................................................................................... 162LHE................................................................................................................................................................. 164LHU ................................................................................................................................................................ 165LHUE .............................................................................................................................................................. 166LL.................................................................................................................................................................... 167LLE ................................................................................................................................................................. 168LUI .................................................................................................................................................................. 170LUXC1 ............................................................................................................................................................ 171LW .................................................................................................................................................................. 172LWC1.............................................................................................................................................................. 173LWC2.............................................................................................................................................................. 174LWE................................................................................................................................................................ 176LWL ................................................................................................................................................................ 177LWLE.............................................................................................................................................................. 180LWR................................................................................................................................................................ 182LWRE ............................................................................................................................................................. 184LWXC1 ........................................................................................................................................................... 186MADD ............................................................................................................................................................. 187MADD.fmt ....................................................................................................................................................... 188MADDU .......................................................................................................................................................... 190MFC0.............................................................................................................................................................. 191MFC1.............................................................................................................................................................. 192MFC2.............................................................................................................................................................. 193MFHC0 ........................................................................................................................................................... 195MFHC1 ........................................................................................................................................................... 196MFHC2 ........................................................................................................................................................... 197MFHI............................................................................................................................................................... 198MFLO.............................................................................................................................................................. 199MOV.fmt ......................................................................................................................................................... 200MOVF ............................................................................................................................................................. 201MOVF.fmt ....................................................................................................................................................... 202MOVN............................................................................................................................................................. 203MOVN.fmt....................................................................................................................................................... 204MOVT ............................................................................................................................................................. 205MOVT.fmt ....................................................................................................................................................... 206MOVZ ............................................................................................................................................................. 207MOVZ.fmt ....................................................................................................................................................... 208MSUB ............................................................................................................................................................. 209MSUB.fmt ....................................................................................................................................................... 210


MSUBU........................................................................................................................................................... 211MTC0.............................................................................................................................................................. 212MTC1.............................................................................................................................................................. 213MTC2.............................................................................................................................................................. 215MTHC0 ........................................................................................................................................................... 216MTHC1 ........................................................................................................................................................... 217MTHC2 ........................................................................................................................................................... 218MTHI............................................................................................................................................................... 219MTLO.............................................................................................................................................................. 220MUL ................................................................................................................................................................ 221MUL.fmt .......................................................................................................................................................... 222MULT.............................................................................................................................................................. 223MULTU ........................................................................................................................................................... 224NEG.fmt.......................................................................................................................................................... 225NMADD.fmt .................................................................................................................................................... 226NMSUB.fmt..................................................................................................................................................... 227NOP................................................................................................................................................................ 229NOR................................................................................................................................................................ 230OR .................................................................................................................................................................. 231ORI ................................................................................................................................................................. 232PAUSE ........................................................................................................................................................... 234PLL.PS ........................................................................................................................................................... 236PLU.PS........................................................................................................................................................... 237PREF .............................................................................................................................................................. 238PREFE............................................................................................................................................................ 242PREFX............................................................................................................................................................ 245PUL.PS........................................................................................................................................................... 246PUU.PS .......................................................................................................................................................... 247RDHWR.......................................................................................................................................................... 248RDPGPR ........................................................................................................................................................ 250RECIP.fmt....................................................................................................................................................... 251ROTR ............................................................................................................................................................. 252ROTRV ........................................................................................................................................................... 253ROUND.L.fmt ................................................................................................................................................. 254ROUND.W.fmt ................................................................................................................................................ 255RSQRT.fmt ..................................................................................................................................................... 256SB................................................................................................................................................................... 257SBE ................................................................................................................................................................ 258SC................................................................................................................................................................... 259SCE ................................................................................................................................................................ 262SDBBP ........................................................................................................................................................... 265SDC1 .............................................................................................................................................................. 266SDC2 .............................................................................................................................................................. 267SDXC1............................................................................................................................................................ 268SEB ................................................................................................................................................................ 269SEH ................................................................................................................................................................ 270SH................................................................................................................................................................... 271SHE ................................................................................................................................................................ 272SLL ................................................................................................................................................................. 273SLLV............................................................................................................................................................... 274SLT ................................................................................................................................................................. 275SLTI ................................................................................................................................................................ 276SLTIU ............................................................................................................................................................. 277


SLTU .............................................................................................................................................................. 278SQRT.fmt........................................................................................................................................................ 279SRA ................................................................................................................................................................ 280SRAV.............................................................................................................................................................. 281SRL................................................................................................................................................................. 282SRLV .............................................................................................................................................................. 283SSNOP ........................................................................................................................................................... 284SUB ................................................................................................................................................................ 285SUB.fmt .......................................................................................................................................................... 286SUBU.............................................................................................................................................................. 287SUXC1............................................................................................................................................................ 288SW.................................................................................................................................................................. 289SWC1 ............................................................................................................................................................. 290SWC2 ............................................................................................................................................................. 291SWE ............................................................................................................................................................... 292SWL................................................................................................................................................................ 293SWLE ............................................................................................................................................................. 296SWR ............................................................................................................................................................... 298SWRE............................................................................................................................................................. 300SWXC1........................................................................................................................................................... 302SYNC.............................................................................................................................................................. 303SYNCI............................................................................................................................................................. 308SYSCALL ....................................................................................................................................................... 310TEQ ................................................................................................................................................................ 311TEQI ............................................................................................................................................................... 312TGE ................................................................................................................................................................ 313TGEI ............................................................................................................................................................... 314TGEIU............................................................................................................................................................. 315TGEU.............................................................................................................................................................. 316TLBINV ........................................................................................................................................................... 318TLBINVF......................................................................................................................................................... 320TLBP............................................................................................................................................................... 322TLBR .............................................................................................................................................................. 323TLBWI............................................................................................................................................................. 325TLBWR ........................................................................................................................................................... 327TLT ................................................................................................................................................................. 329TLTI ................................................................................................................................................................ 330TLTIU.............................................................................................................................................................. 331TLTU............................................................................................................................................................... 332TNE ................................................................................................................................................................ 333TNEI ............................................................................................................................................................... 334TRUNC.L.fmt .................................................................................................................................................. 335TRUNC.W.fmt................................................................................................................................................. 336WAIT............................................................................................................................................................... 337WRPGPR ....................................................................................................................................................... 338WSBH............................................................................................................................................................. 339XOR................................................................................................................................................................ 340XORI............................................................................................................................................................... 341

Appendix A: Instruction Bit Encodings............................................................................................ 342A.1: Instruction Encodings and Instruction Classes ....................................................................................... 342A.2: Instruction Bit Encoding Tables............................................................................................................... 342A.3: Floating Point Unit Instruction Format Encodings ................................................................................... 350


Appendix B: Misaligned Memory Accesses..................................................................................... 353B.1: Terminology ............................................................................................................................................ 353B.2: Hardware versus software support for misaligned memory accesses .................................................... 354B.3: Detecting misaligned support.................................................................................................................. 355B.4: Misaligned semantics.............................................................................................................................. 355

B.4.1: Misaligned Fundamental Rules: Single Thread Atomic, but not Multi-thread ................................ 355B.4.2: Permissions and misaligned memory accesses ............................................................................ 355B.4.3: Misaligned Memory Accesses Past the End of Memory................................................................ 356B.4.4: TLBs and Misaligned Memory Accesses....................................................................................... 357B.4.5: Memory Types and Misaligned Memory Accesses ....................................................................... 358B.4.6: Misaligneds, Memory Ordering, and Coherence ........................................................................... 358

B.5: Pseudocode ............................................................................................................................................ 360B.5.1: Pseudocode distinguishing Actually Aligned from Actually Misaligned ......................................... 361B.5.2: Actually Aligned ............................................................................................................................. 361B.5.3: Byte Swapping............................................................................................................................... 362B.5.4: Pseudocode Expressing Most General Misaligned Semantics ..................................................... 363B.5.5: Example Pseudocode for Possible Implementations..................................................................... 363

B.6: Misalignment and MSA vector memory accesses .................................................................................. 364B.6.1: Semantics ...................................................................................................................................... 364B.6.2: Pseudocode for MSA memory operations with misalignment ....................................................... 365

Appendix C: Revision History ........................................................................................................... 368


Figures

Figure 2.1: Example of Instruction Description ....................................................................................................... 21Figure 2.2: Example of Instruction Fields................................................................................................................ 22Figure 2.3: Example of Instruction Descriptive Name and Mnemonic .................................................................... 22Figure 2.4: Example of Instruction Format .............................................................................................................. 22Figure 2.5: Example of Instruction Purpose............................................................................................................ 23Figure 2.6: Example of Instruction Description ....................................................................................................... 23Figure 2.7: Example of Instruction Restrictions....................................................................................................... 24Figure 2.8: Example of Instruction Operation.......................................................................................................... 24Figure 2.9: Example of Instruction Exception.......................................................................................................... 24Figure 2.10: Example of Instruction Programming Notes ....................................................................................... 25Figure 2.11: COP_LW Pseudocode Function......................................................................................................... 26Figure 2.12: COP_LD Pseudocode Function.......................................................................................................... 26Figure 2.13: COP_SW Pseudocode Function......................................................................................................... 26Figure 2.14: COP_SD Pseudocode Function ......................................................................................................... 27Figure 2.15: CoprocessorOperation Pseudocode Function.................................................................................... 27Figure 2.16: AddressTranslation Pseudocode Function ......................................................................................... 27Figure 2.17: LoadMemory Pseudocode Function ................................................................................................... 28Figure 2.18: StoreMemory Pseudocode Function................................................................................................... 28Figure 2.19: Prefetch Pseudocode Function........................................................................................................... 29Figure 2.20: SyncOperation Pseudocode Function ................................................................................................ 30Figure 2.21: ValueFPR Pseudocode Function........................................................................................................ 30Figure 2.22: StoreFPR Pseudocode Function ........................................................................................................ 31Figure 2.23: CheckFPException Pseudocode Function.......................................................................................... 32Figure 2.24: FPConditionCode Pseudocode Function............................................................................................ 32Figure 2.25: SetFPConditionCode Pseudocode Function ...................................................................................... 32Figure 2.26: SignalException Pseudocode Function .............................................................................................. 33Figure 2.27: SignalDebugBreakpointException Pseudocode Function................................................................... 33Figure 2.28: SignalDebugModeBreakpointException Pseudocode Function.......................................................... 33Figure 2.29: NullifyCurrentInstruction PseudoCode Function ................................................................................. 34Figure 2.30: JumpDelaySlot Pseudocode Function................................................................................................ 34Figure 2.31: PolyMult Pseudocode Function .......................................................................................................... 34Figure 3.1: Example of an ALNV.PS Operation...................................................................................................... 52Figure 3.2: Usage of Address Fields to Select Index and Way............................................................................... 94Figure 3.1: Usage of Address Fields to Select Index and Way............................................................................. 100Figure 3.2: Operation of the EXT Instruction ........................................................................................................ 136Figure 3.3: Operation of the INS Instruction ......................................................................................................... 140Figure 3.4: Unaligned Word Load Using LWL and LWR....................................................................................... 177Figure 3.5: Bytes Loaded by LWL Instruction ....................................................................................................... 178Figure 3.6: Unaligned Word Load Using LWLE and LWRE.................................................................................. 180Figure 3.7: Bytes Loaded by LWLE Instruction..................................................................................................... 181Figure 3.8: Unaligned Word Load Using LWL and LWR....................................................................................... 182Figure 3.9: Bytes Loaded by LWR Instruction....................................................................................................... 183Figure 3.10: Unaligned Word Load Using LWLE and LWRE................................................................................ 184Figure 3.11: Bytes Loaded by LWRE Instruction .................................................................................................. 185Figure 4.12: Unaligned Word Store Using SWL and SWR ................................................................................... 293Figure 4.13: Bytes Stored by an SWL Instruction ................................................................................................. 294Figure 4.14: Unaligned Word Store Using SWLE and SWRE .............................................................................. 296


Figure 4.15: Bytes Stored by an SWLE Instruction............................................................................................... 297Figure 4.16: Unaligned Word Store Using SWR and SWL ................................................................................... 298Figure 4.17: Bytes Stored by SWR Instruction...................................................................................................... 299Figure 4.18: Unaligned Word Store Using SWRE and SWLE .............................................................................. 300Figure 4.19: Bytes Stored by SWRE Instruction ................................................................................................... 301Figure A.1: Sample Bit Encoding Table ................................................................................................................ 343Figure B.1: LoadPossiblyMisaligned / StorePossiblyMisaligned pseudocode ...................................................... 361Figure B.2: LoadAligned / StoreAligned pseudocode ........................................................................................... 361Figure B.3: LoadRawMemory Pseudocode Function............................................................................................ 362Figure B.4: StoreRawMemory Pseudocode Function........................................................................................... 362Figure B.5: Byteswapping pseudocode functions ................................................................................................. 362Figure B.6: LoadMisaligned most general pseudocode........................................................................................ 363Figure B.7: Byte-by-byte pseudocode for LoadMisaligned / StoreMisaligned....................................................... 364Figure B.8: LoadTYPEVector / StoreTYPEVector used by MSA specification ..................................................... 365Figure B.9: Pseudocode for LoadVector ............................................................................................................... 366Figure B.10: Pseudocode for StoreVector ............................................................................................................ 366


Tables

Table 1.1: Symbols Used in Instruction Operation Statements............................................................................... 16Table 2.1: AccessLength Specifications for Loads/Stores...................................................................................... 29Table 3.1: CPU Arithmetic Instructions ................................................................................................................... 37Table 3.2: CPU Branch and Jump Instructions....................................................................................................... 38Table 3.3: CPU Instruction Control Instructions...................................................................................................... 38Table 3.4: CPU Load, Store, and Memory Control Instructions .............................................................................. 38Table 3.5: CPU Logical Instructions........................................................................................................................ 39Table 3.6: CPU Insert/Extract Instructions.............................................................................................................. 40Table 3.7: CPU Move Instructions .......................................................................................................................... 40Table 3.8: CPU Shift Instructions............................................................................................................................ 40Table 3.9: CPU Trap Instructions............................................................................................................................ 41Table 3.10: Obsolete CPU Branch Instructions ...................................................................................................... 41Table 3.11: FPU Arithmetic Instructions.................................................................................................................. 41Table 3.12: FPU Branch Instructions ...................................................................................................................... 42Table 3.13: FPU Compare Instructions................................................................................................................... 42Table 3.14: FPU Convert Instructions..................................................................................................................... 42Table 3.15: FPU Load, Store, and Memory Control Instructions ............................................................................ 43Table 3.16: FPU Move Instructions......................................................................................................................... 43Table 3.17: Obsolete FPU Branch Instructions....................................................................................................... 44Table 3.18: Coprocessor Branch Instructions......................................................................................................... 44Table 3.19: Coprocessor Execute Instructions ....................................................................................................... 44Table 3.20: Coprocessor Load and Store Instructions............................................................................................ 44Table 3.21: Coprocessor Move Instructions............................................................................................................ 44Table 3.22: Obsolete Coprocessor Branch Instructions.......................................................................................... 45Table 3.23: Privileged Instructions.......................................................................................................................... 45Table 3.24: EJTAG Instructions .............................................................................................................................. 45Table 3.25: FPU Comparisons Without Special Operand Exceptions .................................................................... 91Table 3.26: FPU Comparisons With Special Operand Exceptions for QNaNs ....................................................... 92Table 3.27: Usage of Effective Address.................................................................................................................. 94Table 3.28: Encoding of Bits[17:16] of CACHE Instruction..................................................................................... 95Table 3.29: Encoding of Bits [20:18] of the CACHE Instruction.............................................................................. 96Table 3.1: Usage of Effective Address.................................................................................................................. 100Table 3.2: Encoding of Bits[17:16] of CACHEE Instruction................................................................................... 101Table 3.3: Encoding of Bits [20:18] of the CACHEE Instruction............................................................................ 102Table 4.4: Values of hint Field for PREF Instruction ............................................................................................. 238Table 4.5: Values of hint Field for PREFE Instruction........................................................................................... 243Table 4.6: RDHWR Register Numbers ................................................................................................................. 248Table 4.7: Encodings of the Bits[10:6] of the SYNC instruction; the SType Field................................................. 305Table A.1: Symbols Used in the Instruction Encoding Tables .............................................................................. 343Table A.2: MIPS32 Encoding of the Opcode Field ............................................................................................... 344Table A.3: MIPS32 SPECIAL Opcode Encoding of Function Field....................................................................... 345Table A.4: MIPS32 REGIMM Encoding of rt Field ................................................................................................ 345Table A.5: MIPS32 SPECIAL2 Encoding of Function Field .................................................................................. 345Table A.6: MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture.............................. 346Table A.7: MIPS32 MOVCI Encoding of tf Bit ....................................................................................................... 346Table A.8: MIPS32 SRL Encoding of Shift/Rotate ................................................................................................ 346Table A.9: MIPS32 SRLV Encoding of Shift/Rotate.............................................................................................. 346


Table A.10: MIPS32 BSHFL Encoding of sa Field................................................................................................ 347Table A.11: MIPS32 COP0 Encoding of rs Field .................................................................................................. 347Table A.12: MIPS32 COP0 Encoding of Function Field When rs=CO.................................................................. 347Table A.13: MIPS32 COP1 Encoding of rs Field .................................................................................................. 348Table A.14: MIPS32 COP1 Encoding of Function Field When rs=S..................................................................... 348Table A.15: MIPS32 COP1 Encoding of Function Field When rs=D .................................................................... 348Table A.16: MIPS32 COP1 Encoding of Function Field When rs=W or L ............................................................ 349Table A.17: MIPS32 COP1 Encoding of Function Field When rs=PS .................................................................. 349Table A.18: MIPS32 COP1 Encoding of tf Bit When rs=S, D, or PS, Function=MOVCF...................................... 349Table A.19: MIPS32 COP2 Encoding of rs Field .................................................................................................. 350Table A.20: MIPS32 COP1X Encoding of Function Field ..................................................................................... 350Table A.21: Floating Point Unit Instruction Format Encodings.............................................................................. 350

Chapter 1


About This Book

The MIPS® Architecture For Programmers Volume II-A: The MIPS32® Instruction Set comes as part of a multi-vol-ume set.

• Volume I-A describes conventions used throughout the document set, and provides an introduction to theMIPS32® Architecture

• Volume I-B describes conventions used throughout the document set, and provides an introduction to themicroMIPS32™ Architecture

• Volume II-A provides detailed descriptions of each instruction in the MIPS32® instruction set

• Volume II-B provides detailed descriptions of each instruction in the microMIPS32™ instruction set

• Volume III describes the MIPS32® and microMIPS32™ Privileged Resource Architecture which defines andgoverns the behavior of the privileged resources included in a MIPS® processor implementation

• Volume IV-a describes the MIPS16e™ Application-Specific Extension to the MIPS32® Architecture. Beginningwith Release 3 of the Architecture, microMIPS is the preferred solution for smaller code size.

• Volume IV-b describes the MDMX™ Application-Specific Extension to the MIPS64® Architecture andmicroMIPS64™. It is not applicable to the MIPS32® document set nor the microMIPS32™ document set. WithRelease 5 of the Architecture, MDMX is deprecated. MDMX and MSA can not be implemented at the sametime.

• Volume IV-c describes the MIPS-3D® Application-Specific Extension to the MIPS® Architecture

• Volume IV-d describes the SmartMIPS®Application-Specific Extension to the MIPS32® Architecture and themicroMIPS32™ Architecture .

• Volume IV-e describes the MIPS® DSP Module to the MIPS® Architecture

• Volume IV-f describes the MIPS® MT Module to the MIPS® Architecture

• Volume IV-h describes the MIPS® MCU Application-Specific Extension to the MIPS® Architecture

• Volume IV-i describes the MIPS® Virtualization Module to the MIPS® Architecture

• Volume IV-j describes the MIPS® SIMD Architecture Module to the MIPS® Architecture

1.1 Typographical Conventions

This section describes the use of italic, bold and courier fonts in this book.

About This Book


1.1.1 Italic Text

• is used for emphasis

• is used for bits, fields, registers, that are important from a software perspective (for instance, address bits used bysoftware, and programmable fields and registers), and various floating point instruction formats, such as S, D,and PS

• is used for the memory access types, such as cached and uncached

1.1.2 Bold Text

• represents a term that is being defined

• is used for bits and fields that are important from a hardware perspective (for instance, register bits, which arenot programmable but accessible only to hardware)

• is used for ranges of numbers; the range is indicated by an ellipsis. For instance, 5..1 indicates numbers 5 through1

• is used to emphasize UNPREDICTABLE and UNDEFINED behavior, as defined below.

1.1.3 Courier Text

Courier fixed-width font is used for text that is displayed on the screen, and for examples of code and instructionpseudocode.

1.2 UNPREDICTABLE and UNDEFINED

The terms UNPREDICTABLE and UNDEFINED are used throughout this book to describe the behavior of theprocessor in certain cases. UNDEFINED behavior or operations can occur only as the result of executing instructionsin a privileged mode (i.e., in Kernel Mode or Debug Mode, or with the CP0 usable bit set in the Status register).Unprivileged software can never cause UNDEFINED behavior or operations. Conversely, both privileged andunprivileged software can cause UNPREDICTABLE results or operations.

1.2.1 UNPREDICTABLE

UNPREDICTABLE results may vary from processor implementation to implementation, instruction to instruction,or as a function of time on the same implementation or instruction. Software can never depend on results that areUNPREDICTABLE. UNPREDICTABLE operations may cause a result to be generated or not. If a result is gener-ated, it is UNPREDICTABLE. UNPREDICTABLE operations may cause arbitrary exceptions.

UNPREDICTABLE results or operations have several implementation restrictions:

• Implementations of operations generating UNPREDICTABLE results must not depend on any data source(memory or internal state) which is inaccessible in the current processor mode

• UNPREDICTABLE operations must not read, write, or modify the contents of memory or internal state whichis inaccessible in the current processor mode. For example, UNPREDICTABLE operations executed in usermode must not access memory or internal state that is only accessible in Kernel Mode or Debug Mode or inanother process

1.3 Special Symbols in Pseudocode Notation


• UNPREDICTABLE operations must not halt or hang the processor

1.2.2 UNDEFINED

UNDEFINED operations or behavior may vary from processor implementation to implementation, instruction toinstruction, or as a function of time on the same implementation or instruction. UNDEFINED operations or behaviormay vary from nothing to creating an environment in which execution can no longer continue. UNDEFINED opera-tions or behavior may cause data loss.

UNDEFINED operations or behavior has one implementation restriction:

• UNDEFINED operations or behavior must not cause the processor to hang (that is, enter a state from whichthere is no exit other than powering down the processor). The assertion of any of the reset signals must restorethe processor to an operational state

1.2.3 UNSTABLE

UNSTABLE results or values may vary as a function of time on the same implementation or instruction. UnlikeUNPREDICTABLE values, software may depend on the fact that a sampling of an UNSTABLE value results in alegal transient value that was correct at some point in time prior to the sampling.

UNSTABLE values have one implementation restriction:

• Implementations of operations generating UNSTABLE results must not depend on any data source (memory orinternal state) which is inaccessible in the current processor mode


In this book, algorithmic descriptions of an operation are described as pseudocode in a high-level language notationresembling Pascal. Special symbols used in the pseudocode notation are listed in Table 1.1.

Table 1.1 Symbols Used in Instruction Operation Statements

Symbol Meaning

← Assignment

=, ≠ Tests for equality and inequality

|| Bit string concatenation

xy A y-bit string formed by y copies of the single-bit value x

b#n A constant value n in base b. For instance 10#100 represents the decimal value 100, 2#100 represents thebinary value 100 (decimal 4), and 16#100 represents the hexadecimal value 100 (decimal 256). If the "b#"prefix is omitted, the default base is 10.

0bn A constant value n in base 2. For instance 0b100 represents the binary value 100 (decimal 4).

0xn A constant value n in base 16. For instance 0x100 represents the hexadecimal value 100 (decimal 256).

xy z Selection of bits y through z of bit string x. Little-endian bit notation (rightmost bit is 0) is used. If y is lessthan z, this expression is an empty (zero length) bit string.

+, − 2’s complement or floating point arithmetic: addition, subtraction

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*, × 2’s complement or floating point multiplication (both used for either)

div 2’s complement integer division

mod 2’s complement modulo

/ Floating point division

< 2’s complement less-than comparison

> 2’s complement greater-than comparison

≤ 2’s complement less-than or equal comparison

≥ 2’s complement greater-than or equal comparison

nor Bitwise logical NOR

xor Bitwise logical XOR

and Bitwise logical AND

or Bitwise logical OR

not Bitwise inversion

&& Logical (non-Bitwise) AND

> Logical Shift right (shift in zeros at left-hand-side)

GPRLEN The length in bits (32 or 64) of the CPU general-purpose registers

GPR[x] CPU general-purpose register x. The content of GPR[0] is always zero. In Release 2 of the Architecture,GPR[x] is a short-hand notation for SGPR[ SRSCtlCSS, x].

SGPR[s,x] In Release 2 of the Architecture and subsequent releases, multiple copies of the CPU general-purpose regis-ters may be implemented. SGPR[s,x] refers to GPR set s, register x.

FPR[x] Floating Point operand register x

FCC[CC] Floating Point condition code CC. FCC[0] has the same value as COC[1].

FPR[x] Floating Point (Coprocessor unit 1), general register x

CPR[z,x,s] Coprocessor unit z, general register x, select s

CP2CPR[x] Coprocessor unit 2, general register x

CCR[z,x] Coprocessor unit z, control register x

CP2CCR[x] Coprocessor unit 2, control register x

COC[z] Coprocessor unit z condition signal

Xlat[x] Translation of the MIPS16e GPR number x into the corresponding 32-bit GPR number

BigEndianMem Endian mode as configured at chip reset (0 →Little-Endian, 1 → Big-Endian). Specifies the endianness ofthe memory interface (see LoadMemory and StoreMemory pseudocode function descriptions), and the endi-anness of Kernel and Supervisor mode execution.

BigEndianCPU The endianness for load and store instructions (0 → Little-Endian, 1 → Big-Endian). In User mode, thisendianness may be switched by setting the RE bit in the Status register. Thus, BigEndianCPU may be com-puted as (BigEndianMem XOR ReverseEndian).

ReverseEndian Signal to reverse the endianness of load and store instructions. This feature is available in User mode only,and is implemented by setting the RE bit of the Status register. Thus, ReverseEndian may be computed as(SRRE and User mode).

Table 1.1 Symbols Used in Instruction Operation Statements (Continued)

Symbol Meaning



LLbit Bit of virtual state used to specify operation for instructions that provide atomic read-modify-write. LLbit isset when a linked load occurs and is tested by the conditional store. It is cleared, during other CPU operation,when a store to the location would no longer be atomic. In particular, it is cleared by exception return instruc-tions.

I:,I+n:,I-n:

This occurs as a prefix to Operation description lines and functions as a label. It indicates the instructiontime during which the pseudocode appears to “execute.” Unless otherwise indicated, all effects of the currentinstruction appear to occur during the instruction time of the current instruction. No label is equivalent to atime label of I. Sometimes effects of an instruction appear to occur either earlier or later — that is, during theinstruction time of another instruction. When this happens, the instruction operation is written in sectionslabeled with the instruction time, relative to the current instruction I, in which the effect of that pseudocodeappears to occur. For example, an instruction may have a result that is not available until after the nextinstruction. Such an instruction has the portion of the instruction operation description that writes the resultregister in a section labeled I+1.The effect of pseudocode statements for the current instruction labelled I+1 appears to occur “at the sametime” as the effect of pseudocode statements labeled I for the following instruction. Within one pseudocodesequence, the effects of the statements take place in order. However, between sequences of statements fordifferent instructions that occur “at the same time,” there is no defined order. Programs must not depend on aparticular order of evaluation between such sections.

PC The Program Counter value. During the instruction time of an instruction, this is the address of the instruc-tion word. The address of the instruction that occurs during the next instruction time is determined by assign-ing a value to PC during an instruction time. If no value is assigned to PC during an instruction time by anypseudocode statement, it is automatically incremented by either 2 (in the case of a 16-bit MIPS16e instruc-tion) or 4 before the next instruction time. A taken branch assigns the target address to the PC during theinstruction time of the instruction in the branch delay slot.In the MIPS Architecture, the PC value is only visible indirectly, such as when the processor stores therestart address into a GPR on a jump-and-link or branch-and-link instruction, or into a Coprocessor 0 registeron an exception. The PC value contains a full 32-bit address all of which are significant during a memory ref-erence.

ISA Mode In processors that implement the MIPS16e Application Specific Extension or the microMIPS base architec-tures, the ISA Mode is a single-bit register that determines in which mode the processor is executing, as fol-lows:

In the MIPS Architecture, the ISA Mode value is only visible indirectly, such as when the processor stores acombined value of the upper bits of PC and the ISA Mode into a GPR on a jump-and-link or branch-and-linkinstruction, or into a Coprocessor 0 register on an exception.

PABITS The number of physical address bits implemented is represented by the symbol PABITS. As such, if 36

physical address bits were implemented, the size of the physical address space would be 2PABITS = 236 bytes.


Symbol Meaning

Encoding Meaning

0 The processor is executing 32-bit MIPS instructions

1 The processor is executing MIIPS16e or microMIPSinstructions

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1.4 For More Information

Various MIPS RISC processor manuals and additional information about MIPS products can be found at the MIPSURL: http://www mips.com

For comments or questions on the MIPS32® Architecture or this document, send Email to [email protected].

FP32RegistersMode Indicates whether the FPU has 32-bit or 64-bit floating point registers (FPRs). In MIPS32 Release 1, the FPUhas 32 32-bit FPRs in which 64-bit data types are stored in even-odd pairs of FPRs. In MIPS64, (and option-ally in MIPS32 Release2 and MIPSr3) the FPU has 32 64-bit FPRs in which 64-bit data types are stored inany FPR.

In MIPS32 Release 1 implementations, FP32RegistersMode is always a 0. MIPS64 implementations have acompatibility mode in which the processor references the FPRs as if it were a MIPS32 implementation. Insuch a case FP32RegisterMode is computed from the FR bit in the Status register. If this bit is a 0, the pro-cessor operates as if it had 32 32-bit FPRs. If this bit is a 1, the processor operates with 32 64-bit FPRs.The value of FP32RegistersMode is computed from the FR bit in the Status register.

InstructionInBranchDe-laySlot

Indicates whether the instruction at the Program Counter address was executed in the delay slot of a branchor jump. This condition reflects the dynamic state of the instruction, not the static state. That is, the value isfalse if a branch or jump occurs to an instruction whose PC immediately follows a branch or jump, but whichis not executed in the delay slot of a branch or jump.

SignalException(excep-tion, argument)

Causes an exception to be signaled, using the exception parameter as the type of exception and the argumentparameter as an exception-specific argument). Control does not return from this pseudocode function—theexception is signaled at the point of the call.


Symbol Meaning

Chapter 2


Guide to the Instruction Set

This chapter provides a detailed guide to understanding the instruction descriptions, which are listed in alphabeticalorder in the tables at the beginning of the next chapter.

2.1 Understanding the Instruction Fields

Figure 2.1 shows an example instruction. Following the figure are descriptions of the fields listed below:

• “Instruction Fields” on page 21

• “Instruction Descriptive Name and Mnemonic” on page 22

• “Format Field” on page 22

• “Purpose Field” on page 23

• “Description Field” on page 23

• “Restrictions Field” on page 23

• “Operation Field” on page 24

• “Exceptions Field” on page 24

• “Programming Notes and Implementation Notes Fields” on page 25

Guide to the Instruction Set


Figure 2.1 Example of Instruction Description

2.1.1 Instruction Fields

EXAMPLE31 26 25 21 20 16 15 11 10 6 5 0

SPECIAL000000

0 rt rd0

00000EXAMPLE

000000

6 5 5 5 5 6

Format: EXAMPLE fd,rs,rt MIPS32

Purpose: Example Instruction Name

To execute an EXAMPLE op.

Description: GPR[rd] ← GPR[r]s exampleop GPR[rt]

This section describes the operation of the instruction in text, tables, and illustrations. Itincludes information that would be difficult to encode in the Operation section.

Restrictions:

This section lists any restrictions for the instruction. This can include values of the instruc-tion encoding fields such as register specifiers, operand values, operand formats, addressalignment, instruction scheduling hazards, and type of memory access for addressed loca-tions.

Operation:

/* This section describes the operation of an instruction in *//* a high-level pseudo-language. It is precise in ways that *//* the Description section is not, but is also missing *//* information that is hard to express in pseudocode. */temp ← GPR[rs] exampleop GPR[rt]GPR[rd] ← temp

Exceptions:

A list of exceptions taken by the instruction

Programming Notes:

Information useful to programmers, but not necessary to describe the operation of theinstruction

Implementation Notes:

Like Programming Notes, except for processor implementors

Example Instruction Name EXAMPLEInstruction Mnemonic andDescriptive Name

Instruction encodingconstant and variable fieldnames and values

Architecture level at whichinstruction was defined/redefined

Assembler format(s) for eachdefinition

Short description

Symbolic description

Full description ofinstruction operation

Restrictions on instructionand operands

High-level languagedescription of instructionoperation

Exceptions thatinstruction can cause

Notes for programmers

Notes for implementors

2.1 Understanding the Instruction Fields


Fields encoding the instruction word are shown in register form at the top of the instruction description. The follow-ing rules are followed:

• The values of constant fields and the opcode names are listed in uppercase (SPECIAL and ADD in Figure 2.2).Constant values in a field are shown in binary below the symbolic or hexadecimal value.

• All variable fields are listed with the lowercase names used in the instruction description (rs, rt, and rd in Figure2.2).

• Fields that contain zeros but are not named are unused fields that are required to be zero (bits 10:6 in Figure 2.2).If such fields are set to non-zero values, the operation of the processor is UNPREDICTABLE.

Figure 2.2 Example of Instruction Fields

2.1.2 Instruction Descriptive Name and Mnemonic

The instruction descriptive name and mnemonic are printed as page headings for each instruction, as shown in Figure2.3.

Figure 2.3 Example of Instruction Descriptive Name and Mnemonic

2.1.3 Format Field

The assembler formats for the instruction and the architecture level at which the instruction was originally defined aregiven in the Format field. If the instruction definition was later extended, the architecture levels at which it wasextended and the assembler formats for the extended definition are shown in their order of extension (for an example,see C.cond fmt

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