mipi devcon 2016: robust debug and conformance verification ensures interoperability
TRANSCRIPT
Ross Nelson, Protocol Insight MIPI JEDEC & UFSA Liaisons
Test & UniPro Working Groups
Robust Debug and Conformance Verification Ensures Interoperability
MIPIMobileTechnologies
MIPIISTHEPREDOMINANTINTERFACETECHNOLOGYFOR
HIGH-BANDWIDTHLOWPOWERINTERCONNECTS
Debugging and Verifying Conformance of MIPI Devices
REDUCINGTIMETOMARKET
1lessprototypecycle=2-3months
New Product
New Product Development Methodology Prototype Debug and Verification Cycle
• Interoperability testing
• Conformance/compliance verification
• Stress and automated testing
• Margin and corner case testing
• Link/interface debug
• Power on/device bring-up
Typical Tx Setup
• Oscilloscope – 25GHz or higher
• Probes – N7020A recommanded
• Switch matrix automates lane switching and test
InfiniiumDSAV254A25GHzOscilloscope
2x6(1x6differenTal)SwitchMatrixKeysightU3020AS26
Typical Rx Setup
Simplifiedset-upwithKeysightJ-BERTM8020AISIconformancechannelintegrated
J-BERT M8020A
N7010A
Typical Protocol Setup
Protocol Insight Test Executive™
• UniPro • UFS • Ara
Keysight Analyzer • Up to HS-G3 x4 • UniPro/UFS • Packet Generator • SMA probing
Link/Interface Debug Common Challenges
Customer Interactions Challenges Observed
Interop events (IOTs)
UniPro workshops
GoogleProject Ara
• Ara module initialization • UFS boot • Power Mode changes • Capabilities exchange • Link Startup Sequence
UniProExample
UniPro Common Challenges
• Link Startup Sequence Phase 0 thru 4 • Invalid Packet Order or Sequence • Timing violations
• LSS Capabilities Exchange • Invalid Packet Order or Sequence • Non-PACP_CAP packets on link
• Power Mode Change • Invalid Packet Order or Sequence • Device cannot change power modes reliably • After multiple Power Mode changes device does not respond
Link Startup Sequence
SevenphasesofLinkStartup:
Analyzing Link Traffic
State machine trace analysis • Evaluate every packet in a trace • Look for states and subsequent events • Log messages and attributes • Flag Failure, Warning, Pass, Info and Debug
Link Startup Sequence Debug
Common LSS Phase 0 thru 4 Failures
• Invalid Packet Order or Sequence
• Timing violations
Common LSS Failures – Timing Violations Time between TRG_UPR0 not ≥ 1.6ms
ReferenceUniProv1.6Table28PA_GranularityandPA_TAcFvateandSecFon5.7.8.2,lines1148and1154TheTAcTvateresetvalueis1.6ms,andthedeviceshallwaitPA_TAcTvatebeforebeginningaburst.ThustheTmebetweenTRG_UPRshallbeatleast1.6ms.
Common LSS Capabilities Exchange Failures
• Invalid Packet Order or Sequence
• Non-PACP_CAP packets on link
Common LSS Failures – Capabilities Exchange Packets other than EOB, SOB, CAP found before exchange complete
ReferenceUniProv1.6SecFon5.7.8.5“AeerfinishingPhase4oftheLinkStartupSequence,thePALayershallstartaBurstonlogicalLane#0andtransmitsitscapabiliTesandthelocalversioninformaTontothepeerDeviceusingPACP_CAP_EXT1_ind(seeSecTon5.7.7.4)andPACP_CAP_ind(seeSecTon5.7.7.3)inthisorder.”Thusallotherpacketsarenotallowedtobesent.
1. FoundEOB,transiToningtoPhase52. FoundPACP_CAP_ind,withnoEOBfollowing3. FoundAFCTC1beforeCAPExchangefinishedinit4. FoundAFCTC0beforeCAPExchangefinishedinit5. FoundEOB,transiToningtoDLiniTalizaTon
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Power Mode Change
Power Mode Change Debug
Common PMC Failures
• Invalid Packet Order or Sequence
• Device cannot change power modes reliably (FAST/SLOW, AUTO/nonAUTO)
• After multiple Power Mode changes device does not respond
Common PMC Failures – Packet Order Packets other than deskew or another PACP_PWR_req sent while waiting for the PACP_PWR_cnf
ReferenceUniProv1.6SecFon5.7.12LinkConfiguraFonProcedureOtherpacketsarenotallowedtobesentbetweenPACP_PWR_reqandPACP_PWR_cnf.
12345
1. FoundaPACP_PWR_req2. Nootherpacketbesidesdeskeworanother
PACP_PWR_reqshallbesentwhilewaiTngforthePACP_PWR_cnf
3. FoundanotherPACP_PWR_req4. FoundanotherPACP_PWR_req5. TherequestorshallnotstartanewburstunTlthe
peerdeviceclosesitsburst6. PACP_PWRexchangefinished
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Margin and Corner Case Testing
• Inject corrupted bits on the link… • Tx and Rx
• Mask test margin • Eye width/height • Unit interval • Jitter • Risetime/falltime
• Protocol • Corrupt packet header/payload • Invalid packet sequences • Timing violations • Timeout errors
then verify appropriate response
Example UniPro Error Injection Scripts
AFCParametersCRC-invertsCRCofAFCCREQ_BIT-setsCReqBitofAFCRSVD_BITS-invertsreservedbitsinAFCINCR_SEQ_NUM-increasesthesequencenumberinAFCby1DECR_SEQ_NUM-decreasesthesequencenumberinAFCby1TC0-replacesTC0byTC1SYMB-resultsinsymbolerrorinAFCDISP-resultsindisparityerrorinAFCCREDIT-followedby8bitvalueinhexwithwhichAFCistobereplacedREPLACE-followedby3bitvalueinhexwithwhichAFCistobereplacedEXTRASYMBOL-resultsinextrasymbolinAFC
PACPParametersCRC:-invertsCRCofPACPFrameRSVD_BITS:-invertsReservedbitsofPACPFrameFUNC_ID:-increasesthefuncTonidby1ofPACPFrameSYMB:-resultsinsymbolerrorinPACPFrameDISP:-resultsindisparityerrorinPACPFrameSKIP:-resultsinnotsendingPACP_CAP_indFrame
Stress and Automated Testing
• Corner case and margin testing
• Conformance and compliance testing
• Random order sequencing, traceable deterministic results
• Test loop management
Automated PHY Tx Testing Stress and Conformance
Configure the Device Under Test
(make sure proper data rate are supported)
Select Tests.
Automatically generate test report.
D-PHYExample
Automated PHY Rx Testing Stress and Conformance
M-PHYExample
Automated Protocol Testing Stress and Conformance
• Execute any loop order by Speed, Link widths, or individual test cases
• Each category can be run ascending, descending, or random seed order
• Stop after a specified number of test case configuration loops, Warnings, Failures or No Result Test Cases
UniProExample
C-PHYv1.1CSI-2v1.3CSI-3v1.1D-PHY2.0DSIv1.3.1DSI-2v1.0M-PHY4.0UniProv1.61
JEDECUFS2.xArav0.11
Conformance/Compliance Verification
Conformance/Compliance Verification
UFSJESD224CTSforJESD220Bspec UniProv1.1CTSfor
UniProv1.6andv1.61spec BIFv1.0CTSforBIFv1.0andv1.1spec
Signal Access and Design for Testability
• Board-level signal access • SMA • ZIF • RTB
• Boot or reset signal access
• Automatic DUT Link Startup Sequence
MIPI Product Registry Testing Process
• New Membership benefit launched August 2016.
• Allows MIPI Members to showcase commitment to conformance testing
• Important Documents: • MIPI Test Policy • MIPI Product Registry Program
Policy • Specifications • Conformance Test Suite (CTS) • Method of Implementations
(MOI)
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hlps://members.mipi.org/wg/All-Members/home/registry-faq
Conformance vs. Compliance • MIPI differentiates between conformance and compliance
• Conformance means: • An implementation on Product Registry, confirming it meets the normative
requirements of the relevant Specification or
• a Member-company verified implementation adheres to a Specification’s requirements
• Compliance implies that a formal evaluation has been made, e.g. as part of a certification program, which serves as a guarantee of a company’s right to enjoy applicable licenses.
Test Working Group
• Chartered to support conformance and interoperability activities
• Works with technical work groups in development of conformance testing resources
• Developed the Product Registry Program
• All Contributor or Board-level Members may participate in the Test Working Group
MIPI Product Registry Testing Process
• Conformance Test Suites (CTS)
• Unique to each MIPI Specification.
• Authored by MIPI Specification Working Group.
• Reviewed by MIPI Test Working Group.
• Outlines test procedures and requirements.
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MIPI Product Registry Testing Process
• Method of Implementation (MOI) • Describes how to perform CTS using specific
Test Equipment
• Authored by Test Equipment Manufacturer
• Approved by Test Working Group
• Outlines how to perform testing using specific test equipment • Calibration
• Connecting DUT
• Automation
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MIPI Product Registry Testing Process
• Contributor Members may perform self testing or use a MIPI approved test lab • All products noted as self-tested or independently tested
• Adopter members must use a MIPI approved test lab
• Member provides results summary to MIPI Product Registry Administrator
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• Products are tested
• according to test procedures defined in current approved CTS
• Or using alternate test methodology if no CTS is available
• Products must pass all applicable tests in CTS
• If an implementation has optional features, it must also pass those applicable tests
• Listing by similarity determined by the Administrator and the Test WG
Product Listing Process
PHY solution for Debug, Analysis, and Conformance
Transmitter Characterization
DSAV334A Infiniium 33 GHz scope
U7238B D-PHY, U7249B M-PHY, N5467B C-PHY UDA
InfiniiMax Probes
Switch matrix N5465A InfiniiSim
N2809A PrecisionProbe
Receiver Characterization
M8020A JBERT
M8190 AWG
N5990A Automated characterization
Impedance/Return Loss Validation
E5071CENAOpTonTDR
DCA 86100D Wideband sampling oscilloscope
N1055A TDR/TDT
54754A TDR/TDT
KeysightTechnologiesProtocolAnalyzer
ProtocolInsightTestExecuTve™
• CTStestcaseexecuTon
• ProtocolsequenceandpacketinspecTon
• STmulusmode
• StresstesTng
• Customtestcasebuilder
Protocol solution for Debug, Analysis, and Conformance
Summary • Effective verification methods shorten
time to market by reducing prototype spins
• Product registry showcases implementations with a commitment to interoperability
• Comprehensive tools for Debug, Analysis, and Conformance are available