midterm project report
DESCRIPTION
Midterm Project Report. Double buffer SDRAM Memory Controller. Project Number: D0713. Presented by: Yael Dresner Andre Steiner Instructed by: Michael Levilov. Project Description. - PowerPoint PPT PresentationTRANSCRIPT
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Double buffer SDRAM Memory ControllerDouble buffer SDRAM Memory Controller
Presented by:
Yael Dresner
Andre Steiner
Instructed by:
Michael Levilov
Project Number: D0713
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Project DescriptionProject Description
• Implementation of a device that receives a
grayscale bit map video stream from a digital video
camera, performs a simple pixel processing and
transfers it to a CPU through a double buffer
SDRAM memory.
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Blocks DiagramBlocks Diagram
Pixel Processing
Unit
SDRAM controller write part
SDRAM controller read part
Data Bus
Control signal
CPU FPGA CAMERA
Sync
FIFOSwitch
SDRAM A
SDRAM B
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Camera ModuleCamera Module• This module is implemented by a test-bench process, which
simulates a digital video camera.
Test BenchTest Bench
synch
Clock – 100MHz
reset
Pixels Data
1024 pixels * t clock period
2 us interval between lines
Start pulse
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Pixel Processing ModulePixel Processing Module
synch
clock
reset
Pixels DataProcessed Pixels Data
synch
Simple image
processing
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Write Controller ModuleWrite Controller Module
synch
clock
reset
Pixels Data
Control
Addresses Data Path
Input Data
Moore
State Machine
Start pulse
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Write Controller ModuleWrite Controller Module
Initialization Write full page Refresh
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Write Controller ModuleWrite Controller ModuleWrite Algorithm
• The data is sent to the Sdram block and switched to the Sdram memory which is not used for reading. The switching is done by a different unit in the read controller.
• The data is written to the memory in Full-Page mode (bursts of 1024 bytes).
• One bank is used (out of four).
• Refresh cycles are being done in the time interval between lines.
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Switching DiagramSwitching Diagram
SDRAM controller write part
SDRAM controller read part
Switch
SDRAM ASDRAM B
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Write Controller ModuleWrite Controller ModuleRefresh Algorithm
• One refresh cycle : 80ns (8 clock periods)
• Time interval between 2 lines : 2us
• 2us/80ns = 25 refresh cycles
• In order to refresh all the 4096 lines we need 4096/25 (163.84) time intervals
• Refreshing the whole memory takes 163.84*(2us + 1024*10ns) = 2msec
• Each line should be refreshed every 64 msec
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Cpu ModuleCpu Module• This module is implemented by a test-bench process,
which simulates a Cpu.
• The Cpu asks for the data pixels randomly, using the
“RD” control line.
• The Cpu reads bursts of bytes from the fifo, after
receiving a “RDY” control line. The burst length is set
randomly for each request.
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Handling Cpu RequestHandling Cpu Request
Test BenchTest Bench
Pixels Data
RD
RDY
Cpu Clock -100MHz
FIFOFIFO
Read Part
Write Part
SYNCH MODULESYNCH MODULERead Read
ControllerController
RD
RDY
read write
Sdram Clock
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Read Controller ModuleRead Controller Module
Read Controller Responsibilities
• Handling The switching between Sdrams
• Reading from Sdram and writing to fifo
• Refreshing
• Handling Cpu requests & reading data from FIFO to Cpu
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Read Controller ModuleRead Controller ModuleReading from Sdram algorithm
• The read controller ensures that the FIFO is always full.
• The read controller keeps 2 pointers:
• The address from which reading should continue
• The address which once accessed, switching should occur. This is the last address of data that was written before the previous switching.
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Read Controller ModuleRead Controller ModuleRefreshing algorithm
• The read controller is responsible for the refreshing of the Sdram that is currently switched for reading.
• Refreshing all Sdram lines should be done every 64 ms. This process takes 4096*80ns=0.33ms
• during this time the data is not transferred to the FIFO.
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Read Controller ModuleRead Controller ModuleSwitching algorithm
• Switching is done after:
• The last address of data that was written is read to the FIFO
• Time interval between lines and refreshing of the write controller is done
• Before switching the write controller stores the last address of written data and sends it to the read controller
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Read Controller ModuleRead Controller Module
Switching Unit
Fifo Handling unit
Reading from Sdram Unit
Switch
SDRAM B SDRAM A
FIFOControl & AddressControl
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Alternative Write AlgorithmAlternative Write Algorithm
Full page mode Burst mode
1 bank 4 banks
Less complicated implementation of the
write & read controllers
More complicated implementation of the
write & read controllers
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Time ScheduleTime Schedule• Implementing the camera test-bench module
• Implementing the pixel processing unit
• Implementing the write part of the SDRAM (Initialization, writing and refreshing)
• Implementing the Cpu Test Bench – One week
• Implementing the fifo and sync module – One week
• Implementing the read controller –Two weeks
• Integration and testing – Two weeks
• learning synthesys and PLACE&ROUTE" tools – Two weeks
• Documentation