mid term 3 review - university of california, san...
TRANSCRIPT
Mid Term 3 ReviewExercise 5
Timing and RetimingTpcq(FF) = 40ps, Tccq(FF) = 30ps, Tsetup(FF) = 50ps, Tpd = 35ps.
What is the maximumclock frequency?
Setup time violation (Recap)
Max Clock FrequencyConcept:● Ensure that setup time is not violated at any flip flop● So, at each flip flop, before the clock ticks (rises), its
input lines should have been stable for Tsetup time
Walk throughLine State How long?
Q1 Stable LONG
Q2 Stable LONG
Q3 Stable LONG
OR Stable LONG
NOT1 Stable LONG
NOT2 Stable LONG
AND Stable LONG
Before clock tick, t = 0
Walk throughLine State How long?
Q1 Stable LONG
Q2 Stable LONG
Q3 Stable LONG
OR Stable LONG
NOT1 Stable LONG
NOT2 Stable LONG
AND Stable LONG
Clock ticks, t = 0
All 3 flip flops have started processing
Walk throughLine State How long?
Q1 Stable LONG
Q2 Stable LONG
Q3 Stable LONG
OR Stable LONG
NOT1 Stable LONG
NOT2 Stable LONG
AND Stable LONG
Clock ticks, t = 5ps
All 3 flip flops are still processingAll flip flop outputs unchanged because < Tccq
Walk throughLine State How long?
Q1 Stable LONG
Q2 Stable LONG
Q3 Stable LONG
OR Stable LONG
NOT1 Stable LONG
NOT2 Stable LONG
AND Stable LONG
Clock ticks, t = 10ps
All 3 flip flops are still processingAll flip flop outputs unchanged because < Tccq
Walk throughLine State How long?
Q1 Stable LONG
Q2 Stable LONG
Q3 Stable LONG
OR Stable LONG
NOT1 Stable LONG
NOT2 Stable LONG
AND Stable LONG
Clock ticks, t = 25ps
All 3 flip flops are still processingAll flip flop outputs unchanged because < Tccq
Walk throughLine State How long?
Q1 Unstable 0
Q2 Unstable 0
Q3 Unstable 0
OR Stable LONG(input chg @30ps)
NOT1 Stable LONG
NOT2 Stable LONG(input chg @30ps)
AND Stable LONG(input chg @30ps)
Clock ticks, t = 30ps
All 3 flip flops are still processingAll flip flop outputs unstable! (t = Tccq)
Walk through
Clock ticks, t = 35ps
All 3 flip flops are still processingAll flip flop outputs unstable! (t > Tccq)
Line State How long?
Q1 Unstable 5ps
Q2 Unstable 5ps
Q3 Unstable 5ps
OR Stable LONG(input chg @30ps)
NOT1 Stable LONG
NOT2 Stable LONG(input chg @30ps)
AND Stable LONG(input chg @30ps)
Walk through
Clock ticks, t = 40ps
All 3 flip flops are done processingAll flip flop outputs stable! (t = Tpcq)
Line State How long?
Q1 Stable 0ps
Q2 Stable 0ps
Q3 Stable 0ps
OR Stable LONG(input chg @30ps)
(input stb @40ps)
NOT1 Stable LONG
NOT2 Stable LONG(input chg @30ps)
(input stb @40ps)
AND Stable LONG(input chg @30ps)
(input stb @40ps)
Walk through
Clock ticks, t = 45ps
All flip flop outputs still stable (t > Tpcq)
Line State How long?
Q1 Stable 5ps
Q2 Stable 5ps
Q3 Stable 5ps
OR Stable LONG(input chg @30ps)
(input stb @40ps)
NOT1 Stable LONG
NOT2 Stable LONG(input chg @30ps)
(input stb @40ps)
AND Stable LONG(input chg @30ps)
(input stb @40ps)
Walk through
Clock ticks, t = 55ps
OR, AND and NOT2 have unstable outputs because their inputs changed Tcd ps ago
Line State How long?
Q1 Stable 15ps
Q2 Stable 15ps
Q3 Stable 15ps
OR Unstable 0(input stb @40ps)
(input chg @55ps)
NOT1 Stable LONG(input chg @55ps)
NOT2 Unstable 0(input stb @40ps)
AND Unstable 0(input stb @40ps)
Walk through
Clock ticks, t = 60ps
OR, AND and NOT2 have unstable outputs because their inputs changed Tcd ps ago
Line State How long?
Q1 Stable 20ps
Q2 Stable 20ps
Q3 Stable 20ps
OR Unstable 5ps(input stb @40ps)
(input chg @55ps)
NOT1 Stable LONG(input chg @55ps)
NOT2 Unstable 5ps(input stb @40ps)
AND Unstable 5ps(input stb @40ps)
Walk through
Clock ticks, t = 75ps
OR, AND and NOT2 have stable outputs because their inputs stabilized Tpd ps ago
Line State How long?
Q1 Stable 35ps
Q2 Stable 35ps
Q3 Stable 35ps
OR Stable 0ps(input chg @55ps)
(input stb @75ps)
NOT1 Stable LONG(input chg @55ps)
(input stb @75ps)
NOT2 Stable 0ps
AND Stable 0ps
Walk through
Clock ticks, t = 80ps
NOT1 unstable (stable @ 110ps)OR will become unstable in Tcd time (@100ps)
Line State How long?
Q1 Stable 30ps
Q2 Stable 30ps
Q3 Stable 30ps
OR Unstable 0ps(input stb @75ps)
NOT1 Unstable 0ps(input stb @75ps)
NOT2 Stable 5ps
AND Stable 5ps
Walk through
Clock ticks, t = 90ps
NOT1 unstable (stable @ 110ps)OR will become unstable @100ps
Line State How long?
Q1 Stable LONG
Q2 Stable LONG
Q3 Stable LONG
OR Unstable 10ps(input stb @75ps)
NOT1 Unstable 10ps(input stb @75ps)
NOT2 Stable 15ps
AND Stable 15ps
Walk through
Clock ticks, t = 100ps
NOT1 unstable (stable @ 110ps)OR unstable (stable @110ps)
Line State How long?
Q1 Stable LONG
Q2 Stable LONG
Q3 Stable LONG
OR Unstable 0ps
NOT1 Unstable 20ps(input stb @75ps)
(input ch @100ps)
NOT2 Stable LONG
AND Stable LONG
Walk through
Clock ticks, t = 110ps
NOT1 stable (becomes unstable @125ps)OR stable
Line State How long?
Q1 Stable LONG
Q2 Stable LONG
Q3 Stable LONG
OR Unstable 5ps
NOT1 Stable 0ps(input ch @100ps)
NOT2 Stable LONG
AND Stable LONG
Walk through
Clock ticks, t = 115ps
NOT1 stable (becomes unstable @125ps)
Line State How long?
Q1 Stable LONG
Q2 Stable LONG
Q3 Stable LONG
OR Stable 0ps
NOT1 Stable 5ps(input ch @100ps)
(input st @110ps)
NOT2 Stable LONG
AND Stable LONG
Walk through
Clock ticks, t = 125ps
NOT1 unstable (becomes stable @145ps)
Line State How long?
Q1 Stable LONG
Q2 Stable LONG
Q3 Stable LONG
OR Stable LONG
NOT1 Unstable 0ps(input stb @110ps)
NOT2 Stable LONG
AND Stable LONG
Walk through
Clock ticks, t = 145ps
All stable
Line State How long?
Q1 Stable LONG
Q2 Stable LONG
Q3 Stable LONG
OR Stable LONG
NOT1 Stable 0ps
NOT2 Stable LONG
AND Stable LONG
Walk through
Clock ticks, t = 195ps
All stable for Tsetup time!!
Line State How long?
Q1 Stable LONG
Q2 Stable LONG
Q3 Stable LONG
OR Stable LONG
NOT1 Stable 50ps
NOT2 Stable LONG
AND Stable LONG
Max Clock FrequencyProcedure● Find the longest path in the circuit
○ Between a clock pin and a flip-flop input pin○ Longest path => Largest total propagation delay
across all combinational logic gates● Calculate Tc > Tpcq + Tpd + Tsetup● Maximum frequency, f = 1/Tc
Max Clock FrequencyNotes:● A path starts at a flip flop and ends at another flip flop,
but has no other flip flops in between● Tpcq = maximum clock-to-Q delay for the starting flip
flop● Tsetup = setup time of the ending flip flop
Max Clock FrequencyLongest path => FF1 -> NOT2 -> OR -> NOT1 -> FF1/2
Max Clock FrequencyTc >= Tpcq + Tpd + Tsetup
Max Clock FrequencyTc >= Tpcq + Tpd + Tsetup >= 40 + (3*35) + 50 ps
Max Clock FrequencyTc >= 195ps => Max Freq = 1/195ps = 5.128GHz
Hold time violation (Recap)
Max SkewProcedure● Find the shortest path in the circuit
○ Between a clock pin and a flip-flop input pin○ Shortest path => Shortest total contamination
delay across all combinational logic gates● Calculate Tskew < Tccq + Tcd - Thold
Max SkewNotes:● A path starts at a flip flop and ends at another flip flop,
but has no other flip flops in between● Tccq = minimum clock-to-Q delay for the starting flip
flop● Thold = hold time of the ending flip flop
Max SkewShortest path => FF1 -> NOT2 -> FF3
Max SkewTskew < Tccq + Tcd - Thold
Max SkewTskew < Tccq + Tcd - Thold < 40 + 25 - 60ps
Max SkewTskew < 5ps
