microsequencer

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MicrosequencerMicrosequencer Control Unit Control Unit DesignDesign

Chapter 7 Chapter 7 –– John D. John D. CarpinelliCarpinelli

Chapter OutlineChapter Outline•• Basic Microsequencer DesignBasic Microsequencer Design•• Very Simple MicrosequencerVery Simple Microsequencer•• Relatively Simple MicrosequencerRelatively Simple Microsequencer•• Reducing the Number of Reducing the Number of

MicroinstructionsMicroinstructions•• Microcoded vs. Hardwired ControlMicrocoded vs. Hardwired Control•• Pentium MicroprocessorPentium Microprocessor

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MicroMicro--stuffstuff‘Registers and data paths are the same as before’

•• MicroMicro--operations (register transfers)operations (register transfers)

•• Microinstructions (Microinstructions (μμ--operations + operations + sequencing information)sequencing information)

•• MicroprogramMicroprogram (collection of all (collection of all microinstructions for a processor)microinstructions for a processor)

Generic MicrosequencerGeneric Microsequencer

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Generating the Next AddressGenerating the Next AddressPossible next addresses:Possible next addresses:•• Current Address + 1(sequential states)Current Address + 1(sequential states)( q )( q )•• Address specified by microinstruction Address specified by microinstruction

(jump after every execute routine)(jump after every execute routine)•• Mapping hardware (to jump to correct Mapping hardware (to jump to correct

execute routine after fetch)execute routine after fetch)Mi b ti i t (t i l tMi b ti i t (t i l t•• Microsubroutine register (to implement a Microsubroutine register (to implement a common routine for several instructions)common routine for several instructions)

Microinstruction FormatMicroinstruction Format

SELECT: Indicates the source of the next address (absolute or a derived address)

ADDR: Specifies an absolute addressp

μ‐OPERATIONS: lists the μ‐OPS to be carried out

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MicroMicro--operations for VS CPUoperations for VS CPU

“AR” AR“AR” AR PC; ARPC; AR DR[5..0]DR[5..0][ ][ ]“PC” PC“PC” PC PC + 1; PCPC + 1; PC DR[5..0]DR[5..0]“DR” DR“DR” DR MM“IR” IR“IR” IR DR[7..6]DR[7..6]“AC” AC“AC” AC AC + DR; ACAC + DR; AC AC^DR; ACAC^DR; AC AC AC ;; ;;

+ 1 + 1

Types of MicrocodeTypes of Microcode•• Horizontal (a bit is allocated in the Horizontal (a bit is allocated in the

microinstruction for each microinstruction for each μ-OP of the processor) could be long only one/aprocessor) – could be long, only one/a few are used at a time, 16 μ-Ops =>

•• Vertical (Vertical (μ-Ops are grouped and assigned a code) 16 μ-Ops => H & V need control signals to be derived H & V need control signals to be derived from from μ-Ops Di t ( t th t l i l hDi t ( t th t l i l h•• Direct (stores the control signals, such Direct (stores the control signals, such as as --ld, inc,.. in ld, inc,.. in memorymemory-- and directly and directly generates them)generates them)

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Very Simple CPU SpecificationVery Simple CPU Specification

FETCH1: AR FETCH1: AR ←← PCPCFETCH2: DRFETCH2: DR ←← M PCM PC ←← PC + 1PC + 1FETCH2: DR FETCH2: DR ←← M, PC M, PC ←← PC + 1PC + 1FETCH3: IR FETCH3: IR ←← DR[7..6], AR DR[7..6], AR ←← DR[5..0]DR[5..0]ADD1: DR ADD1: DR ←← MMADD2: AC ADD2: AC ←← AC + DRAC + DRAND1: DR AND1: DR ←← MMAND2: AC AND2: AC ←← AC ^ DRAC ^ DRJMP1: PC JMP1: PC ←← DR[5..0]DR[5..0]INC1: AC INC1: AC ←← AC + 1AC + 1

Very Simple CPU State DiagramVery Simple CPU State Diagram

‘To sequence through gthese states and to generate the μ‐ops

For that state’

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A Very Simple MicrosequencerA Very Simple MicrosequencerSize of micro code memory?code memory?

Register?

Mux. In/out?

InstructionInstruction First StateFirst State IRIR Counter ValueCounter Value

State AssignmentsState Assignments

ADDADD ADD1 00 1000 (8)

AND AND1 01 1010 (10)

JMP JMP1 10 1100 (12)JMP JMP1 10 1100 (12)

INC INC1 11 1110 (14)

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Mapping LogicMapping Logic

State AddressesState AddressesStateState AddressAddress

FETCH1FETCH1 0000 (0)0000 (0)FETCH1FETCH1 0000 (0)0000 (0)FETCH2FETCH2 0001 (1)0001 (1)FETCH3FETCH3 0010 (2)0010 (2)

ADD1ADD1 1000 (8)1000 (8)ADD2ADD2 1001 (9)1001 (9)AND1AND1 1010 (10)1010 (10)AND1AND1 1010 (10)1010 (10)AND2AND2 1011 (11)1011 (11)JMP1JMP1 1100 (12)1100 (12)INC1INC1 1110 (14)1110 (14)

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Partial Microcode (sequencing)Partial Microcode (sequencing)

microinstructionmicroinstructionStateState AddressAddress SELSEL NXT. ADDRNXT. ADDR

FETCH1FETCH1 0000 (0)0000 (0) 00 00010001FETCH2FETCH2 0001 (1)0001 (1) 00 00100010FETCH3FETCH3 0010 (2)0010 (2) 11 XXXXXXXX

ADD1ADD1 1000 (8)1000 (8) 00 10011001ADD2ADD2 1001 (9)1001 (9) 00 00000000AND1AND1 1010 (10)1010 (10) 00 10111011AND2AND2 1011 (11)1011 (11) 00 00000000JMP1JMP1 1100 (12)1100 (12) 00 00000000INC1INC1 1110 (14)1110 (14) 00 00000000

Very Simple CPU SpecificationVery Simple CPU Specification

FETCH1: AR FETCH1: AR ←← PCPCFETCH2: DRFETCH2: DR ←← M PCM PC ←← PC + 1PC + 1FETCH2: DR FETCH2: DR ←← M, PC M, PC ←← PC + 1PC + 1FETCH3: IR FETCH3: IR ←← DR[7..6], AR DR[7..6], AR ←← DR[5..0]DR[5..0]ADD1: DR ADD1: DR ←← MMADD2: AC ADD2: AC ←← AC + DRAC + DRAND1: DR AND1: DR ←← MMAND2: AC AND2: AC ←← AC ^ DRAC ^ DRJMP1: PC JMP1: PC ←← DR[5..0]DR[5..0]INC1: AC INC1: AC ←← AC + 1AC + 1

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MicroMicro--operationsoperationsMnemonicMnemonic MicroMicro--OperationOperation

ARPCARPC ARAR PCPCARDRARDR ARAR DR[5..0]DR[5..0]PCINPCIN PCPC PC + 1PC + 1PCDRPCDR PCPC DR[5..0]DR[5..0]DRMDRM DRDR MMIRDRIRDR IRIR DR[7..6]DR[7..6]PLUSPLUS ACAC AC + DRAC + DRANDAND ACAC AC^DRAC^DRACINACIN ACAC AC + 1AC + 1

Preliminary Horizontal MicrocodePreliminary Horizontal Microcode‘μ‐ops field’ in micro instruction accommodates all μ‐ops

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Optimized Horizontal MicrocodeOptimized Horizontal MicrocodeARDR and IRDR has the same value in all states ‐ combine

Control SignalsControl Signals‘Derived from the RTL code of all the states’

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Control SignalsControl Signals

Regroup operations by destinationRegroup operations by destinationg p p yg p p y

“AR” AR“AR” AR PC; ARPC; AR DR[5..0]DR[5..0]“PC” PC“PC” PC PC + 1; PCPC + 1; PC DR[5..0]DR[5..0]“DR” DR“DR” DR MM“IR” IR“IR” IR DR[7..6]DR[7..6]“AC” AC“AC” AC AC + DR; ACAC + DR; AC AC^DR; ACAC^DR; AC AC + 1 AC + 1

Control SignalsControl SignalsSavings in logic: DRLOAD,

MEMBUS

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Generic Vertical Microcode Generic Vertical Microcode DecodingDecoding

‘Lots of zeros‘Lots of zeros in horizontal μcode - most are inactive’

Grouped into fi ldfields: no more than one μ-op in a field is active in a state

Field Field Assignment GuidelinesAssignment Guidelines‘Other part of the design remains the same’

•• Simultaneous microSimultaneous micro--operations in operations in different fieldsdifferent fields

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•• Simultaneous microSimultaneous micro operations inoperations in

Field Assignment GuidelinesField Assignment Guidelines


•• Include a NOP in each fieldInclude a NOP in each field

•• Simultaneous microSimultaneous micro operations inoperations in



•• Include a NOP in each fieldInclude a NOP in each field•• Group together microGroup together micro--operations that operations that

modify the same registermodify the same registerod y e sa e eg s eod y e sa e eg s e

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•• Simultaneous microSimultaneous micro operations inoperations in•• Simultaneous microSimultaneous micro--operations in operations in different fieldsdifferent fields

•• Include a NOP in each fieldInclude a NOP in each field•• Group together microGroup together micro--operations that operations that

modify the same registermodify the same registerod y e sa e eg s eod y e sa e eg s e•• Distribute remaining microDistribute remaining micro--operations to operations to

minimize total number of bits requiredminimize total number of bits required

Very Simple CPU Very Simple CPU SpecificationSpecification

FETCH1: AR FETCH1: AR ←← PCPCFETCH2 DRFETCH2 DR M PCM PC PC + 1PC + 1FETCH2: DR FETCH2: DR ←← M, PC M, PC ←← PC + 1PC + 1FETCH3: IR FETCH3: IR ←← DR[7..6], AR DR[7..6], AR ←← DR[5..0]DR[5..0]ADD1: DR ADD1: DR ←← MMADD2: AC ADD2: AC ←← AC + DRAC + DRAND1: DR AND1: DR ←← MMAND2: AC AND2: AC ←← AC ^ DRAC ^ DRJMP1: PC JMP1: PC ←← DR[5..0]DR[5..0]INC1: AC INC1: AC ←← AC + 1AC + 1

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MicroMicro--operationsoperationsMnemonicMnemonic MicroMicro--OperationOperation

ARPCARPC ARAR PCPCAIDRAIDR ARAR DR[5..0]DR[5..0]PCINPCIN PCPC PC + 1PC + 1PCDRPCDR PCPC DR[5..0]DR[5..0]DRMDRM DRDR MMPLUSPLUS ACAC AC + DRAC + DRANDAND ACAC AC^DRAC^DRACINACIN ACAC AC + 1AC + 1

MicroMicro--operation Assignmentsoperation Assignments

M1M1 M2M2M1M1 M2M2NOPNOP NOPNOPDRMDRM PCINPCIN

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M1M1 M2M2NOPNOP NOPNOPDRMDRM PCINPCINACINACIN PCDRPCDRPLUSPLUS ARPCARPCPLUSPLUS ARPCARPCANDAND AIDRAIDR

(Data related)(Data related) (Address related)(Address related)


M1M1 M2M2M1M1 M2M2NOPNOP NOPNOPDRMDRM PCINPCINACINACIN PCDRPCDRPLUSPLUS ARPCARPCPLUSPLUS ARPCARPCANDANDAIDRAIDR

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MicroMicro--operation Assignments operation Assignments and Field Valuesand Field Values

Vertical MicrocodeVertical Microcode

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MicroMicro--operation Generationoperation Generation

NanoinstructionsNanoinstructions128 μ-instructions with 32 μ-operations need 128*32bits.

16 unique combinations: nano-memory 16*32,

Access these 16 locations using 4-bits.

Microcode memory is then 128*4

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Directly Generating Control Directly Generating Control SignalsSignals

•• Output control signals instead of microOutput control signals instead of micro•• Output control signals instead of microOutput control signals instead of micro--operationsoperations

•• No external decoding requiredNo external decoding required•• No external hardware required to No external hardware required to

generate control signalsgenerate control signalsge e a e co o s g a sge e a e co o s g a s•• More difficult to codeMore difficult to code

Final Register SectionFinal Register Section

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Very Simple CPU Very Simple CPU SpecificationSpecification

FETCH1: AR FETCH1: AR ←← PCPCFETCH2 DRFETCH2 DR M PCM PC PC + 1PC + 1FETCH2: DR FETCH2: DR ←← M, PC M, PC ←← PC + 1PC + 1FETCH3: IR FETCH3: IR ←← DR[7..6], AR DR[7..6], AR ←← DR[5..0]DR[5..0]ADD1: DR ADD1: DR ←← MMADD2: AC ADD2: AC ←← AC + DRAC + DRAND1: DR AND1: DR ←← MMAND2: AC AND2: AC ←← AC ^ DRAC ^ DRJMP1: PC JMP1: PC ←← DR[5..0]DR[5..0]INC1: AC INC1: AC ←← AC + 1AC + 1

Preliminary Direct MicrocodePreliminary Direct Microcode

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Optimize Direct MicrocodeOptimize Direct MicrocodeDRLOAD, MEMBUS, READ have same values- combine

Relatively Simple Relatively Simple MicrosequencerMicrosequencer

•• No changes toNo changes to•• No changes toNo changes to–– Instruction setInstruction set–– Data pathsData paths–– ALUALU

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Modified State DiagramModified State Diagram

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State AssignmentsState AssignmentsMapping:IR[3..0]00[ ]

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Microsequencer HardwareMicrosequencer HardwareThree sources of next address

> larger mux-> larger mux.,

To support conditional jump, ‘+1’ circuit is necessary

Error in figure?

Condition ValuesCondition ValuesCondition Condition

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Branch TypesBranch Types

Branch LogicBranch Logic

Expressions for S1 and S0 of top MUX?

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Partial Microcode (Sequencing)Partial Microcode (Sequencing)

Partial Microcode (continued)Partial Microcode (continued)

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MicroMicro--operationsoperations‘22-bits for them’

Horizontal MicrocodeHorizontal Microcode

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Control SignalsControl Signals

Reducing the Number of Reducing the Number of MicroinstructionsMicroinstructions

‘Sharing common operations’‘Sharing common operations’Sharing common operationsSharing common operations•• MicrosubroutinesMicrosubroutines•• Microcode JumpsMicrocode Jumps

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MicrosubroutinesMicrosubroutines

Revised State AssignmentsRevised State AssignmentsSUB1, SUB2, SUB3 does same

LDAC1as LDAC1, LDAC2, LDAC3

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Microsequencer with Microsequencer with MicrosubroutinesMicrosubroutines

Revised Branch TypesRevised Branch Types

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Revised Branch LogicRevised Branch Logic

Revised MicrocodeRevised Microcode

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Microcode JumpsMicrocode Jumps‘Sharing states under certain condition’

Revised MicrocodeRevised Microcode

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Microprogrammed Control vs. Microprogrammed Control vs. Hardwired ControlHardwired Control

•• Complexity of the instruction setComplexity of the instruction setComplexity of the instruction setComplexity of the instruction set-- more instructions implies more states, more instructions implies more states, means more complex logic to generate means more complex logic to generate control signals in HW control unitcontrol signals in HW control unit-- as long as the microas long as the micro--operations are operations are the same, increasing state implies more the same, increasing state implies more

l i b i il i b i imemory locations but no increase in memory locations but no increase in logic to generate control signals in logic to generate control signals in MS/MP control unitMS/MP control unit

Control SignalsControl Signals‘Derived from the RTL code of all the states’

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•• Complexity of the instruction setComplexity of the instruction set•• Complexity of the instruction setComplexity of the instruction set•• Ease of modificationEase of modification

-- generally it is easier to add generally it is easier to add instructions, that is states in MS/MP instructions, that is states in MS/MP control units than HW control units. This control units than HW control units. This co o u s a co o u s sco o u s a co o u s simplies expandability for MS/MP control implies expandability for MS/MP control unit. unit.


•• Complexity of the instruction setComplexity of the instruction set•• Complexity of the instruction setComplexity of the instruction set•• Ease of modificationEase of modification•• Clock speedClock speed

-- as HW control unit is built from as HW control unit is built from combinatorial circuits generally thecombinatorial circuits generally thecombinatorial circuits, generally the combinatorial circuits, generally the instruction execution is faster. MP/MS instruction execution is faster. MP/MS control unit involves access delay for control unit involves access delay for the Lookthe Look--up ROM.up ROM.

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The Pentium MicroprocessorThe Pentium Microprocessor

SummarySummary•• Basic Microsequencer DesignBasic Microsequencer Design•• Very Simple MicrosequencerVery Simple Microsequencer•• Relatively Simple MicrosequencerRelatively Simple Microsequencer•• Reducing the Number of Reducing the Number of

MicroinstructionsMicroinstructions•• Microcoded vs. Hardwired ControlMicrocoded vs. Hardwired Control•• Pentium MicroprocessorPentium Microprocessor

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Next Address Generation

Op-code Conditions Absolute Next AddressCurrent Address

Next Address Generation

Address Register

Microcode Memory (Micro-operations and Next

Address)

5-bit Carry Save Adder

Partial Product 0 Partial Product 1 Partial Product 2

Carry Sum

6-bit Binary Parallel Adder

Final Product

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Mask Register

Data Register

DataReadWrite

MatchRegisterMemory

Output Register

microsequencer

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