microprocessor week2: data transfer
TRANSCRIPT
May 1, 2023 MCS51 Instruction 1
MCS-51 Data Transfer Instructions
May 1, 2023 MCS51 Instruction 2
Developing
Save / Load
Build
Assembly file (.asm)
Hex file
Emulator
Circuit Simulator
Microcontroller Board
Assembly Editor
May 1, 2023 MCS51 Instruction 3
Assembly Language
• Low-level programming• Specific to physical computer architecture
Assembly Language structure• [Header]• [Program Instructions]• [END Instruction]
May 1, 2023 MCS51 Instruction 4
Assembly Language SampleORG 00HMOV A, #45HANL A, P1 ; Get status from sensors and processMOV R0, P2 ; Get settingLoop:
MOV P3, A ; Send Output to Display unitDJNZ R0, Loop
END
May 1, 2023 MCS51 Instruction 5
• Appendix 2: MCS-51 Instruction set
May 1, 2023 MCS51 Instruction 6
Instruction set
• MCS51 is 8 bit microcontroller, there for 28 or 256 difference instructions possible for CPU.
• Types of instructions– Data Transfer Instruction– Logical Instruction– Arithmetic Instruction– Branch Instruction– Bit Operation Instruction
May 1, 2023 MCS51 Instruction 7
Machine Code
May 1, 2023 MCS51 Instruction 8
Description of MCS51 instruction’s parameter
• A• Rn• Ri• Rx (Ry)• Address• #X• #X16• Rel• Bit• C
May 1, 2023 MCS51 Instruction 9
Data Transfer Instructions• These instructions move the content of one register to another
one. The register which content is moved remains unchanged. If they have the suffix “X” (MOVX), the data is exchanged with external memory.
• MOV• MOVC• MOVX• PUSH• POP• XCH
May 1, 2023 MCS51 Instruction 10
MOV A, Rn
• MOV A, R3• MOV A, 03h
May 1, 2023 MCS51 Instruction 11
MOV A, #X
• MOV A, #78H• MOV A, #00101010B
May 1, 2023 MCS51 Instruction 12
MOV @Ri, #X
• MOV @R1, #78H• MOV @R0, #00101010B
May 1, 2023 MCS51 Instruction 13
MOV DPTR, #XX
• MOV DPTR, #78E5H• MOV DPTR, #1101010100101010B
78 E5DPH DPL
DPTR
May 1, 2023 MCS51 Instruction 14
MOV @Ri, A
E E
0001
0002
0003
0004
0005
…
0 4Ri
Acc
Data Memory
Ri is R0 or R1 register
3 5
7 E
6 8
E E
5 F
May 1, 2023 MCS51 Instruction 15
MOV A, @Ri
6 8
0001
0002
0003
0004
0005
…
0 3Ri
Acc
Data Memory
Ri is R0 or R1 register
3 5
7 E
6 8
E E
5 F
May 1, 2023 MCS51 Instruction 16
XCH A, @Ri
1 5
0001
0002
0003
0004
0005
…
0 5Ri
Acc
Data Memory
Ri is R0 or R1 register
3 5
7 E
6 8
E E
5 F
May 1, 2023 MCS51 Instruction 17
PUSH Rx
1 5
0006
0007
0008
0009
000A
000B
0 7SP
Rx
Data Memory
Increase SP. then …
To address SP+1
0 D
0 0
1 5
0 0
0 0
0 0
May 1, 2023 MCS51 Instruction 18
POP Rx
4 B
0006
0007
0008
0009
000A
000B
0 ASP
Rx
Data Memory
Then decrease SP.
from address SP
0 D
0 0
1 5
E F
4 B
0 0
May 1, 2023 MCS51 Instruction 19
XCH A, Rn
45H
F5H
Acc RN
May 1, 2023 MCS51 Instruction 20
XCHD A, @Ri
1 5
0001
0002
0003
0004
0005
0006
0 5Ri
Acc
Data Memory
Ri is R0 or R1 register
3 5
7 E
6 8
E E
3 F
E 2