MICROPROCESSOR BASED MICROPROCESSOR BASED SYSTEM DESIGNSYSTEM DESIGN

BYBY

PROF. DR. B. S. PROF. DR. B. S. CHOWDHRYCHOWDHRY

Lecture # 13 - Lecture # 13 - 14 14

        CLEAR YOUR CONCEPTS

This is how a Professor explained Marketing Concepts to a class:

1. You see a Gorgeous Girl at a party. You go up to her and say: "I am very rich. Marry me!"- That's Direct Marketing.

2. You are at a party with a bunch of friends and see a Gorgeous Girl. One of your friends goes up to her and pointing at you says: "He's very rich. Marry him!"- That's Advertising.

3. You are at a party and see a Gorgeous Girl. She walks up to you and says: "You are very rich! Can I marry you?"- That's Brand Recognition.

4. You see a Gorgeous Girl at a party. You go upto her and say: "I am very rich. Marry me!" She gives you a nice hard slap on your face.- That's Customer Feedback.

5. You see a Gorgeous Girl at a party. You go upto her and say: "I am very rich. Marry me!" And she introduces you to her husband.- That's Demand and Supply Gap.

6. You see a Gorgeous Girl  at a party. You go upto her and before you say: "I m rich, Marry me!", your wife arrives.- That's Restriction for Entering New Markets. 

I hope Concepts are clear...

8086 / 8088 HARDWARE 8086 / 8088 HARDWARE

SPECIFICATIONSSPECIFICATIONS Pin functions of 8086 / 8088 Pin functions of 8086 / 8088

MicroprocessorsMicroprocessorsClock Generation (Use of 8284 Clock Generation (Use of 8284

IC)IC)Bus Latching, Bus BufferingBus Latching, Bus BufferingTiming DiagramsTiming DiagramsWait statesWait statesBus Controller (8288)Bus Controller (8288)

PIN FUNCTIONSPIN FUNCTIONS

Both 8086 & 8088 are packaged in Both 8086 & 8088 are packaged in 40 Pin DIP (Virtually no difference 40 Pin DIP (Virtually no difference between two microprocessors).between two microprocessors).

8086 is a 16-bit processor with 16-8086 is a 16-bit processor with 16-bit data bus.bit data bus.

8088 is a 16-bit processor with 8-bit 8088 is a 16-bit processor with 8-bit data bus (DATA BUS WIDH IS A MAJOR data bus (DATA BUS WIDH IS A MAJOR DIFFERENCE BETWEEN THESE DIFFERENCE BETWEEN THESE PS). PS).

PIN FUNCTIONS (Cont..)PIN FUNCTIONS (Cont..) Minor DifferencesMinor Differences

8086 has M/ I0 pin8086 has M/ I0 pin 8088 has I0 / M pin8088 has I0 / M pin8086 has BHE/ S78086 has BHE/ S7 8088 has SSO pin8088 has SSO pin

Both Both P require + 5.0VP require + 5.0V Both Both P operate in ambient temperatures P operate in ambient temperatures

of between 32of between 3200F (0F (000C) and about 180C) and about 18000F F (82(8200C). (This is not enough range to be C). (This is not enough range to be used outdoors in the winter or even in the used outdoors in the winter or even in the summer). But extended temperature-range summer). But extended temperature-range versions of 8086 / 8088 versions of 8086 / 8088 P are also P are also available from -40available from -4000 F ( 40 F ( 4000C) through + C) through + 25525500F (125F (12500C). C).

PIN CONNECTIONSPIN CONNECTIONS

ADAD77-AD-AD00 The 8088 address/data The 8088 address/data bus lines compose bus lines compose

the the multiplexed address/ multiplexed address/ data data busbus of the 8088 and of the 8088 and contain contain the rightmost 8-bits the rightmost 8-bits of the of the memory address or memory address or I/O port I/O port number whenever number whenever ALE is ALE is active high active high (logic 1) or data (logic 1) or data whenever whenever ALE is active low ALE is active low (logic 0). (logic 0). These pins are at These pins are at their their high-high-impedance stateimpedance state during a during a hold acknowledge hold acknowledge (HLDA)(HLDA)..

PIN CONNECTIONS (Cont...)PIN CONNECTIONS (Cont...)

AA1515-A-A88 The 8088 address The 8088 address bus bus provides the provides the upper-half upper-half memory memory address bits that address bits that are are present throughout a present throughout a bus cycle. These address bus cycle. These address

connections go to their connections go to their high-impedance statehigh-impedance state

during a during a hold hold acknowledgeacknowledge (HLDA). (HLDA).

PIN CONNECTIONS (Cont...)PIN CONNECTIONS (Cont...) ADAD1515-AD-AD88 The 8086 The 8086 address/dataaddress/data bus bus

lines Compose the upper lines Compose the upper multiplexed address/data multiplexed address/data bus on the 8086. These bus on the 8086. These

lines contain address lines contain address bits bits AA1515-A-A8 8 whenever ALE is whenever ALE is a a logic 1, and data bus logic 1, and data bus

connections connections whenever ALE is whenever ALE is Logic Logic 0. D0. D1515-D-D88. These . These pins enter a high-pins enter a high-

impedance state whenever impedance state whenever a hold acknowledge occursa hold acknowledge occurs..

PIN CONNECTIONS (Cont...)PIN CONNECTIONS (Cont...) AA1919/S/S66-A-A1616/S/S33 The address/status bus bits The address/status bus bits

are are multiplexed to provide multiplexed to provide address address signals Asignals A1919-A-A1616 and also and also status status bits Sbits S66-S-S33. These pins . These pins also attain also attain a high-impedance state a high-impedance state during the during the hold acknowledgehold acknowledge

Status bit SStatus bit S66 always remains a always remains a logic 0, bit Slogic 0, bit S55 indicates the indicates the

condition of the condition of the IF flag IF flag bitsbits, and , and SS44 and S and S33 show which show which segment segment is accessedis accessed during the during the current current bus bus cycle. Refer to cycle. Refer to Table 1for Table 1for the truth table of Sthe truth table of S44 and and SS33. .

PIN CONNECTIONS (Cont...)PIN CONNECTIONS (Cont...)RDRD Whenever the Whenever the read signalread signal is a is a

logic 0, logic 0, the data bus is receptive to the data bus is receptive to data from data from the memory or I/O devices the memory or I/O devices connected to connected to the system. This pin the system. This pin floats to its high-floats to its high- impedance state impedance state during a hold during a hold acknowledge.acknowledge.

READY READY This input is controlled to insert This input is controlled to insert wait wait statesstates into the timing of the into the timing of the

microprocessor. If the microprocessor. If the READY pin is READY pin is placed at a logic0 placed at a logic0 level, the level, the microprocessor microprocessor enters into wait states enters into wait states and remains and remains idle. If the READY pin is idle. If the READY pin is placed at a placed at a logic 1 level, it has no effect logic 1 level, it has no effect on the on the operation of the microprocessoroperation of the microprocessor

PIN CONNECTIONS (Cont...)PIN CONNECTIONS (Cont...)INTR INTR Interrupt requestInterrupt request is used to is used to

request a request a hardware interrupt. If INTR is hardware interrupt. If INTR is held high held high when IF = 1, the 8086/8088 when IF = 1, the 8086/8088 enters an enters an interrupt acknowledge cycle interrupt acknowledge cycle (INTA (INTA becomes active) after becomes active) after the current the current instruction has instruction has completed execution.completed execution.

TESTTEST The The Test Test pin is an input that is pin is an input that is tested by tested by the WAIT instruction. IF TEST the WAIT instruction. IF TEST is a logic is a logic 0, the WAIT instruction 0, the WAIT instruction functions as a functions as a NOP. If TEST is a logic 1, NOP. If TEST is a logic 1, then the WAIT then the WAIT instruction waits for instruction waits for TEST to be become TEST to be become a logic 0. This pin a logic 0. This pin is most often is most often connected to the connected to the 8087 numeric 8087 numeric coprocessor.coprocessor.

NMI NMI The The non-maskable interruptnon-maskable interrupt input is input is similar to INTR except that the similar to INTR except that the

NMI NMI interrupt does not check to see if interrupt does not check to see if the IF the IF flag bit is a logic1. If NMI is flag bit is a logic1. If NMI is activated, activated, this interrupt input uses this interrupt input uses interrupt interrupt vector 2.vector 2.

RESET RESET The reset input causes the microprocessor The reset input causes the microprocessor

to to reset itself if this pin is held high for a reset itself if this pin is held high for a minimum of four clocking minimum of four clocking

periods. Whenever periods. Whenever the 8086 or 8088 is the 8086 or 8088 is reset, it begins executingreset, it begins executing instructions at instructions at memory location FFFFOH and memory location FFFFOH and disables disables future interrupts by clearing the IF future interrupts by clearing the IF flag bit. flag bit.

CLK CLK The The clock pinclock pin provides the basic timing provides the basic timing signal to the microprocessor. signal to the microprocessor.

VCC VCC This This power supplypower supply input provides a input provides a +5.0 +5.0 V, V, 10 % signal to the microprocessor.10 % signal to the microprocessor.

GND GND The The groundground connection is the return for connection is the return for the the power supply. Note that the 8086/8088 power supply. Note that the 8086/8088

microprocessors have two pins microprocessors have two pins labeled GND labeled GND both must be connected to both must be connected to ground for proper ground for proper operation.operation.

MN/MX MN/MX The The minimum/maximum modeminimum/maximum mode pin selects pin selects

either minimum mode or maximum either minimum mode or maximum mode mode operation for the microprocessor. operation for the microprocessor. If minimum If minimum mode is selected, the mode is selected, the MN/MX pin must be MN/MX pin must be connected directly to connected directly to +5.0 V.+5.0 V.

BHE/SBHE/S77 The The bus high enablebus high enable pin is used in the 8086 pin is used in the 8086

to enable the most- significant data bus to enable the most- significant data bus bits bits (D(D1515-D-D88) during a read or a write ) during a read or a write operation. operation. The state of SThe state of S77 is always a logic1. is always a logic1.

Minimum Mode Pins.Minimum Mode Pins. Minimum mode operation Minimum mode operation of the 8086/8088 is obtained by connecting the of the 8086/8088 is obtained by connecting the MN/MX pin directly to +5.0 V. MN/MX pin directly to +5.0 V.

I0/M or M/IO I0/M or M/IO The IO/M (8088) or the M/IO (8086) The IO/M (8088) or the M/IO (8086) pin selects memory or I/O. This pin pin selects memory or I/O. This pin indicates that the microprocessor indicates that the microprocessor

address bus contains either a address bus contains either a memory memory address or an I/O port address or an I/O port address. This address. This pin is at its high-pin is at its high-impedance state impedance state during a hold during a hold acknowledge.acknowledge.

WRWR The The write linewrite line is a strobe that is a strobe that indicates indicates that the 8086/808 is that the 8086/808 is outputting data to outputting data to a memory or I/O a memory or I/O device. During the device. During the time that the WR time that the WR is a logic 0, the data is a logic 0, the data bus contains bus contains valid data for memory or valid data for memory or I/O. This I/O. This pin floats to a high-pin floats to a high- impedance impedance during a hold acknowledge.during a hold acknowledge.

INTA INTA The The interrupt acknowledgeinterrupt acknowledge signal signal

is a response to the INTR is a response to the INTR input input pin. The INTA pin is normally pin. The INTA pin is normally used used to gate the interrupt vector to gate the interrupt vector

number onto the data bus in number onto the data bus in response to an interrupt request. response to an interrupt request.

ALE ALE Address latch enableAddress latch enable shows shows that that the 8086/8088 the 8086/8088 address/data bus address/data bus contains address contains address information. This information. This address can be a address can be a memory address memory address or an I/O port or an I/O port number. Note that number. Note that the ALE the ALE signal does not float signal does not float during during a hold acknowledge.a hold acknowledge.

DT/R DT/R The The data transmit/receivedata transmit/receive signal signal shows that the shows that the

microprocessor microprocessor data bus is data bus is transmitting (DT/R = transmitting (DT/R = 1) or 1) or receiving (DT/R = 0) data. receiving (DT/R = 0) data. This This signal is used to enable signal is used to enable external data bus buffers.external data bus buffers.

HOLD HOLD The The holdhold input requests a direct memory input requests a direct memory access (DMA). If the HOLD signal is a access (DMA). If the HOLD signal is a

logic 1, logic 1, the microprocessor stops the microprocessor stops executing software executing software and places its address, and places its address, data, and control bus data, and control bus at the high-impedance at the high-impedance state. If the HOLD pin state. If the HOLD pin is a logic 0, the is a logic 0, the microprocessor executes microprocessor executes software software normally. normally.

HLDA HLDA Hold acknowledgeHold acknowledge indicates that the indicates that the 8086/8088 microprocessors have 8086/8088 microprocessors have

entered the hold state. entered the hold state.

SSO SSO The SSO status line is equivalent to the The SSO status line is equivalent to the S0 S0 pin in maximum mode operation of the pin in maximum mode operation of the

microprocessor. This signal is microprocessor. This signal is combined with combined with IO/R and DT/R to decode the IO/R and DT/R to decode the function of the function of the current bus cycle (refer to current bus cycle (refer to Table 2). Table 2).

Maximum Mode Pins. Maximum Mode Pins. In order to achieve In order to achieve maximum mode for use with external maximum mode for use with external coprocessors, connect the MN/MX pin to coprocessors, connect the MN/MX pin to ground.ground.

S2, S1, and SO S2, S1, and SO The The status bitsstatus bits indicate indicate the the function of function of the current bus cycle. the current bus cycle. These signals are normally These signals are normally decoded by the 8288 bus decoded by the 8288 bus controller. Table 3 shows the controller. Table 3 shows the function of these three status bits function of these three status bits in the maximum in the maximum mode.mode.

RO/GTI and RO/GTI and The request/grant pins request The request/grant pins request RO/GTO RO/GTO direct memory accesses (DMA) direct memory accesses (DMA)

during maximum modeduring maximum mode operation. These lines are both bi-operation. These lines are both bi-directional and are used to directional and are used to request and grant a DMA request and grant a DMA operation.operation.

LOCK LOCK The lock output is used to The lock output is used to locklock peripherals off the peripherals off the

system.system.

QSQS11 and QS and QS00 The The queue statusqueue status bits bits show the status of show the status of

the internal the internal instruction instruction queue. queue.

These pins are provided These pins are provided for for access by the numeric access by the numeric

coprocessor (8087). coprocessor (8087). Refer to Refer to Table 4 for the Table 4 for the operation of operation of the queue the queue status bits.status bits.

Clock Generator (8284A)Clock Generator (8284A)

8284A clock generator is supporting IC 8284A clock generator is supporting IC of 8086/8088 of 8086/8088 P.P.

X1 & X2X1 & X2 – – Crystal InputsCrystal Inputs: Pins connect : Pins connect to an external crystal used as the to an external crystal used as the timing source for the clock generator timing source for the clock generator and all of its functions.and all of its functions.

RES – RES – Reset InputReset Input: To provide power : To provide power on resetting.on resetting.

RESETRESET- - Reset OutputReset Output: The signal is : The signal is connected to 8086/8088 RESET input connected to 8086/8088 RESET input pin.pin.

CLKCLK – – Clock:Clock: An output pin that An output pin that provides the CLK input signal to provides the CLK input signal to 8088/86 8088/86 P and OTHER COMPONENTS P and OTHER COMPONENTS in the systems.in the systems.

Bus Buffering & LatchingBus Buffering & Latching

Before the 8086/8088 Before the 8086/8088 P can be used with P can be used with memory or I/O interfaces, their memory or I/O interfaces, their multiplexed bus multiplexed bus must be must be demultiplexed.demultiplexed.

Buses need to be buffered for large Buses need to be buffered for large systems. Because the maximum fan-out is systems. Because the maximum fan-out is 10, the system must be buffered if it 10, the system must be buffered if it contains more than 10 other components.contains more than 10 other components.

74LS373 Latches are used to demultiplex 74LS373 Latches are used to demultiplex the address/dada bus connection & the address/dada bus connection & multiplexed address/status connections.multiplexed address/status connections.

373 act as a latch, buffer & demultiplexer.373 act as a latch, buffer & demultiplexer.

Bus Timing Bus Timing It is essential to understand It is essential to understand bus timing bus timing

before choosing a memory or I/O device for before choosing a memory or I/O device for interfacing with 8086/8088 interfacing with 8086/8088 P.P.

It provides insight into the operation of the It provides insight into the operation of the bus signals and the basic bus signals and the basic read read & & write write timing timing of the 8086/8088.of the 8086/8088.

The three buses of 8086/8088 –address, data, The three buses of 8086/8088 –address, data, and control- function in exactly the same and control- function in exactly the same manner as those of any other manner as those of any other P.P.

The 8086/8088 The 8086/8088 Ps use the memory & I/O in Ps use the memory & I/O in periods of time called periods of time called BUS CYCLES.BUS CYCLES.

Each bys cycle equals four system-clock Each bys cycle equals four system-clock periods (periods (T StatesT States).).

If the clock is operated at 5MHz (The basic If the clock is operated at 5MHz (The basic operating frequency for these two operating frequency for these two Ps), then Ps), then one 8085/8088 bus cycle is complete in 800 one 8085/8088 bus cycle is complete in 800 ns.ns.

The Ready & Wait StateThe Ready & Wait State

The READY input causes The READY input causes wait states wait states for slower memory & I/O components.for slower memory & I/O components.

A A wait state(Tw) wait state(Tw) is an extra clocking is an extra clocking period, inserted between T2 & T3, period, inserted between T2 & T3, that lengthens the bus cycle.that lengthens the bus cycle.

If one wait state in inserted, then the If one wait state in inserted, then the memory access timememory access time, normally 460 ns , normally 460 ns with a 5 MHz clock, is lengthened by with a 5 MHz clock, is lengthened by one clocking period (200ns) to 660 one clocking period (200ns) to 660 ns.ns.

MINIMUM MODE VERSUS MAXIMUM MODEMINIMUM MODE VERSUS MAXIMUM MODE

These are two available modes of These are two available modes of operations for the 8086/8088 operations for the 8086/8088 P.P.

Minimum mode operation is obtained by Minimum mode operation is obtained by connecting the mode selection pin MN/MX connecting the mode selection pin MN/MX to +5.0V, 2 maximum mode is selected by to +5.0V, 2 maximum mode is selected by grounding this pin.grounding this pin.

Maximum mode is new and unique and Maximum mode is new and unique and designed to be used when ever coprocessor designed to be used when ever coprocessor exists in a system.exists in a system.

Maximum mode operation differs from Maximum mode operation differs from minimum mode in that some of the control minimum mode in that some of the control signals must be externally generated.signals must be externally generated.

THIS REQUIRES THE ADDITION OF AN THIS REQUIRES THE ADDITION OF AN EXTERNAL BUS CONTROLLER- the 8288 chip.EXTERNAL BUS CONTROLLER- the 8288 chip.